CLR (a2)
CLR (a1)
- CPI (t, 0x58)
- BREQ (mul_58)
- CPI (t, 0x69)
+ //sorted by ocurrence, then longest cycle count first
+ CPI (t, 0x69) // most common
BREQ (mul_69)
CPI (t, 0x75)
BREQ (mul_75)
- CPI (t, 0x84)
- BREQ (mul_84)
- CPI (t, 0x8c)
- BREQ (mul_8c)
CPI (t, 0x9d)
BREQ (mul_9d)
+ CPI (t, 0x58)
+ BREQ (mul_58)
+ CPI (t, 0x8c)
+ BREQ (mul_8c)
+ CPI (t, 0x84)
+ BREQ (mul_84)
CPI (t, 0xb0)
BREQ (mul_b0)
- mul_58: // 0101 1000
+ mul_58: // 0101 1000 (24cy)
LSR (a2)
ROR (a1)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_69: // 0110 1001
+ mul_69: // 0110 1001 (26cy)
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_75: // 0111 0101
+ mul_75: // 0111 0101 (28cy)
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_84: // 1000 0100
+ mul_84: // 1000 0100 (22cy)
LSR (a2)
ROR (a1)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_8c: // 1000 1100
+ mul_8c: // 1000 1100 (24cy)
LSR (a2)
ROR (a1)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_9d: // 1001 1101
+ mul_9d: // 1001 1101 (28cy)
ADD (a1, i0)
ADC (a2, i1, carry)
LSR (a2)
LSR (a2)
ROR (a1)
RJMP (endmul)
- mul_b0: // 1011 0000
+ mul_b0: // 1011 0000 (22cy)
LSR (a2)
ROR (a1)
LSR (a2)