Add included header file and fix debug print
[tmk_keyboard.git] / converter / ps2_usb / config.h
CommitLineData
0dde25e8 1/*
1ac674db 2Copyright 2012 Jun Wako <wakojun@gmail.com>
0dde25e8 3
4This program is free software: you can redistribute it and/or modify
5it under the terms of the GNU General Public License as published by
6the Free Software Foundation, either version 2 of the License, or
7(at your option) any later version.
8
9This program is distributed in the hope that it will be useful,
10but WITHOUT ANY WARRANTY; without even the implied warranty of
11MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12GNU General Public License for more details.
13
14You should have received a copy of the GNU General Public License
15along with this program. If not, see <http://www.gnu.org/licenses/>.
16*/
17
4f5f1a53 18#ifndef CONFIG_H
19#define CONFIG_H
20
1ac674db 21#include <avr/interrupt.h>
4f5f1a53 22
23#define VENDOR_ID 0xFEED
1ac674db 24#define PRODUCT_ID 0x6512
04c95015 25#define DEVICE_VER 0x0001
4f5f1a53 26#define MANUFACTURER t.m.k.
27#define PRODUCT PS/2 keyboard converter
28#define DESCRIPTION convert PS/2 keyboard to USB
29
fb8d23c6 30
4f5f1a53 31/* matrix size */
32#define MATRIX_ROWS 32 // keycode bit: 3-0
33#define MATRIX_COLS 8 // keycode bit: 6-4
9a938eec 34
fb8d23c6 35
9a938eec 36/* key combination for command */
37#define IS_COMMAND() ( \
ce2e06c3 38 keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) || \
39 keyboard_report->mods == (MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RSHIFT)) \
9a938eec 40)
41
4f5f1a53 42
1ac674db 43#ifdef PS2_USE_USART
44#if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
45/* XCK for clock line and RXD for data line */
4f5f1a53 46#define PS2_CLOCK_PORT PORTD
47#define PS2_CLOCK_PIN PIND
48#define PS2_CLOCK_DDR DDRD
1ac674db 49#define PS2_CLOCK_BIT 5
4f5f1a53 50#define PS2_DATA_PORT PORTD
51#define PS2_DATA_PIN PIND
52#define PS2_DATA_DDR DDRD
1ac674db 53#define PS2_DATA_BIT 2
4f5f1a53 54
1ac674db 55/* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
56/* set DDR of CLOCK as input to be slave */
57#define PS2_USART_INIT() do { \
58 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
59 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
60 UCSR1C = ((1 << UMSEL10) | \
61 (3 << UPM10) | \
62 (0 << USBS1) | \
63 (3 << UCSZ10) | \
64 (0 << UCPOL1)); \
65 UCSR1A = 0; \
66 UBRR1H = 0; \
67 UBRR1L = 0; \
68} while (0)
69#define PS2_USART_RX_INT_ON() do { \
70 UCSR1B = ((1 << RXCIE1) | \
71 (1 << RXEN1)); \
72} while (0)
73#define PS2_USART_RX_POLL_ON() do { \
74 UCSR1B = (1 << RXEN1); \
75} while (0)
76#define PS2_USART_OFF() do { \
77 UCSR1C = 0; \
78 UCSR1B &= ~((1 << RXEN1) | \
79 (1 << TXEN1)); \
80} while (0)
81#define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
82#define PS2_USART_RX_DATA UDR1
83#define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
84#define PS2_USART_RX_VECT USART1_RX_vect
47f5d8b5 85
1ac674db 86#elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
87/* XCK for clock line and RXD for data line */
88#define PS2_CLOCK_PORT PORTD
89#define PS2_CLOCK_PIN PIND
90#define PS2_CLOCK_DDR DDRD
91#define PS2_CLOCK_BIT 4
92#define PS2_DATA_PORT PORTD
93#define PS2_DATA_PIN PIND
94#define PS2_DATA_DDR DDRD
95#define PS2_DATA_BIT 0
47f5d8b5 96
1ac674db 97/* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
98/* set DDR of CLOCK as input to be slave */
47f5d8b5 99#define PS2_USART_INIT() do { \
100 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
101 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
102 UCSR0C = ((1 << UMSEL00) | \
103 (3 << UPM00) | \
104 (0 << USBS0) | \
105 (3 << UCSZ00) | \
106 (0 << UCPOL0)); \
107 UCSR0A = 0; \
108 UBRR0H = 0; \
109 UBRR0L = 0; \
04f351b8 110} while (0)
47f5d8b5 111#define PS2_USART_RX_INT_ON() do { \
112 UCSR0B = ((1 << RXCIE0) | \
113 (1 << RXEN0)); \
114} while (0)
115#define PS2_USART_RX_POLL_ON() do { \
116 UCSR0B = (1 << RXEN0); \
117} while (0)
118#define PS2_USART_OFF() do { \
119 UCSR0C = 0; \
120 UCSR0B &= ~((1 << RXEN0) | \
121 (1 << TXEN0)); \
122} while (0)
123#define PS2_USART_RX_READY (UCSR0A & (1<<RXC0))
124#define PS2_USART_RX_DATA UDR0
125#define PS2_USART_ERROR (UCSR0A & ((1<<FE0) | (1<<DOR0) | (1<<UPE0)))
126#define PS2_USART_RX_VECT USART_RX_vect
127#endif
1ac674db 128#endif
2b8cd88a 129
47f5d8b5 130
131#ifdef PS2_USE_INT
1ac674db 132/* uses INT1 for clock line(ATMega32U4) */
133#define PS2_CLOCK_PORT PORTD
134#define PS2_CLOCK_PIN PIND
135#define PS2_CLOCK_DDR DDRD
04c95015 136#define PS2_CLOCK_BIT 5
1ac674db 137#define PS2_DATA_PORT PORTD
138#define PS2_DATA_PIN PIND
139#define PS2_DATA_DDR DDRD
140#define PS2_DATA_BIT 2
141
47f5d8b5 142#define PS2_INT_INIT() do { \
143 EICRA |= ((1<<ISC11) | \
144 (0<<ISC10)); \
145} while (0)
146#define PS2_INT_ON() do { \
147 EIMSK |= (1<<INT1); \
148} while (0)
149#define PS2_INT_OFF() do { \
04f351b8 150 EIMSK &= ~(1<<INT1); \
151} while (0)
152#define PS2_INT_VECT INT1_vect
1ac674db 153#endif
04f351b8 154
1ac674db 155
156#ifdef PS2_USE_BUSYWAIT
04c95015 157#define PS2_CLOCK_PORT PORTD
158#define PS2_CLOCK_PIN PIND
159#define PS2_CLOCK_DDR DDRD
160#define PS2_CLOCK_BIT 5
161#define PS2_DATA_PORT PORTD
162#define PS2_DATA_PIN PIND
163#define PS2_DATA_DDR DDRD
164#define PS2_DATA_BIT 2
47f5d8b5 165#endif
04f351b8 166
4f5f1a53 167#endif
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