keyboard/infinity/mbed-infinity/system_MK20D5.c

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           ARM Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manuals:   K20P64M50SF0RM Rev. 1, Oct 2011
   9 **                          K20P32M50SF0RM Rev. 1, Oct 2011
  10 **                          K20P48M50SF0RM Rev. 1, Oct 2011
  11 **
  12 **     Version:             rev. 1.0, 2011-12-15
  13 **
  14 **     Abstract:
  15 **         Provides a system configuration function and a global variable that
  16 **         contains the system frequency. It configures the device and initializes
  17 **         the oscillator (PLL) that is part of the microcontroller device.
  18 **
  19 **     Copyright: 2011 Freescale Semiconductor, Inc. All Rights Reserved.
  20 **
  21 **     http:                 www.freescale.com
  22 **     mail:                 support@freescale.com
  23 **
  24 **     Revisions:
  25 **     - rev. 1.0 (2011-12-15)
  26 **         Initial version
  27 **
  28 ** ###################################################################
  29 */
  30
  31 /**
  32  * @file MK20D5
  33  * @version 1.0
  34  * @date 2011-12-15
  35  * @brief Device specific configuration file for MK20D5 (implementation file)
  36  *
  37  * Provides a system configuration function and a global variable that contains
  38  * the system frequency. It configures the device and initializes the oscillator
  39  * (PLL) that is part of the microcontroller device.
  40  */
  41
  42 #include <stdint.h>
  43 #include "MK20D5.h"
  44
  45 #define DISABLE_WDOG    1
  46
  47 #define CLOCK_SETUP     3
  48 /* Predefined clock setups
  49    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
  50          Reference clock source for MCG module is the slow internal clock source 32.768kHz
  51          Core clock = 41.94MHz, BusClock = 41.94MHz
  52    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
  53          Reference clock source for MCG module is an external crystal 8MHz
  54          Core clock = 48MHz, BusClock = 48MHz
  55    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
  56          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
  57          Core clock = 8MHz, BusClock = 8MHz
  58 */
  59
  60 /*----------------------------------------------------------------------------
  61   Define clock source values
  62  *----------------------------------------------------------------------------*/
  63 #if (CLOCK_SETUP == 0)
  64     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  65     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  66     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  67     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  68     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
  69 #elif (CLOCK_SETUP == 1)
  70     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  71     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  72     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  73     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  74     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
  75 #elif (CLOCK_SETUP == 2)
  76     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  77     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  78     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  79     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  80     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
  81 #elif (CLOCK_SETUP == 3)
  82     /* for Infinity */
  83     #define CPU_XTAL_CLK_HZ                 8000000u
  84     #define CPU_XTAL32k_CLK_HZ              32768u
  85     #define CPU_INT_SLOW_CLK_HZ             32768u
  86     #define CPU_INT_FAST_CLK_HZ             4000000u
  87     #define DEFAULT_SYSTEM_CLOCK            48000000u
  88 #endif
  89
  90
  91 /* ----------------------------------------------------------------------------
  92    -- Core clock
  93    ---------------------------------------------------------------------------- */
  94
  95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  96
  97 /* ----------------------------------------------------------------------------
  98    -- SystemInit()
  99    ---------------------------------------------------------------------------- */
 100
 101 void SystemInit (void) {
 102 #if (DISABLE_WDOG)
 103   /* Disable the WDOG module */
 104   /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
 105   WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
 106   /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
 107   WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
 108   /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
 109   WDOG->STCTRLH = (uint16_t)0x01D2u;
 110 #endif /* (DISABLE_WDOG) */
 111 #if (CLOCK_SETUP == 0)
 112   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 113   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 114   /* Switch to FEI Mode */
 115   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 116   MCG->C1 = (uint8_t)0x06u;
 117   /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
 118   MCG->C2 = (uint8_t)0x00u;
 119   /* MCG_C4: DMX32=0,DRST_DRS=1 */
 120   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
 121   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
 122   MCG->C5 = (uint8_t)0x00u;
 123   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 124   MCG->C6 = (uint8_t)0x00u;
 125   while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 126   }
 127   while((MCG->S & 0x0Cu) != 0x00u) {    /* Wait until output of the FLL is selected */
 128   }
 129 #elif (CLOCK_SETUP == 1)
 130   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 131   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 132   /* Switch to FBE Mode */
 133   /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 134   OSC0->CR = (uint8_t)0x00u;
 135   /* MCG->C7: OSCSEL=0 */
 136   MCG->C7 = (uint8_t)0x00u;
 137   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 138   MCG->C2 = (uint8_t)0x24u;
 139   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 140   MCG->C1 = (uint8_t)0x9Au;
 141   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 142   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
 143   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
 144   MCG->C5 = (uint8_t)0x03u;
 145   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 146   MCG->C6 = (uint8_t)0x00u;
 147   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
 148   }
 149 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
 150   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
 151   }
 152 #endif
 153   while((MCG->S & 0x0Cu) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
 154   }
 155   /* Switch to PBE Mode */
 156   /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
 157   MCG->C5 = (uint8_t)0x03u;
 158   /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
 159   MCG->C6 = (uint8_t)0x40u;
 160   while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
 161   }
 162   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
 163   }
 164   /* Switch to PEE Mode */
 165   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 166   MCG->C1 = (uint8_t)0x1Au;
 167   while((MCG->S & 0x0Cu) != 0x0Cu) {    /* Wait until output of the PLL is selected */
 168   }
 169   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
 170   }
 171 #elif (CLOCK_SETUP == 2)
 172   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 173   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 174   /* Switch to FBE Mode */
 175   /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 176   OSC0->CR = (uint8_t)0x00u;
 177   /* MCG->C7: OSCSEL=0 */
 178   MCG->C7 = (uint8_t)0x00u;
 179   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 180   MCG->C2 = (uint8_t)0x24u;
 181   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 182   MCG->C1 = (uint8_t)0x9Au;
 183   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 184   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
 185   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
 186   MCG->C5 = (uint8_t)0x00u;
 187   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 188   MCG->C6 = (uint8_t)0x00u;
 189   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
 190   }
 191 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
 192   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
 193   }
 194 #endif
 195   while((MCG->S & 0x0CU) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
 196   }
 197   /* Switch to BLPE Mode */
 198   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 199   MCG->C2 = (uint8_t)0x24u;
 200
 201 #elif (CLOCK_SETUP == 3)
 202   /* for Infinity FEI: 48MHz */
 203
 204   /* OUTDIV1(core/system): 48/1, OUTDIV2(bus): 48/1, OUTDIV4(flash): 48/2 */
 205   SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0) | SIM_CLKDIV1_OUTDIV2(0) | SIM_CLKDIV1_OUTDIV4(1);
 206   MCG->C1 = MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK;
 207   /* 32.768KHz x FLL(1464) = 48MHz */
 208   MCG->C4 = MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(1);
 209   /* USB clock source: MCGPLLCLK/MCGFLLCLK */
 210   //SIM->SOPT2 = SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_TRACECLKSEL_MASK;
 211
 212   while((MCG->S & MCG_S_IREFST_MASK) == 0u) { }
 213   while((MCG->S & 0x0Cu) != 0x00u) { }
 214 #endif
 215 }
 216
 217 /* ----------------------------------------------------------------------------
 218    -- SystemCoreClockUpdate()
 219    ---------------------------------------------------------------------------- */
 220
 221 void SystemCoreClockUpdate (void) {
 222   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
 223   uint8_t Divider;
 224
 225   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
 226     /* Output of FLL or PLL is selected */
 227     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
 228       /* FLL is selected */
 229       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
 230         /* External reference clock is selected */
 231         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
 232           MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
 233         } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 234           MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
 235         } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 236         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 237         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
 238         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
 239           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
 240         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
 241       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 242         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
 243       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 244       /* Select correct multiplier to calculate the MCG output clock  */
 245       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 246         case 0x0u:
 247           MCGOUTClock *= 640u;
 248           break;
 249         case 0x20u:
 250           MCGOUTClock *= 1280u;
 251           break;
 252         case 0x40u:
 253           MCGOUTClock *= 1920u;
 254           break;
 255         case 0x60u:
 256           MCGOUTClock *= 2560u;
 257           break;
 258         case 0x80u:
 259           MCGOUTClock *= 732u;
 260           break;
 261         case 0xA0u:
 262           MCGOUTClock *= 1464u;
 263           break;
 264         case 0xC0u:
 265           MCGOUTClock *= 2197u;
 266           break;
 267         case 0xE0u:
 268           MCGOUTClock *= 2929u;
 269           break;
 270         default:
 271           break;
 272       }
 273     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 274       /* PLL is selected */
 275       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
 276       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
 277       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
 278       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
 279     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 280   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
 281     /* Internal reference clock is selected */
 282     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
 283       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
 284     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 285       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
 286     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 287   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
 288     /* External reference clock is selected */
 289     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
 290       MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
 291     } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 292       MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
 293     } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 294   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 295     /* Reserved value */
 296     return;
 297   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 298   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 299 }