Remove common/controller_teensy.h
[tmk_keyboard.git] / converter / ps2_usb / config.h
1 /*
2 Copyright 2012 Jun Wako <wakojun@gmail.com>
3
4 This program is free software: you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation, either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef CONFIG_H
19 #define CONFIG_H
20
21 #include <avr/interrupt.h>
22
23 #define VENDOR_ID 0xFEED
24 #define PRODUCT_ID 0x6512
25 #define MANUFACTURER t.m.k.
26 #define PRODUCT PS/2 keyboard converter
27 #define DESCRIPTION convert PS/2 keyboard to USB
28
29
30 /* matrix size */
31 #define MATRIX_ROWS 32 // keycode bit: 3-0
32 #define MATRIX_COLS 8 // keycode bit: 6-4
33
34
35 /* key combination for command */
36 #define IS_COMMAND() ( \
37 keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) || \
38 keyboard_report->mods == (MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RSHIFT)) \
39 )
40
41
42 /* mouse keys */
43 #ifdef MOUSEKEY_ENABLE
44 # define MOUSEKEY_DELAY_TIME 255
45 #endif
46
47
48 #ifdef PS2_USE_USART
49 #if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
50 /* XCK for clock line and RXD for data line */
51 #define PS2_CLOCK_PORT PORTD
52 #define PS2_CLOCK_PIN PIND
53 #define PS2_CLOCK_DDR DDRD
54 #define PS2_CLOCK_BIT 5
55 #define PS2_DATA_PORT PORTD
56 #define PS2_DATA_PIN PIND
57 #define PS2_DATA_DDR DDRD
58 #define PS2_DATA_BIT 2
59
60 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
61 /* set DDR of CLOCK as input to be slave */
62 #define PS2_USART_INIT() do { \
63 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
64 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
65 UCSR1C = ((1 << UMSEL10) | \
66 (3 << UPM10) | \
67 (0 << USBS1) | \
68 (3 << UCSZ10) | \
69 (0 << UCPOL1)); \
70 UCSR1A = 0; \
71 UBRR1H = 0; \
72 UBRR1L = 0; \
73 } while (0)
74 #define PS2_USART_RX_INT_ON() do { \
75 UCSR1B = ((1 << RXCIE1) | \
76 (1 << RXEN1)); \
77 } while (0)
78 #define PS2_USART_RX_POLL_ON() do { \
79 UCSR1B = (1 << RXEN1); \
80 } while (0)
81 #define PS2_USART_OFF() do { \
82 UCSR1C = 0; \
83 UCSR1B &= ~((1 << RXEN1) | \
84 (1 << TXEN1)); \
85 } while (0)
86 #define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
87 #define PS2_USART_RX_DATA UDR1
88 #define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
89 #define PS2_USART_RX_VECT USART1_RX_vect
90
91 #elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
92 /* XCK for clock line and RXD for data line */
93 #define PS2_CLOCK_PORT PORTD
94 #define PS2_CLOCK_PIN PIND
95 #define PS2_CLOCK_DDR DDRD
96 #define PS2_CLOCK_BIT 4
97 #define PS2_DATA_PORT PORTD
98 #define PS2_DATA_PIN PIND
99 #define PS2_DATA_DDR DDRD
100 #define PS2_DATA_BIT 0
101
102 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
103 /* set DDR of CLOCK as input to be slave */
104 #define PS2_USART_INIT() do { \
105 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
106 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
107 UCSR0C = ((1 << UMSEL00) | \
108 (3 << UPM00) | \
109 (0 << USBS0) | \
110 (3 << UCSZ00) | \
111 (0 << UCPOL0)); \
112 UCSR0A = 0; \
113 UBRR0H = 0; \
114 UBRR0L = 0; \
115 } while (0)
116 #define PS2_USART_RX_INT_ON() do { \
117 UCSR0B = ((1 << RXCIE0) | \
118 (1 << RXEN0)); \
119 } while (0)
120 #define PS2_USART_RX_POLL_ON() do { \
121 UCSR0B = (1 << RXEN0); \
122 } while (0)
123 #define PS2_USART_OFF() do { \
124 UCSR0C = 0; \
125 UCSR0B &= ~((1 << RXEN0) | \
126 (1 << TXEN0)); \
127 } while (0)
128 #define PS2_USART_RX_READY (UCSR0A & (1<<RXC0))
129 #define PS2_USART_RX_DATA UDR0
130 #define PS2_USART_ERROR (UCSR0A & ((1<<FE0) | (1<<DOR0) | (1<<UPE0)))
131 #define PS2_USART_RX_VECT USART_RX_vect
132 #endif
133 #endif
134
135
136 #ifdef PS2_USE_INT
137 /* uses INT1 for clock line(ATMega32U4) */
138 #define PS2_CLOCK_PORT PORTD
139 #define PS2_CLOCK_PIN PIND
140 #define PS2_CLOCK_DDR DDRD
141 #define PS2_CLOCK_BIT 1
142 #define PS2_DATA_PORT PORTD
143 #define PS2_DATA_PIN PIND
144 #define PS2_DATA_DDR DDRD
145 #define PS2_DATA_BIT 2
146
147 #define PS2_INT_INIT() do { \
148 EICRA |= ((1<<ISC11) | \
149 (0<<ISC10)); \
150 } while (0)
151 #define PS2_INT_ON() do { \
152 EIMSK |= (1<<INT1); \
153 } while (0)
154 #define PS2_INT_OFF() do { \
155 EIMSK &= ~(1<<INT1); \
156 } while (0)
157 #define PS2_INT_VECT INT1_vect
158 #endif
159
160
161 #ifdef PS2_USE_BUSYWAIT
162 #define PS2_CLOCK_PORT PORTF
163 #define PS2_CLOCK_PIN PINF
164 #define PS2_CLOCK_DDR DDRF
165 #define PS2_CLOCK_BIT 0
166 #define PS2_DATA_PORT PORTF
167 #define PS2_DATA_PIN PINF
168 #define PS2_DATA_DDR DDRF
169 #define PS2_DATA_BIT 1
170 #endif
171
172 #endif
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