keyboard/infinity/mbed-infinity/startup_MK20D5.s

   1 /* File: startup_MK20D5.s
   2  * Purpose: startup file for Cortex-M4 devices. Should use with
   3  *   GCC for ARM Embedded Processors
   4  * Version: V1.3
   5  * Date: 08 Feb 2012
   6  *
   7  * Copyright (c) 2012, ARM Limited
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions are met:
  12     * Redistributions of source code must retain the above copyright
  13       notice, this list of conditions and the following disclaimer.
  14     * Redistributions in binary form must reproduce the above copyright
  15       notice, this list of conditions and the following disclaimer in the
  16       documentation and/or other materials provided with the distribution.
  17     * Neither the name of the ARM Limited nor the
  18       names of its contributors may be used to endorse or promote products
  19       derived from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  24  * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
  25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  27  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  30  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31  */
  32     .syntax unified
  33     .arch armv7-m
  34
  35     .section .stack
  36     .align 3
  37 #ifdef __STACK_SIZE
  38     .equ    Stack_Size, __STACK_SIZE
  39 #else
  40     .equ    Stack_Size, 0x400
  41 #endif
  42     .globl    __StackTop
  43     .globl    __StackLimit
  44 __StackLimit:
  45     .space    Stack_Size
  46     .size __StackLimit, . - __StackLimit
  47 __StackTop:
  48     .size __StackTop, . - __StackTop
  49
  50     .section .heap
  51     .align 3
  52 #ifdef __HEAP_SIZE
  53     .equ    Heap_Size, __HEAP_SIZE
  54 #else
  55     .equ    Heap_Size, 0xC00
  56 #endif
  57     .globl    __HeapBase
  58     .globl    __HeapLimit
  59 __HeapBase:
  60     .if    Heap_Size
  61     .space    Heap_Size
  62     .endif
  63     .size __HeapBase, . - __HeapBase
  64 __HeapLimit:
  65     .size __HeapLimit, . - __HeapLimit
  66
  67     .section .isr_vector
  68     .align 2
  69     .globl __isr_vector
  70 __isr_vector:
  71     .long    __StackTop            /* Top of Stack */
  72     .long    Reset_Handler         /* Reset Handler */
  73     .long    NMI_Handler           /* NMI Handler */
  74     .long    HardFault_Handler     /* Hard Fault Handler */
  75     .long    MemManage_Handler     /* MPU Fault Handler */
  76     .long    BusFault_Handler      /* Bus Fault Handler */
  77     .long    UsageFault_Handler    /* Usage Fault Handler */
  78     .long    0                     /* Reserved */
  79     .long    0                     /* Reserved */
  80     .long    0                     /* Reserved */
  81     .long    0                     /* Reserved */
  82     .long    SVC_Handler           /* SVCall Handler */
  83     .long    DebugMon_Handler      /* Debug Monitor Handler */
  84     .long    0                     /* Reserved */
  85     .long    PendSV_Handler        /* PendSV Handler */
  86     .long    SysTick_Handler       /* SysTick Handler */
  87
  88     /* External interrupts */
  89     .long    DMA0_IRQHandler        /*  0:  Watchdog Timer            */
  90     .long    DMA1_IRQHandler        /*  1:  Real Time Clock           */
  91     .long    DMA2_IRQHandler       /*  2:  Timer0 / Timer1           */
  92     .long    DMA3_IRQHandler       /*  3:  Timer2 / Timer3           */
  93     .long    DMA_Error_IRQHandler       /*  4:  MCIa                      */
  94     .long    0       /*  5:  MCIb                      */
  95     .long    FTFL_IRQHandler      /*  6:  UART0 - DUT FPGA          */
  96     .long    Read_Collision_IRQHandler      /*  7:  UART1 - DUT FPGA          */
  97     .long    LVD_LVW_IRQHandler      /*  8:  UART2 - DUT FPGA          */
  98     .long    LLW_IRQHandler      /*  9:  UART4 - not connected     */
  99     .long    Watchdog_IRQHandler       /* 10: AACI / AC97                */
 100     .long    I2C0_IRQHandler       /* 11: CLCD Combined Interrupt    */
 101     .long    SPI0_IRQHandler       /* 12: Ethernet                   */
 102     .long    I2S0_Tx_IRQHandler      /* 13: USB Device                 */
 103     .long    I2S0_Rx_IRQHandler      /* 14: USB Host Controller        */
 104     .long    UART0_LON_IRQHandler      /* 15: Character LCD              */
 105     .long    UART0_RX_TX_IRQHandler    /* 16: Flexray                    */
 106     .long    UART0_ERR_IRQHandler        /* 17: CAN                        */
 107     .long    UART1_RX_TX_IRQHandler        /* 18: LIN                        */
 108     .long    UART1_ERR_IRQHandler        /* 19: I2C ADC/DAC                */
 109     .long    UART2_RX_TX_IRQHandler                     /* 20: Reserved                   */
 110     .long    UART2_ERR_IRQHandler                     /* 21: Reserved                   */
 111     .long    ADC0_IRQHandler                     /* 22: Reserved                   */
 112     .long    CMP0_IRQHandler                     /* 23: Reserved                   */
 113     .long    CMP1_IRQHandler                     /* 24: Reserved                   */
 114     .long    FTM0_IRQHandler                     /* 25: Reserved                   */
 115     .long    FTM1_IRQHandler                     /* 26: Reserved                   */
 116     .long    CMT_IRQHandler                     /* 27: Reserved                   */
 117     .long    RTC_IRQHandler   /* 28: Reserved - CPU FPGA CLCD   */
 118     .long    RTC_Seconds_IRQHandler                     /* 29: Reserved - CPU FPGA        */
 119     .long    PIT0_IRQHandler      /* 30: UART3    - CPU FPGA        */
 120     .long    PIT1_IRQHandler        /* 31: SPI Touchscreen - CPU FPGA */
 121     .long    PIT2_IRQHandler
 122     .long    PIT3_IRQHandler
 123     .long    PDB0_IRQHandler
 124     .long    USB0_IRQHandler
 125     .long    USBDCD_IRQHandler
 126     .long    TSI0_IRQHandler
 127     .long    MCG_IRQHandler
 128     .long    LPTimer_IRQHandler
 129     .long    PORTA_IRQHandler
 130     .long    PORTB_IRQHandler
 131     .long    PORTC_IRQHandler
 132     .long    PORTD_IRQHandler
 133     .long    PORTE_IRQHandler
 134     .long    SWI_IRQHandler
 135     .size    __isr_vector, . - __isr_vector
 136
 137     .section .text.Reset_Handler
 138     .thumb
 139     .thumb_func
 140     .align 2
 141     .globl    Reset_Handler
 142     .type    Reset_Handler, %function
 143 Reset_Handler:
 144 /*     Loop to copy data from read only memory to RAM. The ranges
 145  *      of copy from/to are specified by following symbols evaluated in
 146  *      linker script.
 147  *      __etext: End of code section, i.e., begin of data sections to copy from.
 148  *      __data_start__/__data_end__: RAM address range that data should be
 149  *      copied to. Both must be aligned to 4 bytes boundary.  */
 150     ldr    r0, =SystemInit
 151     blx    r0
 152
 153     ldr    r1, =__etext
 154     ldr    r2, =__data_start__
 155     ldr    r3, =__data_end__
 156
 157 .Lflash_to_ram_loop:
 158     cmp     r2, r3
 159     ittt    lt
 160     ldrlt   r0, [r1], #4
 161     strlt   r0, [r2], #4
 162     blt    .Lflash_to_ram_loop
 163
 164 .Lflash_to_ram_loop_end:
 165
 166     ldr    r0, =_start
 167     bx    r0
 168     .pool
 169     .size Reset_Handler, . - Reset_Handler
 170
 171     .text
 172 /*    Macro to define default handlers. Default handler
 173  *    will be weak symbol and just dead loops. They can be
 174  *    overwritten by other handlers */
 175     .macro    def_default_handler    handler_name
 176     .align 1
 177     .thumb_func
 178     .weak    \handler_name
 179     .type    \handler_name, %function
 180 \handler_name :
 181     b    .
 182     .size    \handler_name, . - \handler_name
 183     .endm
 184
 185     def_default_handler    NMI_Handler
 186     def_default_handler    HardFault_Handler
 187     def_default_handler    MemManage_Handler
 188     def_default_handler    BusFault_Handler
 189     def_default_handler    UsageFault_Handler
 190     def_default_handler    SVC_Handler
 191     def_default_handler    DebugMon_Handler
 192     def_default_handler    PendSV_Handler
 193     def_default_handler    SysTick_Handler
 194     def_default_handler    Default_Handler
 195
 196     .macro    def_irq_default_handler    handler_name
 197     .weak     \handler_name
 198     .set      \handler_name, Default_Handler
 199     .endm
 200
 201     def_irq_default_handler    DMA0_IRQHandler
 202     def_irq_default_handler    DMA1_IRQHandler
 203     def_irq_default_handler    DMA2_IRQHandler
 204     def_irq_default_handler    DMA3_IRQHandler
 205     def_irq_default_handler    DMA_Error_IRQHandler
 206     def_irq_default_handler    FTFL_IRQHandler
 207     def_irq_default_handler    Read_Collision_IRQHandler
 208     def_irq_default_handler    LVD_LVW_IRQHandler
 209     def_irq_default_handler    LLW_IRQHandler
 210     def_irq_default_handler    Watchdog_IRQHandler
 211     def_irq_default_handler    I2C0_IRQHandler
 212     def_irq_default_handler    SPI0_IRQHandler
 213     def_irq_default_handler    I2S0_Tx_IRQHandler
 214     def_irq_default_handler    I2S0_Rx_IRQHandler
 215     def_irq_default_handler    UART0_LON_IRQHandler
 216     def_irq_default_handler    UART0_RX_TX_IRQHandler
 217     def_irq_default_handler    UART0_ERR_IRQHandler
 218     def_irq_default_handler    UART1_RX_TX_IRQHandler
 219     def_irq_default_handler    UART1_ERR_IRQHandler
 220     def_irq_default_handler    UART2_RX_TX_IRQHandler
 221     def_irq_default_handler    UART2_ERR_IRQHandler
 222     def_irq_default_handler    ADC0_IRQHandler
 223     def_irq_default_handler    CMP0_IRQHandler
 224     def_irq_default_handler    CMP1_IRQHandler
 225     def_irq_default_handler    FTM0_IRQHandler
 226     def_irq_default_handler    FTM1_IRQHandler
 227     def_irq_default_handler    CMT_IRQHandler
 228     def_irq_default_handler    RTC_IRQHandler
 229     def_irq_default_handler    RTC_Seconds_IRQHandler
 230     def_irq_default_handler    PIT0_IRQHandler
 231     def_irq_default_handler    PIT1_IRQHandler
 232     def_irq_default_handler    PIT2_IRQHandler
 233     def_irq_default_handler    PIT3_IRQHandler
 234     def_irq_default_handler    PDB0_IRQHandler
 235     def_irq_default_handler    USB0_IRQHandler
 236     def_irq_default_handler    USBDCD_IRQHandler
 237     def_irq_default_handler    TSI0_IRQHandler
 238     def_irq_default_handler    MCG_IRQHandler
 239     def_irq_default_handler    LPTimer_IRQHandler
 240     def_irq_default_handler    PORTA_IRQHandler
 241     def_irq_default_handler    PORTB_IRQHandler
 242     def_irq_default_handler    PORTC_IRQHandler
 243     def_irq_default_handler    PORTD_IRQHandler
 244     def_irq_default_handler    PORTE_IRQHandler
 245     def_irq_default_handler    SWI_IRQHandler
 246     def_irq_default_handler    DEF_IRQHandler
 247
 248 /* Flash protection region, placed at 0x400 */
 249     .text
 250     .thumb
 251     .align 2
 252     .section .kinetis_flash_config_field,"a",%progbits
 253 kinetis_flash_config:
 254     .long 0xffffffff
 255     .long 0xffffffff
 256     .long 0xffffffff
 257     .long 0xfffffffe
 258
 259     .end