tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/ohci_wrapp_RZ_A1.h

   1 /* Copyright (c) 2010-2011 mbed.org, MIT License
   2 *
   3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
   4 * and associated documentation files (the "Software"), to deal in the Software without
   5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
   6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
   7 * Software is furnished to do so, subject to the following conditions:
   8 *
   9 * The above copyright notice and this permission notice shall be included in all copies or
  10 * substantial portions of the Software.
  11 *
  12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
  13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
  15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  17 */
  18
  19 #ifndef OHCI_WRAPP_RZ_A1_H
  20 #define OHCI_WRAPP_RZ_A1_H
  21
  22 #ifdef __cplusplus
  23 extern "C" {
  24 #endif
  25
  26 #define OHCI_REG_REVISION           (0x00)    /* HcRevision         */
  27 #define OHCI_REG_CONTROL            (0x04)    /* HcControl          */
  28 #define OHCI_REG_COMMANDSTATUS      (0x08)    /* HcCommandStatus    */
  29 #define OHCI_REG_INTERRUPTSTATUS    (0x0C)    /* HcInterruptStatus  */
  30 #define OHCI_REG_INTERRUPTENABLE    (0x10)    /* HcInterruptEnable  */
  31 #define OHCI_REG_INTERRUPTDISABLE   (0x14)    /* HcInterruptDisable */
  32 #define OHCI_REG_HCCA               (0x18)    /* HcHCCA             */
  33 #define OHCI_REG_PERIODCURRENTED    (0x1C)    /* HcPeriodCurrentED  */
  34 #define OHCI_REG_CONTROLHEADED      (0x20)    /* HcControlHeadED    */
  35 #define OHCI_REG_CONTROLCURRENTED   (0x24)    /* HcControlCurrentED */
  36 #define OHCI_REG_BULKHEADED         (0x28)    /* HcBulkHeadED       */
  37 #define OHCI_REG_BULKCURRENTED      (0x2C)    /* HcBulkCurrentED    */
  38 #define OHCI_REG_DONEHEADED         (0x30)    /* HcDoneHead         */
  39 #define OHCI_REG_FMINTERVAL         (0x34)    /* HcFmInterval       */
  40 #define OHCI_REG_FMREMAINING        (0x38)    /* HcFmRemaining      */
  41 #define OHCI_REG_FMNUMBER           (0x3C)    /* HcFmNumber         */
  42 #define OHCI_REG_PERIODICSTART      (0x40)    /* HcPeriodicStart    */
  43 #define OHCI_REG_LSTHRESHOLD        (0x44)    /* HcLSThreshold      */
  44 #define OHCI_REG_RHDESCRIPTORA      (0x48)    /* HcRhDescriptorA    */
  45 #define OHCI_REG_RHDESCRIPTORB      (0x4C)    /* HcRhDescriptorB    */
  46 #define OHCI_REG_RHSTATUS           (0x50)    /* HcRhStatus         */
  47 #define OHCI_REG_RHPORTSTATUS1      (0x54)    /* HcRhPortStatus1    */
  48
  49 typedef void (usbisr_fnc_t)(void);
  50
  51 extern void ohciwrapp_init(usbisr_fnc_t *p_usbisr_fnc);
  52 extern uint32_t ohciwrapp_reg_r(uint32_t reg_ofs);
  53 extern void ohciwrapp_reg_w(uint32_t reg_ofs, uint32_t set_data);
  54 extern void ohciwrapp_interrupt(uint32_t int_sense);
  55
  56 #ifdef __cplusplus
  57 }
  58 #endif
  59
  60 #endif  /* OHCI_WRAPP_RZ_A1_H */