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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/TARGET_RENESAS/TARGET_RZ_A1H/usb0/inc/usb0_host_dmacdrv.h
1 /*******************************************************************************
3 * This software is supplied by Renesas Electronics Corporation and is only
4 * intended for use with Renesas products. No other uses are authorized. This
5 * software is owned by Renesas Electronics Corporation and is protected under
6 * all applicable laws, including copyright laws.
7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
16 * Renesas reserves the right, without notice, to make changes to this software
17 * and to discontinue the availability of this software. By using this software,
18 * you agree to the additional terms and conditions found by accessing the
20 * http://www.renesas.com/disclaimer
21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
22 *******************************************************************************/
23 /*******************************************************************************
24 * File Name : usb0_host_dmacdrv.h
26 * $Date:: 2014-07-09 16:29:19 +0900#$
27 * Description : RZ/A1H R7S72100 USB Sample Program
28 *******************************************************************************/
29 #ifndef USB0_HOST_DMACDRV_H
30 #define USB0_HOST_DMACDRV_H
33 /*******************************************************************************
34 Includes <System Includes> , "Project Includes"
35 *******************************************************************************/
38 /*******************************************************************************
40 *******************************************************************************/
41 typedef struct dmac_transinfo
43 uint32_t src_addr
; /* Transfer source address */
44 uint32_t dst_addr
; /* Transfer destination address */
45 uint32_t count
; /* Transfer byte count */
46 uint32_t src_size
; /* Transfer source data size */
47 uint32_t dst_size
; /* Transfer destination data size */
48 uint32_t saddr_dir
; /* Transfer source address direction */
49 uint32_t daddr_dir
; /* Transfer destination address direction */
53 /*******************************************************************************
55 *******************************************************************************/
56 /* ==== Transfer specification of the sample program ==== */
57 #define DMAC_SAMPLE_SINGLE (0) /* Single transfer */
58 #define DMAC_SAMPLE_CONTINUATION (1) /* Continuous transfer (use REN bit) */
60 /* ==== DMA modes ==== */
61 #define DMAC_MODE_REGISTER (0) /* Register mode */
62 #define DMAC_MODE_LINK (1) /* Link mode */
64 /* ==== Transfer requests ==== */
65 #define DMAC_REQ_MODE_EXT (0) /* External request */
66 #define DMAC_REQ_MODE_PERI (1) /* On-chip peripheral module request */
67 #define DMAC_REQ_MODE_SOFT (2) /* Auto-request (request by software) */
69 /* ==== DMAC transfer sizes ==== */
70 #define DMAC_TRANS_SIZE_8 (0) /* 8 bits */
71 #define DMAC_TRANS_SIZE_16 (1) /* 16 bits */
72 #define DMAC_TRANS_SIZE_32 (2) /* 32 bits */
73 #define DMAC_TRANS_SIZE_64 (3) /* 64 bits */
74 #define DMAC_TRANS_SIZE_128 (4) /* 128 bits */
75 #define DMAC_TRANS_SIZE_256 (5) /* 256 bits */
76 #define DMAC_TRANS_SIZE_512 (6) /* 512 bits */
77 #define DMAC_TRANS_SIZE_1024 (7) /* 1024 bits */
79 /* ==== Address increment for transferring ==== */
80 #define DMAC_TRANS_ADR_NO_INC (1) /* Not increment */
81 #define DMAC_TRANS_ADR_INC (0) /* Increment */
83 /* ==== Method for detecting DMA request ==== */
84 #define DMAC_REQ_DET_FALL (0) /* Falling edge detection */
85 #define DMAC_REQ_DET_RISE (1) /* Rising edge detection */
86 #define DMAC_REQ_DET_LOW (2) /* Low level detection */
87 #define DMAC_REQ_DET_HIGH (3) /* High level detection */
89 /* ==== Request Direction ==== */
90 #define DMAC_REQ_DIR_SRC (0) /* DMAREQ is the source/ DMAACK is active when reading */
91 #define DMAC_REQ_DIR_DST (1) /* DMAREQ is the destination/ DMAACK is active when writing */
93 /* ==== Descriptors ==== */
94 #define DMAC_DESC_HEADER (0) /* Header */
95 #define DMAC_DESC_SRC_ADDR (1) /* Source Address */
96 #define DMAC_DESC_DST_ADDR (2) /* Destination Address */
97 #define DMAC_DESC_COUNT (3) /* Transaction Byte */
98 #define DMAC_DESC_CHCFG (4) /* Channel Confg */
99 #define DMAC_DESC_CHITVL (5) /* Channel Interval */
100 #define DMAC_DESC_CHEXT (6) /* Channel Extension */
101 #define DMAC_DESC_LINK_ADDR (7) /* Link Address */
103 /* ==== On-chip peripheral module requests ===== */
104 typedef enum dmac_request_factor
106 DMAC_REQ_USB0_DMA0_TX
, /* USB_0 channel 0 transmit FIFO empty */
107 DMAC_REQ_USB0_DMA0_RX
, /* USB_0 channel 0 receive FIFO full */
108 DMAC_REQ_USB0_DMA1_TX
, /* USB_0 channel 1 transmit FIFO empty */
109 DMAC_REQ_USB0_DMA1_RX
, /* USB_0 channel 1 receive FIFO full */
110 DMAC_REQ_USB1_DMA0_TX
, /* USB_1 channel 0 transmit FIFO empty */
111 DMAC_REQ_USB1_DMA0_RX
, /* USB_1 channel 0 receive FIFO full */
112 DMAC_REQ_USB1_DMA1_TX
, /* USB_1 channel 1 transmit FIFO empty */
113 DMAC_REQ_USB1_DMA1_RX
, /* USB_1 channel 1 receive FIFO full */
114 } dmac_request_factor_t
;
117 /*******************************************************************************
119 *******************************************************************************/
122 /*******************************************************************************
124 *******************************************************************************/
125 void usb0_host_DMAC1_PeriReqInit(const dmac_transinfo_t
* trans_info
, uint32_t dmamode
, uint32_t continuation
,
126 uint32_t request_factor
, uint32_t req_direction
);
127 int32_t usb0_host_DMAC1_Open(uint32_t req
);
128 void usb0_host_DMAC1_Close(uint32_t * remain
);
129 void usb0_host_DMAC1_Load_Set(uint32_t src_addr
, uint32_t dst_addr
, uint32_t count
);
131 void usb0_host_DMAC2_PeriReqInit(const dmac_transinfo_t
* trans_info
, uint32_t dmamode
, uint32_t continuation
,
132 uint32_t request_factor
, uint32_t req_direction
);
133 int32_t usb0_host_DMAC2_Open(uint32_t req
);
134 void usb0_host_DMAC2_Close(uint32_t * remain
);
135 void usb0_host_DMAC2_Load_Set(uint32_t src_addr
, uint32_t dst_addr
, uint32_t count
);
137 #endif /* USB0_HOST_DMACDRV_H */