tmk_core/tool/mbed/mbed-sdk/libraries/USBHost/USBHost/USBHALHost_LPC17.cpp

   1 /* mbed USBHost Library
   2  * Copyright (c) 2006-2013 ARM Limited
   3  *
   4  * Licensed under the Apache License, Version 2.0 (the "License");
   5  * you may not use this file except in compliance with the License.
   6  * You may obtain a copy of the License at
   7  *
   8  *     http://www.apache.org/licenses/LICENSE-2.0
   9  *
  10  * Unless required by applicable law or agreed to in writing, software
  11  * distributed under the License is distributed on an "AS IS" BASIS,
  12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
  13  * See the License for the specific language governing permissions and
  14  * limitations under the License.
  15  */
  16
  17 #if defined(TARGET_LPC1768)
  18
  19 #include "mbed.h"
  20 #include "USBHALHost.h"
  21 #include "dbg.h"
  22
  23 // bits of the USB/OTG clock control register
  24 #define HOST_CLK_EN     (1<<0)
  25 #define DEV_CLK_EN      (1<<1)
  26 #define PORTSEL_CLK_EN  (1<<3)
  27 #define AHB_CLK_EN      (1<<4)
  28
  29 // bits of the USB/OTG clock status register
  30 #define HOST_CLK_ON     (1<<0)
  31 #define DEV_CLK_ON      (1<<1)
  32 #define PORTSEL_CLK_ON  (1<<3)
  33 #define AHB_CLK_ON      (1<<4)
  34
  35 // we need host clock, OTG/portsel clock and AHB clock
  36 #define CLOCK_MASK (HOST_CLK_EN | PORTSEL_CLK_EN | AHB_CLK_EN)
  37
  38 #define HCCA_SIZE sizeof(HCCA)
  39 #define ED_SIZE sizeof(HCED)
  40 #define TD_SIZE sizeof(HCTD)
  41
  42 #define TOTAL_SIZE (HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE) + (MAX_TD*TD_SIZE))
  43
  44 static volatile uint8_t usb_buf[TOTAL_SIZE] __attribute((section("AHBSRAM1"),aligned(256)));  //256 bytes aligned!
  45
  46 USBHALHost * USBHALHost::instHost;
  47
  48 USBHALHost::USBHALHost() {
  49     instHost = this;
  50     memInit();
  51     memset((void*)usb_hcca, 0, HCCA_SIZE);
  52     for (int i = 0; i < MAX_ENDPOINT; i++) {
  53         edBufAlloc[i] = false;
  54     }
  55     for (int i = 0; i < MAX_TD; i++) {
  56         tdBufAlloc[i] = false;
  57     }
  58 }
  59
  60 void USBHALHost::init() {
  61     NVIC_DisableIRQ(USB_IRQn);
  62
  63     //Cut power
  64     LPC_SC->PCONP &= ~(1UL<<31);
  65     wait_ms(100);
  66
  67     // turn on power for USB
  68     LPC_SC->PCONP       |= (1UL<<31);
  69
  70     // Enable USB host clock, port selection and AHB clock
  71     LPC_USB->USBClkCtrl |= CLOCK_MASK;
  72
  73     // Wait for clocks to become available
  74     while ((LPC_USB->USBClkSt & CLOCK_MASK) != CLOCK_MASK);
  75
  76     // it seems the bits[0:1] mean the following
  77     // 0: U1=device, U2=host
  78     // 1: U1=host, U2=host
  79     // 2: reserved
  80     // 3: U1=host, U2=device
  81     // NB: this register is only available if OTG clock (aka "port select") is enabled!!
  82     // since we don't care about port 2, set just bit 0 to 1 (U1=host)
  83     LPC_USB->OTGStCtrl |= 1;
  84
  85     // now that we've configured the ports, we can turn off the portsel clock
  86     LPC_USB->USBClkCtrl &= ~PORTSEL_CLK_EN;
  87
  88     // configure USB D+/D- pins
  89     // P0[29] = USB_D+, 01
  90     // P0[30] = USB_D-, 01
  91     LPC_PINCON->PINSEL1 &= ~((3<<26) | (3<<28));
  92     LPC_PINCON->PINSEL1 |=  ((1<<26) | (1<<28));
  93
  94     LPC_USB->HcControl       = 0; // HARDWARE RESET
  95     LPC_USB->HcControlHeadED = 0; // Initialize Control list head to Zero
  96     LPC_USB->HcBulkHeadED    = 0; // Initialize Bulk list head to Zero
  97
  98     // Wait 100 ms before apply reset
  99     wait_ms(100);
 100
 101     // software reset
 102     LPC_USB->HcCommandStatus = OR_CMD_STATUS_HCR;
 103
 104     // Write Fm Interval and Largest Data Packet Counter
 105     LPC_USB->HcFmInterval    = DEFAULT_FMINTERVAL;
 106     LPC_USB->HcPeriodicStart = FI * 90 / 100;
 107
 108     // Put HC in operational state
 109     LPC_USB->HcControl  = (LPC_USB->HcControl & (~OR_CONTROL_HCFS)) | OR_CONTROL_HC_OPER;
 110     // Set Global Power
 111     LPC_USB->HcRhStatus = OR_RH_STATUS_LPSC;
 112
 113     LPC_USB->HcHCCA = (uint32_t)(usb_hcca);
 114
 115     // Clear Interrrupt Status
 116     LPC_USB->HcInterruptStatus |= LPC_USB->HcInterruptStatus;
 117
 118     LPC_USB->HcInterruptEnable  = OR_INTR_ENABLE_MIE | OR_INTR_ENABLE_WDH | OR_INTR_ENABLE_RHSC;
 119
 120     // Enable the USB Interrupt
 121     NVIC_SetVector(USB_IRQn, (uint32_t)(_usbisr));
 122     LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
 123     LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
 124
 125     NVIC_EnableIRQ(USB_IRQn);
 126
 127     // Check for any connected devices
 128     if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
 129         //Device connected
 130         wait_ms(150);
 131         USB_DBG("Device connected (%08x)\n\r", LPC_USB->HcRhPortStatus1);
 132         deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
 133     }
 134 }
 135
 136 uint32_t USBHALHost::controlHeadED() {
 137     return LPC_USB->HcControlHeadED;
 138 }
 139
 140 uint32_t USBHALHost::bulkHeadED() {
 141     return LPC_USB->HcBulkHeadED;
 142 }
 143
 144 uint32_t USBHALHost::interruptHeadED() {
 145     return usb_hcca->IntTable[0];
 146 }
 147
 148 void USBHALHost::updateBulkHeadED(uint32_t addr) {
 149     LPC_USB->HcBulkHeadED = addr;
 150 }
 151
 152
 153 void USBHALHost::updateControlHeadED(uint32_t addr) {
 154     LPC_USB->HcControlHeadED = addr;
 155 }
 156
 157 void USBHALHost::updateInterruptHeadED(uint32_t addr) {
 158     usb_hcca->IntTable[0] = addr;
 159 }
 160
 161
 162 void USBHALHost::enableList(ENDPOINT_TYPE type) {
 163     switch(type) {
 164         case CONTROL_ENDPOINT:
 165             LPC_USB->HcCommandStatus = OR_CMD_STATUS_CLF;
 166             LPC_USB->HcControl |= OR_CONTROL_CLE;
 167             break;
 168         case ISOCHRONOUS_ENDPOINT:
 169             break;
 170         case BULK_ENDPOINT:
 171             LPC_USB->HcCommandStatus = OR_CMD_STATUS_BLF;
 172             LPC_USB->HcControl |= OR_CONTROL_BLE;
 173             break;
 174         case INTERRUPT_ENDPOINT:
 175             LPC_USB->HcControl |= OR_CONTROL_PLE;
 176             break;
 177     }
 178 }
 179
 180
 181 bool USBHALHost::disableList(ENDPOINT_TYPE type) {
 182     switch(type) {
 183         case CONTROL_ENDPOINT:
 184             if(LPC_USB->HcControl & OR_CONTROL_CLE) {
 185                 LPC_USB->HcControl &= ~OR_CONTROL_CLE;
 186                 return true;
 187             }
 188             return false;
 189         case ISOCHRONOUS_ENDPOINT:
 190             return false;
 191         case BULK_ENDPOINT:
 192             if(LPC_USB->HcControl & OR_CONTROL_BLE){
 193                 LPC_USB->HcControl &= ~OR_CONTROL_BLE;
 194                 return true;
 195             }
 196             return false;
 197         case INTERRUPT_ENDPOINT:
 198             if(LPC_USB->HcControl & OR_CONTROL_PLE) {
 199                 LPC_USB->HcControl &= ~OR_CONTROL_PLE;
 200                 return true;
 201             }
 202             return false;
 203     }
 204     return false;
 205 }
 206
 207
 208 void USBHALHost::memInit() {
 209     usb_hcca = (volatile HCCA *)usb_buf;
 210     usb_edBuf = usb_buf + HCCA_SIZE;
 211     usb_tdBuf = usb_buf + HCCA_SIZE + (MAX_ENDPOINT*ED_SIZE);
 212 }
 213
 214 volatile uint8_t * USBHALHost::getED() {
 215     for (int i = 0; i < MAX_ENDPOINT; i++) {
 216         if ( !edBufAlloc[i] ) {
 217             edBufAlloc[i] = true;
 218             return (volatile uint8_t *)(usb_edBuf + i*ED_SIZE);
 219         }
 220     }
 221     perror("Could not allocate ED\r\n");
 222     return NULL; //Could not alloc ED
 223 }
 224
 225 volatile uint8_t * USBHALHost::getTD() {
 226     int i;
 227     for (i = 0; i < MAX_TD; i++) {
 228         if ( !tdBufAlloc[i] ) {
 229             tdBufAlloc[i] = true;
 230             return (volatile uint8_t *)(usb_tdBuf + i*TD_SIZE);
 231         }
 232     }
 233     perror("Could not allocate TD\r\n");
 234     return NULL; //Could not alloc TD
 235 }
 236
 237
 238 void USBHALHost::freeED(volatile uint8_t * ed) {
 239     int i;
 240     i = (ed - usb_edBuf) / ED_SIZE;
 241     edBufAlloc[i] = false;
 242 }
 243
 244 void USBHALHost::freeTD(volatile uint8_t * td) {
 245     int i;
 246     i = (td - usb_tdBuf) / TD_SIZE;
 247     tdBufAlloc[i] = false;
 248 }
 249
 250
 251 void USBHALHost::resetRootHub() {
 252     // Initiate port reset
 253     LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRS;
 254
 255     while (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRS);
 256
 257     // ...and clear port reset signal
 258     LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
 259 }
 260
 261
 262 void USBHALHost::_usbisr(void) {
 263     if (instHost) {
 264         instHost->UsbIrqhandler();
 265     }
 266 }
 267
 268 void USBHALHost::UsbIrqhandler() {
 269     if( LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable ) //Is there something to actually process?
 270     {
 271
 272         uint32_t int_status = LPC_USB->HcInterruptStatus & LPC_USB->HcInterruptEnable;
 273
 274         // Root hub status change interrupt
 275         if (int_status & OR_INTR_STATUS_RHSC) {
 276             if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CSC) {
 277                 if (LPC_USB->HcRhStatus & OR_RH_STATUS_DRWE) {
 278                     // When DRWE is on, Connect Status Change
 279                     // means a remote wakeup event.
 280                 } else {
 281
 282                     //Root device connected
 283                     if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_CCS) {
 284
 285                         // wait 150ms to avoid bounce
 286                         wait_ms(150);
 287
 288                         //Hub 0 (root hub), Port 1 (count starts at 1), Low or High speed
 289                         deviceConnected(0, 1, LPC_USB->HcRhPortStatus1 & OR_RH_PORT_LSDA);
 290                     }
 291
 292                     //Root device disconnected
 293                     else {
 294
 295                         if (!(int_status & OR_INTR_STATUS_WDH)) {
 296                             usb_hcca->DoneHead = 0;
 297                         }
 298
 299                         // wait 200ms to avoid bounce
 300                         wait_ms(200);
 301
 302                         deviceDisconnected(0, 1, NULL, usb_hcca->DoneHead & 0xFFFFFFFE);
 303
 304                         if (int_status & OR_INTR_STATUS_WDH) {
 305                             usb_hcca->DoneHead = 0;
 306                             LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
 307                         }
 308                     }
 309                 }
 310                 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_CSC;
 311             }
 312             if (LPC_USB->HcRhPortStatus1 & OR_RH_PORT_PRSC) {
 313                 LPC_USB->HcRhPortStatus1 = OR_RH_PORT_PRSC;
 314             }
 315             LPC_USB->HcInterruptStatus = OR_INTR_STATUS_RHSC;
 316         }
 317
 318         // Writeback Done Head interrupt
 319         if (int_status & OR_INTR_STATUS_WDH) {
 320             transferCompleted(usb_hcca->DoneHead & 0xFFFFFFFE);
 321             LPC_USB->HcInterruptStatus = OR_INTR_STATUS_WDH;
 322         }
 323     }
 324 }
 325 #endif