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1 /* mbed USBHost Library
2 * Copyright (c) 2006-2013 ARM Limited
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef USB_INC_H
18 #define USB_INC_H
19
20 #include "mbed.h"
21 #include "toolchain.h"
22
23 enum USB_TYPE {
24 USB_TYPE_OK = 0,
25
26 // completion code
27 USB_TYPE_CRC_ERROR = 1,
28 USB_TYPE_BIT_STUFFING_ERROR = 2,
29 USB_TYPE_DATA_TOGGLE_MISMATCH_ERROR = 3,
30 USB_TYPE_STALL_ERROR = 4,
31 USB_TYPE_DEVICE_NOT_RESPONDING_ERROR = 5,
32 USB_TYPE_PID_CHECK_FAILURE_ERROR = 6,
33 USB_TYPE_UNEXPECTED_PID_ERROR = 7,
34 USB_TYPE_DATA_OVERRUN_ERROR = 8,
35 USB_TYPE_DATA_UNDERRUN_ERROR = 9,
36 USB_TYPE_RESERVED = 9,
37 USB_TYPE_RESERVED_ = 10,
38 USB_TYPE_BUFFER_OVERRUN_ERROR = 12,
39 USB_TYPE_BUFFER_UNDERRUN_ERROR = 13,
40
41 // general usb state
42 USB_TYPE_DISCONNECTED = 14,
43 USB_TYPE_FREE = 15,
44 USB_TYPE_IDLE = 16,
45 USB_TYPE_PROCESSING = 17,
46
47 USB_TYPE_ERROR = 18,
48 };
49
50
51 enum ENDPOINT_DIRECTION {
52 OUT = 1,
53 IN
54 };
55
56 enum ENDPOINT_TYPE {
57 CONTROL_ENDPOINT = 0,
58 ISOCHRONOUS_ENDPOINT,
59 BULK_ENDPOINT,
60 INTERRUPT_ENDPOINT
61 };
62
63 #define AUDIO_CLASS 0x01
64 #define CDC_CLASS 0x02
65 #define HID_CLASS 0x03
66 #define MSD_CLASS 0x08
67 #define HUB_CLASS 0x09
68 #define SERIAL_CLASS 0x0A
69
70 // ------------------ HcControl Register ---------------------
71 #define OR_CONTROL_PLE 0x00000004
72 #define OR_CONTROL_CLE 0x00000010
73 #define OR_CONTROL_BLE 0x00000020
74 #define OR_CONTROL_HCFS 0x000000C0
75 #define OR_CONTROL_HC_OPER 0x00000080
76 // ----------------- HcCommandStatus Register -----------------
77 #define OR_CMD_STATUS_HCR 0x00000001
78 #define OR_CMD_STATUS_CLF 0x00000002
79 #define OR_CMD_STATUS_BLF 0x00000004
80 // --------------- HcInterruptStatus Register -----------------
81 #define OR_INTR_STATUS_WDH 0x00000002
82 #define OR_INTR_STATUS_RHSC 0x00000040
83 #define OR_INTR_STATUS_UE 0x00000010
84 // --------------- HcInterruptEnable Register -----------------
85 #define OR_INTR_ENABLE_WDH 0x00000002
86 #define OR_INTR_ENABLE_RHSC 0x00000040
87 #define OR_INTR_ENABLE_MIE 0x80000000
88 // ---------------- HcRhDescriptorA Register ------------------
89 #define OR_RH_STATUS_LPSC 0x00010000
90 #define OR_RH_STATUS_DRWE 0x00008000
91 // -------------- HcRhPortStatus[1:NDP] Register --------------
92 #define OR_RH_PORT_CCS 0x00000001
93 #define OR_RH_PORT_PRS 0x00000010
94 #define OR_RH_PORT_CSC 0x00010000
95 #define OR_RH_PORT_PRSC 0x00100000
96 #define OR_RH_PORT_LSDA 0x00000200
97
98 #define FI 0x2EDF // 12000 bits per frame (-1)
99 #define DEFAULT_FMINTERVAL ((((6 * (FI - 210)) / 7) << 16) | FI)
100
101 #define ED_SKIP (uint32_t) (0x00001000) // Skip this ep in queue
102
103 #define TD_ROUNDING (uint32_t) (0x00040000) // Buffer Rounding
104 #define TD_SETUP (uint32_t)(0) // Direction of Setup Packet
105 #define TD_IN (uint32_t)(0x00100000) // Direction In
106 #define TD_OUT (uint32_t)(0x00080000) // Direction Out
107 #define TD_DELAY_INT(x) (uint32_t)((x) << 21) // Delay Interrupt
108 #define TD_TOGGLE_0 (uint32_t)(0x02000000) // Toggle 0
109 #define TD_TOGGLE_1 (uint32_t)(0x03000000) // Toggle 1
110 #define TD_CC (uint32_t)(0xF0000000) // Completion Code
111
112 #define DEVICE_DESCRIPTOR (1)
113 #define CONFIGURATION_DESCRIPTOR (2)
114 #define INTERFACE_DESCRIPTOR (4)
115 #define ENDPOINT_DESCRIPTOR (5)
116 #define HID_DESCRIPTOR (33)
117
118 // ----------- Control RequestType Fields -----------
119 #define USB_DEVICE_TO_HOST 0x80
120 #define USB_HOST_TO_DEVICE 0x00
121 #define USB_REQUEST_TYPE_CLASS 0x20
122 #define USB_REQUEST_TYPE_STANDARD 0x00
123 #define USB_RECIPIENT_DEVICE 0x00
124 #define USB_RECIPIENT_INTERFACE 0x01
125 #define USB_RECIPIENT_ENDPOINT 0x02
126
127 // -------------- USB Standard Requests --------------
128 #define SET_ADDRESS 0x05
129 #define GET_DESCRIPTOR 0x06
130 #define SET_CONFIGURATION 0x09
131 #define SET_INTERFACE 0x0b
132 #define CLEAR_FEATURE 0x01
133
134 // -------------- USB Descriptor Length --------------
135 #define DEVICE_DESCRIPTOR_LENGTH 0x12
136 #define CONFIGURATION_DESCRIPTOR_LENGTH 0x09
137
138 // ------------ HostController Transfer Descriptor ------------
139 typedef struct HCTD {
140 __IO uint32_t control; // Transfer descriptor control
141 __IO uint8_t * currBufPtr; // Physical address of current buffer pointer
142 __IO HCTD * nextTD; // Physical pointer to next Transfer Descriptor
143 __IO uint8_t * bufEnd; // Physical address of end of buffer
144 void * ep; // ep address where a td is linked in
145 uint32_t dummy[3]; // padding
146 } PACKED HCTD;
147
148 // ----------- HostController EndPoint Descriptor -------------
149 typedef struct hcEd {
150 __IO uint32_t control; // Endpoint descriptor control
151 __IO HCTD * tailTD; // Physical address of tail in Transfer descriptor list
152 __IO HCTD * headTD; // Physcial address of head in Transfer descriptor list
153 __IO hcEd * nextED; // Physical address of next Endpoint descriptor
154 } PACKED HCED;
155
156
157 // ----------- Host Controller Communication Area ------------
158 typedef struct hcca {
159 __IO uint32_t IntTable[32]; // Interrupt Table
160 __IO uint32_t FrameNumber; // Frame Number
161 __IO uint32_t DoneHead; // Done Head
162 volatile uint8_t Reserved[116]; // Reserved for future use
163 volatile uint8_t Unknown[4]; // Unused
164 } PACKED HCCA;
165
166 typedef struct {
167 uint8_t bLength;
168 uint8_t bDescriptorType;
169 uint16_t bcdUSB;
170 uint8_t bDeviceClass;
171 uint8_t bDeviceSubClass;
172 uint8_t bDeviceProtocol;
173 uint8_t bMaxPacketSize;
174 uint16_t idVendor;
175 uint16_t idProduct;
176 uint16_t bcdDevice;
177 uint8_t iManufacturer;
178 uint8_t iProduct;
179 uint8_t iSerialNumber;
180 uint8_t bNumConfigurations;
181 } PACKED DeviceDescriptor;
182
183 typedef struct {
184 uint8_t bLength;
185 uint8_t bDescriptorType;
186 uint16_t wTotalLength;
187 uint8_t bNumInterfaces;
188 uint8_t bConfigurationValue;
189 uint8_t iConfiguration;
190 uint8_t bmAttributes;
191 uint8_t bMaxPower;
192 } PACKED ConfigurationDescriptor;
193
194 typedef struct {
195 uint8_t bLength;
196 uint8_t bDescriptorType;
197 uint8_t bInterfaceNumber;
198 uint8_t bAlternateSetting;
199 uint8_t bNumEndpoints;
200 uint8_t bInterfaceClass;
201 uint8_t bInterfaceSubClass;
202 uint8_t bInterfaceProtocol;
203 uint8_t iInterface;
204 } InterfaceDescriptor;
205
206 typedef struct {
207 uint8_t bLength;
208 uint8_t bDescriptorType;
209 uint8_t bEndpointAddress;
210 uint8_t bmAttributes;
211 uint16_t wMaxPacketSize;
212 uint8_t bInterval;
213 } EndpointDescriptor;
214
215 typedef struct {
216 uint8_t bDescLength;
217 uint8_t bDescriptorType;
218 uint8_t bNbrPorts;
219 uint16_t wHubCharacteristics;
220 uint8_t bPwrOn2PwrGood;
221 uint8_t bHubContrCurrent;
222 uint8_t DeviceRemovable;
223 uint8_t PortPweCtrlMak;
224 } HubDescriptor;
225
226 #endif
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