tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K20XX/TARGET_K20D50M/system_MK20D5.c

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           ARM Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          IAR ANSI C/C++ Compiler for ARM
   7 **
   8 **     Reference manuals:   K20P64M50SF0RM Rev. 1, Oct 2011
   9 **                          K20P32M50SF0RM Rev. 1, Oct 2011
  10 **                          K20P48M50SF0RM Rev. 1, Oct 2011
  11 **
  12 **     Version:             rev. 1.0, 2011-12-15
  13 **
  14 **     Abstract:
  15 **         Provides a system configuration function and a global variable that
  16 **         contains the system frequency. It configures the device and initializes
  17 **         the oscillator (PLL) that is part of the microcontroller device.
  18 **
  19 **     Copyright: 2015 Freescale Semiconductor, Inc. All Rights Reserved.
  20 **
  21 **     http:                 www.freescale.com
  22 **     mail:                 support@freescale.com
  23 **
  24 **     Revisions:
  25 **     - rev. 1.0 (2011-12-15)
  26 **         Initial version
  27 **
  28 ** ###################################################################
  29 */
  30
  31 /**
  32  * @file MK20D5
  33  * @version 1.0
  34  * @date 2011-12-15
  35  * @brief Device specific configuration file for MK20D5 (implementation file)
  36  *
  37  * Provides a system configuration function and a global variable that contains
  38  * the system frequency. It configures the device and initializes the oscillator
  39  * (PLL) that is part of the microcontroller device.
  40  */
  41
  42 #include <stdint.h>
  43 #include "MK20D5.h"
  44
  45 #define DISABLE_WDOG    1
  46
  47 #define CLOCK_SETUP     1
  48 /* Predefined clock setups
  49    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
  50          Reference clock source for MCG module is the slow internal clock source 32.768kHz
  51          Core clock = 41.94MHz, BusClock = 41.94MHz
  52    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
  53          Reference clock source for MCG module is an external crystal 8MHz
  54          Core clock = 48MHz, BusClock = 48MHz
  55    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
  56          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
  57          Core clock = 8MHz, BusClock = 8MHz
  58 */
  59
  60 /*----------------------------------------------------------------------------
  61   Define clock source values
  62  *----------------------------------------------------------------------------*/
  63 #if (CLOCK_SETUP == 0)
  64     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  65     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  66     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  67     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  68     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
  69 #elif (CLOCK_SETUP == 1)
  70     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  71     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  72     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  73     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  74     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
  75 #elif (CLOCK_SETUP == 2)
  76     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  77     #define CPU_XTAL32k_CLK_HZ              32768u   /* Value of the external 32k crystal or oscillator clock frequency in Hz */
  78     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  79     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  80     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
  81 #endif /* (CLOCK_SETUP == 2) */
  82
  83
  84 /* ----------------------------------------------------------------------------
  85    -- Core clock
  86    ---------------------------------------------------------------------------- */
  87
  88 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  89
  90 /* ----------------------------------------------------------------------------
  91    -- SystemInit()
  92    ---------------------------------------------------------------------------- */
  93
  94 void SystemInit (void) {
  95 #if (DISABLE_WDOG)
  96   /* Disable the WDOG module */
  97   /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
  98   WDOG->UNLOCK = (uint16_t)0xC520u;     /* Key 1 */
  99   /* WDOG_UNLOCK : WDOGUNLOCK=0xD928 */
 100   WDOG->UNLOCK  = (uint16_t)0xD928u;    /* Key 2 */
 101   /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,STNDBYEN=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
 102   WDOG->STCTRLH = (uint16_t)0x01D2u;
 103 #endif /* (DISABLE_WDOG) */
 104 #if (CLOCK_SETUP == 0)
 105   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 106   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 107   /* Switch to FEI Mode */
 108   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 109   MCG->C1 = (uint8_t)0x06u;
 110   /* MCG->C2: ??=0,??=0,RANGE0=0,HGO=0,EREFS=0,LP=0,IRCS=0 */
 111   MCG->C2 = (uint8_t)0x00u;
 112   /* MCG_C4: DMX32=0,DRST_DRS=1 */
 113   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0u) | (uint8_t)0x20u);
 114   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
 115   MCG->C5 = (uint8_t)0x00u;
 116   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 117   MCG->C6 = (uint8_t)0x00u;
 118   while((MCG->S & MCG_S_IREFST_MASK) == 0u) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 119   }
 120   while((MCG->S & 0x0Cu) != 0x00u) {    /* Wait until output of the FLL is selected */
 121   }
 122 #elif (CLOCK_SETUP == 1)
 123   /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 124   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 125   /* Switch to FBE Mode */
 126   /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 127   OSC0->CR = (uint8_t)0x00u;
 128   /* MCG->C7: OSCSEL=0 */
 129   MCG->C7 = (uint8_t)0x00u;
 130   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 131   MCG->C2 = (uint8_t)0x24u;
 132   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 133   MCG->C1 = (uint8_t)0x9Au;
 134   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 135   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
 136   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
 137   MCG->C5 = (uint8_t)0x03u;
 138   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 139   MCG->C6 = (uint8_t)0x00u;
 140   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
 141   }
 142 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
 143   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
 144   }
 145 #endif
 146   while((MCG->S & 0x0Cu) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
 147   }
 148   /* Switch to PBE Mode */
 149   /* MCG_C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=3 */
 150   MCG->C5 = (uint8_t)0x03u;
 151   /* MCG->C6: LOLIE=0,PLLS=1,CME=0,VDIV0=0 */
 152   MCG->C6 = (uint8_t)0x40u;
 153   while((MCG->S & MCG_S_PLLST_MASK) == 0u) { /* Wait until the source of the PLLS clock has switched to the PLL */
 154   }
 155   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
 156   }
 157   /* Switch to PEE Mode */
 158   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 159   MCG->C1 = (uint8_t)0x1Au;
 160   while((MCG->S & 0x0Cu) != 0x0Cu) {    /* Wait until output of the PLL is selected */
 161   }
 162   while((MCG->S & MCG_S_LOCK0_MASK) == 0u) { /* Wait until locked */
 163   }
 164 #elif (CLOCK_SETUP == 2)
 165   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 166   SIM->CLKDIV1 = (uint32_t)0x00110000u; /* Update system prescalers */
 167   /* Switch to FBE Mode */
 168   /* OSC0->CR: ERCLKEN=0,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 169   OSC0->CR = (uint8_t)0x00u;
 170   /* MCG->C7: OSCSEL=0 */
 171   MCG->C7 = (uint8_t)0x00u;
 172   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 173   MCG->C2 = (uint8_t)0x24u;
 174   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 175   MCG->C1 = (uint8_t)0x9Au;
 176   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 177   MCG->C4 &= (uint8_t)~(uint8_t)0xE0u;
 178   /* MCG->C5: ??=0,PLLCLKEN=0,PLLSTEN=0,PRDIV0=0 */
 179   MCG->C5 = (uint8_t)0x00u;
 180   /* MCG->C6: LOLIE=0,PLLS=0,CME=0,VDIV0=0 */
 181   MCG->C6 = (uint8_t)0x00u;
 182   while((MCG->S & MCG_S_OSCINIT0_MASK) == 0u) { /* Check that the oscillator is running */
 183   }
 184 #if 0 /* ARM: THIS CHECK IS REMOVED DUE TO BUG WITH SLOW IRC IN REV. 1.0 */
 185   while((MCG->S & MCG_S_IREFST_MASK) != 0u) { /* Check that the source of the FLL reference clock is the external reference clock. */
 186   }
 187 #endif
 188   while((MCG->S & 0x0CU) != 0x08u) {    /* Wait until external reference clock is selected as MCG output */
 189   }
 190   /* Switch to BLPE Mode */
 191   /* MCG->C2: ??=0,??=0,RANGE0=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 192   MCG->C2 = (uint8_t)0x24u;
 193 #endif /* (CLOCK_SETUP == 2) */
 194 }
 195
 196 /* ----------------------------------------------------------------------------
 197    -- SystemCoreClockUpdate()
 198    ---------------------------------------------------------------------------- */
 199
 200 void SystemCoreClockUpdate (void) {
 201   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
 202   uint8_t Divider;
 203
 204   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
 205     /* Output of FLL or PLL is selected */
 206     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
 207       /* FLL is selected */
 208       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
 209         /* External reference clock is selected */
 210         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
 211           MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
 212         } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 213           MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                    /* RTC 32 kHz oscillator drives MCG clock */
 214         } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 215         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 216         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
 217         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
 218           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
 219         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
 220       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 221         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
 222       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 223       /* Select correct multiplier to calculate the MCG output clock  */
 224       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 225         case 0x0u:
 226           MCGOUTClock *= 640u;
 227           break;
 228         case 0x20u:
 229           MCGOUTClock *= 1280u;
 230           break;
 231         case 0x40u:
 232           MCGOUTClock *= 1920u;
 233           break;
 234         case 0x60u:
 235           MCGOUTClock *= 2560u;
 236           break;
 237         case 0x80u:
 238           MCGOUTClock *= 732u;
 239           break;
 240         case 0xA0u:
 241           MCGOUTClock *= 1464u;
 242           break;
 243         case 0xC0u:
 244           MCGOUTClock *= 2197u;
 245           break;
 246         case 0xE0u:
 247           MCGOUTClock *= 2929u;
 248           break;
 249         default:
 250           break;
 251       }
 252     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 253       /* PLL is selected */
 254       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
 255       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
 256       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
 257       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
 258     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 259   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
 260     /* Internal reference clock is selected */
 261     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
 262       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
 263     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 264       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
 265     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 266   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
 267     /* External reference clock is selected */
 268     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u) {
 269       MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
 270     } else { /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 271       MCGOUTClock = CPU_XTAL32k_CLK_HZ;                                        /* RTC 32 kHz oscillator drives MCG clock */
 272     } /* (!((MCG->C7 & MCG_C7_OSCSEL_MASK) == 0x0u)) */
 273   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 274     /* Reserved value */
 275     return;
 276   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 277   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 278 }