tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.c

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          GNU C Compiler - CodeSourcery Sourcery G++
   7 **                          IAR ANSI C/C++ Compiler for ARM
   8 **
   9 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
  10 **     Version:             rev. 2.5, 2014-05-06
  11 **     Build:               b140611
  12 **
  13 **     Abstract:
  14 **         Provides a system configuration function and a global variable that
  15 **         contains the system frequency. It configures the device and initializes
  16 **         the oscillator (PLL) that is part of the microcontroller device.
  17 **
  18 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  19 **     All rights reserved.
  20 **
  21 **     Redistribution and use in source and binary forms, with or without modification,
  22 **     are permitted provided that the following conditions are met:
  23 **
  24 **     o Redistributions of source code must retain the above copyright notice, this list
  25 **       of conditions and the following disclaimer.
  26 **
  27 **     o Redistributions in binary form must reproduce the above copyright notice, this
  28 **       list of conditions and the following disclaimer in the documentation and/or
  29 **       other materials provided with the distribution.
  30 **
  31 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  32 **       contributors may be used to endorse or promote products derived from this
  33 **       software without specific prior written permission.
  34 **
  35 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  36 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  37 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  38 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  39 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  41 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  42 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  44 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45 **
  46 **     http:                 www.freescale.com
  47 **     mail:                 support@freescale.com
  48 **
  49 **     Revisions:
  50 **     - rev. 1.0 (2013-07-23)
  51 **         Initial version.
  52 **     - rev. 1.1 (2013-09-17)
  53 **         RM rev. 0.4 update.
  54 **     - rev. 2.0 (2013-10-29)
  55 **         Register accessor macros added to the memory map.
  56 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  57 **         Startup file for gcc has been updated according to CMSIS 3.2.
  58 **         System initialization updated.
  59 **     - rev. 2.1 (2013-10-30)
  60 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  61 **     - rev. 2.2 (2013-12-20)
  62 **         Update according to reference manual rev. 0.6,
  63 **     - rev. 2.3 (2014-01-13)
  64 **         Update according to reference manual rev. 0.61,
  65 **     - rev. 2.4 (2014-02-10)
  66 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  67 **     - rev. 2.5 (2014-05-06)
  68 **         Update according to reference manual rev. 1.0,
  69 **         Update of system and startup files.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*!
  76  * @file MK22F51212
  77  * @version 2.5
  78  * @date 2014-05-06
  79  * @brief Device specific configuration file for MK22F51212 (implementation file)
  80  *
  81  * Provides a system configuration function and a global variable that contains
  82  * the system frequency. It configures the device and initializes the oscillator
  83  * (PLL) that is part of the microcontroller device.
  84  */
  85
  86 #include <stdint.h>
  87 #include "cmsis.h"
  88
  89
  90
  91 /* ----------------------------------------------------------------------------
  92    -- Core clock
  93    ---------------------------------------------------------------------------- */
  94
  95 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  96
  97 /* ----------------------------------------------------------------------------
  98    -- SystemInit()
  99    ---------------------------------------------------------------------------- */
 100
 101 void SystemInit (void) {
 102 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
 103   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
 104 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
 105
 106 #if (DISABLE_WDOG)
 107   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
 108   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
 109   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
 110   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
 111   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
 112   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
 113                  WDOG_STCTRLH_WAITEN_MASK |
 114                  WDOG_STCTRLH_STOPEN_MASK |
 115                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
 116                  WDOG_STCTRLH_CLKSRC_MASK |
 117                  0x0100U;
 118 #endif /* (DISABLE_WDOG) */
 119   if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
 120   {
 121     if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
 122     {
 123        PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
 124     }
 125   } else {
 126 #ifdef SYSTEM_RTC_CR_VALUE
 127     SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
 128     if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
 129       RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
 130       RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
 131       RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
 132     }
 133 #endif
 134   }
 135
 136   /* Power mode protection initialization */
 137 #ifdef SYSTEM_SMC_PMPROT_VALUE
 138   SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
 139 #endif
 140
 141   /* High speed run mode enable */
 142 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x03U << SMC_PMCTRL_RUNM_SHIFT))
 143   SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable HSRUN mode */
 144   while(SMC->PMSTAT != 0x80U) {        /* Wait until the system is in HSRUN mode */
 145   }
 146 #endif
 147   /* System clock initialization */
 148   /* Internal reference clock trim initialization */
 149 #if defined(SLOW_TRIM_ADDRESS)
 150   if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
 151     MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
 152   #endif /* defined(SLOW_TRIM_ADDRESS) */
 153   #if defined(SLOW_FINE_TRIM_ADDRESS)
 154     MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
 155   #endif
 156   #if defined(FAST_TRIM_ADDRESS)
 157     MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
 158   #endif
 159   #if defined(FAST_FINE_TRIM_ADDRESS)
 160     MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
 161   #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
 162 #if defined(SLOW_TRIM_ADDRESS)
 163   }
 164   #endif /* defined(SLOW_TRIM_ADDRESS) */
 165
 166   /* Set system prescalers and clock sources */
 167   SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
 168   SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
 169   SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
 170 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 171   /* Set MCG and OSC */
 172 #if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
 173   /* SIM_SCGC5: PORTA=1 */
 174   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 175   /* PORTA_PCR18: ISF=0,MUX=0 */
 176   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 177   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
 178   /* PORTA_PCR19: ISF=0,MUX=0 */
 179   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 180   }
 181 #endif
 182   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
 183   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
 184   /* Check that the source of the FLL reference clock is the requested one. */
 185   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 186     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
 187     }
 188   } else {
 189     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 190     }
 191   }
 192   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
 193   MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
 194   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
 195   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
 196   #if (MCG_MODE == MCG_MODE_BLPI)
 197   /* BLPI specific */
 198   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 199   #endif
 200
 201 #else /* MCG_MODE */
 202   /* Set MCG and OSC */
 203 #if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
 204   /* SIM_SCGC5: PORTA=1 */
 205   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 206   /* PORTA_PCR18: ISF=0,MUX=0 */
 207   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 208   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
 209   /* PORTA_PCR19: ISF=0,MUX=0 */
 210   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 211   }
 212 #endif
 213   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
 214   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
 215   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
 216   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
 217   #if (MCG_MODE == MCG_MODE_PEE)
 218   MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
 219   #else
 220   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
 221   #endif
 222   if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
 223     while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
 224     }
 225   }
 226   /* Check that the source of the FLL reference clock is the requested one. */
 227   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 228     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
 229     }
 230   } else {
 231     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 232     }
 233   }
 234   MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
 235 #endif /* MCG_MODE */
 236
 237   /* Common for all MCG modes */
 238
 239   /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
 240   MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
 241   MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
 242   if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
 243     MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
 244   }
 245   /* BLPE, PEE and PBE MCG mode specific */
 246
 247 #if (MCG_MODE == MCG_MODE_BLPE)
 248   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 249 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
 250   MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
 251   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
 252   }
 253   #if (MCG_MODE == MCG_MODE_PEE)
 254   MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
 255   #endif
 256 #endif
 257 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
 258   while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
 259   }
 260 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 261   while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
 262   }
 263 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
 264   while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
 265   }
 266 #elif (MCG_MODE == MCG_MODE_PEE)
 267   while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
 268   }
 269 #endif
 270 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
 271   SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
 272   while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
 273   }
 274 #endif
 275
 276 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
 277   SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
 278 #endif
 279
 280   /* PLL loss of lock interrupt request initialization */
 281   if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
 282     NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
 283   }
 284 }
 285
 286 /* ----------------------------------------------------------------------------
 287    -- SystemCoreClockUpdate()
 288    ---------------------------------------------------------------------------- */
 289
 290 void SystemCoreClockUpdate (void) {
 291
 292   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
 293   uint16_t Divider;
 294
 295   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
 296     /* Output of FLL or PLL is selected */
 297     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
 298       /* FLL is selected */
 299       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
 300         /* External reference clock is selected */
 301         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
 302         case 0x00U:
 303           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
 304           break;
 305         case 0x01U:
 306           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 307           break;
 308         case 0x02U:
 309         default:
 310           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
 311           break;
 312         }
 313         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
 314           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
 315           case 0x38U:
 316             Divider = 1536U;
 317             break;
 318           case 0x30U:
 319             Divider = 1280U;
 320             break;
 321           default:
 322             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 323             break;
 324           }
 325         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
 326           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 327         }
 328         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
 329       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 330         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
 331       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 332       /* Select correct multiplier to calculate the MCG output clock  */
 333       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 334         case 0x00U:
 335           MCGOUTClock *= 640U;
 336           break;
 337         case 0x20U:
 338           MCGOUTClock *= 1280U;
 339           break;
 340         case 0x40U:
 341           MCGOUTClock *= 1920U;
 342           break;
 343         case 0x60U:
 344           MCGOUTClock *= 2560U;
 345           break;
 346         case 0x80U:
 347           MCGOUTClock *= 732U;
 348           break;
 349         case 0xA0U:
 350           MCGOUTClock *= 1464U;
 351           break;
 352         case 0xC0U:
 353           MCGOUTClock *= 2197U;
 354           break;
 355         case 0xE0U:
 356           MCGOUTClock *= 2929U;
 357           break;
 358         default:
 359           break;
 360       }
 361     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 362       /* PLL is selected */
 363       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
 364       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
 365       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
 366       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
 367     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 368   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
 369     /* Internal reference clock is selected */
 370     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
 371       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
 372     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 373       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
 374       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
 375     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 376   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
 377     /* External reference clock is selected */
 378     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
 379     case 0x00U:
 380       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
 381       break;
 382     case 0x01U:
 383       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 384       break;
 385     case 0x02U:
 386     default:
 387       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
 388       break;
 389     }
 390   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 391     /* Reserved value */
 392     return;
 393   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 394   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 395 }