tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_K22F/system_MK22F51212.h

   1 /*
   2 ** ###################################################################
   3 **     Compilers:           Keil ARM C/C++ Compiler
   4 **                          Freescale C/C++ for Embedded ARM
   5 **                          GNU C Compiler
   6 **                          GNU C Compiler - CodeSourcery Sourcery G++
   7 **                          IAR ANSI C/C++ Compiler for ARM
   8 **
   9 **     Reference manual:    K22P121M120SF7RM, Rev. 1, March 24, 2014
  10 **     Version:             rev. 2.5, 2014-05-06
  11 **     Build:               b140611
  12 **
  13 **     Abstract:
  14 **         Provides a system configuration function and a global variable that
  15 **         contains the system frequency. It configures the device and initializes
  16 **         the oscillator (PLL) that is part of the microcontroller device.
  17 **
  18 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  19 **     All rights reserved.
  20 **
  21 **     Redistribution and use in source and binary forms, with or without modification,
  22 **     are permitted provided that the following conditions are met:
  23 **
  24 **     o Redistributions of source code must retain the above copyright notice, this list
  25 **       of conditions and the following disclaimer.
  26 **
  27 **     o Redistributions in binary form must reproduce the above copyright notice, this
  28 **       list of conditions and the following disclaimer in the documentation and/or
  29 **       other materials provided with the distribution.
  30 **
  31 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  32 **       contributors may be used to endorse or promote products derived from this
  33 **       software without specific prior written permission.
  34 **
  35 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  36 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  37 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  38 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  39 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  41 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  42 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  43 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  44 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  45 **
  46 **     http:                 www.freescale.com
  47 **     mail:                 support@freescale.com
  48 **
  49 **     Revisions:
  50 **     - rev. 1.0 (2013-07-23)
  51 **         Initial version.
  52 **     - rev. 1.1 (2013-09-17)
  53 **         RM rev. 0.4 update.
  54 **     - rev. 2.0 (2013-10-29)
  55 **         Register accessor macros added to the memory map.
  56 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  57 **         Startup file for gcc has been updated according to CMSIS 3.2.
  58 **         System initialization updated.
  59 **     - rev. 2.1 (2013-10-30)
  60 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  61 **     - rev. 2.2 (2013-12-20)
  62 **         Update according to reference manual rev. 0.6,
  63 **     - rev. 2.3 (2014-01-13)
  64 **         Update according to reference manual rev. 0.61,
  65 **     - rev. 2.4 (2014-02-10)
  66 **         The declaration of clock configurations has been moved to separate header file system_MK22F51212.h
  67 **     - rev. 2.5 (2014-05-06)
  68 **         Update according to reference manual rev. 1.0,
  69 **         Update of system and startup files.
  70 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  71 **
  72 ** ###################################################################
  73 */
  74
  75 /*!
  76  * @file MK22F51212
  77  * @version 2.5
  78  * @date 2014-05-06
  79  * @brief Device specific configuration file for MK22F51212 (header file)
  80  *
  81  * Provides a system configuration function and a global variable that contains
  82  * the system frequency. It configures the device and initializes the oscillator
  83  * (PLL) that is part of the microcontroller device.
  84  */
  85
  86 #ifndef SYSTEM_MK22F51212_H_
  87 #define SYSTEM_MK22F51212_H_                     /**< Symbol preventing repeated inclusion */
  88
  89 #ifdef __cplusplus
  90 extern "C" {
  91 #endif
  92
  93 #include <stdint.h>
  94
  95
  96 #define DISABLE_WDOG                   1
  97
  98 #ifndef CLOCK_SETUP
  99   #define CLOCK_SETUP                  4
 100 #endif
 101
 102 /* MCG mode constants */
 103
 104 #define MCG_MODE_FEI                   0U
 105 #define MCG_MODE_FBI                   1U
 106 #define MCG_MODE_BLPI                  2U
 107 #define MCG_MODE_FEE                   3U
 108 #define MCG_MODE_FBE                   4U
 109 #define MCG_MODE_BLPE                  5U
 110 #define MCG_MODE_PBE                   6U
 111 #define MCG_MODE_PEE                   7U
 112
 113 /* Predefined clock setups
 114    0 ... Default  part configuration
 115          Multipurpose Clock Generator (MCG) in FEI mode.
 116          Reference clock source for MCG module: Slow internal reference clock
 117          Core clock = 20.97152MHz
 118          Bus clock  = 20.97152MHz
 119    1 ... Maximum achievable clock frequency configuration
 120          Multipurpose Clock Generator (MCG) in PEE mode.
 121          Reference clock source for MCG module: System oscillator 0 reference clock
 122          Core clock = 120MHz
 123          Bus clock  = 60MHz
 124    2 ... Chip internaly clocked, ready for Very Low Power Run mode.
 125          Multipurpose Clock Generator (MCG) in BLPI mode.
 126          Reference clock source for MCG module: Fast internal reference clock
 127          Core clock = 4MHz
 128          Bus clock  = 4MHz
 129    3 ... Chip externally clocked, ready for Very Low Power Run mode.
 130          Multipurpose Clock Generator (MCG) in BLPE mode.
 131          Reference clock source for MCG module: System oscillator 0 reference clock
 132          Core clock = 4MHz
 133          Bus clock  = 4MHz
 134    4 ... USB clock setup
 135          Multipurpose Clock Generator (MCG) in PEE mode.
 136          Reference clock source for MCG module: System oscillator 0 reference clock
 137          Core clock = 120MHz
 138          Bus clock  = 60MHz
 139    5 ... Maximum achievable clock frequency configuration in RUN mode
 140          Multipurpose Clock Generator (MCG) in PEE mode.
 141          Reference clock source for MCG module: System oscillator 0 reference clock
 142          Core clock = 80MHz
 143          Bus clock  = 40MHz
 144  */
 145
 146 /* Define clock source values */
 147
 148 #define CPU_XTAL_CLK_HZ                8000000u            /* Value of the external crystal or oscillator clock frequency in Hz */
 149 #define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
 150 #define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
 151 #define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
 152 #define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
 153
 154 /* RTC oscillator setting */
 155 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
 156 #define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
 157
 158 /* Low power mode enable */
 159 /* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
 160 #define SYSTEM_SMC_PMPROT_VALUE        0xAAU               /* SMC_PMPROT */
 161
 162 /* Internal reference clock trim */
 163 /* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
 164 /* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
 165 /* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
 166 /* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
 167
 168 #if (CLOCK_SETUP == 0)
 169   #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
 170   #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
 171   /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 172   #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
 173   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 174   #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */
 175   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 176   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 177   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 178   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 179 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 180   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 181 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 182   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 183 /* MCG_C7: OSCSEL=0 */
 184   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 185 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 186   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
 187 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 188   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 189 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
 190   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
 191 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 192   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 193 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 194   #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
 195 #elif (CLOCK_SETUP == 1)
 196   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
 197   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
 198   /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 199   #define SYSTEM_MCG_C1_VALUE          0x1AU               /* MCG_C1 */
 200   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 201   #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */
 202   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 203   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 204   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 205   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 206 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
 207   #define SYSTEM_MCG_C5_VALUE          0x01U               /* MCG_C5 */
 208 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
 209   #define SYSTEM_MCG_C6_VALUE          0x46U               /* MCG_C6 */
 210 /* MCG_C7: OSCSEL=0 */
 211   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 212 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 213   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 214 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
 215   #define SYSTEM_SMC_PMCTRL_VALUE      0x60U               /* SMC_PMCTRL */
 216 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
 217   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
 218 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 219   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 220 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 221   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 222 #elif (CLOCK_SETUP == 2)
 223   #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
 224   #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
 225   /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 226   #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
 227   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
 228   #define SYSTEM_MCG_C2_VALUE          0x27U               /* MCG_C2 */
 229   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 230   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 231   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 232   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 233 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 234   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 235 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 236   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 237 /* MCG_C7: OSCSEL=0 */
 238   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 239 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 240   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 241 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 242   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 243 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
 244   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
 245 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 246   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 247 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 248   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
 249 #elif (CLOCK_SETUP == 3)
 250   #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
 251   #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
 252   /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 253   #define SYSTEM_MCG_C1_VALUE          0x9AU               /* MCG_C1 */
 254   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=1,IRCS=1 */
 255   #define SYSTEM_MCG_C2_VALUE          0x27U               /* MCG_C2 */
 256   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 257   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 258   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
 259   #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
 260 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 261   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 262 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 263   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 264 /* MCG_C7: OSCSEL=0 */
 265   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 266 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 267   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
 268 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 269   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 270 /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV2=1,OUTDIV3=1,OUTDIV4=7 */
 271   #define SYSTEM_SIM_CLKDIV1_VALUE     0x11170000U         /* SIM_CLKDIV1 */
 272 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 273   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 274 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 275   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
 276 #elif (CLOCK_SETUP == 4)
 277   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
 278   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
 279   /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 280   #define SYSTEM_MCG_C1_VALUE          0x1AU               /* MCG_C1 */
 281   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 282   #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */
 283   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 284   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 285   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 286   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 287 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
 288   #define SYSTEM_MCG_C5_VALUE          0x01U               /* MCG_C5 */
 289 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
 290   #define SYSTEM_MCG_C6_VALUE          0x46U               /* MCG_C6 */
 291 /* MCG_C7: OSCSEL=0 */
 292   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 293 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 294   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 295 /* SMC_PMCTRL: RUNM=3,STOPA=0,STOPM=0 */
 296   #define SYSTEM_SMC_PMCTRL_VALUE      0x60U               /* SMC_PMCTRL */
 297 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
 298   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
 299 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
 300   #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
 301 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 302   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 303 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 304   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 305 #elif (CLOCK_SETUP == 5)
 306   #define DEFAULT_SYSTEM_CLOCK         80000000u           /* Default System clock value */
 307   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
 308   /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 309   #define SYSTEM_MCG_C1_VALUE          0x1AU               /* MCG_C1 */
 310   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=1,LP=0,IRCS=0 */
 311   #define SYSTEM_MCG_C2_VALUE          0x24U               /* MCG_C2 */
 312   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 313   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 314   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 315   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 316 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=3 */
 317   #define SYSTEM_MCG_C5_VALUE          0x03U               /* MCG_C5 */
 318 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x10 */
 319   #define SYSTEM_MCG_C6_VALUE          0x50U               /* MCG_C6 */
 320 /* MCG_C7: OSCSEL=0 */
 321   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 322 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 323   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 324 /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 325   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 326 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=3 */
 327   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01130000U         /* SIM_CLKDIV1 */
 328 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,OSC32KOUT=0,RAMSIZE=0 */
 329   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 330 /* SIM_SOPT2: LPUARTSRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 331   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 332 #endif
 333
 334 /**
 335  * @brief System clock frequency (core clock)
 336  *
 337  * The system clock frequency supplied to the SysTick timer and the processor
 338  * core clock. This variable can be used by the user application to setup the
 339  * SysTick timer or configure other parameters. It may also be used by debugger to
 340  * query the frequency of the debug timer or configure the trace clock speed
 341  * SystemCoreClock is initialized with a correct predefined value.
 342  */
 343 extern uint32_t SystemCoreClock;
 344
 345 /**
 346  * @brief Setup the microcontroller system.
 347  *
 348  * Typically this function configures the oscillator (PLL) that is part of the
 349  * microcontroller device. For systems with variable clock speed it also updates
 350  * the variable SystemCoreClock. SystemInit is called from startup_device file.
 351  */
 352 void SystemInit (void);
 353
 354 /**
 355  * @brief Updates the SystemCoreClock variable.
 356  *
 357  * It must be called whenever the core clock is changed during program
 358  * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
 359  * the current core clock.
 360  */
 361 void SystemCoreClockUpdate (void);
 362
 363 #ifdef __cplusplus
 364 }
 365 #endif
 366
 367 #endif  /* #if !defined(SYSTEM_MK22F51212_H_) */