1 ;/*****************************************************************************
2 ; * @file: startup_MKL25Z4.s
3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
12 ; *****************************************************************************/
14 Stack_Size EQU 0x00000400
16 AREA STACK, NOINIT, READWRITE, ALIGN=3
19 Stack_Mem SPACE Stack_Size
20 __initial_sp EQU 0x20000C00 ; Top of RAM
23 Heap_Size EQU 0x00000000
25 AREA HEAP, NOINIT, READWRITE, ALIGN=3
30 Heap_Mem SPACE Heap_Size
37 ; Vector Table Mapped to Address 0 at Reset
39 AREA RESET, DATA, READONLY
44 __Vectors DCD __initial_sp ; Top of Stack
45 DCD Reset_Handler ; Reset Handler
46 DCD NMI_Handler ; NMI Handler
47 DCD HardFault_Handler ; Hard Fault Handler
55 DCD SVC_Handler ; SVCall Handler
58 DCD PendSV_Handler ; PendSV Handler
59 DCD SysTick_Handler ; SysTick Handler
62 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete/error interrupt
63 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete/error interrupt
64 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete/error interrupt
65 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete/error interrupt
66 DCD Reserved20_IRQHandler ; Reserved interrupt 20
67 DCD FTFA_IRQHandler ; FTFA command complete/read collision interrupt
68 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
69 DCD LLW_IRQHandler ; Low Leakage Wakeup
70 DCD I2C0_IRQHandler ; I2C0 interrupt
71 DCD Reserved_25_IRQHandler ; Reserved interrupt 25
72 DCD SPI0_IRQHandler ; SPI0 interrupt
73 DCD Reserved_27_IRQHandler ; Reserved interrupt 27
74 DCD UART0_IRQHandler ; UART0 status and error interrupt
75 DCD Reserved_29_IRQHandler ; Reserved interrupt 29
76 DCD Reserved_30_IRQHandler ; Reserved interrupt 30
77 DCD ADC0_IRQHandler ; ADC0 interrupt
78 DCD CMP0_IRQHandler ; CMP0 interrupt
79 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
80 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
81 DCD Reserved_35_IRQHandler ; Reserved interrupt 35
82 DCD RTC_IRQHandler ; RTC interrupt
83 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
84 DCD PIT_IRQHandler ; PIT timer channel 0 interrupt
85 DCD Reserved_39_IRQHandler ; Reserved interrupt 39
86 DCD Reserved_40_IRQHandler ; Reserved interrupt 40
87 DCD DAC0_IRQHandler ; DAC0 interrupt
88 DCD TSI0_IRQHandler ; TSI0 interrupt
89 DCD MCG_IRQHandler ; MCG interrupt
90 DCD LPTimer_IRQHandler ; LPTimer interrupt
91 DCD Reserved_45_IRQHandler ; Reserved interrupt 45
92 DCD PORTA_IRQHandler ; Port A interrupt
93 DCD PORTB_IRQHandler ; Port B interrupt
96 __Vectors_Size EQU __Vectors_End - __Vectors
98 ; <h> Flash Configuration
99 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
100 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
101 ; <h> Backdoor Comparison Key
102 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
103 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
104 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
105 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
106 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
107 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
108 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
109 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
119 ; <h> Program flash protection bytes (FPROT)
120 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
121 ; <i> Each bit protects a 1/32 region of the program flash memory.
123 ; <i> Program flash protection bytes
124 ; <i> 1/32 - 8/32 region
134 FPROT0 EQU nFPROT0:EOR:0xFF
137 ; <i> Program Flash Region Protect Register 1
138 ; <i> 9/32 - 16/32 region
148 FPROT1 EQU nFPROT1:EOR:0xFF
151 ; <i> Program Flash Region Protect Register 2
152 ; <i> 17/32 - 24/32 region
162 FPROT2 EQU nFPROT2:EOR:0xFF
165 ; <i> Program Flash Region Protect Register 3
166 ; <i> 25/32 - 32/32 region
176 FPROT3 EQU nFPROT3:EOR:0xFF
180 ; <h> Flash nonvolatile option byte (FOPT)
181 ; <i> Allows the user to customize the operation of the MCU at boot time.
183 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
184 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
186 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
187 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
189 ; <0=> NMI interrupts are always blocked
190 ; <1=> NMI pin/interrupts reset default to enabled
191 ; <o.3> RESET_PIN_CFG
192 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
193 ; <1=> RESET pin is dedicated
195 ; <0=> Slower initialization
196 ; <1=> Fast Initialization
199 ; <h> Flash security byte (FSEC)
200 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
201 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
203 ; <2=> MCU security status is unsecure
204 ; <3=> MCU security status is secure
206 ; <i> This bits define the security state of the MCU.
208 ; <2=> Freescale factory access denied
209 ; <3=> Freescale factory access granted
210 ; <i> Freescale Failure Analysis Access Code
211 ; <i> This bits define the security state of the MCU.
213 ; <2=> Mass erase is disabled
214 ; <3=> Mass erase is enabled
215 ; <i> Mass Erase Enable Bits
216 ; <i> Enables and disables mass erase capability of the FTFL module
218 ; <2=> Backdoor key access enabled
219 ; <3=> Backdoor key access disabled
220 ; <i> Backdoor key Security Enable
221 ; <i> These bits enable and disable backdoor key access to the FTFL module.
225 IF :LNOT::DEF:RAM_TARGET
226 AREA |.ARM.__at_0x400|, CODE, READONLY
227 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
228 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
229 DCB FPROT0, FPROT1, FPROT2, FPROT3
230 DCB FSEC, FOPT, 0xFF, 0xFF
233 AREA |.text|, CODE, READONLY
239 EXPORT Reset_Handler [WEAK]
249 ; Dummy Exception Handlers (infinite loops which can be modified)
252 EXPORT NMI_Handler [WEAK]
257 EXPORT HardFault_Handler [WEAK]
261 EXPORT SVC_Handler [WEAK]
265 EXPORT PendSV_Handler [WEAK]
269 EXPORT SysTick_Handler [WEAK]
274 EXPORT DMA0_IRQHandler [WEAK]
275 EXPORT DMA1_IRQHandler [WEAK]
276 EXPORT DMA2_IRQHandler [WEAK]
277 EXPORT DMA3_IRQHandler [WEAK]
278 EXPORT Reserved20_IRQHandler [WEAK]
279 EXPORT FTFA_IRQHandler [WEAK]
280 EXPORT LVD_LVW_IRQHandler [WEAK]
281 EXPORT LLW_IRQHandler [WEAK]
282 EXPORT I2C0_IRQHandler [WEAK]
283 EXPORT Reserved_25_IRQHandler [WEAK]
284 EXPORT SPI0_IRQHandler [WEAK]
285 EXPORT Reserved_27_IRQHandler [WEAK]
286 EXPORT UART0_IRQHandler [WEAK]
287 EXPORT Reserved_29_IRQHandler [WEAK]
288 EXPORT Reserved_30_IRQHandler [WEAK]
289 EXPORT ADC0_IRQHandler [WEAK]
290 EXPORT CMP0_IRQHandler [WEAK]
291 EXPORT TPM0_IRQHandler [WEAK]
292 EXPORT TPM1_IRQHandler [WEAK]
293 EXPORT Reserved_35_IRQHandler [WEAK]
294 EXPORT RTC_IRQHandler [WEAK]
295 EXPORT RTC_Seconds_IRQHandler [WEAK]
296 EXPORT PIT_IRQHandler [WEAK]
297 EXPORT Reserved_39_IRQHandler [WEAK]
298 EXPORT Reserved_40_IRQHandler [WEAK]
299 EXPORT DAC0_IRQHandler [WEAK]
300 EXPORT TSI0_IRQHandler [WEAK]
301 EXPORT MCG_IRQHandler [WEAK]
302 EXPORT LPTimer_IRQHandler [WEAK]
303 EXPORT Reserved_45_IRQHandler [WEAK]
304 EXPORT PORTA_IRQHandler [WEAK]
305 EXPORT PORTB_IRQHandler [WEAK]
306 EXPORT DefaultISR [WEAK]
312 Reserved20_IRQHandler
317 Reserved_25_IRQHandler
319 Reserved_27_IRQHandler
321 Reserved_29_IRQHandler
322 Reserved_30_IRQHandler
327 Reserved_35_IRQHandler
329 RTC_Seconds_IRQHandler
331 Reserved_39_IRQHandler
332 Reserved_40_IRQHandler
337 Reserved_45_IRQHandler