tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c

   1 /*
   2 ** ###################################################################
   3 **     Processors:          MKL05Z32FK4
   4 **                          MKL05Z32LC4
   5 **                          MKL05Z32VLF4
   6 **
   7 **     Compilers:           ARM Compiler
   8 **                          Freescale C/C++ for Embedded ARM
   9 **                          GNU C Compiler
  10 **                          IAR ANSI C/C++ Compiler for ARM
  11 **
  12 **     Reference manual:    KL05P48M48SF1RM, Rev.3, Sep 2012
  13 **     Version:             rev. 1.6, 2013-04-11
  14 **
  15 **     Abstract:
  16 **         Provides a system configuration function and a global variable that
  17 **         contains the system frequency. It configures the device and initializes
  18 **         the oscillator (PLL) that is part of the microcontroller device.
  19 **
  20 **     Copyright: 2013 Freescale, Inc. All Rights Reserved.
  21 **
  22 **     http:                 www.freescale.com
  23 **     mail:                 support@freescale.com
  24 **
  25 **     Revisions:
  26 **     - rev. 1.0 (2012-06-08)
  27 **         Initial version.
  28 **     - rev. 1.1 (2012-06-21)
  29 **         Update according to reference manual rev. 1.
  30 **     - rev. 1.2 (2012-08-01)
  31 **         Device type UARTLP changed to UART0.
  32 **         Missing PORTB_IRQn interrupt number definition added.
  33 **     - rev. 1.3 (2012-10-04)
  34 **         Update according to reference manual rev. 3.
  35 **     - rev. 1.4 (2012-11-22)
  36 **         MCG module - bit LOLS in MCG_S register renamed to LOLS0.
  37 **         NV registers - bit EZPORT_DIS in NV_FOPT register removed.
  38 **     - rev. 1.5 (2013-04-05)
  39 **         Changed start of doxygen comment.
  40 **     - rev. 1.6 (2013-04-11)
  41 **         SystemInit methods updated with predefined initialization sequence.
  42 **
  43 ** ###################################################################
  44 */
  45
  46 /*!
  47  * @file MKL05Z4
  48  * @version 1.6
  49  * @date 2013-04-11
  50  * @brief Device specific configuration file for MKL05Z4 (implementation file)
  51  *
  52  * Provides a system configuration function and a global variable that contains
  53  * the system frequency. It configures the device and initializes the oscillator
  54  * (PLL) that is part of the microcontroller device.
  55  */
  56
  57 #include <stdint.h>
  58 #include "MKL05Z4.h"
  59
  60 #define DISABLE_WDOG    1
  61
  62 #define CLOCK_SETUP     1
  63 /* Predefined clock setups
  64    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
  65          Reference clock source for MCG module is the slow internal clock source 32.768kHz
  66          Core clock = 41.94MHz, BusClock = 20.97MHz
  67    1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
  68          Reference clock source for MCG module is an external crystal 32.768kHz
  69          Core clock = 47.97MHz, BusClock = 23.98MHz
  70    2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
  71          Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
  72          Core clock = 4MHz, BusClock = 4MHz
  73 */
  74
  75 /*----------------------------------------------------------------------------
  76   Define clock source values
  77  *----------------------------------------------------------------------------*/
  78 #if (CLOCK_SETUP == 0)
  79     #define CPU_XTAL_CLK_HZ                 32768u   /* Value of the external crystal or oscillator clock frequency in Hz */
  80     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  81     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  82     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
  83 #elif (CLOCK_SETUP == 1)
  84     #define CPU_XTAL_CLK_HZ                 32768u   /* Value of the external crystal or oscillator clock frequency in Hz */
  85     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  86     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  87     #define DEFAULT_SYSTEM_CLOCK            47972352u /* Default System clock value */
  88 #elif (CLOCK_SETUP == 2)
  89     #define CPU_XTAL_CLK_HZ                 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
  90     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  91     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  92     #define DEFAULT_SYSTEM_CLOCK            4000000u /* Default System clock value */
  93 #endif /* (CLOCK_SETUP == 2) */
  94
  95
  96 /* ----------------------------------------------------------------------------
  97    -- Core clock
  98    ---------------------------------------------------------------------------- */
  99
 100 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
 101
 102 /* ----------------------------------------------------------------------------
 103    -- SystemInit()
 104    ---------------------------------------------------------------------------- */
 105
 106 void SystemInit (void) {
 107 #if (DISABLE_WDOG)
 108   /* Disable the WDOG module */
 109   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
 110   SIM->COPC = (uint32_t)0x00u;
 111 #endif /* (DISABLE_WDOG) */
 112 #if (CLOCK_SETUP == 0)
 113   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 114   SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
 115   /* Switch to FEI Mode */
 116   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 117   MCG->C1 = MCG_C1_CLKS(0x00) |
 118            MCG_C1_FRDIV(0x00) |
 119            MCG_C1_IREFS_MASK |
 120            MCG_C1_IRCLKEN_MASK;
 121     /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
 122   MCG->C2 = MCG_C2_RANGE0(0x00);
 123   /* MCG_C4: DMX32=0,DRST_DRS=1 */
 124   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
 125             MCG_C4_DMX32_MASK |
 126             MCG_C4_DRST_DRS(0x02)
 127            )) | (uint8_t)(
 128             MCG_C4_DRST_DRS(0x01)
 129            ));
 130   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 131   OSC0->CR = OSC_CR_ERCLKEN_MASK;
 132   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 133   }
 134   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
 135   }
 136 #elif (CLOCK_SETUP == 1)
 137   /* SIM->SCGC5: PORTA=1 */
 138   SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
 139   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 140   SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
 141   /* PORTA->PCR[3]: ISF=0,MUX=0 */
 142   PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 143   /* PORTA->PCR[4]: ISF=0,MUX=0 */
 144   PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 145   /* Switch to FEE Mode */
 146   /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
 147   MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
 148   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=1,SC8P=1,SC16P=0 */
 149   OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC4P_MASK;
 150   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 151   MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
 152   /* MCG->C4: DMX32=1,DRST_DRS=1 */
 153   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
 154             MCG_C4_DRST_DRS(0x02)
 155            )) | (uint8_t)(
 156             MCG_C4_DMX32_MASK |
 157             MCG_C4_DRST_DRS(0x01)
 158            ));
 159   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
 160   }
 161   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
 162   }
 163 #elif (CLOCK_SETUP == 2)
 164   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 165   SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
 166   /* MCG->SC: FCRDIV=0 */
 167   MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
 168   /* Switch to FBI Mode */
 169   /* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 170   MCG->C1 = MCG_C1_CLKS(0x01) |
 171            MCG_C1_FRDIV(0x00) |
 172            MCG_C1_IREFS_MASK |
 173            MCG_C1_IRCLKEN_MASK;
 174   /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
 175   MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
 176   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 177   MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
 178   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 179   OSC0->CR = OSC_CR_ERCLKEN_MASK;
 180   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 181   }
 182   while((MCG->S & 0x0CU) != 0x04U) {    /* Wait until internal reference clock is selected as MCG output */
 183   }
 184   /* Switch to BLPI Mode */
 185   /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
 186   MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
 187   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 188   }
 189   while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
 190   }
 191 #endif /* (CLOCK_SETUP == 2) */
 192 }
 193
 194 /* ----------------------------------------------------------------------------
 195    -- SystemCoreClockUpdate()
 196    ---------------------------------------------------------------------------- */
 197
 198 void SystemCoreClockUpdate (void) {
 199   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
 200   uint8_t Divider;
 201
 202   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
 203     /* Output of FLL is selected */
 204     if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
 205       /* External reference clock is selected */
 206       MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
 207       Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 208       MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
 209     } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 210       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
 211     } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 212     /* Select correct multiplier to calculate the MCG output clock  */
 213     switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 214       case 0x0u:
 215         MCGOUTClock *= 640u;
 216         break;
 217       case 0x20u:
 218         MCGOUTClock *= 1280u;
 219         break;
 220       case 0x40u:
 221         MCGOUTClock *= 1920u;
 222         break;
 223       case 0x60u:
 224         MCGOUTClock *= 2560u;
 225         break;
 226       case 0x80u:
 227         MCGOUTClock *= 732u;
 228         break;
 229       case 0xA0u:
 230         MCGOUTClock *= 1464u;
 231         break;
 232       case 0xC0u:
 233         MCGOUTClock *= 2197u;
 234         break;
 235       case 0xE0u:
 236         MCGOUTClock *= 2929u;
 237         break;
 238       default:
 239         break;
 240     }
 241   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
 242     /* Internal reference clock is selected */
 243     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
 244       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
 245     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 246       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
 247     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 248   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
 249     /* External reference clock is selected */
 250     MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
 251   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 252     /* Reserved value */
 253     return;
 254   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 255   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 256 }