1 ;/*****************************************************************************
2 ; * @file: startup_MKL25Z4.s
3 ; * @purpose: CMSIS Cortex-M0plus Core Device Startup File for the
8 ; * Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
10 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
12 ; *****************************************************************************/
15 ; <h> Stack Configuration
16 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
19 Stack_Size EQU 0x00000400
21 AREA STACK, NOINIT, READWRITE, ALIGN=3
24 Stack_Mem SPACE Stack_Size
25 __initial_sp EQU 0x20003000 ; Top of RAM
28 Heap_Size EQU 0x00000000
30 AREA HEAP, NOINIT, READWRITE, ALIGN=3
35 Heap_Mem SPACE Heap_Size
42 ; Vector Table Mapped to Address 0 at Reset
44 AREA RESET, DATA, READONLY
49 __Vectors DCD __initial_sp ; Top of Stack
50 DCD Reset_Handler ; Reset Handler
51 DCD NMI_Handler ; NMI Handler
52 DCD HardFault_Handler ; Hard Fault Handler
60 DCD SVC_Handler ; SVCall Handler
63 DCD PendSV_Handler ; PendSV Handler
64 DCD SysTick_Handler ; SysTick Handler
67 DCD DMA0_IRQHandler ; DMA channel 0 transfer complete interrupt
68 DCD DMA1_IRQHandler ; DMA channel 1 transfer complete interrupt
69 DCD DMA2_IRQHandler ; DMA channel 2 transfer complete interrupt
70 DCD DMA3_IRQHandler ; DMA channel 3 transfer complete interrupt
71 DCD Reserved20_IRQHandler ; Reserved interrupt 20
72 DCD FTFA_IRQHandler ; FTFA interrupt
73 DCD LVD_LVW_IRQHandler ; Low Voltage Detect, Low Voltage Warning
74 DCD LLW_IRQHandler ; Low Leakage Wakeup
75 DCD I2C0_IRQHandler ; I2C0 interrupt
76 DCD I2C1_IRQHandler ; I2C0 interrupt 25
77 DCD SPI0_IRQHandler ; SPI0 interrupt
78 DCD SPI1_IRQHandler ; SPI1 interrupt
79 DCD UART0_IRQHandler ; UART0 status/error interrupt
80 DCD UART1_IRQHandler ; UART1 status/error interrupt
81 DCD UART2_IRQHandler ; UART2 status/error interrupt
82 DCD ADC0_IRQHandler ; ADC0 interrupt
83 DCD CMP0_IRQHandler ; CMP0 interrupt
84 DCD TPM0_IRQHandler ; TPM0 fault, overflow and channels interrupt
85 DCD TPM1_IRQHandler ; TPM1 fault, overflow and channels interrupt
86 DCD TPM2_IRQHandler ; TPM2 fault, overflow and channels interrupt
87 DCD RTC_IRQHandler ; RTC interrupt
88 DCD RTC_Seconds_IRQHandler ; RTC seconds interrupt
89 DCD PIT_IRQHandler ; PIT timer interrupt
90 DCD Reserved39_IRQHandler ; Reserved interrupt 39
91 DCD USB0_IRQHandler ; USB0 interrupt
92 DCD DAC0_IRQHandler ; DAC interrupt
93 DCD TSI0_IRQHandler ; TSI0 interrupt
94 DCD MCG_IRQHandler ; MCG interrupt
95 DCD LPTimer_IRQHandler ; LPTimer interrupt
96 DCD Reserved45_IRQHandler ; Reserved interrupt 45
97 DCD PORTA_IRQHandler ; Port A interrupt
98 DCD PORTD_IRQHandler ; Port D interrupt
101 __Vectors_Size EQU __Vectors_End - __Vectors
103 ; <h> Flash Configuration
104 ; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset)
105 ; <i> and security information that allows the MCU to restrict acces to the FTFL module.
106 ; <h> Backdoor Comparison Key
107 ; <o0> Backdoor Key 0 <0x0-0xFF:2>
108 ; <o1> Backdoor Key 1 <0x0-0xFF:2>
109 ; <o2> Backdoor Key 2 <0x0-0xFF:2>
110 ; <o3> Backdoor Key 3 <0x0-0xFF:2>
111 ; <o4> Backdoor Key 4 <0x0-0xFF:2>
112 ; <o5> Backdoor Key 5 <0x0-0xFF:2>
113 ; <o6> Backdoor Key 6 <0x0-0xFF:2>
114 ; <o7> Backdoor Key 7 <0x0-0xFF:2>
124 ; <h> Program flash protection bytes (FPROT)
125 ; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit.
126 ; <i> Each bit protects a 1/32 region of the program flash memory.
128 ; <i> Program flash protection bytes
129 ; <i> 1/32 - 8/32 region
139 FPROT0 EQU nFPROT0:EOR:0xFF
142 ; <i> Program Flash Region Protect Register 1
143 ; <i> 9/32 - 16/32 region
153 FPROT1 EQU nFPROT1:EOR:0xFF
156 ; <i> Program Flash Region Protect Register 2
157 ; <i> 17/32 - 24/32 region
167 FPROT2 EQU nFPROT2:EOR:0xFF
170 ; <i> Program Flash Region Protect Register 3
171 ; <i> 25/32 - 32/32 region
181 FPROT3 EQU nFPROT3:EOR:0xFF
185 ; <h> Flash nonvolatile option byte (FOPT)
186 ; <i> Allows the user to customize the operation of the MCU at boot time.
188 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x3 (divide by 4)
189 ; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) or 0x0 (divide by 1)
191 ; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) or 0x1 (divide by 2)
192 ; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) or 0x0 (divide by 1)
194 ; <0=> NMI interrupts are always blocked
195 ; <1=> NMI pin/interrupts reset default to enabled
196 ; <o.3> RESET_PIN_CFG
197 ; <0=> RESET pin is disabled following a POR and cannot be enabled as RESET function
198 ; <1=> RESET pin is dedicated
200 ; <0=> Slower initialization
201 ; <1=> Fast Initialization
204 ; <h> Flash security byte (FSEC)
205 ; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled",
206 ; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!!
208 ; <2=> MCU security status is unsecure
209 ; <3=> MCU security status is secure
211 ; <i> This bits define the security state of the MCU.
213 ; <2=> Freescale factory access denied
214 ; <3=> Freescale factory access granted
215 ; <i> Freescale Failure Analysis Access Code
216 ; <i> This bits define the security state of the MCU.
218 ; <2=> Mass erase is disabled
219 ; <3=> Mass erase is enabled
220 ; <i> Mass Erase Enable Bits
221 ; <i> Enables and disables mass erase capability of the FTFL module
223 ; <2=> Backdoor key access enabled
224 ; <3=> Backdoor key access disabled
225 ; <i> Backdoor key Security Enable
226 ; <i> These bits enable and disable backdoor key access to the FTFL module.
230 IF :LNOT::DEF:RAM_TARGET
231 AREA |.ARM.__at_0x400|, CODE, READONLY
232 DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3
233 DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7
234 DCB FPROT0, FPROT1, FPROT2, FPROT3
235 DCB FSEC, FOPT, 0xFF, 0xFF
238 AREA |.text|, CODE, READONLY
244 EXPORT Reset_Handler [WEAK]
254 ; Dummy Exception Handlers (infinite loops which can be modified)
257 EXPORT NMI_Handler [WEAK]
262 EXPORT HardFault_Handler [WEAK]
266 EXPORT SVC_Handler [WEAK]
270 EXPORT PendSV_Handler [WEAK]
274 EXPORT SysTick_Handler [WEAK]
279 EXPORT DMA0_IRQHandler [WEAK]
280 EXPORT DMA1_IRQHandler [WEAK]
281 EXPORT DMA2_IRQHandler [WEAK]
282 EXPORT DMA3_IRQHandler [WEAK]
283 EXPORT Reserved20_IRQHandler [WEAK]
284 EXPORT FTFA_IRQHandler [WEAK]
285 EXPORT LVD_LVW_IRQHandler [WEAK]
286 EXPORT LLW_IRQHandler [WEAK]
287 EXPORT I2C0_IRQHandler [WEAK]
288 EXPORT I2C1_IRQHandler [WEAK]
289 EXPORT SPI0_IRQHandler [WEAK]
290 EXPORT SPI1_IRQHandler [WEAK]
291 EXPORT UART0_IRQHandler [WEAK]
292 EXPORT UART1_IRQHandler [WEAK]
293 EXPORT UART2_IRQHandler [WEAK]
294 EXPORT ADC0_IRQHandler [WEAK]
295 EXPORT CMP0_IRQHandler [WEAK]
296 EXPORT TPM0_IRQHandler [WEAK]
297 EXPORT TPM1_IRQHandler [WEAK]
298 EXPORT TPM2_IRQHandler [WEAK]
299 EXPORT RTC_IRQHandler [WEAK]
300 EXPORT RTC_Seconds_IRQHandler [WEAK]
301 EXPORT PIT_IRQHandler [WEAK]
302 EXPORT Reserved39_IRQHandler [WEAK]
303 EXPORT USB0_IRQHandler [WEAK]
304 EXPORT DAC0_IRQHandler [WEAK]
305 EXPORT TSI0_IRQHandler [WEAK]
306 EXPORT MCG_IRQHandler [WEAK]
307 EXPORT LPTimer_IRQHandler [WEAK]
308 EXPORT Reserved45_IRQHandler [WEAK]
309 EXPORT PORTA_IRQHandler [WEAK]
310 EXPORT PORTD_IRQHandler [WEAK]
311 EXPORT DefaultISR [WEAK]
317 Reserved20_IRQHandler
334 RTC_Seconds_IRQHandler
336 Reserved39_IRQHandler
342 Reserved45_IRQHandler