tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL25Z/system_MKL25Z4.c

   1 /*
   2 ** ###################################################################
   3 **     Processor:           MKL25Z128VLK4
   4 **     Compilers:           ARM Compiler
   5 **                          Freescale C/C++ for Embedded ARM
   6 **                          GNU C Compiler
   7 **                          IAR ANSI C/C++ Compiler for ARM
   8 **
   9 **     Reference manual:    KL25RM, Rev.1, Jun 2012
  10 **     Version:             rev. 1.1, 2012-06-21
  11 **
  12 **     Abstract:
  13 **         Provides a system configuration function and a global variable that
  14 **         contains the system frequency. It configures the device and initializes
  15 **         the oscillator (PLL) that is part of the microcontroller device.
  16 **
  17 **     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
  18 **
  19 **     http:                 www.freescale.com
  20 **     mail:                 support@freescale.com
  21 **
  22 **     Revisions:
  23 **     - rev. 1.0 (2012-06-13)
  24 **         Initial version.
  25 **     - rev. 1.1 (2012-06-21)
  26 **         Update according to reference manual rev. 1.
  27 **
  28 ** ###################################################################
  29 */
  30
  31 /**
  32  * @file MKL25Z4
  33  * @version 1.1
  34  * @date 2012-06-21
  35  * @brief Device specific configuration file for MKL25Z4 (implementation file)
  36  *
  37  * Provides a system configuration function and a global variable that contains
  38  * the system frequency. It configures the device and initializes the oscillator
  39  * (PLL) that is part of the microcontroller device.
  40  */
  41
  42 #include <stdint.h>
  43 #include "MKL25Z4.h"
  44
  45 #define DISABLE_WDOG    1
  46
  47 #define CLOCK_SETUP     1
  48 /* Predefined clock setups
  49    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
  50          Reference clock source for MCG module is the slow internal clock source 32.768kHz
  51          Core clock = 41.94MHz, BusClock = 13.98MHz
  52    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
  53          Reference clock source for MCG module is an external crystal 8MHz
  54          Core clock = 48MHz, BusClock = 24MHz
  55    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
  56          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
  57          Core clock = 8MHz, BusClock = 8MHz
  58 */
  59
  60 /*----------------------------------------------------------------------------
  61   Define clock source values
  62  *----------------------------------------------------------------------------*/
  63 #if (CLOCK_SETUP == 0)
  64     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  65     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  66     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  67     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
  68 #elif (CLOCK_SETUP == 1)
  69     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  70     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  71     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  72     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
  73 #elif (CLOCK_SETUP == 2)
  74     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
  75     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
  76     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
  77     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
  78 #endif /* (CLOCK_SETUP == 2) */
  79
  80
  81 /* ----------------------------------------------------------------------------
  82    -- Core clock
  83    ---------------------------------------------------------------------------- */
  84
  85 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
  86
  87 /* ----------------------------------------------------------------------------
  88    -- SystemInit()
  89    ---------------------------------------------------------------------------- */
  90
  91 void SystemInit (void) {
  92 #if (DISABLE_WDOG)
  93   /* Disable the WDOG module */
  94   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
  95   SIM->COPC = (uint32_t)0x00u;
  96 #endif /* (DISABLE_WDOG) */
  97 #if (CLOCK_SETUP == 0)
  98   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  99   SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
 100   /* Switch to FEI Mode */
 101   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 102   MCG->C1 = (uint8_t)0x06U;
 103   /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
 104   MCG->C2 = (uint8_t)0x00U;
 105   /* MCG->C4: DMX32=0,DRST_DRS=1 */
 106   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
 107   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 108   OSC0->CR = (uint8_t)0x80U;
 109   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 110   MCG->C5 = (uint8_t)0x00U;
 111   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 112   MCG->C6 = (uint8_t)0x00U;
 113   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
 114   }
 115   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
 116   }
 117 #elif (CLOCK_SETUP == 1)
 118   /* SIM->SCGC5: PORTA=1 */
 119   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
 120   /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 121   SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
 122   /* PORTA->PCR18: ISF=0,MUX=0 */
 123   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
 124   /* PORTA->PCR19: ISF=0,MUX=0 */
 125   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
 126   /* Switch to FBE Mode */
 127   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
 128   OSC0->CR = (uint8_t)0x89U;
 129   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
 130   MCG->C2 = (uint8_t)0x24U;
 131   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 132   MCG->C1 = (uint8_t)0x9AU;
 133   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 134   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
 135   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
 136   MCG->C5 = (uint8_t)0x01U;
 137   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 138   MCG->C6 = (uint8_t)0x00U;
 139   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
 140   }
 141   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
 142   }
 143   /* Switch to PBE Mode */
 144   /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
 145   MCG->C6 = (uint8_t)0x40U;
 146   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
 147   }
 148   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
 149   }
 150   /* Switch to PEE Mode */
 151   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 152   MCG->C1 = (uint8_t)0x1AU;
 153   while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
 154   }
 155 #elif (CLOCK_SETUP == 2)
 156   /* SIM->SCGC5: PORTA=1 */
 157   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
 158   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
 159   SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
 160   /* PORTA->PCR18: ISF=0,MUX=0 */
 161   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
 162   /* PORTA->PCR19: ISF=0,MUX=0 */
 163   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
 164   /* Switch to FBE Mode */
 165   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
 166   OSC0->CR = (uint8_t)0x89U;
 167   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
 168   MCG->C2 = (uint8_t)0x24U;
 169   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 170   MCG->C1 = (uint8_t)0x9AU;
 171   /* MCG->C4: DMX32=0,DRST_DRS=0 */
 172   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
 173   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 174   MCG->C5 = (uint8_t)0x00U;
 175   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 176   MCG->C6 = (uint8_t)0x00U;
 177   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
 178   }
 179   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
 180   }
 181   /* Switch to BLPE Mode */
 182   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
 183   MCG->C2 = (uint8_t)0x26U;
 184   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
 185   }
 186 #endif /* (CLOCK_SETUP == 2) */
 187 }
 188
 189 /* ----------------------------------------------------------------------------
 190    -- SystemCoreClockUpdate()
 191    ---------------------------------------------------------------------------- */
 192
 193 void SystemCoreClockUpdate (void) {
 194   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
 195   uint8_t Divider;
 196
 197   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
 198     /* Output of FLL or PLL is selected */
 199     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
 200       /* FLL is selected */
 201       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
 202         /* External reference clock is selected */
 203         MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
 204         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 205         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
 206         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
 207           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
 208         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
 209       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 210         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
 211       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
 212       /* Select correct multiplier to calculate the MCG output clock  */
 213       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 214         case 0x0u:
 215           MCGOUTClock *= 640u;
 216           break;
 217         case 0x20u:
 218           MCGOUTClock *= 1280u;
 219           break;
 220         case 0x40u:
 221           MCGOUTClock *= 1920u;
 222           break;
 223         case 0x60u:
 224           MCGOUTClock *= 2560u;
 225           break;
 226         case 0x80u:
 227           MCGOUTClock *= 732u;
 228           break;
 229         case 0xA0u:
 230           MCGOUTClock *= 1464u;
 231           break;
 232         case 0xC0u:
 233           MCGOUTClock *= 2197u;
 234           break;
 235         case 0xE0u:
 236           MCGOUTClock *= 2929u;
 237           break;
 238         default:
 239           break;
 240       }
 241     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 242       /* PLL is selected */
 243       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
 244       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
 245       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
 246       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
 247     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
 248   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
 249     /* Internal reference clock is selected */
 250     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
 251       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
 252     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 253       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
 254     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
 255   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
 256     /* External reference clock is selected */
 257     MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
 258   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 259     /* Reserved value */
 260     return;
 261   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
 262   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 263 }