]> git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/MKL43Z4.h
git://git.gir.st / tmk_keyboard.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_KLXX / TARGET_KL43Z / MKL43Z4.h
1 /*
2 ** ###################################################################
3 ** Processors: MKL43Z256VLH4
4 ** MKL43Z128VLH4
5 ** MKL43Z64VLH4
6 ** MKL43Z256VMP4
7 ** MKL43Z128VMP4
8 ** MKL43Z64VMP4
9 **
10 ** Compilers: Keil ARM C/C++ Compiler
11 ** Freescale C/C++ for Embedded ARM
12 ** GNU C Compiler
13 ** GNU C Compiler - CodeSourcery Sourcery G++
14 ** IAR ANSI C/C++ Compiler for ARM
15 **
16 ** Reference manual: KL43P64M48SF6RM, Rev.3, Aug 2014
17 ** Version: rev. 1.5, 2014-09-05
18 ** Build: b140905
19 **
20 ** Abstract:
21 ** CMSIS Peripheral Access Layer for MKL43Z4
22 **
23 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
24 ** All rights reserved.
25 **
26 ** Redistribution and use in source and binary forms, with or without modification,
27 ** are permitted provided that the following conditions are met:
28 **
29 ** o Redistributions of source code must retain the above copyright notice, this list
30 ** of conditions and the following disclaimer.
31 **
32 ** o Redistributions in binary form must reproduce the above copyright notice, this
33 ** list of conditions and the following disclaimer in the documentation and/or
34 ** other materials provided with the distribution.
35 **
36 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
37 ** contributors may be used to endorse or promote products derived from this
38 ** software without specific prior written permission.
39 **
40 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
41 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
42 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
43 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
44 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
45 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
46 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
47 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
48 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
49 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
50 **
51 ** http: www.freescale.com
52 ** mail: support@freescale.com
53 **
54 ** Revisions:
55 ** - rev. 1.0 (2014-03-27)
56 ** Initial version.
57 ** - rev. 1.1 (2014-05-26)
58 ** I2S registers TCR2/RCR2 and others were changed.
59 ** FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
60 ** Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
61 ** Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
62 ** Clock configuration for high range external oscillator has been added.
63 ** RFSYS module access has been added.
64 ** - rev. 1.2 (2014-07-10)
65 ** GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
66 ** UART0 - UART0 module renamed to UART2.
67 ** I2S - removed MDR register.
68 ** - rev. 1.3 (2014-08-21)
69 ** UART2 - Removed ED register.
70 ** UART2 - Removed MODEM register.
71 ** UART2 - Removed IR register.
72 ** UART2 - Removed PFIFO register.
73 ** UART2 - Removed CFIFO register.
74 ** UART2 - Removed SFIFO register.
75 ** UART2 - Removed TWFIFO register.
76 ** UART2 - Removed TCFIFO register.
77 ** UART2 - Removed RWFIFO register.
78 ** UART2 - Removed RCFIFO register.
79 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
80 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
81 ** SIM - Removed bitfield DIEID in SDID register.
82 ** - rev. 1.4 (2014-09-01)
83 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
84 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
85 ** - rev. 1.5 (2014-09-05)
86 ** USB - USBEN bitfield of the USB0_CTL renamed to USBENSOFEN.
87 **
88 ** ###################################################################
89 */
90
91 /*!
92 * @file MKL43Z4.h
93 * @version 1.5
94 * @date 2014-09-05
95 * @brief CMSIS Peripheral Access Layer for MKL43Z4
96 *
97 * CMSIS Peripheral Access Layer for MKL43Z4
98 */
99
100
101 /* ----------------------------------------------------------------------------
102 -- MCU activation
103 ---------------------------------------------------------------------------- */
104
105 /* Prevention from multiple including the same memory map */
106 #if !defined(MKL43Z4_H_) /* Check if memory map has not been already included */
107 #define MKL43Z4_H_
108 #define MCU_MKL43Z4
109
110 /* Check if another memory map has not been also included */
111 #if (defined(MCU_ACTIVE))
112 #error MKL43Z4 memory map: There is already included another memory map. Only one memory map can be included.
113 #endif /* (defined(MCU_ACTIVE)) */
114 #define MCU_ACTIVE
115
116 #include <stdint.h>
117
118 /** Memory map major version (memory maps with equal major version number are
119 * compatible) */
120 #define MCU_MEM_MAP_VERSION 0x0100u
121 /** Memory map minor version */
122 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
123
124
125 /* ----------------------------------------------------------------------------
126 -- Interrupt vector numbers
127 ---------------------------------------------------------------------------- */
128
129 /*!
130 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
131 * @{
132 */
133
134 /** Interrupt Number Definitions */
135 #define NUMBER_OF_INT_VECTORS 48 /**< Number of interrupts in the Vector table */
136
137 typedef enum IRQn {
138 /* Auxiliary constants */
139 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
140
141 /* Core interrupts */
142 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
143 HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */
144 SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */
145 PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */
146 SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */
147
148 /* Device specific interrupts */
149 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
150 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
151 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
152 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
153 Reserved20_IRQn = 4, /**< Reserved interrupt */
154 FTFA_IRQn = 5, /**< Command complete and read collision */
155 PMC_IRQn = 6, /**< Low-voltage detect, low-voltage warning */
156 LLWU_IRQn = 7, /**< Low leakage wakeup */
157 I2C0_IRQn = 8, /**< I2C0 interrupt */
158 I2C1_IRQn = 9, /**< I2C1 interrupt */
159 SPI0_IRQn = 10, /**< SPI0 single interrupt vector for all sources */
160 SPI1_IRQn = 11, /**< SPI1 single interrupt vector for all sources */
161 LPUART0_IRQn = 12, /**< LPUART0 status and error */
162 LPUART1_IRQn = 13, /**< LPUART1 status and error */
163 UART2_FLEXIO_IRQn = 14, /**< UART2 or FLEXIO */
164 ADC0_IRQn = 15, /**< ADC0 interrupt */
165 CMP0_IRQn = 16, /**< CMP0 interrupt */
166 TPM0_IRQn = 17, /**< TPM0 single interrupt vector for all sources */
167 TPM1_IRQn = 18, /**< TPM1 single interrupt vector for all sources */
168 TPM2_IRQn = 19, /**< TPM2 single interrupt vector for all sources */
169 RTC_IRQn = 20, /**< RTC alarm */
170 RTC_Seconds_IRQn = 21, /**< RTC seconds */
171 PIT_IRQn = 22, /**< PIT interrupt */
172 I2S0_IRQn = 23, /**< I2S0 interrupt */
173 USB0_IRQn = 24, /**< USB0 interrupt */
174 DAC0_IRQn = 25, /**< DAC0 interrupt */
175 Reserved42_IRQn = 26, /**< Reserved interrupt */
176 Reserved43_IRQn = 27, /**< Reserved interrupt */
177 LPTMR0_IRQn = 28, /**< LPTMR0 interrupt */
178 LCD_IRQn = 29, /**< LCD interrupt */
179 PORTA_IRQn = 30, /**< PORTA Pin detect */
180 PORTCD_IRQn = 31 /**< Single interrupt vector for PORTC; PORTD Pin detect */
181 } IRQn_Type;
182
183 /*!
184 * @}
185 */ /* end of group Interrupt_vector_numbers */
186
187
188 /* ----------------------------------------------------------------------------
189 -- Cortex M0 Core Configuration
190 ---------------------------------------------------------------------------- */
191
192 /*!
193 * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
194 * @{
195 */
196
197 #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */
198 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
199 #define __VTOR_PRESENT 1 /**< Defines if an MPU is present or not */
200 #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */
201 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
202
203 #include "core_cm0plus.h" /* Core Peripheral Access Layer */
204 #include "system_MKL43Z4.h" /* Device specific configuration file */
205
206 /*!
207 * @}
208 */ /* end of group Cortex_Core_Configuration */
209
210
211 /* ----------------------------------------------------------------------------
212 -- Device Peripheral Access Layer
213 ---------------------------------------------------------------------------- */
214
215 /*!
216 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
217 * @{
218 */
219
220
221 /*
222 ** Start of section using anonymous unions
223 */
224
225 #if defined(__ARMCC_VERSION)
226 #pragma push
227 #pragma anon_unions
228 #elif defined(__CWCC__)
229 #pragma push
230 #pragma cpp_extensions on
231 #elif defined(__GNUC__)
232 /* anonymous unions are enabled by default */
233 #elif defined(__IAR_SYSTEMS_ICC__)
234 #pragma language=extended
235 #else
236 #error Not supported compiler type
237 #endif
238
239 /* ----------------------------------------------------------------------------
240 -- ADC Peripheral Access Layer
241 ---------------------------------------------------------------------------- */
242
243 /*!
244 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
245 * @{
246 */
247
248 /** ADC - Register Layout Typedef */
249 typedef struct {
250 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
251 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
252 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
253 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
254 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
255 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
256 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
257 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
258 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
259 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
260 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
261 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
262 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
263 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
264 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
265 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
266 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
267 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
268 uint8_t RESERVED_0[4];
269 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
270 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
271 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
272 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
273 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
274 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
275 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
276 } ADC_Type, *ADC_MemMapPtr;
277
278 /* ----------------------------------------------------------------------------
279 -- ADC - Register accessor macros
280 ---------------------------------------------------------------------------- */
281
282 /*!
283 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
284 * @{
285 */
286
287
288 /* ADC - Register accessors */
289 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
290 #define ADC_CFG1_REG(base) ((base)->CFG1)
291 #define ADC_CFG2_REG(base) ((base)->CFG2)
292 #define ADC_R_REG(base,index) ((base)->R[index])
293 #define ADC_CV1_REG(base) ((base)->CV1)
294 #define ADC_CV2_REG(base) ((base)->CV2)
295 #define ADC_SC2_REG(base) ((base)->SC2)
296 #define ADC_SC3_REG(base) ((base)->SC3)
297 #define ADC_OFS_REG(base) ((base)->OFS)
298 #define ADC_PG_REG(base) ((base)->PG)
299 #define ADC_MG_REG(base) ((base)->MG)
300 #define ADC_CLPD_REG(base) ((base)->CLPD)
301 #define ADC_CLPS_REG(base) ((base)->CLPS)
302 #define ADC_CLP4_REG(base) ((base)->CLP4)
303 #define ADC_CLP3_REG(base) ((base)->CLP3)
304 #define ADC_CLP2_REG(base) ((base)->CLP2)
305 #define ADC_CLP1_REG(base) ((base)->CLP1)
306 #define ADC_CLP0_REG(base) ((base)->CLP0)
307 #define ADC_CLMD_REG(base) ((base)->CLMD)
308 #define ADC_CLMS_REG(base) ((base)->CLMS)
309 #define ADC_CLM4_REG(base) ((base)->CLM4)
310 #define ADC_CLM3_REG(base) ((base)->CLM3)
311 #define ADC_CLM2_REG(base) ((base)->CLM2)
312 #define ADC_CLM1_REG(base) ((base)->CLM1)
313 #define ADC_CLM0_REG(base) ((base)->CLM0)
314
315 /*!
316 * @}
317 */ /* end of group ADC_Register_Accessor_Macros */
318
319
320 /* ----------------------------------------------------------------------------
321 -- ADC Register Masks
322 ---------------------------------------------------------------------------- */
323
324 /*!
325 * @addtogroup ADC_Register_Masks ADC Register Masks
326 * @{
327 */
328
329 /* SC1 Bit Fields */
330 #define ADC_SC1_ADCH_MASK 0x1Fu
331 #define ADC_SC1_ADCH_SHIFT 0
332 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
333 #define ADC_SC1_DIFF_MASK 0x20u
334 #define ADC_SC1_DIFF_SHIFT 5
335 #define ADC_SC1_AIEN_MASK 0x40u
336 #define ADC_SC1_AIEN_SHIFT 6
337 #define ADC_SC1_COCO_MASK 0x80u
338 #define ADC_SC1_COCO_SHIFT 7
339 /* CFG1 Bit Fields */
340 #define ADC_CFG1_ADICLK_MASK 0x3u
341 #define ADC_CFG1_ADICLK_SHIFT 0
342 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
343 #define ADC_CFG1_MODE_MASK 0xCu
344 #define ADC_CFG1_MODE_SHIFT 2
345 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
346 #define ADC_CFG1_ADLSMP_MASK 0x10u
347 #define ADC_CFG1_ADLSMP_SHIFT 4
348 #define ADC_CFG1_ADIV_MASK 0x60u
349 #define ADC_CFG1_ADIV_SHIFT 5
350 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
351 #define ADC_CFG1_ADLPC_MASK 0x80u
352 #define ADC_CFG1_ADLPC_SHIFT 7
353 /* CFG2 Bit Fields */
354 #define ADC_CFG2_ADLSTS_MASK 0x3u
355 #define ADC_CFG2_ADLSTS_SHIFT 0
356 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
357 #define ADC_CFG2_ADHSC_MASK 0x4u
358 #define ADC_CFG2_ADHSC_SHIFT 2
359 #define ADC_CFG2_ADACKEN_MASK 0x8u
360 #define ADC_CFG2_ADACKEN_SHIFT 3
361 #define ADC_CFG2_MUXSEL_MASK 0x10u
362 #define ADC_CFG2_MUXSEL_SHIFT 4
363 /* R Bit Fields */
364 #define ADC_R_D_MASK 0xFFFFu
365 #define ADC_R_D_SHIFT 0
366 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
367 /* CV1 Bit Fields */
368 #define ADC_CV1_CV_MASK 0xFFFFu
369 #define ADC_CV1_CV_SHIFT 0
370 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
371 /* CV2 Bit Fields */
372 #define ADC_CV2_CV_MASK 0xFFFFu
373 #define ADC_CV2_CV_SHIFT 0
374 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
375 /* SC2 Bit Fields */
376 #define ADC_SC2_REFSEL_MASK 0x3u
377 #define ADC_SC2_REFSEL_SHIFT 0
378 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
379 #define ADC_SC2_DMAEN_MASK 0x4u
380 #define ADC_SC2_DMAEN_SHIFT 2
381 #define ADC_SC2_ACREN_MASK 0x8u
382 #define ADC_SC2_ACREN_SHIFT 3
383 #define ADC_SC2_ACFGT_MASK 0x10u
384 #define ADC_SC2_ACFGT_SHIFT 4
385 #define ADC_SC2_ACFE_MASK 0x20u
386 #define ADC_SC2_ACFE_SHIFT 5
387 #define ADC_SC2_ADTRG_MASK 0x40u
388 #define ADC_SC2_ADTRG_SHIFT 6
389 #define ADC_SC2_ADACT_MASK 0x80u
390 #define ADC_SC2_ADACT_SHIFT 7
391 /* SC3 Bit Fields */
392 #define ADC_SC3_AVGS_MASK 0x3u
393 #define ADC_SC3_AVGS_SHIFT 0
394 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
395 #define ADC_SC3_AVGE_MASK 0x4u
396 #define ADC_SC3_AVGE_SHIFT 2
397 #define ADC_SC3_ADCO_MASK 0x8u
398 #define ADC_SC3_ADCO_SHIFT 3
399 #define ADC_SC3_CALF_MASK 0x40u
400 #define ADC_SC3_CALF_SHIFT 6
401 #define ADC_SC3_CAL_MASK 0x80u
402 #define ADC_SC3_CAL_SHIFT 7
403 /* OFS Bit Fields */
404 #define ADC_OFS_OFS_MASK 0xFFFFu
405 #define ADC_OFS_OFS_SHIFT 0
406 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
407 /* PG Bit Fields */
408 #define ADC_PG_PG_MASK 0xFFFFu
409 #define ADC_PG_PG_SHIFT 0
410 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
411 /* MG Bit Fields */
412 #define ADC_MG_MG_MASK 0xFFFFu
413 #define ADC_MG_MG_SHIFT 0
414 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
415 /* CLPD Bit Fields */
416 #define ADC_CLPD_CLPD_MASK 0x3Fu
417 #define ADC_CLPD_CLPD_SHIFT 0
418 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
419 /* CLPS Bit Fields */
420 #define ADC_CLPS_CLPS_MASK 0x3Fu
421 #define ADC_CLPS_CLPS_SHIFT 0
422 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
423 /* CLP4 Bit Fields */
424 #define ADC_CLP4_CLP4_MASK 0x3FFu
425 #define ADC_CLP4_CLP4_SHIFT 0
426 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
427 /* CLP3 Bit Fields */
428 #define ADC_CLP3_CLP3_MASK 0x1FFu
429 #define ADC_CLP3_CLP3_SHIFT 0
430 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
431 /* CLP2 Bit Fields */
432 #define ADC_CLP2_CLP2_MASK 0xFFu
433 #define ADC_CLP2_CLP2_SHIFT 0
434 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
435 /* CLP1 Bit Fields */
436 #define ADC_CLP1_CLP1_MASK 0x7Fu
437 #define ADC_CLP1_CLP1_SHIFT 0
438 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
439 /* CLP0 Bit Fields */
440 #define ADC_CLP0_CLP0_MASK 0x3Fu
441 #define ADC_CLP0_CLP0_SHIFT 0
442 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
443 /* CLMD Bit Fields */
444 #define ADC_CLMD_CLMD_MASK 0x3Fu
445 #define ADC_CLMD_CLMD_SHIFT 0
446 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
447 /* CLMS Bit Fields */
448 #define ADC_CLMS_CLMS_MASK 0x3Fu
449 #define ADC_CLMS_CLMS_SHIFT 0
450 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
451 /* CLM4 Bit Fields */
452 #define ADC_CLM4_CLM4_MASK 0x3FFu
453 #define ADC_CLM4_CLM4_SHIFT 0
454 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
455 /* CLM3 Bit Fields */
456 #define ADC_CLM3_CLM3_MASK 0x1FFu
457 #define ADC_CLM3_CLM3_SHIFT 0
458 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
459 /* CLM2 Bit Fields */
460 #define ADC_CLM2_CLM2_MASK 0xFFu
461 #define ADC_CLM2_CLM2_SHIFT 0
462 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
463 /* CLM1 Bit Fields */
464 #define ADC_CLM1_CLM1_MASK 0x7Fu
465 #define ADC_CLM1_CLM1_SHIFT 0
466 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
467 /* CLM0 Bit Fields */
468 #define ADC_CLM0_CLM0_MASK 0x3Fu
469 #define ADC_CLM0_CLM0_SHIFT 0
470 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
471
472 /*!
473 * @}
474 */ /* end of group ADC_Register_Masks */
475
476
477 /* ADC - Peripheral instance base addresses */
478 /** Peripheral ADC0 base address */
479 #define ADC0_BASE (0x4003B000u)
480 /** Peripheral ADC0 base pointer */
481 #define ADC0 ((ADC_Type *)ADC0_BASE)
482 #define ADC0_BASE_PTR (ADC0)
483 /** Array initializer of ADC peripheral base addresses */
484 #define ADC_BASE_ADDRS { ADC0_BASE }
485 /** Array initializer of ADC peripheral base pointers */
486 #define ADC_BASE_PTRS { ADC0 }
487 /** Interrupt vectors for the ADC peripheral type */
488 #define ADC_IRQS { ADC0_IRQn }
489
490 /* ----------------------------------------------------------------------------
491 -- ADC - Register accessor macros
492 ---------------------------------------------------------------------------- */
493
494 /*!
495 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
496 * @{
497 */
498
499
500 /* ADC - Register instance definitions */
501 /* ADC0 */
502 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
503 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
504 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
505 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
506 #define ADC0_RA ADC_R_REG(ADC0,0)
507 #define ADC0_RB ADC_R_REG(ADC0,1)
508 #define ADC0_CV1 ADC_CV1_REG(ADC0)
509 #define ADC0_CV2 ADC_CV2_REG(ADC0)
510 #define ADC0_SC2 ADC_SC2_REG(ADC0)
511 #define ADC0_SC3 ADC_SC3_REG(ADC0)
512 #define ADC0_OFS ADC_OFS_REG(ADC0)
513 #define ADC0_PG ADC_PG_REG(ADC0)
514 #define ADC0_MG ADC_MG_REG(ADC0)
515 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
516 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
517 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
518 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
519 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
520 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
521 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
522 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
523 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
524 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
525 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
526 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
527 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
528 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
529
530 /* ADC - Register array accessors */
531 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
532 #define ADC0_R(index) ADC_R_REG(ADC0,index)
533
534 /*!
535 * @}
536 */ /* end of group ADC_Register_Accessor_Macros */
537
538
539 /*!
540 * @}
541 */ /* end of group ADC_Peripheral_Access_Layer */
542
543
544 /* ----------------------------------------------------------------------------
545 -- CMP Peripheral Access Layer
546 ---------------------------------------------------------------------------- */
547
548 /*!
549 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
550 * @{
551 */
552
553 /** CMP - Register Layout Typedef */
554 typedef struct {
555 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
556 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
557 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
558 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
559 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
560 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
561 } CMP_Type, *CMP_MemMapPtr;
562
563 /* ----------------------------------------------------------------------------
564 -- CMP - Register accessor macros
565 ---------------------------------------------------------------------------- */
566
567 /*!
568 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
569 * @{
570 */
571
572
573 /* CMP - Register accessors */
574 #define CMP_CR0_REG(base) ((base)->CR0)
575 #define CMP_CR1_REG(base) ((base)->CR1)
576 #define CMP_FPR_REG(base) ((base)->FPR)
577 #define CMP_SCR_REG(base) ((base)->SCR)
578 #define CMP_DACCR_REG(base) ((base)->DACCR)
579 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
580
581 /*!
582 * @}
583 */ /* end of group CMP_Register_Accessor_Macros */
584
585
586 /* ----------------------------------------------------------------------------
587 -- CMP Register Masks
588 ---------------------------------------------------------------------------- */
589
590 /*!
591 * @addtogroup CMP_Register_Masks CMP Register Masks
592 * @{
593 */
594
595 /* CR0 Bit Fields */
596 #define CMP_CR0_HYSTCTR_MASK 0x3u
597 #define CMP_CR0_HYSTCTR_SHIFT 0
598 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
599 #define CMP_CR0_FILTER_CNT_MASK 0x70u
600 #define CMP_CR0_FILTER_CNT_SHIFT 4
601 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
602 /* CR1 Bit Fields */
603 #define CMP_CR1_EN_MASK 0x1u
604 #define CMP_CR1_EN_SHIFT 0
605 #define CMP_CR1_OPE_MASK 0x2u
606 #define CMP_CR1_OPE_SHIFT 1
607 #define CMP_CR1_COS_MASK 0x4u
608 #define CMP_CR1_COS_SHIFT 2
609 #define CMP_CR1_INV_MASK 0x8u
610 #define CMP_CR1_INV_SHIFT 3
611 #define CMP_CR1_PMODE_MASK 0x10u
612 #define CMP_CR1_PMODE_SHIFT 4
613 #define CMP_CR1_TRIGM_MASK 0x20u
614 #define CMP_CR1_TRIGM_SHIFT 5
615 #define CMP_CR1_WE_MASK 0x40u
616 #define CMP_CR1_WE_SHIFT 6
617 #define CMP_CR1_SE_MASK 0x80u
618 #define CMP_CR1_SE_SHIFT 7
619 /* FPR Bit Fields */
620 #define CMP_FPR_FILT_PER_MASK 0xFFu
621 #define CMP_FPR_FILT_PER_SHIFT 0
622 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
623 /* SCR Bit Fields */
624 #define CMP_SCR_COUT_MASK 0x1u
625 #define CMP_SCR_COUT_SHIFT 0
626 #define CMP_SCR_CFF_MASK 0x2u
627 #define CMP_SCR_CFF_SHIFT 1
628 #define CMP_SCR_CFR_MASK 0x4u
629 #define CMP_SCR_CFR_SHIFT 2
630 #define CMP_SCR_IEF_MASK 0x8u
631 #define CMP_SCR_IEF_SHIFT 3
632 #define CMP_SCR_IER_MASK 0x10u
633 #define CMP_SCR_IER_SHIFT 4
634 #define CMP_SCR_DMAEN_MASK 0x40u
635 #define CMP_SCR_DMAEN_SHIFT 6
636 /* DACCR Bit Fields */
637 #define CMP_DACCR_VOSEL_MASK 0x3Fu
638 #define CMP_DACCR_VOSEL_SHIFT 0
639 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
640 #define CMP_DACCR_VRSEL_MASK 0x40u
641 #define CMP_DACCR_VRSEL_SHIFT 6
642 #define CMP_DACCR_DACEN_MASK 0x80u
643 #define CMP_DACCR_DACEN_SHIFT 7
644 /* MUXCR Bit Fields */
645 #define CMP_MUXCR_MSEL_MASK 0x7u
646 #define CMP_MUXCR_MSEL_SHIFT 0
647 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
648 #define CMP_MUXCR_PSEL_MASK 0x38u
649 #define CMP_MUXCR_PSEL_SHIFT 3
650 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
651 #define CMP_MUXCR_PSTM_MASK 0x80u
652 #define CMP_MUXCR_PSTM_SHIFT 7
653
654 /*!
655 * @}
656 */ /* end of group CMP_Register_Masks */
657
658
659 /* CMP - Peripheral instance base addresses */
660 /** Peripheral CMP0 base address */
661 #define CMP0_BASE (0x40073000u)
662 /** Peripheral CMP0 base pointer */
663 #define CMP0 ((CMP_Type *)CMP0_BASE)
664 #define CMP0_BASE_PTR (CMP0)
665 /** Array initializer of CMP peripheral base addresses */
666 #define CMP_BASE_ADDRS { CMP0_BASE }
667 /** Array initializer of CMP peripheral base pointers */
668 #define CMP_BASE_PTRS { CMP0 }
669 /** Interrupt vectors for the CMP peripheral type */
670 #define CMP_IRQS { CMP0_IRQn }
671
672 /* ----------------------------------------------------------------------------
673 -- CMP - Register accessor macros
674 ---------------------------------------------------------------------------- */
675
676 /*!
677 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
678 * @{
679 */
680
681
682 /* CMP - Register instance definitions */
683 /* CMP0 */
684 #define CMP0_CR0 CMP_CR0_REG(CMP0)
685 #define CMP0_CR1 CMP_CR1_REG(CMP0)
686 #define CMP0_FPR CMP_FPR_REG(CMP0)
687 #define CMP0_SCR CMP_SCR_REG(CMP0)
688 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
689 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
690
691 /*!
692 * @}
693 */ /* end of group CMP_Register_Accessor_Macros */
694
695
696 /*!
697 * @}
698 */ /* end of group CMP_Peripheral_Access_Layer */
699
700
701 /* ----------------------------------------------------------------------------
702 -- DAC Peripheral Access Layer
703 ---------------------------------------------------------------------------- */
704
705 /*!
706 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
707 * @{
708 */
709
710 /** DAC - Register Layout Typedef */
711 typedef struct {
712 struct { /* offset: 0x0, array step: 0x2 */
713 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
714 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
715 } DAT[2];
716 uint8_t RESERVED_0[28];
717 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
718 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
719 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
720 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
721 } DAC_Type, *DAC_MemMapPtr;
722
723 /* ----------------------------------------------------------------------------
724 -- DAC - Register accessor macros
725 ---------------------------------------------------------------------------- */
726
727 /*!
728 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
729 * @{
730 */
731
732
733 /* DAC - Register accessors */
734 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
735 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
736 #define DAC_SR_REG(base) ((base)->SR)
737 #define DAC_C0_REG(base) ((base)->C0)
738 #define DAC_C1_REG(base) ((base)->C1)
739 #define DAC_C2_REG(base) ((base)->C2)
740
741 /*!
742 * @}
743 */ /* end of group DAC_Register_Accessor_Macros */
744
745
746 /* ----------------------------------------------------------------------------
747 -- DAC Register Masks
748 ---------------------------------------------------------------------------- */
749
750 /*!
751 * @addtogroup DAC_Register_Masks DAC Register Masks
752 * @{
753 */
754
755 /* DATL Bit Fields */
756 #define DAC_DATL_DATA0_MASK 0xFFu
757 #define DAC_DATL_DATA0_SHIFT 0
758 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
759 /* DATH Bit Fields */
760 #define DAC_DATH_DATA1_MASK 0xFu
761 #define DAC_DATH_DATA1_SHIFT 0
762 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
763 /* SR Bit Fields */
764 #define DAC_SR_DACBFRPBF_MASK 0x1u
765 #define DAC_SR_DACBFRPBF_SHIFT 0
766 #define DAC_SR_DACBFRPTF_MASK 0x2u
767 #define DAC_SR_DACBFRPTF_SHIFT 1
768 /* C0 Bit Fields */
769 #define DAC_C0_DACBBIEN_MASK 0x1u
770 #define DAC_C0_DACBBIEN_SHIFT 0
771 #define DAC_C0_DACBTIEN_MASK 0x2u
772 #define DAC_C0_DACBTIEN_SHIFT 1
773 #define DAC_C0_LPEN_MASK 0x8u
774 #define DAC_C0_LPEN_SHIFT 3
775 #define DAC_C0_DACSWTRG_MASK 0x10u
776 #define DAC_C0_DACSWTRG_SHIFT 4
777 #define DAC_C0_DACTRGSEL_MASK 0x20u
778 #define DAC_C0_DACTRGSEL_SHIFT 5
779 #define DAC_C0_DACRFS_MASK 0x40u
780 #define DAC_C0_DACRFS_SHIFT 6
781 #define DAC_C0_DACEN_MASK 0x80u
782 #define DAC_C0_DACEN_SHIFT 7
783 /* C1 Bit Fields */
784 #define DAC_C1_DACBFEN_MASK 0x1u
785 #define DAC_C1_DACBFEN_SHIFT 0
786 #define DAC_C1_DACBFMD_MASK 0x6u
787 #define DAC_C1_DACBFMD_SHIFT 1
788 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
789 #define DAC_C1_DMAEN_MASK 0x80u
790 #define DAC_C1_DMAEN_SHIFT 7
791 /* C2 Bit Fields */
792 #define DAC_C2_DACBFUP_MASK 0x1u
793 #define DAC_C2_DACBFUP_SHIFT 0
794 #define DAC_C2_DACBFRP_MASK 0x10u
795 #define DAC_C2_DACBFRP_SHIFT 4
796
797 /*!
798 * @}
799 */ /* end of group DAC_Register_Masks */
800
801
802 /* DAC - Peripheral instance base addresses */
803 /** Peripheral DAC0 base address */
804 #define DAC0_BASE (0x4003F000u)
805 /** Peripheral DAC0 base pointer */
806 #define DAC0 ((DAC_Type *)DAC0_BASE)
807 #define DAC0_BASE_PTR (DAC0)
808 /** Array initializer of DAC peripheral base addresses */
809 #define DAC_BASE_ADDRS { DAC0_BASE }
810 /** Array initializer of DAC peripheral base pointers */
811 #define DAC_BASE_PTRS { DAC0 }
812 /** Interrupt vectors for the DAC peripheral type */
813 #define DAC_IRQS { DAC0_IRQn }
814
815 /* ----------------------------------------------------------------------------
816 -- DAC - Register accessor macros
817 ---------------------------------------------------------------------------- */
818
819 /*!
820 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
821 * @{
822 */
823
824
825 /* DAC - Register instance definitions */
826 /* DAC0 */
827 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
828 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
829 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
830 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
831 #define DAC0_SR DAC_SR_REG(DAC0)
832 #define DAC0_C0 DAC_C0_REG(DAC0)
833 #define DAC0_C1 DAC_C1_REG(DAC0)
834 #define DAC0_C2 DAC_C2_REG(DAC0)
835
836 /* DAC - Register array accessors */
837 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
838 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
839
840 /*!
841 * @}
842 */ /* end of group DAC_Register_Accessor_Macros */
843
844
845 /*!
846 * @}
847 */ /* end of group DAC_Peripheral_Access_Layer */
848
849
850 /* ----------------------------------------------------------------------------
851 -- DMA Peripheral Access Layer
852 ---------------------------------------------------------------------------- */
853
854 /*!
855 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
856 * @{
857 */
858
859 /** DMA - Register Layout Typedef */
860 typedef struct {
861 uint8_t RESERVED_0[256];
862 struct { /* offset: 0x100, array step: 0x10 */
863 __IO uint32_t SAR; /**< Source Address Register, array offset: 0x100, array step: 0x10 */
864 __IO uint32_t DAR; /**< Destination Address Register, array offset: 0x104, array step: 0x10 */
865 union { /* offset: 0x108, array step: 0x10 */
866 __IO uint32_t DSR_BCR; /**< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 */
867 struct { /* offset: 0x108, array step: 0x10 */
868 uint8_t RESERVED_0[3];
869 __IO uint8_t DSR; /**< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 */
870 } DMA_DSR_ACCESS8BIT;
871 };
872 __IO uint32_t DCR; /**< DMA Control Register, array offset: 0x10C, array step: 0x10 */
873 } DMA[4];
874 } DMA_Type, *DMA_MemMapPtr;
875
876 /* ----------------------------------------------------------------------------
877 -- DMA - Register accessor macros
878 ---------------------------------------------------------------------------- */
879
880 /*!
881 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
882 * @{
883 */
884
885
886 /* DMA - Register accessors */
887 #define DMA_SAR_REG(base,index) ((base)->DMA[index].SAR)
888 #define DMA_DAR_REG(base,index) ((base)->DMA[index].DAR)
889 #define DMA_DSR_BCR_REG(base,index) ((base)->DMA[index].DSR_BCR)
890 #define DMA_DSR_REG(base,index) ((base)->DMA[index].DMA_DSR_ACCESS8BIT.DSR)
891 #define DMA_DCR_REG(base,index) ((base)->DMA[index].DCR)
892
893 /*!
894 * @}
895 */ /* end of group DMA_Register_Accessor_Macros */
896
897
898 /* ----------------------------------------------------------------------------
899 -- DMA Register Masks
900 ---------------------------------------------------------------------------- */
901
902 /*!
903 * @addtogroup DMA_Register_Masks DMA Register Masks
904 * @{
905 */
906
907 /* SAR Bit Fields */
908 #define DMA_SAR_SAR_MASK 0xFFFFFFFFu
909 #define DMA_SAR_SAR_SHIFT 0
910 #define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
911 /* DAR Bit Fields */
912 #define DMA_DAR_DAR_MASK 0xFFFFFFFFu
913 #define DMA_DAR_DAR_SHIFT 0
914 #define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
915 /* DSR_BCR Bit Fields */
916 #define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
917 #define DMA_DSR_BCR_BCR_SHIFT 0
918 #define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
919 #define DMA_DSR_BCR_DONE_MASK 0x1000000u
920 #define DMA_DSR_BCR_DONE_SHIFT 24
921 #define DMA_DSR_BCR_BSY_MASK 0x2000000u
922 #define DMA_DSR_BCR_BSY_SHIFT 25
923 #define DMA_DSR_BCR_REQ_MASK 0x4000000u
924 #define DMA_DSR_BCR_REQ_SHIFT 26
925 #define DMA_DSR_BCR_BED_MASK 0x10000000u
926 #define DMA_DSR_BCR_BED_SHIFT 28
927 #define DMA_DSR_BCR_BES_MASK 0x20000000u
928 #define DMA_DSR_BCR_BES_SHIFT 29
929 #define DMA_DSR_BCR_CE_MASK 0x40000000u
930 #define DMA_DSR_BCR_CE_SHIFT 30
931 /* DCR Bit Fields */
932 #define DMA_DCR_LCH2_MASK 0x3u
933 #define DMA_DCR_LCH2_SHIFT 0
934 #define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
935 #define DMA_DCR_LCH1_MASK 0xCu
936 #define DMA_DCR_LCH1_SHIFT 2
937 #define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
938 #define DMA_DCR_LINKCC_MASK 0x30u
939 #define DMA_DCR_LINKCC_SHIFT 4
940 #define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
941 #define DMA_DCR_D_REQ_MASK 0x80u
942 #define DMA_DCR_D_REQ_SHIFT 7
943 #define DMA_DCR_DMOD_MASK 0xF00u
944 #define DMA_DCR_DMOD_SHIFT 8
945 #define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
946 #define DMA_DCR_SMOD_MASK 0xF000u
947 #define DMA_DCR_SMOD_SHIFT 12
948 #define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
949 #define DMA_DCR_START_MASK 0x10000u
950 #define DMA_DCR_START_SHIFT 16
951 #define DMA_DCR_DSIZE_MASK 0x60000u
952 #define DMA_DCR_DSIZE_SHIFT 17
953 #define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
954 #define DMA_DCR_DINC_MASK 0x80000u
955 #define DMA_DCR_DINC_SHIFT 19
956 #define DMA_DCR_SSIZE_MASK 0x300000u
957 #define DMA_DCR_SSIZE_SHIFT 20
958 #define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
959 #define DMA_DCR_SINC_MASK 0x400000u
960 #define DMA_DCR_SINC_SHIFT 22
961 #define DMA_DCR_EADREQ_MASK 0x800000u
962 #define DMA_DCR_EADREQ_SHIFT 23
963 #define DMA_DCR_AA_MASK 0x10000000u
964 #define DMA_DCR_AA_SHIFT 28
965 #define DMA_DCR_CS_MASK 0x20000000u
966 #define DMA_DCR_CS_SHIFT 29
967 #define DMA_DCR_ERQ_MASK 0x40000000u
968 #define DMA_DCR_ERQ_SHIFT 30
969 #define DMA_DCR_EINT_MASK 0x80000000u
970 #define DMA_DCR_EINT_SHIFT 31
971
972 /*!
973 * @}
974 */ /* end of group DMA_Register_Masks */
975
976
977 /* DMA - Peripheral instance base addresses */
978 /** Peripheral DMA base address */
979 #define DMA_BASE (0x40008000u)
980 /** Peripheral DMA base pointer */
981 #define DMA0 ((DMA_Type *)DMA_BASE)
982 #define DMA_BASE_PTR (DMA0)
983 /** Array initializer of DMA peripheral base addresses */
984 #define DMA_BASE_ADDRS { DMA_BASE }
985 /** Array initializer of DMA peripheral base pointers */
986 #define DMA_BASE_PTRS { DMA0 }
987 /** Interrupt vectors for the DMA peripheral type */
988 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn }
989
990 /* ----------------------------------------------------------------------------
991 -- DMA - Register accessor macros
992 ---------------------------------------------------------------------------- */
993
994 /*!
995 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
996 * @{
997 */
998
999
1000 /* DMA - Register instance definitions */
1001 /* DMA */
1002 #define DMA_SAR0 DMA_SAR_REG(DMA0,0)
1003 #define DMA_DAR0 DMA_DAR_REG(DMA0,0)
1004 #define DMA_DSR_BCR0 DMA_DSR_BCR_REG(DMA0,0)
1005 #define DMA_DSR0 DMA_DSR_REG(DMA0,0)
1006 #define DMA_DCR0 DMA_DCR_REG(DMA0,0)
1007 #define DMA_SAR1 DMA_SAR_REG(DMA0,1)
1008 #define DMA_DAR1 DMA_DAR_REG(DMA0,1)
1009 #define DMA_DSR_BCR1 DMA_DSR_BCR_REG(DMA0,1)
1010 #define DMA_DSR1 DMA_DSR_REG(DMA0,1)
1011 #define DMA_DCR1 DMA_DCR_REG(DMA0,1)
1012 #define DMA_SAR2 DMA_SAR_REG(DMA0,2)
1013 #define DMA_DAR2 DMA_DAR_REG(DMA0,2)
1014 #define DMA_DSR_BCR2 DMA_DSR_BCR_REG(DMA0,2)
1015 #define DMA_DSR2 DMA_DSR_REG(DMA0,2)
1016 #define DMA_DCR2 DMA_DCR_REG(DMA0,2)
1017 #define DMA_SAR3 DMA_SAR_REG(DMA0,3)
1018 #define DMA_DAR3 DMA_DAR_REG(DMA0,3)
1019 #define DMA_DSR_BCR3 DMA_DSR_BCR_REG(DMA0,3)
1020 #define DMA_DSR3 DMA_DSR_REG(DMA0,3)
1021 #define DMA_DCR3 DMA_DCR_REG(DMA0,3)
1022
1023 /* DMA - Register array accessors */
1024 #define DMA_SAR(index) DMA_SAR_REG(DMA0,index)
1025 #define DMA_DAR(index) DMA_DAR_REG(DMA0,index)
1026 #define DMA_DSR_BCR(index) DMA_DSR_BCR_REG(DMA0,index)
1027 #define DMA_DSR(index) DMA_DSR_REG(DMA0,index)
1028 #define DMA_DCR(index) DMA_DCR_REG(DMA0,index)
1029
1030 /*!
1031 * @}
1032 */ /* end of group DMA_Register_Accessor_Macros */
1033
1034
1035 /*!
1036 * @}
1037 */ /* end of group DMA_Peripheral_Access_Layer */
1038
1039
1040 /* ----------------------------------------------------------------------------
1041 -- DMAMUX Peripheral Access Layer
1042 ---------------------------------------------------------------------------- */
1043
1044 /*!
1045 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
1046 * @{
1047 */
1048
1049 /** DMAMUX - Register Layout Typedef */
1050 typedef struct {
1051 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
1052 } DMAMUX_Type, *DMAMUX_MemMapPtr;
1053
1054 /* ----------------------------------------------------------------------------
1055 -- DMAMUX - Register accessor macros
1056 ---------------------------------------------------------------------------- */
1057
1058 /*!
1059 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
1060 * @{
1061 */
1062
1063
1064 /* DMAMUX - Register accessors */
1065 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
1066
1067 /*!
1068 * @}
1069 */ /* end of group DMAMUX_Register_Accessor_Macros */
1070
1071
1072 /* ----------------------------------------------------------------------------
1073 -- DMAMUX Register Masks
1074 ---------------------------------------------------------------------------- */
1075
1076 /*!
1077 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
1078 * @{
1079 */
1080
1081 /* CHCFG Bit Fields */
1082 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
1083 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
1084 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
1085 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
1086 #define DMAMUX_CHCFG_TRIG_SHIFT 6
1087 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
1088 #define DMAMUX_CHCFG_ENBL_SHIFT 7
1089
1090 /*!
1091 * @}
1092 */ /* end of group DMAMUX_Register_Masks */
1093
1094
1095 /* DMAMUX - Peripheral instance base addresses */
1096 /** Peripheral DMAMUX0 base address */
1097 #define DMAMUX0_BASE (0x40021000u)
1098 /** Peripheral DMAMUX0 base pointer */
1099 #define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
1100 #define DMAMUX0_BASE_PTR (DMAMUX0)
1101 /** Array initializer of DMAMUX peripheral base addresses */
1102 #define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
1103 /** Array initializer of DMAMUX peripheral base pointers */
1104 #define DMAMUX_BASE_PTRS { DMAMUX0 }
1105
1106 /* ----------------------------------------------------------------------------
1107 -- DMAMUX - Register accessor macros
1108 ---------------------------------------------------------------------------- */
1109
1110 /*!
1111 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
1112 * @{
1113 */
1114
1115
1116 /* DMAMUX - Register instance definitions */
1117 /* DMAMUX0 */
1118 #define DMAMUX0_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX0,0)
1119 #define DMAMUX0_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX0,1)
1120 #define DMAMUX0_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX0,2)
1121 #define DMAMUX0_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX0,3)
1122
1123 /* DMAMUX - Register array accessors */
1124 #define DMAMUX0_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX0,index)
1125
1126 /*!
1127 * @}
1128 */ /* end of group DMAMUX_Register_Accessor_Macros */
1129
1130
1131 /*!
1132 * @}
1133 */ /* end of group DMAMUX_Peripheral_Access_Layer */
1134
1135
1136 /* ----------------------------------------------------------------------------
1137 -- FLEXIO Peripheral Access Layer
1138 ---------------------------------------------------------------------------- */
1139
1140 /*!
1141 * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
1142 * @{
1143 */
1144
1145 /** FLEXIO - Register Layout Typedef */
1146 typedef struct {
1147 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
1148 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
1149 __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
1150 uint8_t RESERVED_0[4];
1151 __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
1152 __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
1153 __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
1154 uint8_t RESERVED_1[4];
1155 __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
1156 __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
1157 __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
1158 uint8_t RESERVED_2[4];
1159 __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
1160 uint8_t RESERVED_3[76];
1161 __IO uint32_t SHIFTCTL[4]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
1162 uint8_t RESERVED_4[112];
1163 __IO uint32_t SHIFTCFG[4]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
1164 uint8_t RESERVED_5[240];
1165 __IO uint32_t SHIFTBUF[4]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
1166 uint8_t RESERVED_6[112];
1167 __IO uint32_t SHIFTBUFBBS[4]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x280, array step: 0x4 */
1168 uint8_t RESERVED_7[112];
1169 __IO uint32_t SHIFTBUFBYS[4]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
1170 uint8_t RESERVED_8[112];
1171 __IO uint32_t SHIFTBUFBIS[4]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x380, array step: 0x4 */
1172 uint8_t RESERVED_9[112];
1173 __IO uint32_t TIMCTL[4]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
1174 uint8_t RESERVED_10[112];
1175 __IO uint32_t TIMCFG[4]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
1176 uint8_t RESERVED_11[112];
1177 __IO uint32_t TIMCMP[4]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
1178 } FLEXIO_Type, *FLEXIO_MemMapPtr;
1179
1180 /* ----------------------------------------------------------------------------
1181 -- FLEXIO - Register accessor macros
1182 ---------------------------------------------------------------------------- */
1183
1184 /*!
1185 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
1186 * @{
1187 */
1188
1189
1190 /* FLEXIO - Register accessors */
1191 #define FLEXIO_VERID_REG(base) ((base)->VERID)
1192 #define FLEXIO_PARAM_REG(base) ((base)->PARAM)
1193 #define FLEXIO_CTRL_REG(base) ((base)->CTRL)
1194 #define FLEXIO_SHIFTSTAT_REG(base) ((base)->SHIFTSTAT)
1195 #define FLEXIO_SHIFTERR_REG(base) ((base)->SHIFTERR)
1196 #define FLEXIO_TIMSTAT_REG(base) ((base)->TIMSTAT)
1197 #define FLEXIO_SHIFTSIEN_REG(base) ((base)->SHIFTSIEN)
1198 #define FLEXIO_SHIFTEIEN_REG(base) ((base)->SHIFTEIEN)
1199 #define FLEXIO_TIMIEN_REG(base) ((base)->TIMIEN)
1200 #define FLEXIO_SHIFTSDEN_REG(base) ((base)->SHIFTSDEN)
1201 #define FLEXIO_SHIFTCTL_REG(base,index) ((base)->SHIFTCTL[index])
1202 #define FLEXIO_SHIFTCFG_REG(base,index) ((base)->SHIFTCFG[index])
1203 #define FLEXIO_SHIFTBUF_REG(base,index) ((base)->SHIFTBUF[index])
1204 #define FLEXIO_SHIFTBUFBBS_REG(base,index) ((base)->SHIFTBUFBBS[index])
1205 #define FLEXIO_SHIFTBUFBYS_REG(base,index) ((base)->SHIFTBUFBYS[index])
1206 #define FLEXIO_SHIFTBUFBIS_REG(base,index) ((base)->SHIFTBUFBIS[index])
1207 #define FLEXIO_TIMCTL_REG(base,index) ((base)->TIMCTL[index])
1208 #define FLEXIO_TIMCFG_REG(base,index) ((base)->TIMCFG[index])
1209 #define FLEXIO_TIMCMP_REG(base,index) ((base)->TIMCMP[index])
1210
1211 /*!
1212 * @}
1213 */ /* end of group FLEXIO_Register_Accessor_Macros */
1214
1215
1216 /* ----------------------------------------------------------------------------
1217 -- FLEXIO Register Masks
1218 ---------------------------------------------------------------------------- */
1219
1220 /*!
1221 * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
1222 * @{
1223 */
1224
1225 /* VERID Bit Fields */
1226 #define FLEXIO_VERID_FEATURE_MASK 0xFFFFu
1227 #define FLEXIO_VERID_FEATURE_SHIFT 0
1228 #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_FEATURE_SHIFT))&FLEXIO_VERID_FEATURE_MASK)
1229 #define FLEXIO_VERID_MINOR_MASK 0xFF0000u
1230 #define FLEXIO_VERID_MINOR_SHIFT 16
1231 #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MINOR_SHIFT))&FLEXIO_VERID_MINOR_MASK)
1232 #define FLEXIO_VERID_MAJOR_MASK 0xFF000000u
1233 #define FLEXIO_VERID_MAJOR_SHIFT 24
1234 #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_VERID_MAJOR_SHIFT))&FLEXIO_VERID_MAJOR_MASK)
1235 /* PARAM Bit Fields */
1236 #define FLEXIO_PARAM_SHIFTER_MASK 0xFFu
1237 #define FLEXIO_PARAM_SHIFTER_SHIFT 0
1238 #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_SHIFTER_SHIFT))&FLEXIO_PARAM_SHIFTER_MASK)
1239 #define FLEXIO_PARAM_TIMER_MASK 0xFF00u
1240 #define FLEXIO_PARAM_TIMER_SHIFT 8
1241 #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TIMER_SHIFT))&FLEXIO_PARAM_TIMER_MASK)
1242 #define FLEXIO_PARAM_PIN_MASK 0xFF0000u
1243 #define FLEXIO_PARAM_PIN_SHIFT 16
1244 #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_PIN_SHIFT))&FLEXIO_PARAM_PIN_MASK)
1245 #define FLEXIO_PARAM_TRIGGER_MASK 0xFF000000u
1246 #define FLEXIO_PARAM_TRIGGER_SHIFT 24
1247 #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_PARAM_TRIGGER_SHIFT))&FLEXIO_PARAM_TRIGGER_MASK)
1248 /* CTRL Bit Fields */
1249 #define FLEXIO_CTRL_FLEXEN_MASK 0x1u
1250 #define FLEXIO_CTRL_FLEXEN_SHIFT 0
1251 #define FLEXIO_CTRL_SWRST_MASK 0x2u
1252 #define FLEXIO_CTRL_SWRST_SHIFT 1
1253 #define FLEXIO_CTRL_FASTACC_MASK 0x4u
1254 #define FLEXIO_CTRL_FASTACC_SHIFT 2
1255 #define FLEXIO_CTRL_DBGE_MASK 0x40000000u
1256 #define FLEXIO_CTRL_DBGE_SHIFT 30
1257 #define FLEXIO_CTRL_DOZEN_MASK 0x80000000u
1258 #define FLEXIO_CTRL_DOZEN_SHIFT 31
1259 /* SHIFTSTAT Bit Fields */
1260 #define FLEXIO_SHIFTSTAT_SSF_MASK 0xFu
1261 #define FLEXIO_SHIFTSTAT_SSF_SHIFT 0
1262 #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSTAT_SSF_SHIFT))&FLEXIO_SHIFTSTAT_SSF_MASK)
1263 /* SHIFTERR Bit Fields */
1264 #define FLEXIO_SHIFTERR_SEF_MASK 0xFu
1265 #define FLEXIO_SHIFTERR_SEF_SHIFT 0
1266 #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTERR_SEF_SHIFT))&FLEXIO_SHIFTERR_SEF_MASK)
1267 /* TIMSTAT Bit Fields */
1268 #define FLEXIO_TIMSTAT_TSF_MASK 0xFu
1269 #define FLEXIO_TIMSTAT_TSF_SHIFT 0
1270 #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMSTAT_TSF_SHIFT))&FLEXIO_TIMSTAT_TSF_MASK)
1271 /* SHIFTSIEN Bit Fields */
1272 #define FLEXIO_SHIFTSIEN_SSIE_MASK 0xFu
1273 #define FLEXIO_SHIFTSIEN_SSIE_SHIFT 0
1274 #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSIEN_SSIE_SHIFT))&FLEXIO_SHIFTSIEN_SSIE_MASK)
1275 /* SHIFTEIEN Bit Fields */
1276 #define FLEXIO_SHIFTEIEN_SEIE_MASK 0xFu
1277 #define FLEXIO_SHIFTEIEN_SEIE_SHIFT 0
1278 #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTEIEN_SEIE_SHIFT))&FLEXIO_SHIFTEIEN_SEIE_MASK)
1279 /* TIMIEN Bit Fields */
1280 #define FLEXIO_TIMIEN_TEIE_MASK 0xFu
1281 #define FLEXIO_TIMIEN_TEIE_SHIFT 0
1282 #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMIEN_TEIE_SHIFT))&FLEXIO_TIMIEN_TEIE_MASK)
1283 /* SHIFTSDEN Bit Fields */
1284 #define FLEXIO_SHIFTSDEN_SSDE_MASK 0xFu
1285 #define FLEXIO_SHIFTSDEN_SSDE_SHIFT 0
1286 #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTSDEN_SSDE_SHIFT))&FLEXIO_SHIFTSDEN_SSDE_MASK)
1287 /* SHIFTCTL Bit Fields */
1288 #define FLEXIO_SHIFTCTL_SMOD_MASK 0x7u
1289 #define FLEXIO_SHIFTCTL_SMOD_SHIFT 0
1290 #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_SMOD_SHIFT))&FLEXIO_SHIFTCTL_SMOD_MASK)
1291 #define FLEXIO_SHIFTCTL_PINPOL_MASK 0x80u
1292 #define FLEXIO_SHIFTCTL_PINPOL_SHIFT 7
1293 #define FLEXIO_SHIFTCTL_PINSEL_MASK 0x700u
1294 #define FLEXIO_SHIFTCTL_PINSEL_SHIFT 8
1295 #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINSEL_SHIFT))&FLEXIO_SHIFTCTL_PINSEL_MASK)
1296 #define FLEXIO_SHIFTCTL_PINCFG_MASK 0x30000u
1297 #define FLEXIO_SHIFTCTL_PINCFG_SHIFT 16
1298 #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_PINCFG_SHIFT))&FLEXIO_SHIFTCTL_PINCFG_MASK)
1299 #define FLEXIO_SHIFTCTL_TIMPOL_MASK 0x800000u
1300 #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT 23
1301 #define FLEXIO_SHIFTCTL_TIMSEL_MASK 0x3000000u
1302 #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT 24
1303 #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCTL_TIMSEL_SHIFT))&FLEXIO_SHIFTCTL_TIMSEL_MASK)
1304 /* SHIFTCFG Bit Fields */
1305 #define FLEXIO_SHIFTCFG_SSTART_MASK 0x3u
1306 #define FLEXIO_SHIFTCFG_SSTART_SHIFT 0
1307 #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTART_SHIFT))&FLEXIO_SHIFTCFG_SSTART_MASK)
1308 #define FLEXIO_SHIFTCFG_SSTOP_MASK 0x30u
1309 #define FLEXIO_SHIFTCFG_SSTOP_SHIFT 4
1310 #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTCFG_SSTOP_SHIFT))&FLEXIO_SHIFTCFG_SSTOP_MASK)
1311 #define FLEXIO_SHIFTCFG_INSRC_MASK 0x100u
1312 #define FLEXIO_SHIFTCFG_INSRC_SHIFT 8
1313 /* SHIFTBUF Bit Fields */
1314 #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK 0xFFFFFFFFu
1315 #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT 0
1316 #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT))&FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
1317 /* SHIFTBUFBBS Bit Fields */
1318 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK 0xFFFFFFFFu
1319 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT 0
1320 #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT))&FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
1321 /* SHIFTBUFBYS Bit Fields */
1322 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK 0xFFFFFFFFu
1323 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT 0
1324 #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT))&FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
1325 /* SHIFTBUFBIS Bit Fields */
1326 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK 0xFFFFFFFFu
1327 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT 0
1328 #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT))&FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
1329 /* TIMCTL Bit Fields */
1330 #define FLEXIO_TIMCTL_TIMOD_MASK 0x3u
1331 #define FLEXIO_TIMCTL_TIMOD_SHIFT 0
1332 #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TIMOD_SHIFT))&FLEXIO_TIMCTL_TIMOD_MASK)
1333 #define FLEXIO_TIMCTL_PINPOL_MASK 0x80u
1334 #define FLEXIO_TIMCTL_PINPOL_SHIFT 7
1335 #define FLEXIO_TIMCTL_PINSEL_MASK 0x700u
1336 #define FLEXIO_TIMCTL_PINSEL_SHIFT 8
1337 #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINSEL_SHIFT))&FLEXIO_TIMCTL_PINSEL_MASK)
1338 #define FLEXIO_TIMCTL_PINCFG_MASK 0x30000u
1339 #define FLEXIO_TIMCTL_PINCFG_SHIFT 16
1340 #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_PINCFG_SHIFT))&FLEXIO_TIMCTL_PINCFG_MASK)
1341 #define FLEXIO_TIMCTL_TRGSRC_MASK 0x400000u
1342 #define FLEXIO_TIMCTL_TRGSRC_SHIFT 22
1343 #define FLEXIO_TIMCTL_TRGPOL_MASK 0x800000u
1344 #define FLEXIO_TIMCTL_TRGPOL_SHIFT 23
1345 #define FLEXIO_TIMCTL_TRGSEL_MASK 0xF000000u
1346 #define FLEXIO_TIMCTL_TRGSEL_SHIFT 24
1347 #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCTL_TRGSEL_SHIFT))&FLEXIO_TIMCTL_TRGSEL_MASK)
1348 /* TIMCFG Bit Fields */
1349 #define FLEXIO_TIMCFG_TSTART_MASK 0x2u
1350 #define FLEXIO_TIMCFG_TSTART_SHIFT 1
1351 #define FLEXIO_TIMCFG_TSTOP_MASK 0x30u
1352 #define FLEXIO_TIMCFG_TSTOP_SHIFT 4
1353 #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TSTOP_SHIFT))&FLEXIO_TIMCFG_TSTOP_MASK)
1354 #define FLEXIO_TIMCFG_TIMENA_MASK 0x700u
1355 #define FLEXIO_TIMCFG_TIMENA_SHIFT 8
1356 #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMENA_SHIFT))&FLEXIO_TIMCFG_TIMENA_MASK)
1357 #define FLEXIO_TIMCFG_TIMDIS_MASK 0x7000u
1358 #define FLEXIO_TIMCFG_TIMDIS_SHIFT 12
1359 #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDIS_SHIFT))&FLEXIO_TIMCFG_TIMDIS_MASK)
1360 #define FLEXIO_TIMCFG_TIMRST_MASK 0x70000u
1361 #define FLEXIO_TIMCFG_TIMRST_SHIFT 16
1362 #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMRST_SHIFT))&FLEXIO_TIMCFG_TIMRST_MASK)
1363 #define FLEXIO_TIMCFG_TIMDEC_MASK 0x300000u
1364 #define FLEXIO_TIMCFG_TIMDEC_SHIFT 20
1365 #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMDEC_SHIFT))&FLEXIO_TIMCFG_TIMDEC_MASK)
1366 #define FLEXIO_TIMCFG_TIMOUT_MASK 0x3000000u
1367 #define FLEXIO_TIMCFG_TIMOUT_SHIFT 24
1368 #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCFG_TIMOUT_SHIFT))&FLEXIO_TIMCFG_TIMOUT_MASK)
1369 /* TIMCMP Bit Fields */
1370 #define FLEXIO_TIMCMP_CMP_MASK 0xFFFFu
1371 #define FLEXIO_TIMCMP_CMP_SHIFT 0
1372 #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x))<<FLEXIO_TIMCMP_CMP_SHIFT))&FLEXIO_TIMCMP_CMP_MASK)
1373
1374 /*!
1375 * @}
1376 */ /* end of group FLEXIO_Register_Masks */
1377
1378
1379 /* FLEXIO - Peripheral instance base addresses */
1380 /** Peripheral FLEXIO base address */
1381 #define FLEXIO_BASE (0x4005F000u)
1382 /** Peripheral FLEXIO base pointer */
1383 #define FLEXIO ((FLEXIO_Type *)FLEXIO_BASE)
1384 #define FLEXIO_BASE_PTR (FLEXIO)
1385 /** Array initializer of FLEXIO peripheral base addresses */
1386 #define FLEXIO_BASE_ADDRS { FLEXIO_BASE }
1387 /** Array initializer of FLEXIO peripheral base pointers */
1388 #define FLEXIO_BASE_PTRS { FLEXIO }
1389
1390 /* ----------------------------------------------------------------------------
1391 -- FLEXIO - Register accessor macros
1392 ---------------------------------------------------------------------------- */
1393
1394 /*!
1395 * @addtogroup FLEXIO_Register_Accessor_Macros FLEXIO - Register accessor macros
1396 * @{
1397 */
1398
1399
1400 /* FLEXIO - Register instance definitions */
1401 /* FLEXIO */
1402 #define FLEXIO_VERID FLEXIO_VERID_REG(FLEXIO)
1403 #define FLEXIO_PARAM FLEXIO_PARAM_REG(FLEXIO)
1404 #define FLEXIO_CTRL FLEXIO_CTRL_REG(FLEXIO)
1405 #define FLEXIO_SHIFTSTAT FLEXIO_SHIFTSTAT_REG(FLEXIO)
1406 #define FLEXIO_SHIFTERR FLEXIO_SHIFTERR_REG(FLEXIO)
1407 #define FLEXIO_TIMSTAT FLEXIO_TIMSTAT_REG(FLEXIO)
1408 #define FLEXIO_SHIFTSIEN FLEXIO_SHIFTSIEN_REG(FLEXIO)
1409 #define FLEXIO_SHIFTEIEN FLEXIO_SHIFTEIEN_REG(FLEXIO)
1410 #define FLEXIO_TIMIEN FLEXIO_TIMIEN_REG(FLEXIO)
1411 #define FLEXIO_SHIFTSDEN FLEXIO_SHIFTSDEN_REG(FLEXIO)
1412 #define FLEXIO_SHIFTCTL0 FLEXIO_SHIFTCTL_REG(FLEXIO,0)
1413 #define FLEXIO_SHIFTCTL1 FLEXIO_SHIFTCTL_REG(FLEXIO,1)
1414 #define FLEXIO_SHIFTCTL2 FLEXIO_SHIFTCTL_REG(FLEXIO,2)
1415 #define FLEXIO_SHIFTCTL3 FLEXIO_SHIFTCTL_REG(FLEXIO,3)
1416 #define FLEXIO_SHIFTCFG0 FLEXIO_SHIFTCFG_REG(FLEXIO,0)
1417 #define FLEXIO_SHIFTCFG1 FLEXIO_SHIFTCFG_REG(FLEXIO,1)
1418 #define FLEXIO_SHIFTCFG2 FLEXIO_SHIFTCFG_REG(FLEXIO,2)
1419 #define FLEXIO_SHIFTCFG3 FLEXIO_SHIFTCFG_REG(FLEXIO,3)
1420 #define FLEXIO_SHIFTBUF0 FLEXIO_SHIFTBUF_REG(FLEXIO,0)
1421 #define FLEXIO_SHIFTBUF1 FLEXIO_SHIFTBUF_REG(FLEXIO,1)
1422 #define FLEXIO_SHIFTBUF2 FLEXIO_SHIFTBUF_REG(FLEXIO,2)
1423 #define FLEXIO_SHIFTBUF3 FLEXIO_SHIFTBUF_REG(FLEXIO,3)
1424 #define FLEXIO_SHIFTBUFBBS0 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,0)
1425 #define FLEXIO_SHIFTBUFBBS1 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,1)
1426 #define FLEXIO_SHIFTBUFBBS2 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,2)
1427 #define FLEXIO_SHIFTBUFBBS3 FLEXIO_SHIFTBUFBBS_REG(FLEXIO,3)
1428 #define FLEXIO_SHIFTBUFBYS0 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,0)
1429 #define FLEXIO_SHIFTBUFBYS1 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,1)
1430 #define FLEXIO_SHIFTBUFBYS2 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,2)
1431 #define FLEXIO_SHIFTBUFBYS3 FLEXIO_SHIFTBUFBYS_REG(FLEXIO,3)
1432 #define FLEXIO_SHIFTBUFBIS0 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,0)
1433 #define FLEXIO_SHIFTBUFBIS1 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,1)
1434 #define FLEXIO_SHIFTBUFBIS2 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,2)
1435 #define FLEXIO_SHIFTBUFBIS3 FLEXIO_SHIFTBUFBIS_REG(FLEXIO,3)
1436 #define FLEXIO_TIMCTL0 FLEXIO_TIMCTL_REG(FLEXIO,0)
1437 #define FLEXIO_TIMCTL1 FLEXIO_TIMCTL_REG(FLEXIO,1)
1438 #define FLEXIO_TIMCTL2 FLEXIO_TIMCTL_REG(FLEXIO,2)
1439 #define FLEXIO_TIMCTL3 FLEXIO_TIMCTL_REG(FLEXIO,3)
1440 #define FLEXIO_TIMCFG0 FLEXIO_TIMCFG_REG(FLEXIO,0)
1441 #define FLEXIO_TIMCFG1 FLEXIO_TIMCFG_REG(FLEXIO,1)
1442 #define FLEXIO_TIMCFG2 FLEXIO_TIMCFG_REG(FLEXIO,2)
1443 #define FLEXIO_TIMCFG3 FLEXIO_TIMCFG_REG(FLEXIO,3)
1444 #define FLEXIO_TIMCMP0 FLEXIO_TIMCMP_REG(FLEXIO,0)
1445 #define FLEXIO_TIMCMP1 FLEXIO_TIMCMP_REG(FLEXIO,1)
1446 #define FLEXIO_TIMCMP2 FLEXIO_TIMCMP_REG(FLEXIO,2)
1447 #define FLEXIO_TIMCMP3 FLEXIO_TIMCMP_REG(FLEXIO,3)
1448
1449 /* FLEXIO - Register array accessors */
1450 #define FLEXIO_SHIFTCTL(index) FLEXIO_SHIFTCTL_REG(FLEXIO,index)
1451 #define FLEXIO_SHIFTCFG(index) FLEXIO_SHIFTCFG_REG(FLEXIO,index)
1452 #define FLEXIO_SHIFTBUF(index) FLEXIO_SHIFTBUF_REG(FLEXIO,index)
1453 #define FLEXIO_SHIFTBUFBBS(index) FLEXIO_SHIFTBUFBBS_REG(FLEXIO,index)
1454 #define FLEXIO_SHIFTBUFBYS(index) FLEXIO_SHIFTBUFBYS_REG(FLEXIO,index)
1455 #define FLEXIO_SHIFTBUFBIS(index) FLEXIO_SHIFTBUFBIS_REG(FLEXIO,index)
1456 #define FLEXIO_TIMCTL(index) FLEXIO_TIMCTL_REG(FLEXIO,index)
1457 #define FLEXIO_TIMCFG(index) FLEXIO_TIMCFG_REG(FLEXIO,index)
1458 #define FLEXIO_TIMCMP(index) FLEXIO_TIMCMP_REG(FLEXIO,index)
1459
1460 /*!
1461 * @}
1462 */ /* end of group FLEXIO_Register_Accessor_Macros */
1463
1464
1465 /*!
1466 * @}
1467 */ /* end of group FLEXIO_Peripheral_Access_Layer */
1468
1469
1470 /* ----------------------------------------------------------------------------
1471 -- FTFA Peripheral Access Layer
1472 ---------------------------------------------------------------------------- */
1473
1474 /*!
1475 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
1476 * @{
1477 */
1478
1479 /** FTFA - Register Layout Typedef */
1480 typedef struct {
1481 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
1482 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
1483 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
1484 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
1485 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
1486 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
1487 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
1488 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
1489 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
1490 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
1491 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
1492 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
1493 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
1494 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
1495 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
1496 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
1497 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
1498 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
1499 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
1500 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
1501 } FTFA_Type, *FTFA_MemMapPtr;
1502
1503 /* ----------------------------------------------------------------------------
1504 -- FTFA - Register accessor macros
1505 ---------------------------------------------------------------------------- */
1506
1507 /*!
1508 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
1509 * @{
1510 */
1511
1512
1513 /* FTFA - Register accessors */
1514 #define FTFA_FSTAT_REG(base) ((base)->FSTAT)
1515 #define FTFA_FCNFG_REG(base) ((base)->FCNFG)
1516 #define FTFA_FSEC_REG(base) ((base)->FSEC)
1517 #define FTFA_FOPT_REG(base) ((base)->FOPT)
1518 #define FTFA_FCCOB3_REG(base) ((base)->FCCOB3)
1519 #define FTFA_FCCOB2_REG(base) ((base)->FCCOB2)
1520 #define FTFA_FCCOB1_REG(base) ((base)->FCCOB1)
1521 #define FTFA_FCCOB0_REG(base) ((base)->FCCOB0)
1522 #define FTFA_FCCOB7_REG(base) ((base)->FCCOB7)
1523 #define FTFA_FCCOB6_REG(base) ((base)->FCCOB6)
1524 #define FTFA_FCCOB5_REG(base) ((base)->FCCOB5)
1525 #define FTFA_FCCOB4_REG(base) ((base)->FCCOB4)
1526 #define FTFA_FCCOBB_REG(base) ((base)->FCCOBB)
1527 #define FTFA_FCCOBA_REG(base) ((base)->FCCOBA)
1528 #define FTFA_FCCOB9_REG(base) ((base)->FCCOB9)
1529 #define FTFA_FCCOB8_REG(base) ((base)->FCCOB8)
1530 #define FTFA_FPROT3_REG(base) ((base)->FPROT3)
1531 #define FTFA_FPROT2_REG(base) ((base)->FPROT2)
1532 #define FTFA_FPROT1_REG(base) ((base)->FPROT1)
1533 #define FTFA_FPROT0_REG(base) ((base)->FPROT0)
1534
1535 /*!
1536 * @}
1537 */ /* end of group FTFA_Register_Accessor_Macros */
1538
1539
1540 /* ----------------------------------------------------------------------------
1541 -- FTFA Register Masks
1542 ---------------------------------------------------------------------------- */
1543
1544 /*!
1545 * @addtogroup FTFA_Register_Masks FTFA Register Masks
1546 * @{
1547 */
1548
1549 /* FSTAT Bit Fields */
1550 #define FTFA_FSTAT_MGSTAT0_MASK 0x1u
1551 #define FTFA_FSTAT_MGSTAT0_SHIFT 0
1552 #define FTFA_FSTAT_FPVIOL_MASK 0x10u
1553 #define FTFA_FSTAT_FPVIOL_SHIFT 4
1554 #define FTFA_FSTAT_ACCERR_MASK 0x20u
1555 #define FTFA_FSTAT_ACCERR_SHIFT 5
1556 #define FTFA_FSTAT_RDCOLERR_MASK 0x40u
1557 #define FTFA_FSTAT_RDCOLERR_SHIFT 6
1558 #define FTFA_FSTAT_CCIF_MASK 0x80u
1559 #define FTFA_FSTAT_CCIF_SHIFT 7
1560 /* FCNFG Bit Fields */
1561 #define FTFA_FCNFG_ERSSUSP_MASK 0x10u
1562 #define FTFA_FCNFG_ERSSUSP_SHIFT 4
1563 #define FTFA_FCNFG_ERSAREQ_MASK 0x20u
1564 #define FTFA_FCNFG_ERSAREQ_SHIFT 5
1565 #define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
1566 #define FTFA_FCNFG_RDCOLLIE_SHIFT 6
1567 #define FTFA_FCNFG_CCIE_MASK 0x80u
1568 #define FTFA_FCNFG_CCIE_SHIFT 7
1569 /* FSEC Bit Fields */
1570 #define FTFA_FSEC_SEC_MASK 0x3u
1571 #define FTFA_FSEC_SEC_SHIFT 0
1572 #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
1573 #define FTFA_FSEC_FSLACC_MASK 0xCu
1574 #define FTFA_FSEC_FSLACC_SHIFT 2
1575 #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
1576 #define FTFA_FSEC_MEEN_MASK 0x30u
1577 #define FTFA_FSEC_MEEN_SHIFT 4
1578 #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
1579 #define FTFA_FSEC_KEYEN_MASK 0xC0u
1580 #define FTFA_FSEC_KEYEN_SHIFT 6
1581 #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
1582 /* FOPT Bit Fields */
1583 #define FTFA_FOPT_OPT_MASK 0xFFu
1584 #define FTFA_FOPT_OPT_SHIFT 0
1585 #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
1586 /* FCCOB3 Bit Fields */
1587 #define FTFA_FCCOB3_CCOBn_MASK 0xFFu
1588 #define FTFA_FCCOB3_CCOBn_SHIFT 0
1589 #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
1590 /* FCCOB2 Bit Fields */
1591 #define FTFA_FCCOB2_CCOBn_MASK 0xFFu
1592 #define FTFA_FCCOB2_CCOBn_SHIFT 0
1593 #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
1594 /* FCCOB1 Bit Fields */
1595 #define FTFA_FCCOB1_CCOBn_MASK 0xFFu
1596 #define FTFA_FCCOB1_CCOBn_SHIFT 0
1597 #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
1598 /* FCCOB0 Bit Fields */
1599 #define FTFA_FCCOB0_CCOBn_MASK 0xFFu
1600 #define FTFA_FCCOB0_CCOBn_SHIFT 0
1601 #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
1602 /* FCCOB7 Bit Fields */
1603 #define FTFA_FCCOB7_CCOBn_MASK 0xFFu
1604 #define FTFA_FCCOB7_CCOBn_SHIFT 0
1605 #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
1606 /* FCCOB6 Bit Fields */
1607 #define FTFA_FCCOB6_CCOBn_MASK 0xFFu
1608 #define FTFA_FCCOB6_CCOBn_SHIFT 0
1609 #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
1610 /* FCCOB5 Bit Fields */
1611 #define FTFA_FCCOB5_CCOBn_MASK 0xFFu
1612 #define FTFA_FCCOB5_CCOBn_SHIFT 0
1613 #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
1614 /* FCCOB4 Bit Fields */
1615 #define FTFA_FCCOB4_CCOBn_MASK 0xFFu
1616 #define FTFA_FCCOB4_CCOBn_SHIFT 0
1617 #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
1618 /* FCCOBB Bit Fields */
1619 #define FTFA_FCCOBB_CCOBn_MASK 0xFFu
1620 #define FTFA_FCCOBB_CCOBn_SHIFT 0
1621 #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
1622 /* FCCOBA Bit Fields */
1623 #define FTFA_FCCOBA_CCOBn_MASK 0xFFu
1624 #define FTFA_FCCOBA_CCOBn_SHIFT 0
1625 #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
1626 /* FCCOB9 Bit Fields */
1627 #define FTFA_FCCOB9_CCOBn_MASK 0xFFu
1628 #define FTFA_FCCOB9_CCOBn_SHIFT 0
1629 #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
1630 /* FCCOB8 Bit Fields */
1631 #define FTFA_FCCOB8_CCOBn_MASK 0xFFu
1632 #define FTFA_FCCOB8_CCOBn_SHIFT 0
1633 #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
1634 /* FPROT3 Bit Fields */
1635 #define FTFA_FPROT3_PROT_MASK 0xFFu
1636 #define FTFA_FPROT3_PROT_SHIFT 0
1637 #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
1638 /* FPROT2 Bit Fields */
1639 #define FTFA_FPROT2_PROT_MASK 0xFFu
1640 #define FTFA_FPROT2_PROT_SHIFT 0
1641 #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
1642 /* FPROT1 Bit Fields */
1643 #define FTFA_FPROT1_PROT_MASK 0xFFu
1644 #define FTFA_FPROT1_PROT_SHIFT 0
1645 #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
1646 /* FPROT0 Bit Fields */
1647 #define FTFA_FPROT0_PROT_MASK 0xFFu
1648 #define FTFA_FPROT0_PROT_SHIFT 0
1649 #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
1650
1651 /*!
1652 * @}
1653 */ /* end of group FTFA_Register_Masks */
1654
1655
1656 /* FTFA - Peripheral instance base addresses */
1657 /** Peripheral FTFA base address */
1658 #define FTFA_BASE (0x40020000u)
1659 /** Peripheral FTFA base pointer */
1660 #define FTFA ((FTFA_Type *)FTFA_BASE)
1661 #define FTFA_BASE_PTR (FTFA)
1662 /** Array initializer of FTFA peripheral base addresses */
1663 #define FTFA_BASE_ADDRS { FTFA_BASE }
1664 /** Array initializer of FTFA peripheral base pointers */
1665 #define FTFA_BASE_PTRS { FTFA }
1666 /** Interrupt vectors for the FTFA peripheral type */
1667 #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn }
1668
1669 /* ----------------------------------------------------------------------------
1670 -- FTFA - Register accessor macros
1671 ---------------------------------------------------------------------------- */
1672
1673 /*!
1674 * @addtogroup FTFA_Register_Accessor_Macros FTFA - Register accessor macros
1675 * @{
1676 */
1677
1678
1679 /* FTFA - Register instance definitions */
1680 /* FTFA */
1681 #define FTFA_FSTAT FTFA_FSTAT_REG(FTFA)
1682 #define FTFA_FCNFG FTFA_FCNFG_REG(FTFA)
1683 #define FTFA_FSEC FTFA_FSEC_REG(FTFA)
1684 #define FTFA_FOPT FTFA_FOPT_REG(FTFA)
1685 #define FTFA_FCCOB3 FTFA_FCCOB3_REG(FTFA)
1686 #define FTFA_FCCOB2 FTFA_FCCOB2_REG(FTFA)
1687 #define FTFA_FCCOB1 FTFA_FCCOB1_REG(FTFA)
1688 #define FTFA_FCCOB0 FTFA_FCCOB0_REG(FTFA)
1689 #define FTFA_FCCOB7 FTFA_FCCOB7_REG(FTFA)
1690 #define FTFA_FCCOB6 FTFA_FCCOB6_REG(FTFA)
1691 #define FTFA_FCCOB5 FTFA_FCCOB5_REG(FTFA)
1692 #define FTFA_FCCOB4 FTFA_FCCOB4_REG(FTFA)
1693 #define FTFA_FCCOBB FTFA_FCCOBB_REG(FTFA)
1694 #define FTFA_FCCOBA FTFA_FCCOBA_REG(FTFA)
1695 #define FTFA_FCCOB9 FTFA_FCCOB9_REG(FTFA)
1696 #define FTFA_FCCOB8 FTFA_FCCOB8_REG(FTFA)
1697 #define FTFA_FPROT3 FTFA_FPROT3_REG(FTFA)
1698 #define FTFA_FPROT2 FTFA_FPROT2_REG(FTFA)
1699 #define FTFA_FPROT1 FTFA_FPROT1_REG(FTFA)
1700 #define FTFA_FPROT0 FTFA_FPROT0_REG(FTFA)
1701
1702 /*!
1703 * @}
1704 */ /* end of group FTFA_Register_Accessor_Macros */
1705
1706
1707 /*!
1708 * @}
1709 */ /* end of group FTFA_Peripheral_Access_Layer */
1710
1711
1712 /* ----------------------------------------------------------------------------
1713 -- GPIO Peripheral Access Layer
1714 ---------------------------------------------------------------------------- */
1715
1716 /*!
1717 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
1718 * @{
1719 */
1720
1721 /** GPIO - Register Layout Typedef */
1722 typedef struct {
1723 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
1724 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
1725 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
1726 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
1727 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
1728 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
1729 } GPIO_Type, *GPIO_MemMapPtr;
1730
1731 /* ----------------------------------------------------------------------------
1732 -- GPIO - Register accessor macros
1733 ---------------------------------------------------------------------------- */
1734
1735 /*!
1736 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
1737 * @{
1738 */
1739
1740
1741 /* GPIO - Register accessors */
1742 #define GPIO_PDOR_REG(base) ((base)->PDOR)
1743 #define GPIO_PSOR_REG(base) ((base)->PSOR)
1744 #define GPIO_PCOR_REG(base) ((base)->PCOR)
1745 #define GPIO_PTOR_REG(base) ((base)->PTOR)
1746 #define GPIO_PDIR_REG(base) ((base)->PDIR)
1747 #define GPIO_PDDR_REG(base) ((base)->PDDR)
1748
1749 /*!
1750 * @}
1751 */ /* end of group GPIO_Register_Accessor_Macros */
1752
1753
1754 /* ----------------------------------------------------------------------------
1755 -- GPIO Register Masks
1756 ---------------------------------------------------------------------------- */
1757
1758 /*!
1759 * @addtogroup GPIO_Register_Masks GPIO Register Masks
1760 * @{
1761 */
1762
1763 /* PDOR Bit Fields */
1764 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
1765 #define GPIO_PDOR_PDO_SHIFT 0
1766 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
1767 /* PSOR Bit Fields */
1768 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
1769 #define GPIO_PSOR_PTSO_SHIFT 0
1770 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
1771 /* PCOR Bit Fields */
1772 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
1773 #define GPIO_PCOR_PTCO_SHIFT 0
1774 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
1775 /* PTOR Bit Fields */
1776 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
1777 #define GPIO_PTOR_PTTO_SHIFT 0
1778 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
1779 /* PDIR Bit Fields */
1780 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
1781 #define GPIO_PDIR_PDI_SHIFT 0
1782 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
1783 /* PDDR Bit Fields */
1784 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
1785 #define GPIO_PDDR_PDD_SHIFT 0
1786 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
1787
1788 /*!
1789 * @}
1790 */ /* end of group GPIO_Register_Masks */
1791
1792
1793 /* GPIO - Peripheral instance base addresses */
1794 /** Peripheral GPIOA base address */
1795 #define GPIOA_BASE (0x400FF000u)
1796 /** Peripheral GPIOA base pointer */
1797 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
1798 #define GPIOA_BASE_PTR (GPIOA)
1799 /** Peripheral GPIOB base address */
1800 #define GPIOB_BASE (0x400FF040u)
1801 /** Peripheral GPIOB base pointer */
1802 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
1803 #define GPIOB_BASE_PTR (GPIOB)
1804 /** Peripheral GPIOC base address */
1805 #define GPIOC_BASE (0x400FF080u)
1806 /** Peripheral GPIOC base pointer */
1807 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
1808 #define GPIOC_BASE_PTR (GPIOC)
1809 /** Peripheral GPIOD base address */
1810 #define GPIOD_BASE (0x400FF0C0u)
1811 /** Peripheral GPIOD base pointer */
1812 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
1813 #define GPIOD_BASE_PTR (GPIOD)
1814 /** Peripheral GPIOE base address */
1815 #define GPIOE_BASE (0x400FF100u)
1816 /** Peripheral GPIOE base pointer */
1817 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
1818 #define GPIOE_BASE_PTR (GPIOE)
1819 /** Array initializer of GPIO peripheral base addresses */
1820 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
1821 /** Array initializer of GPIO peripheral base pointers */
1822 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
1823
1824 /* ----------------------------------------------------------------------------
1825 -- GPIO - Register accessor macros
1826 ---------------------------------------------------------------------------- */
1827
1828 /*!
1829 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
1830 * @{
1831 */
1832
1833
1834 /* GPIO - Register instance definitions */
1835 /* GPIOA */
1836 #define GPIOA_PDOR GPIO_PDOR_REG(GPIOA)
1837 #define GPIOA_PSOR GPIO_PSOR_REG(GPIOA)
1838 #define GPIOA_PCOR GPIO_PCOR_REG(GPIOA)
1839 #define GPIOA_PTOR GPIO_PTOR_REG(GPIOA)
1840 #define GPIOA_PDIR GPIO_PDIR_REG(GPIOA)
1841 #define GPIOA_PDDR GPIO_PDDR_REG(GPIOA)
1842 /* GPIOB */
1843 #define GPIOB_PDOR GPIO_PDOR_REG(GPIOB)
1844 #define GPIOB_PSOR GPIO_PSOR_REG(GPIOB)
1845 #define GPIOB_PCOR GPIO_PCOR_REG(GPIOB)
1846 #define GPIOB_PTOR GPIO_PTOR_REG(GPIOB)
1847 #define GPIOB_PDIR GPIO_PDIR_REG(GPIOB)
1848 #define GPIOB_PDDR GPIO_PDDR_REG(GPIOB)
1849 /* GPIOC */
1850 #define GPIOC_PDOR GPIO_PDOR_REG(GPIOC)
1851 #define GPIOC_PSOR GPIO_PSOR_REG(GPIOC)
1852 #define GPIOC_PCOR GPIO_PCOR_REG(GPIOC)
1853 #define GPIOC_PTOR GPIO_PTOR_REG(GPIOC)
1854 #define GPIOC_PDIR GPIO_PDIR_REG(GPIOC)
1855 #define GPIOC_PDDR GPIO_PDDR_REG(GPIOC)
1856 /* GPIOD */
1857 #define GPIOD_PDOR GPIO_PDOR_REG(GPIOD)
1858 #define GPIOD_PSOR GPIO_PSOR_REG(GPIOD)
1859 #define GPIOD_PCOR GPIO_PCOR_REG(GPIOD)
1860 #define GPIOD_PTOR GPIO_PTOR_REG(GPIOD)
1861 #define GPIOD_PDIR GPIO_PDIR_REG(GPIOD)
1862 #define GPIOD_PDDR GPIO_PDDR_REG(GPIOD)
1863 /* GPIOE */
1864 #define GPIOE_PDOR GPIO_PDOR_REG(GPIOE)
1865 #define GPIOE_PSOR GPIO_PSOR_REG(GPIOE)
1866 #define GPIOE_PCOR GPIO_PCOR_REG(GPIOE)
1867 #define GPIOE_PTOR GPIO_PTOR_REG(GPIOE)
1868 #define GPIOE_PDIR GPIO_PDIR_REG(GPIOE)
1869 #define GPIOE_PDDR GPIO_PDDR_REG(GPIOE)
1870
1871 /*!
1872 * @}
1873 */ /* end of group GPIO_Register_Accessor_Macros */
1874
1875
1876 /*!
1877 * @}
1878 */ /* end of group GPIO_Peripheral_Access_Layer */
1879
1880
1881 /* ----------------------------------------------------------------------------
1882 -- I2C Peripheral Access Layer
1883 ---------------------------------------------------------------------------- */
1884
1885 /*!
1886 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
1887 * @{
1888 */
1889
1890 /** I2C - Register Layout Typedef */
1891 typedef struct {
1892 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
1893 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
1894 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
1895 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
1896 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
1897 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
1898 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
1899 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
1900 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
1901 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
1902 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
1903 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
1904 __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */
1905 } I2C_Type, *I2C_MemMapPtr;
1906
1907 /* ----------------------------------------------------------------------------
1908 -- I2C - Register accessor macros
1909 ---------------------------------------------------------------------------- */
1910
1911 /*!
1912 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
1913 * @{
1914 */
1915
1916
1917 /* I2C - Register accessors */
1918 #define I2C_A1_REG(base) ((base)->A1)
1919 #define I2C_F_REG(base) ((base)->F)
1920 #define I2C_C1_REG(base) ((base)->C1)
1921 #define I2C_S_REG(base) ((base)->S)
1922 #define I2C_D_REG(base) ((base)->D)
1923 #define I2C_C2_REG(base) ((base)->C2)
1924 #define I2C_FLT_REG(base) ((base)->FLT)
1925 #define I2C_RA_REG(base) ((base)->RA)
1926 #define I2C_SMB_REG(base) ((base)->SMB)
1927 #define I2C_A2_REG(base) ((base)->A2)
1928 #define I2C_SLTH_REG(base) ((base)->SLTH)
1929 #define I2C_SLTL_REG(base) ((base)->SLTL)
1930 #define I2C_S2_REG(base) ((base)->S2)
1931
1932 /*!
1933 * @}
1934 */ /* end of group I2C_Register_Accessor_Macros */
1935
1936
1937 /* ----------------------------------------------------------------------------
1938 -- I2C Register Masks
1939 ---------------------------------------------------------------------------- */
1940
1941 /*!
1942 * @addtogroup I2C_Register_Masks I2C Register Masks
1943 * @{
1944 */
1945
1946 /* A1 Bit Fields */
1947 #define I2C_A1_AD_MASK 0xFEu
1948 #define I2C_A1_AD_SHIFT 1
1949 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
1950 /* F Bit Fields */
1951 #define I2C_F_ICR_MASK 0x3Fu
1952 #define I2C_F_ICR_SHIFT 0
1953 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
1954 #define I2C_F_MULT_MASK 0xC0u
1955 #define I2C_F_MULT_SHIFT 6
1956 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
1957 /* C1 Bit Fields */
1958 #define I2C_C1_DMAEN_MASK 0x1u
1959 #define I2C_C1_DMAEN_SHIFT 0
1960 #define I2C_C1_WUEN_MASK 0x2u
1961 #define I2C_C1_WUEN_SHIFT 1
1962 #define I2C_C1_RSTA_MASK 0x4u
1963 #define I2C_C1_RSTA_SHIFT 2
1964 #define I2C_C1_TXAK_MASK 0x8u
1965 #define I2C_C1_TXAK_SHIFT 3
1966 #define I2C_C1_TX_MASK 0x10u
1967 #define I2C_C1_TX_SHIFT 4
1968 #define I2C_C1_MST_MASK 0x20u
1969 #define I2C_C1_MST_SHIFT 5
1970 #define I2C_C1_IICIE_MASK 0x40u
1971 #define I2C_C1_IICIE_SHIFT 6
1972 #define I2C_C1_IICEN_MASK 0x80u
1973 #define I2C_C1_IICEN_SHIFT 7
1974 /* S Bit Fields */
1975 #define I2C_S_RXAK_MASK 0x1u
1976 #define I2C_S_RXAK_SHIFT 0
1977 #define I2C_S_IICIF_MASK 0x2u
1978 #define I2C_S_IICIF_SHIFT 1
1979 #define I2C_S_SRW_MASK 0x4u
1980 #define I2C_S_SRW_SHIFT 2
1981 #define I2C_S_RAM_MASK 0x8u
1982 #define I2C_S_RAM_SHIFT 3
1983 #define I2C_S_ARBL_MASK 0x10u
1984 #define I2C_S_ARBL_SHIFT 4
1985 #define I2C_S_BUSY_MASK 0x20u
1986 #define I2C_S_BUSY_SHIFT 5
1987 #define I2C_S_IAAS_MASK 0x40u
1988 #define I2C_S_IAAS_SHIFT 6
1989 #define I2C_S_TCF_MASK 0x80u
1990 #define I2C_S_TCF_SHIFT 7
1991 /* D Bit Fields */
1992 #define I2C_D_DATA_MASK 0xFFu
1993 #define I2C_D_DATA_SHIFT 0
1994 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
1995 /* C2 Bit Fields */
1996 #define I2C_C2_AD_MASK 0x7u
1997 #define I2C_C2_AD_SHIFT 0
1998 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
1999 #define I2C_C2_RMEN_MASK 0x8u
2000 #define I2C_C2_RMEN_SHIFT 3
2001 #define I2C_C2_SBRC_MASK 0x10u
2002 #define I2C_C2_SBRC_SHIFT 4
2003 #define I2C_C2_HDRS_MASK 0x20u
2004 #define I2C_C2_HDRS_SHIFT 5
2005 #define I2C_C2_ADEXT_MASK 0x40u
2006 #define I2C_C2_ADEXT_SHIFT 6
2007 #define I2C_C2_GCAEN_MASK 0x80u
2008 #define I2C_C2_GCAEN_SHIFT 7
2009 /* FLT Bit Fields */
2010 #define I2C_FLT_FLT_MASK 0xFu
2011 #define I2C_FLT_FLT_SHIFT 0
2012 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
2013 #define I2C_FLT_STARTF_MASK 0x10u
2014 #define I2C_FLT_STARTF_SHIFT 4
2015 #define I2C_FLT_SSIE_MASK 0x20u
2016 #define I2C_FLT_SSIE_SHIFT 5
2017 #define I2C_FLT_STOPF_MASK 0x40u
2018 #define I2C_FLT_STOPF_SHIFT 6
2019 #define I2C_FLT_SHEN_MASK 0x80u
2020 #define I2C_FLT_SHEN_SHIFT 7
2021 /* RA Bit Fields */
2022 #define I2C_RA_RAD_MASK 0xFEu
2023 #define I2C_RA_RAD_SHIFT 1
2024 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
2025 /* SMB Bit Fields */
2026 #define I2C_SMB_SHTF2IE_MASK 0x1u
2027 #define I2C_SMB_SHTF2IE_SHIFT 0
2028 #define I2C_SMB_SHTF2_MASK 0x2u
2029 #define I2C_SMB_SHTF2_SHIFT 1
2030 #define I2C_SMB_SHTF1_MASK 0x4u
2031 #define I2C_SMB_SHTF1_SHIFT 2
2032 #define I2C_SMB_SLTF_MASK 0x8u
2033 #define I2C_SMB_SLTF_SHIFT 3
2034 #define I2C_SMB_TCKSEL_MASK 0x10u
2035 #define I2C_SMB_TCKSEL_SHIFT 4
2036 #define I2C_SMB_SIICAEN_MASK 0x20u
2037 #define I2C_SMB_SIICAEN_SHIFT 5
2038 #define I2C_SMB_ALERTEN_MASK 0x40u
2039 #define I2C_SMB_ALERTEN_SHIFT 6
2040 #define I2C_SMB_FACK_MASK 0x80u
2041 #define I2C_SMB_FACK_SHIFT 7
2042 /* A2 Bit Fields */
2043 #define I2C_A2_SAD_MASK 0xFEu
2044 #define I2C_A2_SAD_SHIFT 1
2045 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
2046 /* SLTH Bit Fields */
2047 #define I2C_SLTH_SSLT_MASK 0xFFu
2048 #define I2C_SLTH_SSLT_SHIFT 0
2049 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
2050 /* SLTL Bit Fields */
2051 #define I2C_SLTL_SSLT_MASK 0xFFu
2052 #define I2C_SLTL_SSLT_SHIFT 0
2053 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
2054 /* S2 Bit Fields */
2055 #define I2C_S2_EMPTY_MASK 0x1u
2056 #define I2C_S2_EMPTY_SHIFT 0
2057 #define I2C_S2_ERROR_MASK 0x2u
2058 #define I2C_S2_ERROR_SHIFT 1
2059
2060 /*!
2061 * @}
2062 */ /* end of group I2C_Register_Masks */
2063
2064
2065 /* I2C - Peripheral instance base addresses */
2066 /** Peripheral I2C0 base address */
2067 #define I2C0_BASE (0x40066000u)
2068 /** Peripheral I2C0 base pointer */
2069 #define I2C0 ((I2C_Type *)I2C0_BASE)
2070 #define I2C0_BASE_PTR (I2C0)
2071 /** Peripheral I2C1 base address */
2072 #define I2C1_BASE (0x40067000u)
2073 /** Peripheral I2C1 base pointer */
2074 #define I2C1 ((I2C_Type *)I2C1_BASE)
2075 #define I2C1_BASE_PTR (I2C1)
2076 /** Array initializer of I2C peripheral base addresses */
2077 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
2078 /** Array initializer of I2C peripheral base pointers */
2079 #define I2C_BASE_PTRS { I2C0, I2C1 }
2080 /** Interrupt vectors for the I2C peripheral type */
2081 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
2082
2083 /* ----------------------------------------------------------------------------
2084 -- I2C - Register accessor macros
2085 ---------------------------------------------------------------------------- */
2086
2087 /*!
2088 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
2089 * @{
2090 */
2091
2092
2093 /* I2C - Register instance definitions */
2094 /* I2C0 */
2095 #define I2C0_A1 I2C_A1_REG(I2C0)
2096 #define I2C0_F I2C_F_REG(I2C0)
2097 #define I2C0_C1 I2C_C1_REG(I2C0)
2098 #define I2C0_S I2C_S_REG(I2C0)
2099 #define I2C0_D I2C_D_REG(I2C0)
2100 #define I2C0_C2 I2C_C2_REG(I2C0)
2101 #define I2C0_FLT I2C_FLT_REG(I2C0)
2102 #define I2C0_RA I2C_RA_REG(I2C0)
2103 #define I2C0_SMB I2C_SMB_REG(I2C0)
2104 #define I2C0_A2 I2C_A2_REG(I2C0)
2105 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
2106 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
2107 #define I2C0_S2 I2C_S2_REG(I2C0)
2108 /* I2C1 */
2109 #define I2C1_A1 I2C_A1_REG(I2C1)
2110 #define I2C1_F I2C_F_REG(I2C1)
2111 #define I2C1_C1 I2C_C1_REG(I2C1)
2112 #define I2C1_S I2C_S_REG(I2C1)
2113 #define I2C1_D I2C_D_REG(I2C1)
2114 #define I2C1_C2 I2C_C2_REG(I2C1)
2115 #define I2C1_FLT I2C_FLT_REG(I2C1)
2116 #define I2C1_RA I2C_RA_REG(I2C1)
2117 #define I2C1_SMB I2C_SMB_REG(I2C1)
2118 #define I2C1_A2 I2C_A2_REG(I2C1)
2119 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
2120 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
2121 #define I2C1_S2 I2C_S2_REG(I2C1)
2122
2123 /*!
2124 * @}
2125 */ /* end of group I2C_Register_Accessor_Macros */
2126
2127
2128 /*!
2129 * @}
2130 */ /* end of group I2C_Peripheral_Access_Layer */
2131
2132
2133 /* ----------------------------------------------------------------------------
2134 -- I2S Peripheral Access Layer
2135 ---------------------------------------------------------------------------- */
2136
2137 /*!
2138 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
2139 * @{
2140 */
2141
2142 /** I2S - Register Layout Typedef */
2143 typedef struct {
2144 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
2145 uint8_t RESERVED_0[4];
2146 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
2147 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
2148 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
2149 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
2150 uint8_t RESERVED_1[8];
2151 __O uint32_t TDR[1]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
2152 uint8_t RESERVED_2[60];
2153 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
2154 uint8_t RESERVED_3[28];
2155 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
2156 uint8_t RESERVED_4[4];
2157 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
2158 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
2159 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
2160 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
2161 uint8_t RESERVED_5[8];
2162 __I uint32_t RDR[1]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
2163 uint8_t RESERVED_6[60];
2164 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
2165 uint8_t RESERVED_7[28];
2166 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
2167 } I2S_Type, *I2S_MemMapPtr;
2168
2169 /* ----------------------------------------------------------------------------
2170 -- I2S - Register accessor macros
2171 ---------------------------------------------------------------------------- */
2172
2173 /*!
2174 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
2175 * @{
2176 */
2177
2178
2179 /* I2S - Register accessors */
2180 #define I2S_TCSR_REG(base) ((base)->TCSR)
2181 #define I2S_TCR2_REG(base) ((base)->TCR2)
2182 #define I2S_TCR3_REG(base) ((base)->TCR3)
2183 #define I2S_TCR4_REG(base) ((base)->TCR4)
2184 #define I2S_TCR5_REG(base) ((base)->TCR5)
2185 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
2186 #define I2S_TMR_REG(base) ((base)->TMR)
2187 #define I2S_RCSR_REG(base) ((base)->RCSR)
2188 #define I2S_RCR2_REG(base) ((base)->RCR2)
2189 #define I2S_RCR3_REG(base) ((base)->RCR3)
2190 #define I2S_RCR4_REG(base) ((base)->RCR4)
2191 #define I2S_RCR5_REG(base) ((base)->RCR5)
2192 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
2193 #define I2S_RMR_REG(base) ((base)->RMR)
2194 #define I2S_MCR_REG(base) ((base)->MCR)
2195
2196 /*!
2197 * @}
2198 */ /* end of group I2S_Register_Accessor_Macros */
2199
2200
2201 /* ----------------------------------------------------------------------------
2202 -- I2S Register Masks
2203 ---------------------------------------------------------------------------- */
2204
2205 /*!
2206 * @addtogroup I2S_Register_Masks I2S Register Masks
2207 * @{
2208 */
2209
2210 /* TCSR Bit Fields */
2211 #define I2S_TCSR_FWDE_MASK 0x2u
2212 #define I2S_TCSR_FWDE_SHIFT 1
2213 #define I2S_TCSR_FWIE_MASK 0x200u
2214 #define I2S_TCSR_FWIE_SHIFT 9
2215 #define I2S_TCSR_FEIE_MASK 0x400u
2216 #define I2S_TCSR_FEIE_SHIFT 10
2217 #define I2S_TCSR_SEIE_MASK 0x800u
2218 #define I2S_TCSR_SEIE_SHIFT 11
2219 #define I2S_TCSR_WSIE_MASK 0x1000u
2220 #define I2S_TCSR_WSIE_SHIFT 12
2221 #define I2S_TCSR_FWF_MASK 0x20000u
2222 #define I2S_TCSR_FWF_SHIFT 17
2223 #define I2S_TCSR_FEF_MASK 0x40000u
2224 #define I2S_TCSR_FEF_SHIFT 18
2225 #define I2S_TCSR_SEF_MASK 0x80000u
2226 #define I2S_TCSR_SEF_SHIFT 19
2227 #define I2S_TCSR_WSF_MASK 0x100000u
2228 #define I2S_TCSR_WSF_SHIFT 20
2229 #define I2S_TCSR_SR_MASK 0x1000000u
2230 #define I2S_TCSR_SR_SHIFT 24
2231 #define I2S_TCSR_FR_MASK 0x2000000u
2232 #define I2S_TCSR_FR_SHIFT 25
2233 #define I2S_TCSR_BCE_MASK 0x10000000u
2234 #define I2S_TCSR_BCE_SHIFT 28
2235 #define I2S_TCSR_DBGE_MASK 0x20000000u
2236 #define I2S_TCSR_DBGE_SHIFT 29
2237 #define I2S_TCSR_STOPE_MASK 0x40000000u
2238 #define I2S_TCSR_STOPE_SHIFT 30
2239 #define I2S_TCSR_TE_MASK 0x80000000u
2240 #define I2S_TCSR_TE_SHIFT 31
2241 /* TCR2 Bit Fields */
2242 #define I2S_TCR2_DIV_MASK 0xFFu
2243 #define I2S_TCR2_DIV_SHIFT 0
2244 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
2245 #define I2S_TCR2_BCD_MASK 0x1000000u
2246 #define I2S_TCR2_BCD_SHIFT 24
2247 #define I2S_TCR2_BCP_MASK 0x2000000u
2248 #define I2S_TCR2_BCP_SHIFT 25
2249 #define I2S_TCR2_MSEL_MASK 0xC000000u
2250 #define I2S_TCR2_MSEL_SHIFT 26
2251 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
2252 #define I2S_TCR2_BCI_MASK 0x10000000u
2253 #define I2S_TCR2_BCI_SHIFT 28
2254 #define I2S_TCR2_BCS_MASK 0x20000000u
2255 #define I2S_TCR2_BCS_SHIFT 29
2256 #define I2S_TCR2_SYNC_MASK 0xC0000000u
2257 #define I2S_TCR2_SYNC_SHIFT 30
2258 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
2259 /* TCR3 Bit Fields */
2260 #define I2S_TCR3_WDFL_MASK 0x1u
2261 #define I2S_TCR3_WDFL_SHIFT 0
2262 #define I2S_TCR3_TCE_MASK 0x10000u
2263 #define I2S_TCR3_TCE_SHIFT 16
2264 /* TCR4 Bit Fields */
2265 #define I2S_TCR4_FSD_MASK 0x1u
2266 #define I2S_TCR4_FSD_SHIFT 0
2267 #define I2S_TCR4_FSP_MASK 0x2u
2268 #define I2S_TCR4_FSP_SHIFT 1
2269 #define I2S_TCR4_ONDEM_MASK 0x4u
2270 #define I2S_TCR4_ONDEM_SHIFT 2
2271 #define I2S_TCR4_FSE_MASK 0x8u
2272 #define I2S_TCR4_FSE_SHIFT 3
2273 #define I2S_TCR4_MF_MASK 0x10u
2274 #define I2S_TCR4_MF_SHIFT 4
2275 #define I2S_TCR4_SYWD_MASK 0x1F00u
2276 #define I2S_TCR4_SYWD_SHIFT 8
2277 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
2278 #define I2S_TCR4_FRSZ_MASK 0x10000u
2279 #define I2S_TCR4_FRSZ_SHIFT 16
2280 #define I2S_TCR4_FPACK_MASK 0x3000000u
2281 #define I2S_TCR4_FPACK_SHIFT 24
2282 #define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FPACK_SHIFT))&I2S_TCR4_FPACK_MASK)
2283 #define I2S_TCR4_FCONT_MASK 0x10000000u
2284 #define I2S_TCR4_FCONT_SHIFT 28
2285 /* TCR5 Bit Fields */
2286 #define I2S_TCR5_FBT_MASK 0x1F00u
2287 #define I2S_TCR5_FBT_SHIFT 8
2288 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
2289 #define I2S_TCR5_W0W_MASK 0x1F0000u
2290 #define I2S_TCR5_W0W_SHIFT 16
2291 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
2292 #define I2S_TCR5_WNW_MASK 0x1F000000u
2293 #define I2S_TCR5_WNW_SHIFT 24
2294 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
2295 /* TDR Bit Fields */
2296 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
2297 #define I2S_TDR_TDR_SHIFT 0
2298 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
2299 /* TMR Bit Fields */
2300 #define I2S_TMR_TWM_MASK 0x3u
2301 #define I2S_TMR_TWM_SHIFT 0
2302 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
2303 /* RCSR Bit Fields */
2304 #define I2S_RCSR_FWDE_MASK 0x2u
2305 #define I2S_RCSR_FWDE_SHIFT 1
2306 #define I2S_RCSR_FWIE_MASK 0x200u
2307 #define I2S_RCSR_FWIE_SHIFT 9
2308 #define I2S_RCSR_FEIE_MASK 0x400u
2309 #define I2S_RCSR_FEIE_SHIFT 10
2310 #define I2S_RCSR_SEIE_MASK 0x800u
2311 #define I2S_RCSR_SEIE_SHIFT 11
2312 #define I2S_RCSR_WSIE_MASK 0x1000u
2313 #define I2S_RCSR_WSIE_SHIFT 12
2314 #define I2S_RCSR_FWF_MASK 0x20000u
2315 #define I2S_RCSR_FWF_SHIFT 17
2316 #define I2S_RCSR_FEF_MASK 0x40000u
2317 #define I2S_RCSR_FEF_SHIFT 18
2318 #define I2S_RCSR_SEF_MASK 0x80000u
2319 #define I2S_RCSR_SEF_SHIFT 19
2320 #define I2S_RCSR_WSF_MASK 0x100000u
2321 #define I2S_RCSR_WSF_SHIFT 20
2322 #define I2S_RCSR_SR_MASK 0x1000000u
2323 #define I2S_RCSR_SR_SHIFT 24
2324 #define I2S_RCSR_FR_MASK 0x2000000u
2325 #define I2S_RCSR_FR_SHIFT 25
2326 #define I2S_RCSR_BCE_MASK 0x10000000u
2327 #define I2S_RCSR_BCE_SHIFT 28
2328 #define I2S_RCSR_DBGE_MASK 0x20000000u
2329 #define I2S_RCSR_DBGE_SHIFT 29
2330 #define I2S_RCSR_STOPE_MASK 0x40000000u
2331 #define I2S_RCSR_STOPE_SHIFT 30
2332 #define I2S_RCSR_RE_MASK 0x80000000u
2333 #define I2S_RCSR_RE_SHIFT 31
2334 /* RCR2 Bit Fields */
2335 #define I2S_RCR2_DIV_MASK 0xFFu
2336 #define I2S_RCR2_DIV_SHIFT 0
2337 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
2338 #define I2S_RCR2_BCD_MASK 0x1000000u
2339 #define I2S_RCR2_BCD_SHIFT 24
2340 #define I2S_RCR2_BCP_MASK 0x2000000u
2341 #define I2S_RCR2_BCP_SHIFT 25
2342 #define I2S_RCR2_MSEL_MASK 0xC000000u
2343 #define I2S_RCR2_MSEL_SHIFT 26
2344 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
2345 #define I2S_RCR2_BCI_MASK 0x10000000u
2346 #define I2S_RCR2_BCI_SHIFT 28
2347 #define I2S_RCR2_BCS_MASK 0x20000000u
2348 #define I2S_RCR2_BCS_SHIFT 29
2349 #define I2S_RCR2_SYNC_MASK 0xC0000000u
2350 #define I2S_RCR2_SYNC_SHIFT 30
2351 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
2352 /* RCR3 Bit Fields */
2353 #define I2S_RCR3_WDFL_MASK 0x1u
2354 #define I2S_RCR3_WDFL_SHIFT 0
2355 #define I2S_RCR3_RCE_MASK 0x10000u
2356 #define I2S_RCR3_RCE_SHIFT 16
2357 /* RCR4 Bit Fields */
2358 #define I2S_RCR4_FSD_MASK 0x1u
2359 #define I2S_RCR4_FSD_SHIFT 0
2360 #define I2S_RCR4_FSP_MASK 0x2u
2361 #define I2S_RCR4_FSP_SHIFT 1
2362 #define I2S_RCR4_ONDEM_MASK 0x4u
2363 #define I2S_RCR4_ONDEM_SHIFT 2
2364 #define I2S_RCR4_FSE_MASK 0x8u
2365 #define I2S_RCR4_FSE_SHIFT 3
2366 #define I2S_RCR4_MF_MASK 0x10u
2367 #define I2S_RCR4_MF_SHIFT 4
2368 #define I2S_RCR4_SYWD_MASK 0x1F00u
2369 #define I2S_RCR4_SYWD_SHIFT 8
2370 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
2371 #define I2S_RCR4_FRSZ_MASK 0x10000u
2372 #define I2S_RCR4_FRSZ_SHIFT 16
2373 #define I2S_RCR4_FPACK_MASK 0x3000000u
2374 #define I2S_RCR4_FPACK_SHIFT 24
2375 #define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FPACK_SHIFT))&I2S_RCR4_FPACK_MASK)
2376 #define I2S_RCR4_FCONT_MASK 0x10000000u
2377 #define I2S_RCR4_FCONT_SHIFT 28
2378 /* RCR5 Bit Fields */
2379 #define I2S_RCR5_FBT_MASK 0x1F00u
2380 #define I2S_RCR5_FBT_SHIFT 8
2381 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
2382 #define I2S_RCR5_W0W_MASK 0x1F0000u
2383 #define I2S_RCR5_W0W_SHIFT 16
2384 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
2385 #define I2S_RCR5_WNW_MASK 0x1F000000u
2386 #define I2S_RCR5_WNW_SHIFT 24
2387 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
2388 /* RDR Bit Fields */
2389 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
2390 #define I2S_RDR_RDR_SHIFT 0
2391 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
2392 /* RMR Bit Fields */
2393 #define I2S_RMR_RWM_MASK 0x3u
2394 #define I2S_RMR_RWM_SHIFT 0
2395 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
2396 /* MCR Bit Fields */
2397 #define I2S_MCR_MICS_MASK 0x3000000u
2398 #define I2S_MCR_MICS_SHIFT 24
2399 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
2400 #define I2S_MCR_MOE_MASK 0x40000000u
2401 #define I2S_MCR_MOE_SHIFT 30
2402 #define I2S_MCR_DUF_MASK 0x80000000u
2403 #define I2S_MCR_DUF_SHIFT 31
2404
2405 /*!
2406 * @}
2407 */ /* end of group I2S_Register_Masks */
2408
2409
2410 /* I2S - Peripheral instance base addresses */
2411 /** Peripheral I2S0 base address */
2412 #define I2S0_BASE (0x4002F000u)
2413 /** Peripheral I2S0 base pointer */
2414 #define I2S0 ((I2S_Type *)I2S0_BASE)
2415 #define I2S0_BASE_PTR (I2S0)
2416 /** Array initializer of I2S peripheral base addresses */
2417 #define I2S_BASE_ADDRS { I2S0_BASE }
2418 /** Array initializer of I2S peripheral base pointers */
2419 #define I2S_BASE_PTRS { I2S0 }
2420 /** Interrupt vectors for the I2S peripheral type */
2421 #define I2S_RX_IRQS { I2S0_IRQn }
2422 #define I2S_TX_IRQS { I2S0_IRQn }
2423
2424 /* ----------------------------------------------------------------------------
2425 -- I2S - Register accessor macros
2426 ---------------------------------------------------------------------------- */
2427
2428 /*!
2429 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
2430 * @{
2431 */
2432
2433
2434 /* I2S - Register instance definitions */
2435 /* I2S0 */
2436 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
2437 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
2438 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
2439 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
2440 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
2441 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
2442 #define I2S0_TMR I2S_TMR_REG(I2S0)
2443 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
2444 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
2445 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
2446 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
2447 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
2448 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
2449 #define I2S0_RMR I2S_RMR_REG(I2S0)
2450 #define I2S0_MCR I2S_MCR_REG(I2S0)
2451
2452 /* I2S - Register array accessors */
2453 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
2454 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
2455
2456 /*!
2457 * @}
2458 */ /* end of group I2S_Register_Accessor_Macros */
2459
2460
2461 /*!
2462 * @}
2463 */ /* end of group I2S_Peripheral_Access_Layer */
2464
2465
2466 /* ----------------------------------------------------------------------------
2467 -- LCD Peripheral Access Layer
2468 ---------------------------------------------------------------------------- */
2469
2470 /*!
2471 * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
2472 * @{
2473 */
2474
2475 /** LCD - Register Layout Typedef */
2476 typedef struct {
2477 __IO uint32_t GCR; /**< LCD General Control Register, offset: 0x0 */
2478 __IO uint32_t AR; /**< LCD Auxiliary Register, offset: 0x4 */
2479 __IO uint32_t FDCR; /**< LCD Fault Detect Control Register, offset: 0x8 */
2480 __IO uint32_t FDSR; /**< LCD Fault Detect Status Register, offset: 0xC */
2481 __IO uint32_t PEN[2]; /**< LCD Pin Enable register, array offset: 0x10, array step: 0x4 */
2482 __IO uint32_t BPEN[2]; /**< LCD Back Plane Enable register, array offset: 0x18, array step: 0x4 */
2483 union { /* offset: 0x20 */
2484 __IO uint32_t WF[16]; /**< LCD Waveform register, array offset: 0x20, array step: 0x4 */
2485 __IO uint8_t WF8B[64]; /**< LCD Waveform Register 0...LCD Waveform Register 63., array offset: 0x20, array step: 0x1 */
2486 };
2487 } LCD_Type, *LCD_MemMapPtr;
2488
2489 /* ----------------------------------------------------------------------------
2490 -- LCD - Register accessor macros
2491 ---------------------------------------------------------------------------- */
2492
2493 /*!
2494 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
2495 * @{
2496 */
2497
2498
2499 /* LCD - Register accessors */
2500 #define LCD_GCR_REG(base) ((base)->GCR)
2501 #define LCD_AR_REG(base) ((base)->AR)
2502 #define LCD_FDCR_REG(base) ((base)->FDCR)
2503 #define LCD_FDSR_REG(base) ((base)->FDSR)
2504 #define LCD_PEN_REG(base,index) ((base)->PEN[index])
2505 #define LCD_BPEN_REG(base,index) ((base)->BPEN[index])
2506 #define LCD_WF_REG(base,index2) ((base)->WF[index2])
2507 #define LCD_WF8B_REG(base,index2) ((base)->WF8B[index2])
2508
2509 /*!
2510 * @}
2511 */ /* end of group LCD_Register_Accessor_Macros */
2512
2513
2514 /* ----------------------------------------------------------------------------
2515 -- LCD Register Masks
2516 ---------------------------------------------------------------------------- */
2517
2518 /*!
2519 * @addtogroup LCD_Register_Masks LCD Register Masks
2520 * @{
2521 */
2522
2523 /* GCR Bit Fields */
2524 #define LCD_GCR_DUTY_MASK 0x7u
2525 #define LCD_GCR_DUTY_SHIFT 0
2526 #define LCD_GCR_DUTY(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_DUTY_SHIFT))&LCD_GCR_DUTY_MASK)
2527 #define LCD_GCR_LCLK_MASK 0x38u
2528 #define LCD_GCR_LCLK_SHIFT 3
2529 #define LCD_GCR_LCLK(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LCLK_SHIFT))&LCD_GCR_LCLK_MASK)
2530 #define LCD_GCR_SOURCE_MASK 0x40u
2531 #define LCD_GCR_SOURCE_SHIFT 6
2532 #define LCD_GCR_LCDEN_MASK 0x80u
2533 #define LCD_GCR_LCDEN_SHIFT 7
2534 #define LCD_GCR_LCDSTP_MASK 0x100u
2535 #define LCD_GCR_LCDSTP_SHIFT 8
2536 #define LCD_GCR_LCDDOZE_MASK 0x200u
2537 #define LCD_GCR_LCDDOZE_SHIFT 9
2538 #define LCD_GCR_FFR_MASK 0x400u
2539 #define LCD_GCR_FFR_SHIFT 10
2540 #define LCD_GCR_ALTSOURCE_MASK 0x800u
2541 #define LCD_GCR_ALTSOURCE_SHIFT 11
2542 #define LCD_GCR_ALTDIV_MASK 0x3000u
2543 #define LCD_GCR_ALTDIV_SHIFT 12
2544 #define LCD_GCR_ALTDIV(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_ALTDIV_SHIFT))&LCD_GCR_ALTDIV_MASK)
2545 #define LCD_GCR_FDCIEN_MASK 0x4000u
2546 #define LCD_GCR_FDCIEN_SHIFT 14
2547 #define LCD_GCR_PADSAFE_MASK 0x8000u
2548 #define LCD_GCR_PADSAFE_SHIFT 15
2549 #define LCD_GCR_VSUPPLY_MASK 0x20000u
2550 #define LCD_GCR_VSUPPLY_SHIFT 17
2551 #define LCD_GCR_LADJ_MASK 0x300000u
2552 #define LCD_GCR_LADJ_SHIFT 20
2553 #define LCD_GCR_LADJ(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_LADJ_SHIFT))&LCD_GCR_LADJ_MASK)
2554 #define LCD_GCR_CPSEL_MASK 0x800000u
2555 #define LCD_GCR_CPSEL_SHIFT 23
2556 #define LCD_GCR_RVTRIM_MASK 0xF000000u
2557 #define LCD_GCR_RVTRIM_SHIFT 24
2558 #define LCD_GCR_RVTRIM(x) (((uint32_t)(((uint32_t)(x))<<LCD_GCR_RVTRIM_SHIFT))&LCD_GCR_RVTRIM_MASK)
2559 #define LCD_GCR_RVEN_MASK 0x80000000u
2560 #define LCD_GCR_RVEN_SHIFT 31
2561 /* AR Bit Fields */
2562 #define LCD_AR_BRATE_MASK 0x7u
2563 #define LCD_AR_BRATE_SHIFT 0
2564 #define LCD_AR_BRATE(x) (((uint32_t)(((uint32_t)(x))<<LCD_AR_BRATE_SHIFT))&LCD_AR_BRATE_MASK)
2565 #define LCD_AR_BMODE_MASK 0x8u
2566 #define LCD_AR_BMODE_SHIFT 3
2567 #define LCD_AR_BLANK_MASK 0x20u
2568 #define LCD_AR_BLANK_SHIFT 5
2569 #define LCD_AR_ALT_MASK 0x40u
2570 #define LCD_AR_ALT_SHIFT 6
2571 #define LCD_AR_BLINK_MASK 0x80u
2572 #define LCD_AR_BLINK_SHIFT 7
2573 /* FDCR Bit Fields */
2574 #define LCD_FDCR_FDPINID_MASK 0x3Fu
2575 #define LCD_FDCR_FDPINID_SHIFT 0
2576 #define LCD_FDCR_FDPINID(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPINID_SHIFT))&LCD_FDCR_FDPINID_MASK)
2577 #define LCD_FDCR_FDBPEN_MASK 0x40u
2578 #define LCD_FDCR_FDBPEN_SHIFT 6
2579 #define LCD_FDCR_FDEN_MASK 0x80u
2580 #define LCD_FDCR_FDEN_SHIFT 7
2581 #define LCD_FDCR_FDSWW_MASK 0xE00u
2582 #define LCD_FDCR_FDSWW_SHIFT 9
2583 #define LCD_FDCR_FDSWW(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDSWW_SHIFT))&LCD_FDCR_FDSWW_MASK)
2584 #define LCD_FDCR_FDPRS_MASK 0x7000u
2585 #define LCD_FDCR_FDPRS_SHIFT 12
2586 #define LCD_FDCR_FDPRS(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDCR_FDPRS_SHIFT))&LCD_FDCR_FDPRS_MASK)
2587 /* FDSR Bit Fields */
2588 #define LCD_FDSR_FDCNT_MASK 0xFFu
2589 #define LCD_FDSR_FDCNT_SHIFT 0
2590 #define LCD_FDSR_FDCNT(x) (((uint32_t)(((uint32_t)(x))<<LCD_FDSR_FDCNT_SHIFT))&LCD_FDSR_FDCNT_MASK)
2591 #define LCD_FDSR_FDCF_MASK 0x8000u
2592 #define LCD_FDSR_FDCF_SHIFT 15
2593 /* PEN Bit Fields */
2594 #define LCD_PEN_PEN_MASK 0xFFFFFFFFu
2595 #define LCD_PEN_PEN_SHIFT 0
2596 #define LCD_PEN_PEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_PEN_PEN_SHIFT))&LCD_PEN_PEN_MASK)
2597 /* BPEN Bit Fields */
2598 #define LCD_BPEN_BPEN_MASK 0xFFFFFFFFu
2599 #define LCD_BPEN_BPEN_SHIFT 0
2600 #define LCD_BPEN_BPEN(x) (((uint32_t)(((uint32_t)(x))<<LCD_BPEN_BPEN_SHIFT))&LCD_BPEN_BPEN_MASK)
2601 /* WF Bit Fields */
2602 #define LCD_WF_WF0_MASK 0xFFu
2603 #define LCD_WF_WF0_SHIFT 0
2604 #define LCD_WF_WF0(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF0_SHIFT))&LCD_WF_WF0_MASK)
2605 #define LCD_WF_WF60_MASK 0xFFu
2606 #define LCD_WF_WF60_SHIFT 0
2607 #define LCD_WF_WF60(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF60_SHIFT))&LCD_WF_WF60_MASK)
2608 #define LCD_WF_WF56_MASK 0xFFu
2609 #define LCD_WF_WF56_SHIFT 0
2610 #define LCD_WF_WF56(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF56_SHIFT))&LCD_WF_WF56_MASK)
2611 #define LCD_WF_WF52_MASK 0xFFu
2612 #define LCD_WF_WF52_SHIFT 0
2613 #define LCD_WF_WF52(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF52_SHIFT))&LCD_WF_WF52_MASK)
2614 #define LCD_WF_WF4_MASK 0xFFu
2615 #define LCD_WF_WF4_SHIFT 0
2616 #define LCD_WF_WF4(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF4_SHIFT))&LCD_WF_WF4_MASK)
2617 #define LCD_WF_WF48_MASK 0xFFu
2618 #define LCD_WF_WF48_SHIFT 0
2619 #define LCD_WF_WF48(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF48_SHIFT))&LCD_WF_WF48_MASK)
2620 #define LCD_WF_WF44_MASK 0xFFu
2621 #define LCD_WF_WF44_SHIFT 0
2622 #define LCD_WF_WF44(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF44_SHIFT))&LCD_WF_WF44_MASK)
2623 #define LCD_WF_WF40_MASK 0xFFu
2624 #define LCD_WF_WF40_SHIFT 0
2625 #define LCD_WF_WF40(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF40_SHIFT))&LCD_WF_WF40_MASK)
2626 #define LCD_WF_WF8_MASK 0xFFu
2627 #define LCD_WF_WF8_SHIFT 0
2628 #define LCD_WF_WF8(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF8_SHIFT))&LCD_WF_WF8_MASK)
2629 #define LCD_WF_WF36_MASK 0xFFu
2630 #define LCD_WF_WF36_SHIFT 0
2631 #define LCD_WF_WF36(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF36_SHIFT))&LCD_WF_WF36_MASK)
2632 #define LCD_WF_WF32_MASK 0xFFu
2633 #define LCD_WF_WF32_SHIFT 0
2634 #define LCD_WF_WF32(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF32_SHIFT))&LCD_WF_WF32_MASK)
2635 #define LCD_WF_WF28_MASK 0xFFu
2636 #define LCD_WF_WF28_SHIFT 0
2637 #define LCD_WF_WF28(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF28_SHIFT))&LCD_WF_WF28_MASK)
2638 #define LCD_WF_WF12_MASK 0xFFu
2639 #define LCD_WF_WF12_SHIFT 0
2640 #define LCD_WF_WF12(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF12_SHIFT))&LCD_WF_WF12_MASK)
2641 #define LCD_WF_WF24_MASK 0xFFu
2642 #define LCD_WF_WF24_SHIFT 0
2643 #define LCD_WF_WF24(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF24_SHIFT))&LCD_WF_WF24_MASK)
2644 #define LCD_WF_WF20_MASK 0xFFu
2645 #define LCD_WF_WF20_SHIFT 0
2646 #define LCD_WF_WF20(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF20_SHIFT))&LCD_WF_WF20_MASK)
2647 #define LCD_WF_WF16_MASK 0xFFu
2648 #define LCD_WF_WF16_SHIFT 0
2649 #define LCD_WF_WF16(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF16_SHIFT))&LCD_WF_WF16_MASK)
2650 #define LCD_WF_WF5_MASK 0xFF00u
2651 #define LCD_WF_WF5_SHIFT 8
2652 #define LCD_WF_WF5(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF5_SHIFT))&LCD_WF_WF5_MASK)
2653 #define LCD_WF_WF49_MASK 0xFF00u
2654 #define LCD_WF_WF49_SHIFT 8
2655 #define LCD_WF_WF49(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF49_SHIFT))&LCD_WF_WF49_MASK)
2656 #define LCD_WF_WF45_MASK 0xFF00u
2657 #define LCD_WF_WF45_SHIFT 8
2658 #define LCD_WF_WF45(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF45_SHIFT))&LCD_WF_WF45_MASK)
2659 #define LCD_WF_WF61_MASK 0xFF00u
2660 #define LCD_WF_WF61_SHIFT 8
2661 #define LCD_WF_WF61(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF61_SHIFT))&LCD_WF_WF61_MASK)
2662 #define LCD_WF_WF25_MASK 0xFF00u
2663 #define LCD_WF_WF25_SHIFT 8
2664 #define LCD_WF_WF25(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF25_SHIFT))&LCD_WF_WF25_MASK)
2665 #define LCD_WF_WF17_MASK 0xFF00u
2666 #define LCD_WF_WF17_SHIFT 8
2667 #define LCD_WF_WF17(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF17_SHIFT))&LCD_WF_WF17_MASK)
2668 #define LCD_WF_WF41_MASK 0xFF00u
2669 #define LCD_WF_WF41_SHIFT 8
2670 #define LCD_WF_WF41(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF41_SHIFT))&LCD_WF_WF41_MASK)
2671 #define LCD_WF_WF13_MASK 0xFF00u
2672 #define LCD_WF_WF13_SHIFT 8
2673 #define LCD_WF_WF13(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF13_SHIFT))&LCD_WF_WF13_MASK)
2674 #define LCD_WF_WF57_MASK 0xFF00u
2675 #define LCD_WF_WF57_SHIFT 8
2676 #define LCD_WF_WF57(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF57_SHIFT))&LCD_WF_WF57_MASK)
2677 #define LCD_WF_WF53_MASK 0xFF00u
2678 #define LCD_WF_WF53_SHIFT 8
2679 #define LCD_WF_WF53(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF53_SHIFT))&LCD_WF_WF53_MASK)
2680 #define LCD_WF_WF37_MASK 0xFF00u
2681 #define LCD_WF_WF37_SHIFT 8
2682 #define LCD_WF_WF37(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF37_SHIFT))&LCD_WF_WF37_MASK)
2683 #define LCD_WF_WF9_MASK 0xFF00u
2684 #define LCD_WF_WF9_SHIFT 8
2685 #define LCD_WF_WF9(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF9_SHIFT))&LCD_WF_WF9_MASK)
2686 #define LCD_WF_WF1_MASK 0xFF00u
2687 #define LCD_WF_WF1_SHIFT 8
2688 #define LCD_WF_WF1(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF1_SHIFT))&LCD_WF_WF1_MASK)
2689 #define LCD_WF_WF29_MASK 0xFF00u
2690 #define LCD_WF_WF29_SHIFT 8
2691 #define LCD_WF_WF29(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF29_SHIFT))&LCD_WF_WF29_MASK)
2692 #define LCD_WF_WF33_MASK 0xFF00u
2693 #define LCD_WF_WF33_SHIFT 8
2694 #define LCD_WF_WF33(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF33_SHIFT))&LCD_WF_WF33_MASK)
2695 #define LCD_WF_WF21_MASK 0xFF00u
2696 #define LCD_WF_WF21_SHIFT 8
2697 #define LCD_WF_WF21(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF21_SHIFT))&LCD_WF_WF21_MASK)
2698 #define LCD_WF_WF26_MASK 0xFF0000u
2699 #define LCD_WF_WF26_SHIFT 16
2700 #define LCD_WF_WF26(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF26_SHIFT))&LCD_WF_WF26_MASK)
2701 #define LCD_WF_WF46_MASK 0xFF0000u
2702 #define LCD_WF_WF46_SHIFT 16
2703 #define LCD_WF_WF46(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF46_SHIFT))&LCD_WF_WF46_MASK)
2704 #define LCD_WF_WF6_MASK 0xFF0000u
2705 #define LCD_WF_WF6_SHIFT 16
2706 #define LCD_WF_WF6(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF6_SHIFT))&LCD_WF_WF6_MASK)
2707 #define LCD_WF_WF42_MASK 0xFF0000u
2708 #define LCD_WF_WF42_SHIFT 16
2709 #define LCD_WF_WF42(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF42_SHIFT))&LCD_WF_WF42_MASK)
2710 #define LCD_WF_WF18_MASK 0xFF0000u
2711 #define LCD_WF_WF18_SHIFT 16
2712 #define LCD_WF_WF18(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF18_SHIFT))&LCD_WF_WF18_MASK)
2713 #define LCD_WF_WF38_MASK 0xFF0000u
2714 #define LCD_WF_WF38_SHIFT 16
2715 #define LCD_WF_WF38(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF38_SHIFT))&LCD_WF_WF38_MASK)
2716 #define LCD_WF_WF22_MASK 0xFF0000u
2717 #define LCD_WF_WF22_SHIFT 16
2718 #define LCD_WF_WF22(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF22_SHIFT))&LCD_WF_WF22_MASK)
2719 #define LCD_WF_WF34_MASK 0xFF0000u
2720 #define LCD_WF_WF34_SHIFT 16
2721 #define LCD_WF_WF34(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF34_SHIFT))&LCD_WF_WF34_MASK)
2722 #define LCD_WF_WF50_MASK 0xFF0000u
2723 #define LCD_WF_WF50_SHIFT 16
2724 #define LCD_WF_WF50(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF50_SHIFT))&LCD_WF_WF50_MASK)
2725 #define LCD_WF_WF14_MASK 0xFF0000u
2726 #define LCD_WF_WF14_SHIFT 16
2727 #define LCD_WF_WF14(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF14_SHIFT))&LCD_WF_WF14_MASK)
2728 #define LCD_WF_WF54_MASK 0xFF0000u
2729 #define LCD_WF_WF54_SHIFT 16
2730 #define LCD_WF_WF54(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF54_SHIFT))&LCD_WF_WF54_MASK)
2731 #define LCD_WF_WF2_MASK 0xFF0000u
2732 #define LCD_WF_WF2_SHIFT 16
2733 #define LCD_WF_WF2(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF2_SHIFT))&LCD_WF_WF2_MASK)
2734 #define LCD_WF_WF58_MASK 0xFF0000u
2735 #define LCD_WF_WF58_SHIFT 16
2736 #define LCD_WF_WF58(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF58_SHIFT))&LCD_WF_WF58_MASK)
2737 #define LCD_WF_WF30_MASK 0xFF0000u
2738 #define LCD_WF_WF30_SHIFT 16
2739 #define LCD_WF_WF30(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF30_SHIFT))&LCD_WF_WF30_MASK)
2740 #define LCD_WF_WF62_MASK 0xFF0000u
2741 #define LCD_WF_WF62_SHIFT 16
2742 #define LCD_WF_WF62(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF62_SHIFT))&LCD_WF_WF62_MASK)
2743 #define LCD_WF_WF10_MASK 0xFF0000u
2744 #define LCD_WF_WF10_SHIFT 16
2745 #define LCD_WF_WF10(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF10_SHIFT))&LCD_WF_WF10_MASK)
2746 #define LCD_WF_WF63_MASK 0xFF000000u
2747 #define LCD_WF_WF63_SHIFT 24
2748 #define LCD_WF_WF63(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF63_SHIFT))&LCD_WF_WF63_MASK)
2749 #define LCD_WF_WF59_MASK 0xFF000000u
2750 #define LCD_WF_WF59_SHIFT 24
2751 #define LCD_WF_WF59(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF59_SHIFT))&LCD_WF_WF59_MASK)
2752 #define LCD_WF_WF55_MASK 0xFF000000u
2753 #define LCD_WF_WF55_SHIFT 24
2754 #define LCD_WF_WF55(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF55_SHIFT))&LCD_WF_WF55_MASK)
2755 #define LCD_WF_WF3_MASK 0xFF000000u
2756 #define LCD_WF_WF3_SHIFT 24
2757 #define LCD_WF_WF3(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF3_SHIFT))&LCD_WF_WF3_MASK)
2758 #define LCD_WF_WF51_MASK 0xFF000000u
2759 #define LCD_WF_WF51_SHIFT 24
2760 #define LCD_WF_WF51(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF51_SHIFT))&LCD_WF_WF51_MASK)
2761 #define LCD_WF_WF47_MASK 0xFF000000u
2762 #define LCD_WF_WF47_SHIFT 24
2763 #define LCD_WF_WF47(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF47_SHIFT))&LCD_WF_WF47_MASK)
2764 #define LCD_WF_WF43_MASK 0xFF000000u
2765 #define LCD_WF_WF43_SHIFT 24
2766 #define LCD_WF_WF43(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF43_SHIFT))&LCD_WF_WF43_MASK)
2767 #define LCD_WF_WF7_MASK 0xFF000000u
2768 #define LCD_WF_WF7_SHIFT 24
2769 #define LCD_WF_WF7(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF7_SHIFT))&LCD_WF_WF7_MASK)
2770 #define LCD_WF_WF39_MASK 0xFF000000u
2771 #define LCD_WF_WF39_SHIFT 24
2772 #define LCD_WF_WF39(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF39_SHIFT))&LCD_WF_WF39_MASK)
2773 #define LCD_WF_WF35_MASK 0xFF000000u
2774 #define LCD_WF_WF35_SHIFT 24
2775 #define LCD_WF_WF35(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF35_SHIFT))&LCD_WF_WF35_MASK)
2776 #define LCD_WF_WF31_MASK 0xFF000000u
2777 #define LCD_WF_WF31_SHIFT 24
2778 #define LCD_WF_WF31(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF31_SHIFT))&LCD_WF_WF31_MASK)
2779 #define LCD_WF_WF11_MASK 0xFF000000u
2780 #define LCD_WF_WF11_SHIFT 24
2781 #define LCD_WF_WF11(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF11_SHIFT))&LCD_WF_WF11_MASK)
2782 #define LCD_WF_WF27_MASK 0xFF000000u
2783 #define LCD_WF_WF27_SHIFT 24
2784 #define LCD_WF_WF27(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF27_SHIFT))&LCD_WF_WF27_MASK)
2785 #define LCD_WF_WF23_MASK 0xFF000000u
2786 #define LCD_WF_WF23_SHIFT 24
2787 #define LCD_WF_WF23(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF23_SHIFT))&LCD_WF_WF23_MASK)
2788 #define LCD_WF_WF19_MASK 0xFF000000u
2789 #define LCD_WF_WF19_SHIFT 24
2790 #define LCD_WF_WF19(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF19_SHIFT))&LCD_WF_WF19_MASK)
2791 #define LCD_WF_WF15_MASK 0xFF000000u
2792 #define LCD_WF_WF15_SHIFT 24
2793 #define LCD_WF_WF15(x) (((uint32_t)(((uint32_t)(x))<<LCD_WF_WF15_SHIFT))&LCD_WF_WF15_MASK)
2794 /* WF8B Bit Fields */
2795 #define LCD_WF8B_BPALCD0_MASK 0x1u
2796 #define LCD_WF8B_BPALCD0_SHIFT 0
2797 #define LCD_WF8B_BPALCD63_MASK 0x1u
2798 #define LCD_WF8B_BPALCD63_SHIFT 0
2799 #define LCD_WF8B_BPALCD62_MASK 0x1u
2800 #define LCD_WF8B_BPALCD62_SHIFT 0
2801 #define LCD_WF8B_BPALCD61_MASK 0x1u
2802 #define LCD_WF8B_BPALCD61_SHIFT 0
2803 #define LCD_WF8B_BPALCD60_MASK 0x1u
2804 #define LCD_WF8B_BPALCD60_SHIFT 0
2805 #define LCD_WF8B_BPALCD59_MASK 0x1u
2806 #define LCD_WF8B_BPALCD59_SHIFT 0
2807 #define LCD_WF8B_BPALCD58_MASK 0x1u
2808 #define LCD_WF8B_BPALCD58_SHIFT 0
2809 #define LCD_WF8B_BPALCD57_MASK 0x1u
2810 #define LCD_WF8B_BPALCD57_SHIFT 0
2811 #define LCD_WF8B_BPALCD1_MASK 0x1u
2812 #define LCD_WF8B_BPALCD1_SHIFT 0
2813 #define LCD_WF8B_BPALCD56_MASK 0x1u
2814 #define LCD_WF8B_BPALCD56_SHIFT 0
2815 #define LCD_WF8B_BPALCD55_MASK 0x1u
2816 #define LCD_WF8B_BPALCD55_SHIFT 0
2817 #define LCD_WF8B_BPALCD54_MASK 0x1u
2818 #define LCD_WF8B_BPALCD54_SHIFT 0
2819 #define LCD_WF8B_BPALCD53_MASK 0x1u
2820 #define LCD_WF8B_BPALCD53_SHIFT 0
2821 #define LCD_WF8B_BPALCD52_MASK 0x1u
2822 #define LCD_WF8B_BPALCD52_SHIFT 0
2823 #define LCD_WF8B_BPALCD51_MASK 0x1u
2824 #define LCD_WF8B_BPALCD51_SHIFT 0
2825 #define LCD_WF8B_BPALCD50_MASK 0x1u
2826 #define LCD_WF8B_BPALCD50_SHIFT 0
2827 #define LCD_WF8B_BPALCD2_MASK 0x1u
2828 #define LCD_WF8B_BPALCD2_SHIFT 0
2829 #define LCD_WF8B_BPALCD49_MASK 0x1u
2830 #define LCD_WF8B_BPALCD49_SHIFT 0
2831 #define LCD_WF8B_BPALCD48_MASK 0x1u
2832 #define LCD_WF8B_BPALCD48_SHIFT 0
2833 #define LCD_WF8B_BPALCD47_MASK 0x1u
2834 #define LCD_WF8B_BPALCD47_SHIFT 0
2835 #define LCD_WF8B_BPALCD46_MASK 0x1u
2836 #define LCD_WF8B_BPALCD46_SHIFT 0
2837 #define LCD_WF8B_BPALCD45_MASK 0x1u
2838 #define LCD_WF8B_BPALCD45_SHIFT 0
2839 #define LCD_WF8B_BPALCD44_MASK 0x1u
2840 #define LCD_WF8B_BPALCD44_SHIFT 0
2841 #define LCD_WF8B_BPALCD43_MASK 0x1u
2842 #define LCD_WF8B_BPALCD43_SHIFT 0
2843 #define LCD_WF8B_BPALCD3_MASK 0x1u
2844 #define LCD_WF8B_BPALCD3_SHIFT 0
2845 #define LCD_WF8B_BPALCD42_MASK 0x1u
2846 #define LCD_WF8B_BPALCD42_SHIFT 0
2847 #define LCD_WF8B_BPALCD41_MASK 0x1u
2848 #define LCD_WF8B_BPALCD41_SHIFT 0
2849 #define LCD_WF8B_BPALCD40_MASK 0x1u
2850 #define LCD_WF8B_BPALCD40_SHIFT 0
2851 #define LCD_WF8B_BPALCD39_MASK 0x1u
2852 #define LCD_WF8B_BPALCD39_SHIFT 0
2853 #define LCD_WF8B_BPALCD38_MASK 0x1u
2854 #define LCD_WF8B_BPALCD38_SHIFT 0
2855 #define LCD_WF8B_BPALCD37_MASK 0x1u
2856 #define LCD_WF8B_BPALCD37_SHIFT 0
2857 #define LCD_WF8B_BPALCD36_MASK 0x1u
2858 #define LCD_WF8B_BPALCD36_SHIFT 0
2859 #define LCD_WF8B_BPALCD4_MASK 0x1u
2860 #define LCD_WF8B_BPALCD4_SHIFT 0
2861 #define LCD_WF8B_BPALCD35_MASK 0x1u
2862 #define LCD_WF8B_BPALCD35_SHIFT 0
2863 #define LCD_WF8B_BPALCD34_MASK 0x1u
2864 #define LCD_WF8B_BPALCD34_SHIFT 0
2865 #define LCD_WF8B_BPALCD33_MASK 0x1u
2866 #define LCD_WF8B_BPALCD33_SHIFT 0
2867 #define LCD_WF8B_BPALCD32_MASK 0x1u
2868 #define LCD_WF8B_BPALCD32_SHIFT 0
2869 #define LCD_WF8B_BPALCD31_MASK 0x1u
2870 #define LCD_WF8B_BPALCD31_SHIFT 0
2871 #define LCD_WF8B_BPALCD30_MASK 0x1u
2872 #define LCD_WF8B_BPALCD30_SHIFT 0
2873 #define LCD_WF8B_BPALCD29_MASK 0x1u
2874 #define LCD_WF8B_BPALCD29_SHIFT 0
2875 #define LCD_WF8B_BPALCD5_MASK 0x1u
2876 #define LCD_WF8B_BPALCD5_SHIFT 0
2877 #define LCD_WF8B_BPALCD28_MASK 0x1u
2878 #define LCD_WF8B_BPALCD28_SHIFT 0
2879 #define LCD_WF8B_BPALCD27_MASK 0x1u
2880 #define LCD_WF8B_BPALCD27_SHIFT 0
2881 #define LCD_WF8B_BPALCD26_MASK 0x1u
2882 #define LCD_WF8B_BPALCD26_SHIFT 0
2883 #define LCD_WF8B_BPALCD25_MASK 0x1u
2884 #define LCD_WF8B_BPALCD25_SHIFT 0
2885 #define LCD_WF8B_BPALCD24_MASK 0x1u
2886 #define LCD_WF8B_BPALCD24_SHIFT 0
2887 #define LCD_WF8B_BPALCD23_MASK 0x1u
2888 #define LCD_WF8B_BPALCD23_SHIFT 0
2889 #define LCD_WF8B_BPALCD22_MASK 0x1u
2890 #define LCD_WF8B_BPALCD22_SHIFT 0
2891 #define LCD_WF8B_BPALCD6_MASK 0x1u
2892 #define LCD_WF8B_BPALCD6_SHIFT 0
2893 #define LCD_WF8B_BPALCD21_MASK 0x1u
2894 #define LCD_WF8B_BPALCD21_SHIFT 0
2895 #define LCD_WF8B_BPALCD20_MASK 0x1u
2896 #define LCD_WF8B_BPALCD20_SHIFT 0
2897 #define LCD_WF8B_BPALCD19_MASK 0x1u
2898 #define LCD_WF8B_BPALCD19_SHIFT 0
2899 #define LCD_WF8B_BPALCD18_MASK 0x1u
2900 #define LCD_WF8B_BPALCD18_SHIFT 0
2901 #define LCD_WF8B_BPALCD17_MASK 0x1u
2902 #define LCD_WF8B_BPALCD17_SHIFT 0
2903 #define LCD_WF8B_BPALCD16_MASK 0x1u
2904 #define LCD_WF8B_BPALCD16_SHIFT 0
2905 #define LCD_WF8B_BPALCD15_MASK 0x1u
2906 #define LCD_WF8B_BPALCD15_SHIFT 0
2907 #define LCD_WF8B_BPALCD7_MASK 0x1u
2908 #define LCD_WF8B_BPALCD7_SHIFT 0
2909 #define LCD_WF8B_BPALCD14_MASK 0x1u
2910 #define LCD_WF8B_BPALCD14_SHIFT 0
2911 #define LCD_WF8B_BPALCD13_MASK 0x1u
2912 #define LCD_WF8B_BPALCD13_SHIFT 0
2913 #define LCD_WF8B_BPALCD12_MASK 0x1u
2914 #define LCD_WF8B_BPALCD12_SHIFT 0
2915 #define LCD_WF8B_BPALCD11_MASK 0x1u
2916 #define LCD_WF8B_BPALCD11_SHIFT 0
2917 #define LCD_WF8B_BPALCD10_MASK 0x1u
2918 #define LCD_WF8B_BPALCD10_SHIFT 0
2919 #define LCD_WF8B_BPALCD9_MASK 0x1u
2920 #define LCD_WF8B_BPALCD9_SHIFT 0
2921 #define LCD_WF8B_BPALCD8_MASK 0x1u
2922 #define LCD_WF8B_BPALCD8_SHIFT 0
2923 #define LCD_WF8B_BPBLCD1_MASK 0x2u
2924 #define LCD_WF8B_BPBLCD1_SHIFT 1
2925 #define LCD_WF8B_BPBLCD32_MASK 0x2u
2926 #define LCD_WF8B_BPBLCD32_SHIFT 1
2927 #define LCD_WF8B_BPBLCD30_MASK 0x2u
2928 #define LCD_WF8B_BPBLCD30_SHIFT 1
2929 #define LCD_WF8B_BPBLCD60_MASK 0x2u
2930 #define LCD_WF8B_BPBLCD60_SHIFT 1
2931 #define LCD_WF8B_BPBLCD24_MASK 0x2u
2932 #define LCD_WF8B_BPBLCD24_SHIFT 1
2933 #define LCD_WF8B_BPBLCD28_MASK 0x2u
2934 #define LCD_WF8B_BPBLCD28_SHIFT 1
2935 #define LCD_WF8B_BPBLCD23_MASK 0x2u
2936 #define LCD_WF8B_BPBLCD23_SHIFT 1
2937 #define LCD_WF8B_BPBLCD48_MASK 0x2u
2938 #define LCD_WF8B_BPBLCD48_SHIFT 1
2939 #define LCD_WF8B_BPBLCD10_MASK 0x2u
2940 #define LCD_WF8B_BPBLCD10_SHIFT 1
2941 #define LCD_WF8B_BPBLCD15_MASK 0x2u
2942 #define LCD_WF8B_BPBLCD15_SHIFT 1
2943 #define LCD_WF8B_BPBLCD36_MASK 0x2u
2944 #define LCD_WF8B_BPBLCD36_SHIFT 1
2945 #define LCD_WF8B_BPBLCD44_MASK 0x2u
2946 #define LCD_WF8B_BPBLCD44_SHIFT 1
2947 #define LCD_WF8B_BPBLCD62_MASK 0x2u
2948 #define LCD_WF8B_BPBLCD62_SHIFT 1
2949 #define LCD_WF8B_BPBLCD53_MASK 0x2u
2950 #define LCD_WF8B_BPBLCD53_SHIFT 1
2951 #define LCD_WF8B_BPBLCD22_MASK 0x2u
2952 #define LCD_WF8B_BPBLCD22_SHIFT 1
2953 #define LCD_WF8B_BPBLCD47_MASK 0x2u
2954 #define LCD_WF8B_BPBLCD47_SHIFT 1
2955 #define LCD_WF8B_BPBLCD33_MASK 0x2u
2956 #define LCD_WF8B_BPBLCD33_SHIFT 1
2957 #define LCD_WF8B_BPBLCD2_MASK 0x2u
2958 #define LCD_WF8B_BPBLCD2_SHIFT 1
2959 #define LCD_WF8B_BPBLCD49_MASK 0x2u
2960 #define LCD_WF8B_BPBLCD49_SHIFT 1
2961 #define LCD_WF8B_BPBLCD0_MASK 0x2u
2962 #define LCD_WF8B_BPBLCD0_SHIFT 1
2963 #define LCD_WF8B_BPBLCD55_MASK 0x2u
2964 #define LCD_WF8B_BPBLCD55_SHIFT 1
2965 #define LCD_WF8B_BPBLCD56_MASK 0x2u
2966 #define LCD_WF8B_BPBLCD56_SHIFT 1
2967 #define LCD_WF8B_BPBLCD21_MASK 0x2u
2968 #define LCD_WF8B_BPBLCD21_SHIFT 1
2969 #define LCD_WF8B_BPBLCD6_MASK 0x2u
2970 #define LCD_WF8B_BPBLCD6_SHIFT 1
2971 #define LCD_WF8B_BPBLCD29_MASK 0x2u
2972 #define LCD_WF8B_BPBLCD29_SHIFT 1
2973 #define LCD_WF8B_BPBLCD25_MASK 0x2u
2974 #define LCD_WF8B_BPBLCD25_SHIFT 1
2975 #define LCD_WF8B_BPBLCD8_MASK 0x2u
2976 #define LCD_WF8B_BPBLCD8_SHIFT 1
2977 #define LCD_WF8B_BPBLCD54_MASK 0x2u
2978 #define LCD_WF8B_BPBLCD54_SHIFT 1
2979 #define LCD_WF8B_BPBLCD38_MASK 0x2u
2980 #define LCD_WF8B_BPBLCD38_SHIFT 1
2981 #define LCD_WF8B_BPBLCD43_MASK 0x2u
2982 #define LCD_WF8B_BPBLCD43_SHIFT 1
2983 #define LCD_WF8B_BPBLCD20_MASK 0x2u
2984 #define LCD_WF8B_BPBLCD20_SHIFT 1
2985 #define LCD_WF8B_BPBLCD9_MASK 0x2u
2986 #define LCD_WF8B_BPBLCD9_SHIFT 1
2987 #define LCD_WF8B_BPBLCD7_MASK 0x2u
2988 #define LCD_WF8B_BPBLCD7_SHIFT 1
2989 #define LCD_WF8B_BPBLCD50_MASK 0x2u
2990 #define LCD_WF8B_BPBLCD50_SHIFT 1
2991 #define LCD_WF8B_BPBLCD40_MASK 0x2u
2992 #define LCD_WF8B_BPBLCD40_SHIFT 1
2993 #define LCD_WF8B_BPBLCD63_MASK 0x2u
2994 #define LCD_WF8B_BPBLCD63_SHIFT 1
2995 #define LCD_WF8B_BPBLCD26_MASK 0x2u
2996 #define LCD_WF8B_BPBLCD26_SHIFT 1
2997 #define LCD_WF8B_BPBLCD12_MASK 0x2u
2998 #define LCD_WF8B_BPBLCD12_SHIFT 1
2999 #define LCD_WF8B_BPBLCD19_MASK 0x2u
3000 #define LCD_WF8B_BPBLCD19_SHIFT 1
3001 #define LCD_WF8B_BPBLCD34_MASK 0x2u
3002 #define LCD_WF8B_BPBLCD34_SHIFT 1
3003 #define LCD_WF8B_BPBLCD39_MASK 0x2u
3004 #define LCD_WF8B_BPBLCD39_SHIFT 1
3005 #define LCD_WF8B_BPBLCD59_MASK 0x2u
3006 #define LCD_WF8B_BPBLCD59_SHIFT 1
3007 #define LCD_WF8B_BPBLCD61_MASK 0x2u
3008 #define LCD_WF8B_BPBLCD61_SHIFT 1
3009 #define LCD_WF8B_BPBLCD37_MASK 0x2u
3010 #define LCD_WF8B_BPBLCD37_SHIFT 1
3011 #define LCD_WF8B_BPBLCD31_MASK 0x2u
3012 #define LCD_WF8B_BPBLCD31_SHIFT 1
3013 #define LCD_WF8B_BPBLCD58_MASK 0x2u
3014 #define LCD_WF8B_BPBLCD58_SHIFT 1
3015 #define LCD_WF8B_BPBLCD18_MASK 0x2u
3016 #define LCD_WF8B_BPBLCD18_SHIFT 1
3017 #define LCD_WF8B_BPBLCD45_MASK 0x2u
3018 #define LCD_WF8B_BPBLCD45_SHIFT 1
3019 #define LCD_WF8B_BPBLCD27_MASK 0x2u
3020 #define LCD_WF8B_BPBLCD27_SHIFT 1
3021 #define LCD_WF8B_BPBLCD14_MASK 0x2u
3022 #define LCD_WF8B_BPBLCD14_SHIFT 1
3023 #define LCD_WF8B_BPBLCD51_MASK 0x2u
3024 #define LCD_WF8B_BPBLCD51_SHIFT 1
3025 #define LCD_WF8B_BPBLCD52_MASK 0x2u
3026 #define LCD_WF8B_BPBLCD52_SHIFT 1
3027 #define LCD_WF8B_BPBLCD4_MASK 0x2u
3028 #define LCD_WF8B_BPBLCD4_SHIFT 1
3029 #define LCD_WF8B_BPBLCD35_MASK 0x2u
3030 #define LCD_WF8B_BPBLCD35_SHIFT 1
3031 #define LCD_WF8B_BPBLCD17_MASK 0x2u
3032 #define LCD_WF8B_BPBLCD17_SHIFT 1
3033 #define LCD_WF8B_BPBLCD41_MASK 0x2u
3034 #define LCD_WF8B_BPBLCD41_SHIFT 1
3035 #define LCD_WF8B_BPBLCD11_MASK 0x2u
3036 #define LCD_WF8B_BPBLCD11_SHIFT 1
3037 #define LCD_WF8B_BPBLCD46_MASK 0x2u
3038 #define LCD_WF8B_BPBLCD46_SHIFT 1
3039 #define LCD_WF8B_BPBLCD57_MASK 0x2u
3040 #define LCD_WF8B_BPBLCD57_SHIFT 1
3041 #define LCD_WF8B_BPBLCD42_MASK 0x2u
3042 #define LCD_WF8B_BPBLCD42_SHIFT 1
3043 #define LCD_WF8B_BPBLCD5_MASK 0x2u
3044 #define LCD_WF8B_BPBLCD5_SHIFT 1
3045 #define LCD_WF8B_BPBLCD3_MASK 0x2u
3046 #define LCD_WF8B_BPBLCD3_SHIFT 1
3047 #define LCD_WF8B_BPBLCD16_MASK 0x2u
3048 #define LCD_WF8B_BPBLCD16_SHIFT 1
3049 #define LCD_WF8B_BPBLCD13_MASK 0x2u
3050 #define LCD_WF8B_BPBLCD13_SHIFT 1
3051 #define LCD_WF8B_BPCLCD10_MASK 0x4u
3052 #define LCD_WF8B_BPCLCD10_SHIFT 2
3053 #define LCD_WF8B_BPCLCD55_MASK 0x4u
3054 #define LCD_WF8B_BPCLCD55_SHIFT 2
3055 #define LCD_WF8B_BPCLCD2_MASK 0x4u
3056 #define LCD_WF8B_BPCLCD2_SHIFT 2
3057 #define LCD_WF8B_BPCLCD23_MASK 0x4u
3058 #define LCD_WF8B_BPCLCD23_SHIFT 2
3059 #define LCD_WF8B_BPCLCD48_MASK 0x4u
3060 #define LCD_WF8B_BPCLCD48_SHIFT 2
3061 #define LCD_WF8B_BPCLCD24_MASK 0x4u
3062 #define LCD_WF8B_BPCLCD24_SHIFT 2
3063 #define LCD_WF8B_BPCLCD60_MASK 0x4u
3064 #define LCD_WF8B_BPCLCD60_SHIFT 2
3065 #define LCD_WF8B_BPCLCD47_MASK 0x4u
3066 #define LCD_WF8B_BPCLCD47_SHIFT 2
3067 #define LCD_WF8B_BPCLCD22_MASK 0x4u
3068 #define LCD_WF8B_BPCLCD22_SHIFT 2
3069 #define LCD_WF8B_BPCLCD8_MASK 0x4u
3070 #define LCD_WF8B_BPCLCD8_SHIFT 2
3071 #define LCD_WF8B_BPCLCD21_MASK 0x4u
3072 #define LCD_WF8B_BPCLCD21_SHIFT 2
3073 #define LCD_WF8B_BPCLCD49_MASK 0x4u
3074 #define LCD_WF8B_BPCLCD49_SHIFT 2
3075 #define LCD_WF8B_BPCLCD25_MASK 0x4u
3076 #define LCD_WF8B_BPCLCD25_SHIFT 2
3077 #define LCD_WF8B_BPCLCD1_MASK 0x4u
3078 #define LCD_WF8B_BPCLCD1_SHIFT 2
3079 #define LCD_WF8B_BPCLCD20_MASK 0x4u
3080 #define LCD_WF8B_BPCLCD20_SHIFT 2
3081 #define LCD_WF8B_BPCLCD50_MASK 0x4u
3082 #define LCD_WF8B_BPCLCD50_SHIFT 2
3083 #define LCD_WF8B_BPCLCD19_MASK 0x4u
3084 #define LCD_WF8B_BPCLCD19_SHIFT 2
3085 #define LCD_WF8B_BPCLCD26_MASK 0x4u
3086 #define LCD_WF8B_BPCLCD26_SHIFT 2
3087 #define LCD_WF8B_BPCLCD59_MASK 0x4u
3088 #define LCD_WF8B_BPCLCD59_SHIFT 2
3089 #define LCD_WF8B_BPCLCD61_MASK 0x4u
3090 #define LCD_WF8B_BPCLCD61_SHIFT 2
3091 #define LCD_WF8B_BPCLCD46_MASK 0x4u
3092 #define LCD_WF8B_BPCLCD46_SHIFT 2
3093 #define LCD_WF8B_BPCLCD18_MASK 0x4u
3094 #define LCD_WF8B_BPCLCD18_SHIFT 2
3095 #define LCD_WF8B_BPCLCD5_MASK 0x4u
3096 #define LCD_WF8B_BPCLCD5_SHIFT 2
3097 #define LCD_WF8B_BPCLCD63_MASK 0x4u
3098 #define LCD_WF8B_BPCLCD63_SHIFT 2
3099 #define LCD_WF8B_BPCLCD27_MASK 0x4u
3100 #define LCD_WF8B_BPCLCD27_SHIFT 2
3101 #define LCD_WF8B_BPCLCD17_MASK 0x4u
3102 #define LCD_WF8B_BPCLCD17_SHIFT 2
3103 #define LCD_WF8B_BPCLCD51_MASK 0x4u
3104 #define LCD_WF8B_BPCLCD51_SHIFT 2
3105 #define LCD_WF8B_BPCLCD9_MASK 0x4u
3106 #define LCD_WF8B_BPCLCD9_SHIFT 2
3107 #define LCD_WF8B_BPCLCD54_MASK 0x4u
3108 #define LCD_WF8B_BPCLCD54_SHIFT 2
3109 #define LCD_WF8B_BPCLCD15_MASK 0x4u
3110 #define LCD_WF8B_BPCLCD15_SHIFT 2
3111 #define LCD_WF8B_BPCLCD16_MASK 0x4u
3112 #define LCD_WF8B_BPCLCD16_SHIFT 2
3113 #define LCD_WF8B_BPCLCD14_MASK 0x4u
3114 #define LCD_WF8B_BPCLCD14_SHIFT 2
3115 #define LCD_WF8B_BPCLCD32_MASK 0x4u
3116 #define LCD_WF8B_BPCLCD32_SHIFT 2
3117 #define LCD_WF8B_BPCLCD28_MASK 0x4u
3118 #define LCD_WF8B_BPCLCD28_SHIFT 2
3119 #define LCD_WF8B_BPCLCD53_MASK 0x4u
3120 #define LCD_WF8B_BPCLCD53_SHIFT 2
3121 #define LCD_WF8B_BPCLCD33_MASK 0x4u
3122 #define LCD_WF8B_BPCLCD33_SHIFT 2
3123 #define LCD_WF8B_BPCLCD0_MASK 0x4u
3124 #define LCD_WF8B_BPCLCD0_SHIFT 2
3125 #define LCD_WF8B_BPCLCD43_MASK 0x4u
3126 #define LCD_WF8B_BPCLCD43_SHIFT 2
3127 #define LCD_WF8B_BPCLCD7_MASK 0x4u
3128 #define LCD_WF8B_BPCLCD7_SHIFT 2
3129 #define LCD_WF8B_BPCLCD4_MASK 0x4u
3130 #define LCD_WF8B_BPCLCD4_SHIFT 2
3131 #define LCD_WF8B_BPCLCD34_MASK 0x4u
3132 #define LCD_WF8B_BPCLCD34_SHIFT 2
3133 #define LCD_WF8B_BPCLCD29_MASK 0x4u
3134 #define LCD_WF8B_BPCLCD29_SHIFT 2
3135 #define LCD_WF8B_BPCLCD45_MASK 0x4u
3136 #define LCD_WF8B_BPCLCD45_SHIFT 2
3137 #define LCD_WF8B_BPCLCD57_MASK 0x4u
3138 #define LCD_WF8B_BPCLCD57_SHIFT 2
3139 #define LCD_WF8B_BPCLCD42_MASK 0x4u
3140 #define LCD_WF8B_BPCLCD42_SHIFT 2
3141 #define LCD_WF8B_BPCLCD35_MASK 0x4u
3142 #define LCD_WF8B_BPCLCD35_SHIFT 2
3143 #define LCD_WF8B_BPCLCD13_MASK 0x4u
3144 #define LCD_WF8B_BPCLCD13_SHIFT 2
3145 #define LCD_WF8B_BPCLCD36_MASK 0x4u
3146 #define LCD_WF8B_BPCLCD36_SHIFT 2
3147 #define LCD_WF8B_BPCLCD30_MASK 0x4u
3148 #define LCD_WF8B_BPCLCD30_SHIFT 2
3149 #define LCD_WF8B_BPCLCD52_MASK 0x4u
3150 #define LCD_WF8B_BPCLCD52_SHIFT 2
3151 #define LCD_WF8B_BPCLCD58_MASK 0x4u
3152 #define LCD_WF8B_BPCLCD58_SHIFT 2
3153 #define LCD_WF8B_BPCLCD41_MASK 0x4u
3154 #define LCD_WF8B_BPCLCD41_SHIFT 2
3155 #define LCD_WF8B_BPCLCD37_MASK 0x4u
3156 #define LCD_WF8B_BPCLCD37_SHIFT 2
3157 #define LCD_WF8B_BPCLCD3_MASK 0x4u
3158 #define LCD_WF8B_BPCLCD3_SHIFT 2
3159 #define LCD_WF8B_BPCLCD12_MASK 0x4u
3160 #define LCD_WF8B_BPCLCD12_SHIFT 2
3161 #define LCD_WF8B_BPCLCD11_MASK 0x4u
3162 #define LCD_WF8B_BPCLCD11_SHIFT 2
3163 #define LCD_WF8B_BPCLCD38_MASK 0x4u
3164 #define LCD_WF8B_BPCLCD38_SHIFT 2
3165 #define LCD_WF8B_BPCLCD44_MASK 0x4u
3166 #define LCD_WF8B_BPCLCD44_SHIFT 2
3167 #define LCD_WF8B_BPCLCD31_MASK 0x4u
3168 #define LCD_WF8B_BPCLCD31_SHIFT 2
3169 #define LCD_WF8B_BPCLCD40_MASK 0x4u
3170 #define LCD_WF8B_BPCLCD40_SHIFT 2
3171 #define LCD_WF8B_BPCLCD62_MASK 0x4u
3172 #define LCD_WF8B_BPCLCD62_SHIFT 2
3173 #define LCD_WF8B_BPCLCD56_MASK 0x4u
3174 #define LCD_WF8B_BPCLCD56_SHIFT 2
3175 #define LCD_WF8B_BPCLCD39_MASK 0x4u
3176 #define LCD_WF8B_BPCLCD39_SHIFT 2
3177 #define LCD_WF8B_BPCLCD6_MASK 0x4u
3178 #define LCD_WF8B_BPCLCD6_SHIFT 2
3179 #define LCD_WF8B_BPDLCD47_MASK 0x8u
3180 #define LCD_WF8B_BPDLCD47_SHIFT 3
3181 #define LCD_WF8B_BPDLCD23_MASK 0x8u
3182 #define LCD_WF8B_BPDLCD23_SHIFT 3
3183 #define LCD_WF8B_BPDLCD48_MASK 0x8u
3184 #define LCD_WF8B_BPDLCD48_SHIFT 3
3185 #define LCD_WF8B_BPDLCD24_MASK 0x8u
3186 #define LCD_WF8B_BPDLCD24_SHIFT 3
3187 #define LCD_WF8B_BPDLCD15_MASK 0x8u
3188 #define LCD_WF8B_BPDLCD15_SHIFT 3
3189 #define LCD_WF8B_BPDLCD22_MASK 0x8u
3190 #define LCD_WF8B_BPDLCD22_SHIFT 3
3191 #define LCD_WF8B_BPDLCD60_MASK 0x8u
3192 #define LCD_WF8B_BPDLCD60_SHIFT 3
3193 #define LCD_WF8B_BPDLCD10_MASK 0x8u
3194 #define LCD_WF8B_BPDLCD10_SHIFT 3
3195 #define LCD_WF8B_BPDLCD21_MASK 0x8u
3196 #define LCD_WF8B_BPDLCD21_SHIFT 3
3197 #define LCD_WF8B_BPDLCD49_MASK 0x8u
3198 #define LCD_WF8B_BPDLCD49_SHIFT 3
3199 #define LCD_WF8B_BPDLCD1_MASK 0x8u
3200 #define LCD_WF8B_BPDLCD1_SHIFT 3
3201 #define LCD_WF8B_BPDLCD25_MASK 0x8u
3202 #define LCD_WF8B_BPDLCD25_SHIFT 3
3203 #define LCD_WF8B_BPDLCD20_MASK 0x8u
3204 #define LCD_WF8B_BPDLCD20_SHIFT 3
3205 #define LCD_WF8B_BPDLCD2_MASK 0x8u
3206 #define LCD_WF8B_BPDLCD2_SHIFT 3
3207 #define LCD_WF8B_BPDLCD55_MASK 0x8u
3208 #define LCD_WF8B_BPDLCD55_SHIFT 3
3209 #define LCD_WF8B_BPDLCD59_MASK 0x8u
3210 #define LCD_WF8B_BPDLCD59_SHIFT 3
3211 #define LCD_WF8B_BPDLCD5_MASK 0x8u
3212 #define LCD_WF8B_BPDLCD5_SHIFT 3
3213 #define LCD_WF8B_BPDLCD19_MASK 0x8u
3214 #define LCD_WF8B_BPDLCD19_SHIFT 3
3215 #define LCD_WF8B_BPDLCD6_MASK 0x8u
3216 #define LCD_WF8B_BPDLCD6_SHIFT 3
3217 #define LCD_WF8B_BPDLCD26_MASK 0x8u
3218 #define LCD_WF8B_BPDLCD26_SHIFT 3
3219 #define LCD_WF8B_BPDLCD0_MASK 0x8u
3220 #define LCD_WF8B_BPDLCD0_SHIFT 3
3221 #define LCD_WF8B_BPDLCD50_MASK 0x8u
3222 #define LCD_WF8B_BPDLCD50_SHIFT 3
3223 #define LCD_WF8B_BPDLCD46_MASK 0x8u
3224 #define LCD_WF8B_BPDLCD46_SHIFT 3
3225 #define LCD_WF8B_BPDLCD18_MASK 0x8u
3226 #define LCD_WF8B_BPDLCD18_SHIFT 3
3227 #define LCD_WF8B_BPDLCD61_MASK 0x8u
3228 #define LCD_WF8B_BPDLCD61_SHIFT 3
3229 #define LCD_WF8B_BPDLCD9_MASK 0x8u
3230 #define LCD_WF8B_BPDLCD9_SHIFT 3
3231 #define LCD_WF8B_BPDLCD17_MASK 0x8u
3232 #define LCD_WF8B_BPDLCD17_SHIFT 3
3233 #define LCD_WF8B_BPDLCD27_MASK 0x8u
3234 #define LCD_WF8B_BPDLCD27_SHIFT 3
3235 #define LCD_WF8B_BPDLCD53_MASK 0x8u
3236 #define LCD_WF8B_BPDLCD53_SHIFT 3
3237 #define LCD_WF8B_BPDLCD51_MASK 0x8u
3238 #define LCD_WF8B_BPDLCD51_SHIFT 3
3239 #define LCD_WF8B_BPDLCD54_MASK 0x8u
3240 #define LCD_WF8B_BPDLCD54_SHIFT 3
3241 #define LCD_WF8B_BPDLCD13_MASK 0x8u
3242 #define LCD_WF8B_BPDLCD13_SHIFT 3
3243 #define LCD_WF8B_BPDLCD16_MASK 0x8u
3244 #define LCD_WF8B_BPDLCD16_SHIFT 3
3245 #define LCD_WF8B_BPDLCD32_MASK 0x8u
3246 #define LCD_WF8B_BPDLCD32_SHIFT 3
3247 #define LCD_WF8B_BPDLCD14_MASK 0x8u
3248 #define LCD_WF8B_BPDLCD14_SHIFT 3
3249 #define LCD_WF8B_BPDLCD28_MASK 0x8u
3250 #define LCD_WF8B_BPDLCD28_SHIFT 3
3251 #define LCD_WF8B_BPDLCD43_MASK 0x8u
3252 #define LCD_WF8B_BPDLCD43_SHIFT 3
3253 #define LCD_WF8B_BPDLCD4_MASK 0x8u
3254 #define LCD_WF8B_BPDLCD4_SHIFT 3
3255 #define LCD_WF8B_BPDLCD45_MASK 0x8u
3256 #define LCD_WF8B_BPDLCD45_SHIFT 3
3257 #define LCD_WF8B_BPDLCD8_MASK 0x8u
3258 #define LCD_WF8B_BPDLCD8_SHIFT 3
3259 #define LCD_WF8B_BPDLCD62_MASK 0x8u
3260 #define LCD_WF8B_BPDLCD62_SHIFT 3
3261 #define LCD_WF8B_BPDLCD33_MASK 0x8u
3262 #define LCD_WF8B_BPDLCD33_SHIFT 3
3263 #define LCD_WF8B_BPDLCD34_MASK 0x8u
3264 #define LCD_WF8B_BPDLCD34_SHIFT 3
3265 #define LCD_WF8B_BPDLCD29_MASK 0x8u
3266 #define LCD_WF8B_BPDLCD29_SHIFT 3
3267 #define LCD_WF8B_BPDLCD58_MASK 0x8u
3268 #define LCD_WF8B_BPDLCD58_SHIFT 3
3269 #define LCD_WF8B_BPDLCD57_MASK 0x8u
3270 #define LCD_WF8B_BPDLCD57_SHIFT 3
3271 #define LCD_WF8B_BPDLCD42_MASK 0x8u
3272 #define LCD_WF8B_BPDLCD42_SHIFT 3
3273 #define LCD_WF8B_BPDLCD35_MASK 0x8u
3274 #define LCD_WF8B_BPDLCD35_SHIFT 3
3275 #define LCD_WF8B_BPDLCD52_MASK 0x8u
3276 #define LCD_WF8B_BPDLCD52_SHIFT 3
3277 #define LCD_WF8B_BPDLCD7_MASK 0x8u
3278 #define LCD_WF8B_BPDLCD7_SHIFT 3
3279 #define LCD_WF8B_BPDLCD36_MASK 0x8u
3280 #define LCD_WF8B_BPDLCD36_SHIFT 3
3281 #define LCD_WF8B_BPDLCD30_MASK 0x8u
3282 #define LCD_WF8B_BPDLCD30_SHIFT 3
3283 #define LCD_WF8B_BPDLCD41_MASK 0x8u
3284 #define LCD_WF8B_BPDLCD41_SHIFT 3
3285 #define LCD_WF8B_BPDLCD37_MASK 0x8u
3286 #define LCD_WF8B_BPDLCD37_SHIFT 3
3287 #define LCD_WF8B_BPDLCD44_MASK 0x8u
3288 #define LCD_WF8B_BPDLCD44_SHIFT 3
3289 #define LCD_WF8B_BPDLCD63_MASK 0x8u
3290 #define LCD_WF8B_BPDLCD63_SHIFT 3
3291 #define LCD_WF8B_BPDLCD38_MASK 0x8u
3292 #define LCD_WF8B_BPDLCD38_SHIFT 3
3293 #define LCD_WF8B_BPDLCD56_MASK 0x8u
3294 #define LCD_WF8B_BPDLCD56_SHIFT 3
3295 #define LCD_WF8B_BPDLCD40_MASK 0x8u
3296 #define LCD_WF8B_BPDLCD40_SHIFT 3
3297 #define LCD_WF8B_BPDLCD31_MASK 0x8u
3298 #define LCD_WF8B_BPDLCD31_SHIFT 3
3299 #define LCD_WF8B_BPDLCD12_MASK 0x8u
3300 #define LCD_WF8B_BPDLCD12_SHIFT 3
3301 #define LCD_WF8B_BPDLCD39_MASK 0x8u
3302 #define LCD_WF8B_BPDLCD39_SHIFT 3
3303 #define LCD_WF8B_BPDLCD3_MASK 0x8u
3304 #define LCD_WF8B_BPDLCD3_SHIFT 3
3305 #define LCD_WF8B_BPDLCD11_MASK 0x8u
3306 #define LCD_WF8B_BPDLCD11_SHIFT 3
3307 #define LCD_WF8B_BPELCD12_MASK 0x10u
3308 #define LCD_WF8B_BPELCD12_SHIFT 4
3309 #define LCD_WF8B_BPELCD39_MASK 0x10u
3310 #define LCD_WF8B_BPELCD39_SHIFT 4
3311 #define LCD_WF8B_BPELCD3_MASK 0x10u
3312 #define LCD_WF8B_BPELCD3_SHIFT 4
3313 #define LCD_WF8B_BPELCD38_MASK 0x10u
3314 #define LCD_WF8B_BPELCD38_SHIFT 4
3315 #define LCD_WF8B_BPELCD40_MASK 0x10u
3316 #define LCD_WF8B_BPELCD40_SHIFT 4
3317 #define LCD_WF8B_BPELCD37_MASK 0x10u
3318 #define LCD_WF8B_BPELCD37_SHIFT 4
3319 #define LCD_WF8B_BPELCD41_MASK 0x10u
3320 #define LCD_WF8B_BPELCD41_SHIFT 4
3321 #define LCD_WF8B_BPELCD36_MASK 0x10u
3322 #define LCD_WF8B_BPELCD36_SHIFT 4
3323 #define LCD_WF8B_BPELCD8_MASK 0x10u
3324 #define LCD_WF8B_BPELCD8_SHIFT 4
3325 #define LCD_WF8B_BPELCD35_MASK 0x10u
3326 #define LCD_WF8B_BPELCD35_SHIFT 4
3327 #define LCD_WF8B_BPELCD42_MASK 0x10u
3328 #define LCD_WF8B_BPELCD42_SHIFT 4
3329 #define LCD_WF8B_BPELCD34_MASK 0x10u
3330 #define LCD_WF8B_BPELCD34_SHIFT 4
3331 #define LCD_WF8B_BPELCD33_MASK 0x10u
3332 #define LCD_WF8B_BPELCD33_SHIFT 4
3333 #define LCD_WF8B_BPELCD11_MASK 0x10u
3334 #define LCD_WF8B_BPELCD11_SHIFT 4
3335 #define LCD_WF8B_BPELCD43_MASK 0x10u
3336 #define LCD_WF8B_BPELCD43_SHIFT 4
3337 #define LCD_WF8B_BPELCD32_MASK 0x10u
3338 #define LCD_WF8B_BPELCD32_SHIFT 4
3339 #define LCD_WF8B_BPELCD31_MASK 0x10u
3340 #define LCD_WF8B_BPELCD31_SHIFT 4
3341 #define LCD_WF8B_BPELCD44_MASK 0x10u
3342 #define LCD_WF8B_BPELCD44_SHIFT 4
3343 #define LCD_WF8B_BPELCD30_MASK 0x10u
3344 #define LCD_WF8B_BPELCD30_SHIFT 4
3345 #define LCD_WF8B_BPELCD29_MASK 0x10u
3346 #define LCD_WF8B_BPELCD29_SHIFT 4
3347 #define LCD_WF8B_BPELCD7_MASK 0x10u
3348 #define LCD_WF8B_BPELCD7_SHIFT 4
3349 #define LCD_WF8B_BPELCD45_MASK 0x10u
3350 #define LCD_WF8B_BPELCD45_SHIFT 4
3351 #define LCD_WF8B_BPELCD28_MASK 0x10u
3352 #define LCD_WF8B_BPELCD28_SHIFT 4
3353 #define LCD_WF8B_BPELCD2_MASK 0x10u
3354 #define LCD_WF8B_BPELCD2_SHIFT 4
3355 #define LCD_WF8B_BPELCD27_MASK 0x10u
3356 #define LCD_WF8B_BPELCD27_SHIFT 4
3357 #define LCD_WF8B_BPELCD46_MASK 0x10u
3358 #define LCD_WF8B_BPELCD46_SHIFT 4
3359 #define LCD_WF8B_BPELCD26_MASK 0x10u
3360 #define LCD_WF8B_BPELCD26_SHIFT 4
3361 #define LCD_WF8B_BPELCD10_MASK 0x10u
3362 #define LCD_WF8B_BPELCD10_SHIFT 4
3363 #define LCD_WF8B_BPELCD13_MASK 0x10u
3364 #define LCD_WF8B_BPELCD13_SHIFT 4
3365 #define LCD_WF8B_BPELCD25_MASK 0x10u
3366 #define LCD_WF8B_BPELCD25_SHIFT 4
3367 #define LCD_WF8B_BPELCD5_MASK 0x10u
3368 #define LCD_WF8B_BPELCD5_SHIFT 4
3369 #define LCD_WF8B_BPELCD24_MASK 0x10u
3370 #define LCD_WF8B_BPELCD24_SHIFT 4
3371 #define LCD_WF8B_BPELCD47_MASK 0x10u
3372 #define LCD_WF8B_BPELCD47_SHIFT 4
3373 #define LCD_WF8B_BPELCD23_MASK 0x10u
3374 #define LCD_WF8B_BPELCD23_SHIFT 4
3375 #define LCD_WF8B_BPELCD22_MASK 0x10u
3376 #define LCD_WF8B_BPELCD22_SHIFT 4
3377 #define LCD_WF8B_BPELCD48_MASK 0x10u
3378 #define LCD_WF8B_BPELCD48_SHIFT 4
3379 #define LCD_WF8B_BPELCD21_MASK 0x10u
3380 #define LCD_WF8B_BPELCD21_SHIFT 4
3381 #define LCD_WF8B_BPELCD49_MASK 0x10u
3382 #define LCD_WF8B_BPELCD49_SHIFT 4
3383 #define LCD_WF8B_BPELCD20_MASK 0x10u
3384 #define LCD_WF8B_BPELCD20_SHIFT 4
3385 #define LCD_WF8B_BPELCD19_MASK 0x10u
3386 #define LCD_WF8B_BPELCD19_SHIFT 4
3387 #define LCD_WF8B_BPELCD9_MASK 0x10u
3388 #define LCD_WF8B_BPELCD9_SHIFT 4
3389 #define LCD_WF8B_BPELCD50_MASK 0x10u
3390 #define LCD_WF8B_BPELCD50_SHIFT 4
3391 #define LCD_WF8B_BPELCD18_MASK 0x10u
3392 #define LCD_WF8B_BPELCD18_SHIFT 4
3393 #define LCD_WF8B_BPELCD6_MASK 0x10u
3394 #define LCD_WF8B_BPELCD6_SHIFT 4
3395 #define LCD_WF8B_BPELCD17_MASK 0x10u
3396 #define LCD_WF8B_BPELCD17_SHIFT 4
3397 #define LCD_WF8B_BPELCD51_MASK 0x10u
3398 #define LCD_WF8B_BPELCD51_SHIFT 4
3399 #define LCD_WF8B_BPELCD16_MASK 0x10u
3400 #define LCD_WF8B_BPELCD16_SHIFT 4
3401 #define LCD_WF8B_BPELCD56_MASK 0x10u
3402 #define LCD_WF8B_BPELCD56_SHIFT 4
3403 #define LCD_WF8B_BPELCD57_MASK 0x10u
3404 #define LCD_WF8B_BPELCD57_SHIFT 4
3405 #define LCD_WF8B_BPELCD52_MASK 0x10u
3406 #define LCD_WF8B_BPELCD52_SHIFT 4
3407 #define LCD_WF8B_BPELCD1_MASK 0x10u
3408 #define LCD_WF8B_BPELCD1_SHIFT 4
3409 #define LCD_WF8B_BPELCD58_MASK 0x10u
3410 #define LCD_WF8B_BPELCD58_SHIFT 4
3411 #define LCD_WF8B_BPELCD59_MASK 0x10u
3412 #define LCD_WF8B_BPELCD59_SHIFT 4
3413 #define LCD_WF8B_BPELCD53_MASK 0x10u
3414 #define LCD_WF8B_BPELCD53_SHIFT 4
3415 #define LCD_WF8B_BPELCD14_MASK 0x10u
3416 #define LCD_WF8B_BPELCD14_SHIFT 4
3417 #define LCD_WF8B_BPELCD0_MASK 0x10u
3418 #define LCD_WF8B_BPELCD0_SHIFT 4
3419 #define LCD_WF8B_BPELCD60_MASK 0x10u
3420 #define LCD_WF8B_BPELCD60_SHIFT 4
3421 #define LCD_WF8B_BPELCD15_MASK 0x10u
3422 #define LCD_WF8B_BPELCD15_SHIFT 4
3423 #define LCD_WF8B_BPELCD61_MASK 0x10u
3424 #define LCD_WF8B_BPELCD61_SHIFT 4
3425 #define LCD_WF8B_BPELCD54_MASK 0x10u
3426 #define LCD_WF8B_BPELCD54_SHIFT 4
3427 #define LCD_WF8B_BPELCD62_MASK 0x10u
3428 #define LCD_WF8B_BPELCD62_SHIFT 4
3429 #define LCD_WF8B_BPELCD63_MASK 0x10u
3430 #define LCD_WF8B_BPELCD63_SHIFT 4
3431 #define LCD_WF8B_BPELCD55_MASK 0x10u
3432 #define LCD_WF8B_BPELCD55_SHIFT 4
3433 #define LCD_WF8B_BPELCD4_MASK 0x10u
3434 #define LCD_WF8B_BPELCD4_SHIFT 4
3435 #define LCD_WF8B_BPFLCD13_MASK 0x20u
3436 #define LCD_WF8B_BPFLCD13_SHIFT 5
3437 #define LCD_WF8B_BPFLCD39_MASK 0x20u
3438 #define LCD_WF8B_BPFLCD39_SHIFT 5
3439 #define LCD_WF8B_BPFLCD55_MASK 0x20u
3440 #define LCD_WF8B_BPFLCD55_SHIFT 5
3441 #define LCD_WF8B_BPFLCD47_MASK 0x20u
3442 #define LCD_WF8B_BPFLCD47_SHIFT 5
3443 #define LCD_WF8B_BPFLCD63_MASK 0x20u
3444 #define LCD_WF8B_BPFLCD63_SHIFT 5
3445 #define LCD_WF8B_BPFLCD43_MASK 0x20u
3446 #define LCD_WF8B_BPFLCD43_SHIFT 5
3447 #define LCD_WF8B_BPFLCD5_MASK 0x20u
3448 #define LCD_WF8B_BPFLCD5_SHIFT 5
3449 #define LCD_WF8B_BPFLCD62_MASK 0x20u
3450 #define LCD_WF8B_BPFLCD62_SHIFT 5
3451 #define LCD_WF8B_BPFLCD14_MASK 0x20u
3452 #define LCD_WF8B_BPFLCD14_SHIFT 5
3453 #define LCD_WF8B_BPFLCD24_MASK 0x20u
3454 #define LCD_WF8B_BPFLCD24_SHIFT 5
3455 #define LCD_WF8B_BPFLCD54_MASK 0x20u
3456 #define LCD_WF8B_BPFLCD54_SHIFT 5
3457 #define LCD_WF8B_BPFLCD15_MASK 0x20u
3458 #define LCD_WF8B_BPFLCD15_SHIFT 5
3459 #define LCD_WF8B_BPFLCD32_MASK 0x20u
3460 #define LCD_WF8B_BPFLCD32_SHIFT 5
3461 #define LCD_WF8B_BPFLCD61_MASK 0x20u
3462 #define LCD_WF8B_BPFLCD61_SHIFT 5
3463 #define LCD_WF8B_BPFLCD25_MASK 0x20u
3464 #define LCD_WF8B_BPFLCD25_SHIFT 5
3465 #define LCD_WF8B_BPFLCD60_MASK 0x20u
3466 #define LCD_WF8B_BPFLCD60_SHIFT 5
3467 #define LCD_WF8B_BPFLCD41_MASK 0x20u
3468 #define LCD_WF8B_BPFLCD41_SHIFT 5
3469 #define LCD_WF8B_BPFLCD33_MASK 0x20u
3470 #define LCD_WF8B_BPFLCD33_SHIFT 5
3471 #define LCD_WF8B_BPFLCD53_MASK 0x20u
3472 #define LCD_WF8B_BPFLCD53_SHIFT 5
3473 #define LCD_WF8B_BPFLCD59_MASK 0x20u
3474 #define LCD_WF8B_BPFLCD59_SHIFT 5
3475 #define LCD_WF8B_BPFLCD0_MASK 0x20u
3476 #define LCD_WF8B_BPFLCD0_SHIFT 5
3477 #define LCD_WF8B_BPFLCD46_MASK 0x20u
3478 #define LCD_WF8B_BPFLCD46_SHIFT 5
3479 #define LCD_WF8B_BPFLCD58_MASK 0x20u
3480 #define LCD_WF8B_BPFLCD58_SHIFT 5
3481 #define LCD_WF8B_BPFLCD26_MASK 0x20u
3482 #define LCD_WF8B_BPFLCD26_SHIFT 5
3483 #define LCD_WF8B_BPFLCD36_MASK 0x20u
3484 #define LCD_WF8B_BPFLCD36_SHIFT 5
3485 #define LCD_WF8B_BPFLCD10_MASK 0x20u
3486 #define LCD_WF8B_BPFLCD10_SHIFT 5
3487 #define LCD_WF8B_BPFLCD52_MASK 0x20u
3488 #define LCD_WF8B_BPFLCD52_SHIFT 5
3489 #define LCD_WF8B_BPFLCD57_MASK 0x20u
3490 #define LCD_WF8B_BPFLCD57_SHIFT 5
3491 #define LCD_WF8B_BPFLCD27_MASK 0x20u
3492 #define LCD_WF8B_BPFLCD27_SHIFT 5
3493 #define LCD_WF8B_BPFLCD11_MASK 0x20u
3494 #define LCD_WF8B_BPFLCD11_SHIFT 5
3495 #define LCD_WF8B_BPFLCD56_MASK 0x20u
3496 #define LCD_WF8B_BPFLCD56_SHIFT 5
3497 #define LCD_WF8B_BPFLCD1_MASK 0x20u
3498 #define LCD_WF8B_BPFLCD1_SHIFT 5
3499 #define LCD_WF8B_BPFLCD8_MASK 0x20u
3500 #define LCD_WF8B_BPFLCD8_SHIFT 5
3501 #define LCD_WF8B_BPFLCD40_MASK 0x20u
3502 #define LCD_WF8B_BPFLCD40_SHIFT 5
3503 #define LCD_WF8B_BPFLCD51_MASK 0x20u
3504 #define LCD_WF8B_BPFLCD51_SHIFT 5
3505 #define LCD_WF8B_BPFLCD16_MASK 0x20u
3506 #define LCD_WF8B_BPFLCD16_SHIFT 5
3507 #define LCD_WF8B_BPFLCD45_MASK 0x20u
3508 #define LCD_WF8B_BPFLCD45_SHIFT 5
3509 #define LCD_WF8B_BPFLCD6_MASK 0x20u
3510 #define LCD_WF8B_BPFLCD6_SHIFT 5
3511 #define LCD_WF8B_BPFLCD17_MASK 0x20u
3512 #define LCD_WF8B_BPFLCD17_SHIFT 5
3513 #define LCD_WF8B_BPFLCD28_MASK 0x20u
3514 #define LCD_WF8B_BPFLCD28_SHIFT 5
3515 #define LCD_WF8B_BPFLCD42_MASK 0x20u
3516 #define LCD_WF8B_BPFLCD42_SHIFT 5
3517 #define LCD_WF8B_BPFLCD29_MASK 0x20u
3518 #define LCD_WF8B_BPFLCD29_SHIFT 5
3519 #define LCD_WF8B_BPFLCD50_MASK 0x20u
3520 #define LCD_WF8B_BPFLCD50_SHIFT 5
3521 #define LCD_WF8B_BPFLCD18_MASK 0x20u
3522 #define LCD_WF8B_BPFLCD18_SHIFT 5
3523 #define LCD_WF8B_BPFLCD34_MASK 0x20u
3524 #define LCD_WF8B_BPFLCD34_SHIFT 5
3525 #define LCD_WF8B_BPFLCD19_MASK 0x20u
3526 #define LCD_WF8B_BPFLCD19_SHIFT 5
3527 #define LCD_WF8B_BPFLCD2_MASK 0x20u
3528 #define LCD_WF8B_BPFLCD2_SHIFT 5
3529 #define LCD_WF8B_BPFLCD9_MASK 0x20u
3530 #define LCD_WF8B_BPFLCD9_SHIFT 5
3531 #define LCD_WF8B_BPFLCD3_MASK 0x20u
3532 #define LCD_WF8B_BPFLCD3_SHIFT 5
3533 #define LCD_WF8B_BPFLCD37_MASK 0x20u
3534 #define LCD_WF8B_BPFLCD37_SHIFT 5
3535 #define LCD_WF8B_BPFLCD49_MASK 0x20u
3536 #define LCD_WF8B_BPFLCD49_SHIFT 5
3537 #define LCD_WF8B_BPFLCD20_MASK 0x20u
3538 #define LCD_WF8B_BPFLCD20_SHIFT 5
3539 #define LCD_WF8B_BPFLCD44_MASK 0x20u
3540 #define LCD_WF8B_BPFLCD44_SHIFT 5
3541 #define LCD_WF8B_BPFLCD30_MASK 0x20u
3542 #define LCD_WF8B_BPFLCD30_SHIFT 5
3543 #define LCD_WF8B_BPFLCD21_MASK 0x20u
3544 #define LCD_WF8B_BPFLCD21_SHIFT 5
3545 #define LCD_WF8B_BPFLCD35_MASK 0x20u
3546 #define LCD_WF8B_BPFLCD35_SHIFT 5
3547 #define LCD_WF8B_BPFLCD4_MASK 0x20u
3548 #define LCD_WF8B_BPFLCD4_SHIFT 5
3549 #define LCD_WF8B_BPFLCD31_MASK 0x20u
3550 #define LCD_WF8B_BPFLCD31_SHIFT 5
3551 #define LCD_WF8B_BPFLCD48_MASK 0x20u
3552 #define LCD_WF8B_BPFLCD48_SHIFT 5
3553 #define LCD_WF8B_BPFLCD7_MASK 0x20u
3554 #define LCD_WF8B_BPFLCD7_SHIFT 5
3555 #define LCD_WF8B_BPFLCD22_MASK 0x20u
3556 #define LCD_WF8B_BPFLCD22_SHIFT 5
3557 #define LCD_WF8B_BPFLCD38_MASK 0x20u
3558 #define LCD_WF8B_BPFLCD38_SHIFT 5
3559 #define LCD_WF8B_BPFLCD12_MASK 0x20u
3560 #define LCD_WF8B_BPFLCD12_SHIFT 5
3561 #define LCD_WF8B_BPFLCD23_MASK 0x20u
3562 #define LCD_WF8B_BPFLCD23_SHIFT 5
3563 #define LCD_WF8B_BPGLCD14_MASK 0x40u
3564 #define LCD_WF8B_BPGLCD14_SHIFT 6
3565 #define LCD_WF8B_BPGLCD55_MASK 0x40u
3566 #define LCD_WF8B_BPGLCD55_SHIFT 6
3567 #define LCD_WF8B_BPGLCD63_MASK 0x40u
3568 #define LCD_WF8B_BPGLCD63_SHIFT 6
3569 #define LCD_WF8B_BPGLCD15_MASK 0x40u
3570 #define LCD_WF8B_BPGLCD15_SHIFT 6
3571 #define LCD_WF8B_BPGLCD62_MASK 0x40u
3572 #define LCD_WF8B_BPGLCD62_SHIFT 6
3573 #define LCD_WF8B_BPGLCD54_MASK 0x40u
3574 #define LCD_WF8B_BPGLCD54_SHIFT 6
3575 #define LCD_WF8B_BPGLCD61_MASK 0x40u
3576 #define LCD_WF8B_BPGLCD61_SHIFT 6
3577 #define LCD_WF8B_BPGLCD60_MASK 0x40u
3578 #define LCD_WF8B_BPGLCD60_SHIFT 6
3579 #define LCD_WF8B_BPGLCD59_MASK 0x40u
3580 #define LCD_WF8B_BPGLCD59_SHIFT 6
3581 #define LCD_WF8B_BPGLCD53_MASK 0x40u
3582 #define LCD_WF8B_BPGLCD53_SHIFT 6
3583 #define LCD_WF8B_BPGLCD58_MASK 0x40u
3584 #define LCD_WF8B_BPGLCD58_SHIFT 6
3585 #define LCD_WF8B_BPGLCD0_MASK 0x40u
3586 #define LCD_WF8B_BPGLCD0_SHIFT 6
3587 #define LCD_WF8B_BPGLCD57_MASK 0x40u
3588 #define LCD_WF8B_BPGLCD57_SHIFT 6
3589 #define LCD_WF8B_BPGLCD52_MASK 0x40u
3590 #define LCD_WF8B_BPGLCD52_SHIFT 6
3591 #define LCD_WF8B_BPGLCD7_MASK 0x40u
3592 #define LCD_WF8B_BPGLCD7_SHIFT 6
3593 #define LCD_WF8B_BPGLCD56_MASK 0x40u
3594 #define LCD_WF8B_BPGLCD56_SHIFT 6
3595 #define LCD_WF8B_BPGLCD6_MASK 0x40u
3596 #define LCD_WF8B_BPGLCD6_SHIFT 6
3597 #define LCD_WF8B_BPGLCD51_MASK 0x40u
3598 #define LCD_WF8B_BPGLCD51_SHIFT 6
3599 #define LCD_WF8B_BPGLCD16_MASK 0x40u
3600 #define LCD_WF8B_BPGLCD16_SHIFT 6
3601 #define LCD_WF8B_BPGLCD1_MASK 0x40u
3602 #define LCD_WF8B_BPGLCD1_SHIFT 6
3603 #define LCD_WF8B_BPGLCD17_MASK 0x40u
3604 #define LCD_WF8B_BPGLCD17_SHIFT 6
3605 #define LCD_WF8B_BPGLCD50_MASK 0x40u
3606 #define LCD_WF8B_BPGLCD50_SHIFT 6
3607 #define LCD_WF8B_BPGLCD18_MASK 0x40u
3608 #define LCD_WF8B_BPGLCD18_SHIFT 6
3609 #define LCD_WF8B_BPGLCD19_MASK 0x40u
3610 #define LCD_WF8B_BPGLCD19_SHIFT 6
3611 #define LCD_WF8B_BPGLCD8_MASK 0x40u
3612 #define LCD_WF8B_BPGLCD8_SHIFT 6
3613 #define LCD_WF8B_BPGLCD49_MASK 0x40u
3614 #define LCD_WF8B_BPGLCD49_SHIFT 6
3615 #define LCD_WF8B_BPGLCD20_MASK 0x40u
3616 #define LCD_WF8B_BPGLCD20_SHIFT 6
3617 #define LCD_WF8B_BPGLCD9_MASK 0x40u
3618 #define LCD_WF8B_BPGLCD9_SHIFT 6
3619 #define LCD_WF8B_BPGLCD21_MASK 0x40u
3620 #define LCD_WF8B_BPGLCD21_SHIFT 6
3621 #define LCD_WF8B_BPGLCD13_MASK 0x40u
3622 #define LCD_WF8B_BPGLCD13_SHIFT 6
3623 #define LCD_WF8B_BPGLCD48_MASK 0x40u
3624 #define LCD_WF8B_BPGLCD48_SHIFT 6
3625 #define LCD_WF8B_BPGLCD22_MASK 0x40u
3626 #define LCD_WF8B_BPGLCD22_SHIFT 6
3627 #define LCD_WF8B_BPGLCD5_MASK 0x40u
3628 #define LCD_WF8B_BPGLCD5_SHIFT 6
3629 #define LCD_WF8B_BPGLCD47_MASK 0x40u
3630 #define LCD_WF8B_BPGLCD47_SHIFT 6
3631 #define LCD_WF8B_BPGLCD23_MASK 0x40u
3632 #define LCD_WF8B_BPGLCD23_SHIFT 6
3633 #define LCD_WF8B_BPGLCD24_MASK 0x40u
3634 #define LCD_WF8B_BPGLCD24_SHIFT 6
3635 #define LCD_WF8B_BPGLCD25_MASK 0x40u
3636 #define LCD_WF8B_BPGLCD25_SHIFT 6
3637 #define LCD_WF8B_BPGLCD46_MASK 0x40u
3638 #define LCD_WF8B_BPGLCD46_SHIFT 6
3639 #define LCD_WF8B_BPGLCD26_MASK 0x40u
3640 #define LCD_WF8B_BPGLCD26_SHIFT 6
3641 #define LCD_WF8B_BPGLCD27_MASK 0x40u
3642 #define LCD_WF8B_BPGLCD27_SHIFT 6
3643 #define LCD_WF8B_BPGLCD10_MASK 0x40u
3644 #define LCD_WF8B_BPGLCD10_SHIFT 6
3645 #define LCD_WF8B_BPGLCD45_MASK 0x40u
3646 #define LCD_WF8B_BPGLCD45_SHIFT 6
3647 #define LCD_WF8B_BPGLCD28_MASK 0x40u
3648 #define LCD_WF8B_BPGLCD28_SHIFT 6
3649 #define LCD_WF8B_BPGLCD29_MASK 0x40u
3650 #define LCD_WF8B_BPGLCD29_SHIFT 6
3651 #define LCD_WF8B_BPGLCD4_MASK 0x40u
3652 #define LCD_WF8B_BPGLCD4_SHIFT 6
3653 #define LCD_WF8B_BPGLCD44_MASK 0x40u
3654 #define LCD_WF8B_BPGLCD44_SHIFT 6
3655 #define LCD_WF8B_BPGLCD30_MASK 0x40u
3656 #define LCD_WF8B_BPGLCD30_SHIFT 6
3657 #define LCD_WF8B_BPGLCD2_MASK 0x40u
3658 #define LCD_WF8B_BPGLCD2_SHIFT 6
3659 #define LCD_WF8B_BPGLCD31_MASK 0x40u
3660 #define LCD_WF8B_BPGLCD31_SHIFT 6
3661 #define LCD_WF8B_BPGLCD43_MASK 0x40u
3662 #define LCD_WF8B_BPGLCD43_SHIFT 6
3663 #define LCD_WF8B_BPGLCD32_MASK 0x40u
3664 #define LCD_WF8B_BPGLCD32_SHIFT 6
3665 #define LCD_WF8B_BPGLCD33_MASK 0x40u
3666 #define LCD_WF8B_BPGLCD33_SHIFT 6
3667 #define LCD_WF8B_BPGLCD42_MASK 0x40u
3668 #define LCD_WF8B_BPGLCD42_SHIFT 6
3669 #define LCD_WF8B_BPGLCD34_MASK 0x40u
3670 #define LCD_WF8B_BPGLCD34_SHIFT 6
3671 #define LCD_WF8B_BPGLCD11_MASK 0x40u
3672 #define LCD_WF8B_BPGLCD11_SHIFT 6
3673 #define LCD_WF8B_BPGLCD35_MASK 0x40u
3674 #define LCD_WF8B_BPGLCD35_SHIFT 6
3675 #define LCD_WF8B_BPGLCD12_MASK 0x40u
3676 #define LCD_WF8B_BPGLCD12_SHIFT 6
3677 #define LCD_WF8B_BPGLCD41_MASK 0x40u
3678 #define LCD_WF8B_BPGLCD41_SHIFT 6
3679 #define LCD_WF8B_BPGLCD36_MASK 0x40u
3680 #define LCD_WF8B_BPGLCD36_SHIFT 6
3681 #define LCD_WF8B_BPGLCD3_MASK 0x40u
3682 #define LCD_WF8B_BPGLCD3_SHIFT 6
3683 #define LCD_WF8B_BPGLCD37_MASK 0x40u
3684 #define LCD_WF8B_BPGLCD37_SHIFT 6
3685 #define LCD_WF8B_BPGLCD40_MASK 0x40u
3686 #define LCD_WF8B_BPGLCD40_SHIFT 6
3687 #define LCD_WF8B_BPGLCD38_MASK 0x40u
3688 #define LCD_WF8B_BPGLCD38_SHIFT 6
3689 #define LCD_WF8B_BPGLCD39_MASK 0x40u
3690 #define LCD_WF8B_BPGLCD39_SHIFT 6
3691 #define LCD_WF8B_BPHLCD63_MASK 0x80u
3692 #define LCD_WF8B_BPHLCD63_SHIFT 7
3693 #define LCD_WF8B_BPHLCD62_MASK 0x80u
3694 #define LCD_WF8B_BPHLCD62_SHIFT 7
3695 #define LCD_WF8B_BPHLCD61_MASK 0x80u
3696 #define LCD_WF8B_BPHLCD61_SHIFT 7
3697 #define LCD_WF8B_BPHLCD60_MASK 0x80u
3698 #define LCD_WF8B_BPHLCD60_SHIFT 7
3699 #define LCD_WF8B_BPHLCD59_MASK 0x80u
3700 #define LCD_WF8B_BPHLCD59_SHIFT 7
3701 #define LCD_WF8B_BPHLCD58_MASK 0x80u
3702 #define LCD_WF8B_BPHLCD58_SHIFT 7
3703 #define LCD_WF8B_BPHLCD57_MASK 0x80u
3704 #define LCD_WF8B_BPHLCD57_SHIFT 7
3705 #define LCD_WF8B_BPHLCD0_MASK 0x80u
3706 #define LCD_WF8B_BPHLCD0_SHIFT 7
3707 #define LCD_WF8B_BPHLCD56_MASK 0x80u
3708 #define LCD_WF8B_BPHLCD56_SHIFT 7
3709 #define LCD_WF8B_BPHLCD55_MASK 0x80u
3710 #define LCD_WF8B_BPHLCD55_SHIFT 7
3711 #define LCD_WF8B_BPHLCD54_MASK 0x80u
3712 #define LCD_WF8B_BPHLCD54_SHIFT 7
3713 #define LCD_WF8B_BPHLCD53_MASK 0x80u
3714 #define LCD_WF8B_BPHLCD53_SHIFT 7
3715 #define LCD_WF8B_BPHLCD52_MASK 0x80u
3716 #define LCD_WF8B_BPHLCD52_SHIFT 7
3717 #define LCD_WF8B_BPHLCD51_MASK 0x80u
3718 #define LCD_WF8B_BPHLCD51_SHIFT 7
3719 #define LCD_WF8B_BPHLCD50_MASK 0x80u
3720 #define LCD_WF8B_BPHLCD50_SHIFT 7
3721 #define LCD_WF8B_BPHLCD1_MASK 0x80u
3722 #define LCD_WF8B_BPHLCD1_SHIFT 7
3723 #define LCD_WF8B_BPHLCD49_MASK 0x80u
3724 #define LCD_WF8B_BPHLCD49_SHIFT 7
3725 #define LCD_WF8B_BPHLCD48_MASK 0x80u
3726 #define LCD_WF8B_BPHLCD48_SHIFT 7
3727 #define LCD_WF8B_BPHLCD47_MASK 0x80u
3728 #define LCD_WF8B_BPHLCD47_SHIFT 7
3729 #define LCD_WF8B_BPHLCD46_MASK 0x80u
3730 #define LCD_WF8B_BPHLCD46_SHIFT 7
3731 #define LCD_WF8B_BPHLCD45_MASK 0x80u
3732 #define LCD_WF8B_BPHLCD45_SHIFT 7
3733 #define LCD_WF8B_BPHLCD44_MASK 0x80u
3734 #define LCD_WF8B_BPHLCD44_SHIFT 7
3735 #define LCD_WF8B_BPHLCD43_MASK 0x80u
3736 #define LCD_WF8B_BPHLCD43_SHIFT 7
3737 #define LCD_WF8B_BPHLCD2_MASK 0x80u
3738 #define LCD_WF8B_BPHLCD2_SHIFT 7
3739 #define LCD_WF8B_BPHLCD42_MASK 0x80u
3740 #define LCD_WF8B_BPHLCD42_SHIFT 7
3741 #define LCD_WF8B_BPHLCD41_MASK 0x80u
3742 #define LCD_WF8B_BPHLCD41_SHIFT 7
3743 #define LCD_WF8B_BPHLCD40_MASK 0x80u
3744 #define LCD_WF8B_BPHLCD40_SHIFT 7
3745 #define LCD_WF8B_BPHLCD39_MASK 0x80u
3746 #define LCD_WF8B_BPHLCD39_SHIFT 7
3747 #define LCD_WF8B_BPHLCD38_MASK 0x80u
3748 #define LCD_WF8B_BPHLCD38_SHIFT 7
3749 #define LCD_WF8B_BPHLCD37_MASK 0x80u
3750 #define LCD_WF8B_BPHLCD37_SHIFT 7
3751 #define LCD_WF8B_BPHLCD36_MASK 0x80u
3752 #define LCD_WF8B_BPHLCD36_SHIFT 7
3753 #define LCD_WF8B_BPHLCD3_MASK 0x80u
3754 #define LCD_WF8B_BPHLCD3_SHIFT 7
3755 #define LCD_WF8B_BPHLCD35_MASK 0x80u
3756 #define LCD_WF8B_BPHLCD35_SHIFT 7
3757 #define LCD_WF8B_BPHLCD34_MASK 0x80u
3758 #define LCD_WF8B_BPHLCD34_SHIFT 7
3759 #define LCD_WF8B_BPHLCD33_MASK 0x80u
3760 #define LCD_WF8B_BPHLCD33_SHIFT 7
3761 #define LCD_WF8B_BPHLCD32_MASK 0x80u
3762 #define LCD_WF8B_BPHLCD32_SHIFT 7
3763 #define LCD_WF8B_BPHLCD31_MASK 0x80u
3764 #define LCD_WF8B_BPHLCD31_SHIFT 7
3765 #define LCD_WF8B_BPHLCD30_MASK 0x80u
3766 #define LCD_WF8B_BPHLCD30_SHIFT 7
3767 #define LCD_WF8B_BPHLCD29_MASK 0x80u
3768 #define LCD_WF8B_BPHLCD29_SHIFT 7
3769 #define LCD_WF8B_BPHLCD4_MASK 0x80u
3770 #define LCD_WF8B_BPHLCD4_SHIFT 7
3771 #define LCD_WF8B_BPHLCD28_MASK 0x80u
3772 #define LCD_WF8B_BPHLCD28_SHIFT 7
3773 #define LCD_WF8B_BPHLCD27_MASK 0x80u
3774 #define LCD_WF8B_BPHLCD27_SHIFT 7
3775 #define LCD_WF8B_BPHLCD26_MASK 0x80u
3776 #define LCD_WF8B_BPHLCD26_SHIFT 7
3777 #define LCD_WF8B_BPHLCD25_MASK 0x80u
3778 #define LCD_WF8B_BPHLCD25_SHIFT 7
3779 #define LCD_WF8B_BPHLCD24_MASK 0x80u
3780 #define LCD_WF8B_BPHLCD24_SHIFT 7
3781 #define LCD_WF8B_BPHLCD23_MASK 0x80u
3782 #define LCD_WF8B_BPHLCD23_SHIFT 7
3783 #define LCD_WF8B_BPHLCD22_MASK 0x80u
3784 #define LCD_WF8B_BPHLCD22_SHIFT 7
3785 #define LCD_WF8B_BPHLCD5_MASK 0x80u
3786 #define LCD_WF8B_BPHLCD5_SHIFT 7
3787 #define LCD_WF8B_BPHLCD21_MASK 0x80u
3788 #define LCD_WF8B_BPHLCD21_SHIFT 7
3789 #define LCD_WF8B_BPHLCD20_MASK 0x80u
3790 #define LCD_WF8B_BPHLCD20_SHIFT 7
3791 #define LCD_WF8B_BPHLCD19_MASK 0x80u
3792 #define LCD_WF8B_BPHLCD19_SHIFT 7
3793 #define LCD_WF8B_BPHLCD18_MASK 0x80u
3794 #define LCD_WF8B_BPHLCD18_SHIFT 7
3795 #define LCD_WF8B_BPHLCD17_MASK 0x80u
3796 #define LCD_WF8B_BPHLCD17_SHIFT 7
3797 #define LCD_WF8B_BPHLCD16_MASK 0x80u
3798 #define LCD_WF8B_BPHLCD16_SHIFT 7
3799 #define LCD_WF8B_BPHLCD15_MASK 0x80u
3800 #define LCD_WF8B_BPHLCD15_SHIFT 7
3801 #define LCD_WF8B_BPHLCD6_MASK 0x80u
3802 #define LCD_WF8B_BPHLCD6_SHIFT 7
3803 #define LCD_WF8B_BPHLCD14_MASK 0x80u
3804 #define LCD_WF8B_BPHLCD14_SHIFT 7
3805 #define LCD_WF8B_BPHLCD13_MASK 0x80u
3806 #define LCD_WF8B_BPHLCD13_SHIFT 7
3807 #define LCD_WF8B_BPHLCD12_MASK 0x80u
3808 #define LCD_WF8B_BPHLCD12_SHIFT 7
3809 #define LCD_WF8B_BPHLCD11_MASK 0x80u
3810 #define LCD_WF8B_BPHLCD11_SHIFT 7
3811 #define LCD_WF8B_BPHLCD10_MASK 0x80u
3812 #define LCD_WF8B_BPHLCD10_SHIFT 7
3813 #define LCD_WF8B_BPHLCD9_MASK 0x80u
3814 #define LCD_WF8B_BPHLCD9_SHIFT 7
3815 #define LCD_WF8B_BPHLCD8_MASK 0x80u
3816 #define LCD_WF8B_BPHLCD8_SHIFT 7
3817 #define LCD_WF8B_BPHLCD7_MASK 0x80u
3818 #define LCD_WF8B_BPHLCD7_SHIFT 7
3819
3820 /*!
3821 * @}
3822 */ /* end of group LCD_Register_Masks */
3823
3824
3825 /* LCD - Peripheral instance base addresses */
3826 /** Peripheral LCD base address */
3827 #define LCD_BASE (0x40053000u)
3828 /** Peripheral LCD base pointer */
3829 #define LCD ((LCD_Type *)LCD_BASE)
3830 #define LCD_BASE_PTR (LCD)
3831 /** Array initializer of LCD peripheral base addresses */
3832 #define LCD_BASE_ADDRS { LCD_BASE }
3833 /** Array initializer of LCD peripheral base pointers */
3834 #define LCD_BASE_PTRS { LCD }
3835 /** Interrupt vectors for the LCD peripheral type */
3836 #define LCD_LCD_IRQS { LCD_IRQn }
3837
3838 /* ----------------------------------------------------------------------------
3839 -- LCD - Register accessor macros
3840 ---------------------------------------------------------------------------- */
3841
3842 /*!
3843 * @addtogroup LCD_Register_Accessor_Macros LCD - Register accessor macros
3844 * @{
3845 */
3846
3847
3848 /* LCD - Register instance definitions */
3849 /* LCD */
3850 #define LCD_GCR LCD_GCR_REG(LCD)
3851 #define LCD_AR LCD_AR_REG(LCD)
3852 #define LCD_FDCR LCD_FDCR_REG(LCD)
3853 #define LCD_FDSR LCD_FDSR_REG(LCD)
3854 #define LCD_PENL LCD_PEN_REG(LCD,0)
3855 #define LCD_PENH LCD_PEN_REG(LCD,1)
3856 #define LCD_BPENL LCD_BPEN_REG(LCD,0)
3857 #define LCD_BPENH LCD_BPEN_REG(LCD,1)
3858 #define LCD_WF0 LCD_WF8B_REG(LCD,0)
3859 #define LCD_WF3TO0 LCD_WF_REG(LCD,0)
3860 #define LCD_WF1 LCD_WF8B_REG(LCD,1)
3861 #define LCD_WF2 LCD_WF8B_REG(LCD,2)
3862 #define LCD_WF3 LCD_WF8B_REG(LCD,3)
3863 #define LCD_WF4 LCD_WF8B_REG(LCD,4)
3864 #define LCD_WF7TO4 LCD_WF_REG(LCD,1)
3865 #define LCD_WF5 LCD_WF8B_REG(LCD,5)
3866 #define LCD_WF6 LCD_WF8B_REG(LCD,6)
3867 #define LCD_WF7 LCD_WF8B_REG(LCD,7)
3868 #define LCD_WF11TO8 LCD_WF_REG(LCD,2)
3869 #define LCD_WF8 LCD_WF8B_REG(LCD,8)
3870 #define LCD_WF9 LCD_WF8B_REG(LCD,9)
3871 #define LCD_WF10 LCD_WF8B_REG(LCD,10)
3872 #define LCD_WF11 LCD_WF8B_REG(LCD,11)
3873 #define LCD_WF12 LCD_WF8B_REG(LCD,12)
3874 #define LCD_WF15TO12 LCD_WF_REG(LCD,3)
3875 #define LCD_WF13 LCD_WF8B_REG(LCD,13)
3876 #define LCD_WF14 LCD_WF8B_REG(LCD,14)
3877 #define LCD_WF15 LCD_WF8B_REG(LCD,15)
3878 #define LCD_WF16 LCD_WF8B_REG(LCD,16)
3879 #define LCD_WF19TO16 LCD_WF_REG(LCD,4)
3880 #define LCD_WF17 LCD_WF8B_REG(LCD,17)
3881 #define LCD_WF18 LCD_WF8B_REG(LCD,18)
3882 #define LCD_WF19 LCD_WF8B_REG(LCD,19)
3883 #define LCD_WF20 LCD_WF8B_REG(LCD,20)
3884 #define LCD_WF23TO20 LCD_WF_REG(LCD,5)
3885 #define LCD_WF21 LCD_WF8B_REG(LCD,21)
3886 #define LCD_WF22 LCD_WF8B_REG(LCD,22)
3887 #define LCD_WF23 LCD_WF8B_REG(LCD,23)
3888 #define LCD_WF24 LCD_WF8B_REG(LCD,24)
3889 #define LCD_WF27TO24 LCD_WF_REG(LCD,6)
3890 #define LCD_WF25 LCD_WF8B_REG(LCD,25)
3891 #define LCD_WF26 LCD_WF8B_REG(LCD,26)
3892 #define LCD_WF27 LCD_WF8B_REG(LCD,27)
3893 #define LCD_WF28 LCD_WF8B_REG(LCD,28)
3894 #define LCD_WF31TO28 LCD_WF_REG(LCD,7)
3895 #define LCD_WF29 LCD_WF8B_REG(LCD,29)
3896 #define LCD_WF30 LCD_WF8B_REG(LCD,30)
3897 #define LCD_WF31 LCD_WF8B_REG(LCD,31)
3898 #define LCD_WF32 LCD_WF8B_REG(LCD,32)
3899 #define LCD_WF35TO32 LCD_WF_REG(LCD,8)
3900 #define LCD_WF33 LCD_WF8B_REG(LCD,33)
3901 #define LCD_WF34 LCD_WF8B_REG(LCD,34)
3902 #define LCD_WF35 LCD_WF8B_REG(LCD,35)
3903 #define LCD_WF36 LCD_WF8B_REG(LCD,36)
3904 #define LCD_WF39TO36 LCD_WF_REG(LCD,9)
3905 #define LCD_WF37 LCD_WF8B_REG(LCD,37)
3906 #define LCD_WF38 LCD_WF8B_REG(LCD,38)
3907 #define LCD_WF39 LCD_WF8B_REG(LCD,39)
3908 #define LCD_WF40 LCD_WF8B_REG(LCD,40)
3909 #define LCD_WF43TO40 LCD_WF_REG(LCD,10)
3910 #define LCD_WF41 LCD_WF8B_REG(LCD,41)
3911 #define LCD_WF42 LCD_WF8B_REG(LCD,42)
3912 #define LCD_WF43 LCD_WF8B_REG(LCD,43)
3913 #define LCD_WF44 LCD_WF8B_REG(LCD,44)
3914 #define LCD_WF47TO44 LCD_WF_REG(LCD,11)
3915 #define LCD_WF45 LCD_WF8B_REG(LCD,45)
3916 #define LCD_WF46 LCD_WF8B_REG(LCD,46)
3917 #define LCD_WF47 LCD_WF8B_REG(LCD,47)
3918 #define LCD_WF48 LCD_WF8B_REG(LCD,48)
3919 #define LCD_WF51TO48 LCD_WF_REG(LCD,12)
3920 #define LCD_WF49 LCD_WF8B_REG(LCD,49)
3921 #define LCD_WF50 LCD_WF8B_REG(LCD,50)
3922 #define LCD_WF51 LCD_WF8B_REG(LCD,51)
3923 #define LCD_WF52 LCD_WF8B_REG(LCD,52)
3924 #define LCD_WF55TO52 LCD_WF_REG(LCD,13)
3925 #define LCD_WF53 LCD_WF8B_REG(LCD,53)
3926 #define LCD_WF54 LCD_WF8B_REG(LCD,54)
3927 #define LCD_WF55 LCD_WF8B_REG(LCD,55)
3928 #define LCD_WF56 LCD_WF8B_REG(LCD,56)
3929 #define LCD_WF59TO56 LCD_WF_REG(LCD,14)
3930 #define LCD_WF57 LCD_WF8B_REG(LCD,57)
3931 #define LCD_WF58 LCD_WF8B_REG(LCD,58)
3932 #define LCD_WF59 LCD_WF8B_REG(LCD,59)
3933 #define LCD_WF60 LCD_WF8B_REG(LCD,60)
3934 #define LCD_WF63TO60 LCD_WF_REG(LCD,15)
3935 #define LCD_WF61 LCD_WF8B_REG(LCD,61)
3936 #define LCD_WF62 LCD_WF8B_REG(LCD,62)
3937 #define LCD_WF63 LCD_WF8B_REG(LCD,63)
3938
3939 /* LCD - Register array accessors */
3940 #define LCD_PEN(index) LCD_PEN_REG(LCD,index)
3941 #define LCD_BPEN(index) LCD_BPEN_REG(LCD,index)
3942 #define LCD_WF(index2) LCD_WF_REG(LCD,index2)
3943 #define LCD_WF8B(index2) LCD_WF8B_REG(LCD,index2)
3944
3945 /*!
3946 * @}
3947 */ /* end of group LCD_Register_Accessor_Macros */
3948
3949
3950 /*!
3951 * @}
3952 */ /* end of group LCD_Peripheral_Access_Layer */
3953
3954
3955 /* ----------------------------------------------------------------------------
3956 -- LLWU Peripheral Access Layer
3957 ---------------------------------------------------------------------------- */
3958
3959 /*!
3960 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
3961 * @{
3962 */
3963
3964 /** LLWU - Register Layout Typedef */
3965 typedef struct {
3966 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
3967 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
3968 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
3969 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
3970 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
3971 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
3972 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
3973 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
3974 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
3975 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
3976 } LLWU_Type, *LLWU_MemMapPtr;
3977
3978 /* ----------------------------------------------------------------------------
3979 -- LLWU - Register accessor macros
3980 ---------------------------------------------------------------------------- */
3981
3982 /*!
3983 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
3984 * @{
3985 */
3986
3987
3988 /* LLWU - Register accessors */
3989 #define LLWU_PE1_REG(base) ((base)->PE1)
3990 #define LLWU_PE2_REG(base) ((base)->PE2)
3991 #define LLWU_PE3_REG(base) ((base)->PE3)
3992 #define LLWU_PE4_REG(base) ((base)->PE4)
3993 #define LLWU_ME_REG(base) ((base)->ME)
3994 #define LLWU_F1_REG(base) ((base)->F1)
3995 #define LLWU_F2_REG(base) ((base)->F2)
3996 #define LLWU_F3_REG(base) ((base)->F3)
3997 #define LLWU_FILT1_REG(base) ((base)->FILT1)
3998 #define LLWU_FILT2_REG(base) ((base)->FILT2)
3999
4000 /*!
4001 * @}
4002 */ /* end of group LLWU_Register_Accessor_Macros */
4003
4004
4005 /* ----------------------------------------------------------------------------
4006 -- LLWU Register Masks
4007 ---------------------------------------------------------------------------- */
4008
4009 /*!
4010 * @addtogroup LLWU_Register_Masks LLWU Register Masks
4011 * @{
4012 */
4013
4014 /* PE1 Bit Fields */
4015 #define LLWU_PE1_WUPE0_MASK 0x3u
4016 #define LLWU_PE1_WUPE0_SHIFT 0
4017 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
4018 #define LLWU_PE1_WUPE1_MASK 0xCu
4019 #define LLWU_PE1_WUPE1_SHIFT 2
4020 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
4021 #define LLWU_PE1_WUPE2_MASK 0x30u
4022 #define LLWU_PE1_WUPE2_SHIFT 4
4023 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
4024 #define LLWU_PE1_WUPE3_MASK 0xC0u
4025 #define LLWU_PE1_WUPE3_SHIFT 6
4026 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
4027 /* PE2 Bit Fields */
4028 #define LLWU_PE2_WUPE4_MASK 0x3u
4029 #define LLWU_PE2_WUPE4_SHIFT 0
4030 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
4031 #define LLWU_PE2_WUPE5_MASK 0xCu
4032 #define LLWU_PE2_WUPE5_SHIFT 2
4033 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
4034 #define LLWU_PE2_WUPE6_MASK 0x30u
4035 #define LLWU_PE2_WUPE6_SHIFT 4
4036 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
4037 #define LLWU_PE2_WUPE7_MASK 0xC0u
4038 #define LLWU_PE2_WUPE7_SHIFT 6
4039 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
4040 /* PE3 Bit Fields */
4041 #define LLWU_PE3_WUPE8_MASK 0x3u
4042 #define LLWU_PE3_WUPE8_SHIFT 0
4043 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
4044 #define LLWU_PE3_WUPE9_MASK 0xCu
4045 #define LLWU_PE3_WUPE9_SHIFT 2
4046 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
4047 #define LLWU_PE3_WUPE10_MASK 0x30u
4048 #define LLWU_PE3_WUPE10_SHIFT 4
4049 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
4050 #define LLWU_PE3_WUPE11_MASK 0xC0u
4051 #define LLWU_PE3_WUPE11_SHIFT 6
4052 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
4053 /* PE4 Bit Fields */
4054 #define LLWU_PE4_WUPE12_MASK 0x3u
4055 #define LLWU_PE4_WUPE12_SHIFT 0
4056 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
4057 #define LLWU_PE4_WUPE13_MASK 0xCu
4058 #define LLWU_PE4_WUPE13_SHIFT 2
4059 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
4060 #define LLWU_PE4_WUPE14_MASK 0x30u
4061 #define LLWU_PE4_WUPE14_SHIFT 4
4062 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
4063 #define LLWU_PE4_WUPE15_MASK 0xC0u
4064 #define LLWU_PE4_WUPE15_SHIFT 6
4065 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
4066 /* ME Bit Fields */
4067 #define LLWU_ME_WUME0_MASK 0x1u
4068 #define LLWU_ME_WUME0_SHIFT 0
4069 #define LLWU_ME_WUME1_MASK 0x2u
4070 #define LLWU_ME_WUME1_SHIFT 1
4071 #define LLWU_ME_WUME2_MASK 0x4u
4072 #define LLWU_ME_WUME2_SHIFT 2
4073 #define LLWU_ME_WUME3_MASK 0x8u
4074 #define LLWU_ME_WUME3_SHIFT 3
4075 #define LLWU_ME_WUME4_MASK 0x10u
4076 #define LLWU_ME_WUME4_SHIFT 4
4077 #define LLWU_ME_WUME5_MASK 0x20u
4078 #define LLWU_ME_WUME5_SHIFT 5
4079 #define LLWU_ME_WUME6_MASK 0x40u
4080 #define LLWU_ME_WUME6_SHIFT 6
4081 #define LLWU_ME_WUME7_MASK 0x80u
4082 #define LLWU_ME_WUME7_SHIFT 7
4083 /* F1 Bit Fields */
4084 #define LLWU_F1_WUF0_MASK 0x1u
4085 #define LLWU_F1_WUF0_SHIFT 0
4086 #define LLWU_F1_WUF1_MASK 0x2u
4087 #define LLWU_F1_WUF1_SHIFT 1
4088 #define LLWU_F1_WUF2_MASK 0x4u
4089 #define LLWU_F1_WUF2_SHIFT 2
4090 #define LLWU_F1_WUF3_MASK 0x8u
4091 #define LLWU_F1_WUF3_SHIFT 3
4092 #define LLWU_F1_WUF4_MASK 0x10u
4093 #define LLWU_F1_WUF4_SHIFT 4
4094 #define LLWU_F1_WUF5_MASK 0x20u
4095 #define LLWU_F1_WUF5_SHIFT 5
4096 #define LLWU_F1_WUF6_MASK 0x40u
4097 #define LLWU_F1_WUF6_SHIFT 6
4098 #define LLWU_F1_WUF7_MASK 0x80u
4099 #define LLWU_F1_WUF7_SHIFT 7
4100 /* F2 Bit Fields */
4101 #define LLWU_F2_WUF8_MASK 0x1u
4102 #define LLWU_F2_WUF8_SHIFT 0
4103 #define LLWU_F2_WUF9_MASK 0x2u
4104 #define LLWU_F2_WUF9_SHIFT 1
4105 #define LLWU_F2_WUF10_MASK 0x4u
4106 #define LLWU_F2_WUF10_SHIFT 2
4107 #define LLWU_F2_WUF11_MASK 0x8u
4108 #define LLWU_F2_WUF11_SHIFT 3
4109 #define LLWU_F2_WUF12_MASK 0x10u
4110 #define LLWU_F2_WUF12_SHIFT 4
4111 #define LLWU_F2_WUF13_MASK 0x20u
4112 #define LLWU_F2_WUF13_SHIFT 5
4113 #define LLWU_F2_WUF14_MASK 0x40u
4114 #define LLWU_F2_WUF14_SHIFT 6
4115 #define LLWU_F2_WUF15_MASK 0x80u
4116 #define LLWU_F2_WUF15_SHIFT 7
4117 /* F3 Bit Fields */
4118 #define LLWU_F3_MWUF0_MASK 0x1u
4119 #define LLWU_F3_MWUF0_SHIFT 0
4120 #define LLWU_F3_MWUF1_MASK 0x2u
4121 #define LLWU_F3_MWUF1_SHIFT 1
4122 #define LLWU_F3_MWUF2_MASK 0x4u
4123 #define LLWU_F3_MWUF2_SHIFT 2
4124 #define LLWU_F3_MWUF3_MASK 0x8u
4125 #define LLWU_F3_MWUF3_SHIFT 3
4126 #define LLWU_F3_MWUF4_MASK 0x10u
4127 #define LLWU_F3_MWUF4_SHIFT 4
4128 #define LLWU_F3_MWUF5_MASK 0x20u
4129 #define LLWU_F3_MWUF5_SHIFT 5
4130 #define LLWU_F3_MWUF6_MASK 0x40u
4131 #define LLWU_F3_MWUF6_SHIFT 6
4132 #define LLWU_F3_MWUF7_MASK 0x80u
4133 #define LLWU_F3_MWUF7_SHIFT 7
4134 /* FILT1 Bit Fields */
4135 #define LLWU_FILT1_FILTSEL_MASK 0xFu
4136 #define LLWU_FILT1_FILTSEL_SHIFT 0
4137 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
4138 #define LLWU_FILT1_FILTE_MASK 0x60u
4139 #define LLWU_FILT1_FILTE_SHIFT 5
4140 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
4141 #define LLWU_FILT1_FILTF_MASK 0x80u
4142 #define LLWU_FILT1_FILTF_SHIFT 7
4143 /* FILT2 Bit Fields */
4144 #define LLWU_FILT2_FILTSEL_MASK 0xFu
4145 #define LLWU_FILT2_FILTSEL_SHIFT 0
4146 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
4147 #define LLWU_FILT2_FILTE_MASK 0x60u
4148 #define LLWU_FILT2_FILTE_SHIFT 5
4149 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
4150 #define LLWU_FILT2_FILTF_MASK 0x80u
4151 #define LLWU_FILT2_FILTF_SHIFT 7
4152
4153 /*!
4154 * @}
4155 */ /* end of group LLWU_Register_Masks */
4156
4157
4158 /* LLWU - Peripheral instance base addresses */
4159 /** Peripheral LLWU base address */
4160 #define LLWU_BASE (0x4007C000u)
4161 /** Peripheral LLWU base pointer */
4162 #define LLWU ((LLWU_Type *)LLWU_BASE)
4163 #define LLWU_BASE_PTR (LLWU)
4164 /** Array initializer of LLWU peripheral base addresses */
4165 #define LLWU_BASE_ADDRS { LLWU_BASE }
4166 /** Array initializer of LLWU peripheral base pointers */
4167 #define LLWU_BASE_PTRS { LLWU }
4168 /** Interrupt vectors for the LLWU peripheral type */
4169 #define LLWU_IRQS { LLWU_IRQn }
4170
4171 /* ----------------------------------------------------------------------------
4172 -- LLWU - Register accessor macros
4173 ---------------------------------------------------------------------------- */
4174
4175 /*!
4176 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
4177 * @{
4178 */
4179
4180
4181 /* LLWU - Register instance definitions */
4182 /* LLWU */
4183 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
4184 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
4185 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
4186 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
4187 #define LLWU_ME LLWU_ME_REG(LLWU)
4188 #define LLWU_F1 LLWU_F1_REG(LLWU)
4189 #define LLWU_F2 LLWU_F2_REG(LLWU)
4190 #define LLWU_F3 LLWU_F3_REG(LLWU)
4191 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
4192 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
4193
4194 /*!
4195 * @}
4196 */ /* end of group LLWU_Register_Accessor_Macros */
4197
4198
4199 /*!
4200 * @}
4201 */ /* end of group LLWU_Peripheral_Access_Layer */
4202
4203
4204 /* ----------------------------------------------------------------------------
4205 -- LPTMR Peripheral Access Layer
4206 ---------------------------------------------------------------------------- */
4207
4208 /*!
4209 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
4210 * @{
4211 */
4212
4213 /** LPTMR - Register Layout Typedef */
4214 typedef struct {
4215 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
4216 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
4217 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
4218 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
4219 } LPTMR_Type, *LPTMR_MemMapPtr;
4220
4221 /* ----------------------------------------------------------------------------
4222 -- LPTMR - Register accessor macros
4223 ---------------------------------------------------------------------------- */
4224
4225 /*!
4226 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
4227 * @{
4228 */
4229
4230
4231 /* LPTMR - Register accessors */
4232 #define LPTMR_CSR_REG(base) ((base)->CSR)
4233 #define LPTMR_PSR_REG(base) ((base)->PSR)
4234 #define LPTMR_CMR_REG(base) ((base)->CMR)
4235 #define LPTMR_CNR_REG(base) ((base)->CNR)
4236
4237 /*!
4238 * @}
4239 */ /* end of group LPTMR_Register_Accessor_Macros */
4240
4241
4242 /* ----------------------------------------------------------------------------
4243 -- LPTMR Register Masks
4244 ---------------------------------------------------------------------------- */
4245
4246 /*!
4247 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
4248 * @{
4249 */
4250
4251 /* CSR Bit Fields */
4252 #define LPTMR_CSR_TEN_MASK 0x1u
4253 #define LPTMR_CSR_TEN_SHIFT 0
4254 #define LPTMR_CSR_TMS_MASK 0x2u
4255 #define LPTMR_CSR_TMS_SHIFT 1
4256 #define LPTMR_CSR_TFC_MASK 0x4u
4257 #define LPTMR_CSR_TFC_SHIFT 2
4258 #define LPTMR_CSR_TPP_MASK 0x8u
4259 #define LPTMR_CSR_TPP_SHIFT 3
4260 #define LPTMR_CSR_TPS_MASK 0x30u
4261 #define LPTMR_CSR_TPS_SHIFT 4
4262 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
4263 #define LPTMR_CSR_TIE_MASK 0x40u
4264 #define LPTMR_CSR_TIE_SHIFT 6
4265 #define LPTMR_CSR_TCF_MASK 0x80u
4266 #define LPTMR_CSR_TCF_SHIFT 7
4267 /* PSR Bit Fields */
4268 #define LPTMR_PSR_PCS_MASK 0x3u
4269 #define LPTMR_PSR_PCS_SHIFT 0
4270 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
4271 #define LPTMR_PSR_PBYP_MASK 0x4u
4272 #define LPTMR_PSR_PBYP_SHIFT 2
4273 #define LPTMR_PSR_PRESCALE_MASK 0x78u
4274 #define LPTMR_PSR_PRESCALE_SHIFT 3
4275 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
4276 /* CMR Bit Fields */
4277 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
4278 #define LPTMR_CMR_COMPARE_SHIFT 0
4279 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
4280 /* CNR Bit Fields */
4281 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
4282 #define LPTMR_CNR_COUNTER_SHIFT 0
4283 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
4284
4285 /*!
4286 * @}
4287 */ /* end of group LPTMR_Register_Masks */
4288
4289
4290 /* LPTMR - Peripheral instance base addresses */
4291 /** Peripheral LPTMR0 base address */
4292 #define LPTMR0_BASE (0x40040000u)
4293 /** Peripheral LPTMR0 base pointer */
4294 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
4295 #define LPTMR0_BASE_PTR (LPTMR0)
4296 /** Array initializer of LPTMR peripheral base addresses */
4297 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
4298 /** Array initializer of LPTMR peripheral base pointers */
4299 #define LPTMR_BASE_PTRS { LPTMR0 }
4300 /** Interrupt vectors for the LPTMR peripheral type */
4301 #define LPTMR_IRQS { LPTMR0_IRQn }
4302
4303 /* ----------------------------------------------------------------------------
4304 -- LPTMR - Register accessor macros
4305 ---------------------------------------------------------------------------- */
4306
4307 /*!
4308 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
4309 * @{
4310 */
4311
4312
4313 /* LPTMR - Register instance definitions */
4314 /* LPTMR0 */
4315 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
4316 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
4317 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
4318 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
4319
4320 /*!
4321 * @}
4322 */ /* end of group LPTMR_Register_Accessor_Macros */
4323
4324
4325 /*!
4326 * @}
4327 */ /* end of group LPTMR_Peripheral_Access_Layer */
4328
4329
4330 /* ----------------------------------------------------------------------------
4331 -- LPUART Peripheral Access Layer
4332 ---------------------------------------------------------------------------- */
4333
4334 /*!
4335 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
4336 * @{
4337 */
4338
4339 /** LPUART - Register Layout Typedef */
4340 typedef struct {
4341 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
4342 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
4343 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
4344 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
4345 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
4346 } LPUART_Type, *LPUART_MemMapPtr;
4347
4348 /* ----------------------------------------------------------------------------
4349 -- LPUART - Register accessor macros
4350 ---------------------------------------------------------------------------- */
4351
4352 /*!
4353 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
4354 * @{
4355 */
4356
4357
4358 /* LPUART - Register accessors */
4359 #define LPUART_BAUD_REG(base) ((base)->BAUD)
4360 #define LPUART_STAT_REG(base) ((base)->STAT)
4361 #define LPUART_CTRL_REG(base) ((base)->CTRL)
4362 #define LPUART_DATA_REG(base) ((base)->DATA)
4363 #define LPUART_MATCH_REG(base) ((base)->MATCH)
4364
4365 /*!
4366 * @}
4367 */ /* end of group LPUART_Register_Accessor_Macros */
4368
4369
4370 /* ----------------------------------------------------------------------------
4371 -- LPUART Register Masks
4372 ---------------------------------------------------------------------------- */
4373
4374 /*!
4375 * @addtogroup LPUART_Register_Masks LPUART Register Masks
4376 * @{
4377 */
4378
4379 /* BAUD Bit Fields */
4380 #define LPUART_BAUD_SBR_MASK 0x1FFFu
4381 #define LPUART_BAUD_SBR_SHIFT 0
4382 #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_SBR_SHIFT))&LPUART_BAUD_SBR_MASK)
4383 #define LPUART_BAUD_SBNS_MASK 0x2000u
4384 #define LPUART_BAUD_SBNS_SHIFT 13
4385 #define LPUART_BAUD_RXEDGIE_MASK 0x4000u
4386 #define LPUART_BAUD_RXEDGIE_SHIFT 14
4387 #define LPUART_BAUD_LBKDIE_MASK 0x8000u
4388 #define LPUART_BAUD_LBKDIE_SHIFT 15
4389 #define LPUART_BAUD_RESYNCDIS_MASK 0x10000u
4390 #define LPUART_BAUD_RESYNCDIS_SHIFT 16
4391 #define LPUART_BAUD_BOTHEDGE_MASK 0x20000u
4392 #define LPUART_BAUD_BOTHEDGE_SHIFT 17
4393 #define LPUART_BAUD_MATCFG_MASK 0xC0000u
4394 #define LPUART_BAUD_MATCFG_SHIFT 18
4395 #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_MATCFG_SHIFT))&LPUART_BAUD_MATCFG_MASK)
4396 #define LPUART_BAUD_RDMAE_MASK 0x200000u
4397 #define LPUART_BAUD_RDMAE_SHIFT 21
4398 #define LPUART_BAUD_TDMAE_MASK 0x800000u
4399 #define LPUART_BAUD_TDMAE_SHIFT 23
4400 #define LPUART_BAUD_OSR_MASK 0x1F000000u
4401 #define LPUART_BAUD_OSR_SHIFT 24
4402 #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x))<<LPUART_BAUD_OSR_SHIFT))&LPUART_BAUD_OSR_MASK)
4403 #define LPUART_BAUD_M10_MASK 0x20000000u
4404 #define LPUART_BAUD_M10_SHIFT 29
4405 #define LPUART_BAUD_MAEN2_MASK 0x40000000u
4406 #define LPUART_BAUD_MAEN2_SHIFT 30
4407 #define LPUART_BAUD_MAEN1_MASK 0x80000000u
4408 #define LPUART_BAUD_MAEN1_SHIFT 31
4409 /* STAT Bit Fields */
4410 #define LPUART_STAT_MA2F_MASK 0x4000u
4411 #define LPUART_STAT_MA2F_SHIFT 14
4412 #define LPUART_STAT_MA1F_MASK 0x8000u
4413 #define LPUART_STAT_MA1F_SHIFT 15
4414 #define LPUART_STAT_PF_MASK 0x10000u
4415 #define LPUART_STAT_PF_SHIFT 16
4416 #define LPUART_STAT_FE_MASK 0x20000u
4417 #define LPUART_STAT_FE_SHIFT 17
4418 #define LPUART_STAT_NF_MASK 0x40000u
4419 #define LPUART_STAT_NF_SHIFT 18
4420 #define LPUART_STAT_OR_MASK 0x80000u
4421 #define LPUART_STAT_OR_SHIFT 19
4422 #define LPUART_STAT_IDLE_MASK 0x100000u
4423 #define LPUART_STAT_IDLE_SHIFT 20
4424 #define LPUART_STAT_RDRF_MASK 0x200000u
4425 #define LPUART_STAT_RDRF_SHIFT 21
4426 #define LPUART_STAT_TC_MASK 0x400000u
4427 #define LPUART_STAT_TC_SHIFT 22
4428 #define LPUART_STAT_TDRE_MASK 0x800000u
4429 #define LPUART_STAT_TDRE_SHIFT 23
4430 #define LPUART_STAT_RAF_MASK 0x1000000u
4431 #define LPUART_STAT_RAF_SHIFT 24
4432 #define LPUART_STAT_LBKDE_MASK 0x2000000u
4433 #define LPUART_STAT_LBKDE_SHIFT 25
4434 #define LPUART_STAT_BRK13_MASK 0x4000000u
4435 #define LPUART_STAT_BRK13_SHIFT 26
4436 #define LPUART_STAT_RWUID_MASK 0x8000000u
4437 #define LPUART_STAT_RWUID_SHIFT 27
4438 #define LPUART_STAT_RXINV_MASK 0x10000000u
4439 #define LPUART_STAT_RXINV_SHIFT 28
4440 #define LPUART_STAT_MSBF_MASK 0x20000000u
4441 #define LPUART_STAT_MSBF_SHIFT 29
4442 #define LPUART_STAT_RXEDGIF_MASK 0x40000000u
4443 #define LPUART_STAT_RXEDGIF_SHIFT 30
4444 #define LPUART_STAT_LBKDIF_MASK 0x80000000u
4445 #define LPUART_STAT_LBKDIF_SHIFT 31
4446 /* CTRL Bit Fields */
4447 #define LPUART_CTRL_PT_MASK 0x1u
4448 #define LPUART_CTRL_PT_SHIFT 0
4449 #define LPUART_CTRL_PE_MASK 0x2u
4450 #define LPUART_CTRL_PE_SHIFT 1
4451 #define LPUART_CTRL_ILT_MASK 0x4u
4452 #define LPUART_CTRL_ILT_SHIFT 2
4453 #define LPUART_CTRL_WAKE_MASK 0x8u
4454 #define LPUART_CTRL_WAKE_SHIFT 3
4455 #define LPUART_CTRL_M_MASK 0x10u
4456 #define LPUART_CTRL_M_SHIFT 4
4457 #define LPUART_CTRL_RSRC_MASK 0x20u
4458 #define LPUART_CTRL_RSRC_SHIFT 5
4459 #define LPUART_CTRL_DOZEEN_MASK 0x40u
4460 #define LPUART_CTRL_DOZEEN_SHIFT 6
4461 #define LPUART_CTRL_LOOPS_MASK 0x80u
4462 #define LPUART_CTRL_LOOPS_SHIFT 7
4463 #define LPUART_CTRL_IDLECFG_MASK 0x700u
4464 #define LPUART_CTRL_IDLECFG_SHIFT 8
4465 #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x))<<LPUART_CTRL_IDLECFG_SHIFT))&LPUART_CTRL_IDLECFG_MASK)
4466 #define LPUART_CTRL_MA2IE_MASK 0x4000u
4467 #define LPUART_CTRL_MA2IE_SHIFT 14
4468 #define LPUART_CTRL_MA1IE_MASK 0x8000u
4469 #define LPUART_CTRL_MA1IE_SHIFT 15
4470 #define LPUART_CTRL_SBK_MASK 0x10000u
4471 #define LPUART_CTRL_SBK_SHIFT 16
4472 #define LPUART_CTRL_RWU_MASK 0x20000u
4473 #define LPUART_CTRL_RWU_SHIFT 17
4474 #define LPUART_CTRL_RE_MASK 0x40000u
4475 #define LPUART_CTRL_RE_SHIFT 18
4476 #define LPUART_CTRL_TE_MASK 0x80000u
4477 #define LPUART_CTRL_TE_SHIFT 19
4478 #define LPUART_CTRL_ILIE_MASK 0x100000u
4479 #define LPUART_CTRL_ILIE_SHIFT 20
4480 #define LPUART_CTRL_RIE_MASK 0x200000u
4481 #define LPUART_CTRL_RIE_SHIFT 21
4482 #define LPUART_CTRL_TCIE_MASK 0x400000u
4483 #define LPUART_CTRL_TCIE_SHIFT 22
4484 #define LPUART_CTRL_TIE_MASK 0x800000u
4485 #define LPUART_CTRL_TIE_SHIFT 23
4486 #define LPUART_CTRL_PEIE_MASK 0x1000000u
4487 #define LPUART_CTRL_PEIE_SHIFT 24
4488 #define LPUART_CTRL_FEIE_MASK 0x2000000u
4489 #define LPUART_CTRL_FEIE_SHIFT 25
4490 #define LPUART_CTRL_NEIE_MASK 0x4000000u
4491 #define LPUART_CTRL_NEIE_SHIFT 26
4492 #define LPUART_CTRL_ORIE_MASK 0x8000000u
4493 #define LPUART_CTRL_ORIE_SHIFT 27
4494 #define LPUART_CTRL_TXINV_MASK 0x10000000u
4495 #define LPUART_CTRL_TXINV_SHIFT 28
4496 #define LPUART_CTRL_TXDIR_MASK 0x20000000u
4497 #define LPUART_CTRL_TXDIR_SHIFT 29
4498 #define LPUART_CTRL_R9T8_MASK 0x40000000u
4499 #define LPUART_CTRL_R9T8_SHIFT 30
4500 #define LPUART_CTRL_R8T9_MASK 0x80000000u
4501 #define LPUART_CTRL_R8T9_SHIFT 31
4502 /* DATA Bit Fields */
4503 #define LPUART_DATA_R0T0_MASK 0x1u
4504 #define LPUART_DATA_R0T0_SHIFT 0
4505 #define LPUART_DATA_R1T1_MASK 0x2u
4506 #define LPUART_DATA_R1T1_SHIFT 1
4507 #define LPUART_DATA_R2T2_MASK 0x4u
4508 #define LPUART_DATA_R2T2_SHIFT 2
4509 #define LPUART_DATA_R3T3_MASK 0x8u
4510 #define LPUART_DATA_R3T3_SHIFT 3
4511 #define LPUART_DATA_R4T4_MASK 0x10u
4512 #define LPUART_DATA_R4T4_SHIFT 4
4513 #define LPUART_DATA_R5T5_MASK 0x20u
4514 #define LPUART_DATA_R5T5_SHIFT 5
4515 #define LPUART_DATA_R6T6_MASK 0x40u
4516 #define LPUART_DATA_R6T6_SHIFT 6
4517 #define LPUART_DATA_R7T7_MASK 0x80u
4518 #define LPUART_DATA_R7T7_SHIFT 7
4519 #define LPUART_DATA_R8T8_MASK 0x100u
4520 #define LPUART_DATA_R8T8_SHIFT 8
4521 #define LPUART_DATA_R9T9_MASK 0x200u
4522 #define LPUART_DATA_R9T9_SHIFT 9
4523 #define LPUART_DATA_IDLINE_MASK 0x800u
4524 #define LPUART_DATA_IDLINE_SHIFT 11
4525 #define LPUART_DATA_RXEMPT_MASK 0x1000u
4526 #define LPUART_DATA_RXEMPT_SHIFT 12
4527 #define LPUART_DATA_FRETSC_MASK 0x2000u
4528 #define LPUART_DATA_FRETSC_SHIFT 13
4529 #define LPUART_DATA_PARITYE_MASK 0x4000u
4530 #define LPUART_DATA_PARITYE_SHIFT 14
4531 #define LPUART_DATA_NOISY_MASK 0x8000u
4532 #define LPUART_DATA_NOISY_SHIFT 15
4533 /* MATCH Bit Fields */
4534 #define LPUART_MATCH_MA1_MASK 0x3FFu
4535 #define LPUART_MATCH_MA1_SHIFT 0
4536 #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA1_SHIFT))&LPUART_MATCH_MA1_MASK)
4537 #define LPUART_MATCH_MA2_MASK 0x3FF0000u
4538 #define LPUART_MATCH_MA2_SHIFT 16
4539 #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x))<<LPUART_MATCH_MA2_SHIFT))&LPUART_MATCH_MA2_MASK)
4540
4541 /*!
4542 * @}
4543 */ /* end of group LPUART_Register_Masks */
4544
4545
4546 /* LPUART - Peripheral instance base addresses */
4547 /** Peripheral LPUART0 base address */
4548 #define LPUART0_BASE (0x40054000u)
4549 /** Peripheral LPUART0 base pointer */
4550 #define LPUART0 ((LPUART_Type *)LPUART0_BASE)
4551 #define LPUART0_BASE_PTR (LPUART0)
4552 /** Peripheral LPUART1 base address */
4553 #define LPUART1_BASE (0x40055000u)
4554 /** Peripheral LPUART1 base pointer */
4555 #define LPUART1 ((LPUART_Type *)LPUART1_BASE)
4556 #define LPUART1_BASE_PTR (LPUART1)
4557 /** Array initializer of LPUART peripheral base addresses */
4558 #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE }
4559 /** Array initializer of LPUART peripheral base pointers */
4560 #define LPUART_BASE_PTRS { LPUART0, LPUART1 }
4561 /** Interrupt vectors for the LPUART peripheral type */
4562 #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn }
4563 #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn }
4564
4565 /* ----------------------------------------------------------------------------
4566 -- LPUART - Register accessor macros
4567 ---------------------------------------------------------------------------- */
4568
4569 /*!
4570 * @addtogroup LPUART_Register_Accessor_Macros LPUART - Register accessor macros
4571 * @{
4572 */
4573
4574
4575 /* LPUART - Register instance definitions */
4576 /* LPUART0 */
4577 #define LPUART0_BAUD LPUART_BAUD_REG(LPUART0)
4578 #define LPUART0_STAT LPUART_STAT_REG(LPUART0)
4579 #define LPUART0_CTRL LPUART_CTRL_REG(LPUART0)
4580 #define LPUART0_DATA LPUART_DATA_REG(LPUART0)
4581 #define LPUART0_MATCH LPUART_MATCH_REG(LPUART0)
4582 /* LPUART1 */
4583 #define LPUART1_BAUD LPUART_BAUD_REG(LPUART1)
4584 #define LPUART1_STAT LPUART_STAT_REG(LPUART1)
4585 #define LPUART1_CTRL LPUART_CTRL_REG(LPUART1)
4586 #define LPUART1_DATA LPUART_DATA_REG(LPUART1)
4587 #define LPUART1_MATCH LPUART_MATCH_REG(LPUART1)
4588
4589 /*!
4590 * @}
4591 */ /* end of group LPUART_Register_Accessor_Macros */
4592
4593
4594 /*!
4595 * @}
4596 */ /* end of group LPUART_Peripheral_Access_Layer */
4597
4598
4599 /* ----------------------------------------------------------------------------
4600 -- MCG Peripheral Access Layer
4601 ---------------------------------------------------------------------------- */
4602
4603 /*!
4604 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
4605 * @{
4606 */
4607
4608 /** MCG - Register Layout Typedef */
4609 typedef struct {
4610 __IO uint8_t C1; /**< MCG Control Register 1, offset: 0x0 */
4611 __IO uint8_t C2; /**< MCG Control Register 2, offset: 0x1 */
4612 uint8_t RESERVED_0[4];
4613 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
4614 uint8_t RESERVED_1[1];
4615 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
4616 uint8_t RESERVED_2[11];
4617 __I uint8_t HCTRIM; /**< MCG High-frequency IRC Coarse Trim Register, offset: 0x14 */
4618 __I uint8_t HTTRIM; /**< MCG High-frequency IRC Tempco (Temperature Coefficient) Trim Register, offset: 0x15 */
4619 __I uint8_t HFTRIM; /**< MCG High-frequency IRC Fine Trim Register, offset: 0x16 */
4620 uint8_t RESERVED_3[1];
4621 __IO uint8_t MC; /**< MCG Miscellaneous Control Register, offset: 0x18 */
4622 __I uint8_t LTRIMRNG; /**< MCG Low-frequency IRC Trim Range Register, offset: 0x19 */
4623 __I uint8_t LFTRIM; /**< MCG Low-frequency IRC8M Trim Register, offset: 0x1A */
4624 __I uint8_t LSTRIM; /**< MCG Low-frequency IRC2M Trim Register, offset: 0x1B */
4625 } MCG_Type, *MCG_MemMapPtr;
4626
4627 /* ----------------------------------------------------------------------------
4628 -- MCG - Register accessor macros
4629 ---------------------------------------------------------------------------- */
4630
4631 /*!
4632 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
4633 * @{
4634 */
4635
4636
4637 /* MCG - Register accessors */
4638 #define MCG_C1_REG(base) ((base)->C1)
4639 #define MCG_C2_REG(base) ((base)->C2)
4640 #define MCG_S_REG(base) ((base)->S)
4641 #define MCG_SC_REG(base) ((base)->SC)
4642 #define MCG_HCTRIM_REG(base) ((base)->HCTRIM)
4643 #define MCG_HTTRIM_REG(base) ((base)->HTTRIM)
4644 #define MCG_HFTRIM_REG(base) ((base)->HFTRIM)
4645 #define MCG_MC_REG(base) ((base)->MC)
4646 #define MCG_LTRIMRNG_REG(base) ((base)->LTRIMRNG)
4647 #define MCG_LFTRIM_REG(base) ((base)->LFTRIM)
4648 #define MCG_LSTRIM_REG(base) ((base)->LSTRIM)
4649
4650 /*!
4651 * @}
4652 */ /* end of group MCG_Register_Accessor_Macros */
4653
4654
4655 /* ----------------------------------------------------------------------------
4656 -- MCG Register Masks
4657 ---------------------------------------------------------------------------- */
4658
4659 /*!
4660 * @addtogroup MCG_Register_Masks MCG Register Masks
4661 * @{
4662 */
4663
4664 /* C1 Bit Fields */
4665 #define MCG_C1_IREFSTEN_MASK 0x1u
4666 #define MCG_C1_IREFSTEN_SHIFT 0
4667 #define MCG_C1_IRCLKEN_MASK 0x2u
4668 #define MCG_C1_IRCLKEN_SHIFT 1
4669 #define MCG_C1_CLKS_MASK 0xC0u
4670 #define MCG_C1_CLKS_SHIFT 6
4671 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
4672 /* C2 Bit Fields */
4673 #define MCG_C2_IRCS_MASK 0x1u
4674 #define MCG_C2_IRCS_SHIFT 0
4675 #define MCG_C2_EREFS0_MASK 0x4u
4676 #define MCG_C2_EREFS0_SHIFT 2
4677 #define MCG_C2_HGO0_MASK 0x8u
4678 #define MCG_C2_HGO0_SHIFT 3
4679 #define MCG_C2_RANGE0_MASK 0x30u
4680 #define MCG_C2_RANGE0_SHIFT 4
4681 #define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
4682 /* S Bit Fields */
4683 #define MCG_S_OSCINIT0_MASK 0x2u
4684 #define MCG_S_OSCINIT0_SHIFT 1
4685 #define MCG_S_CLKST_MASK 0xCu
4686 #define MCG_S_CLKST_SHIFT 2
4687 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
4688 /* SC Bit Fields */
4689 #define MCG_SC_FCRDIV_MASK 0xEu
4690 #define MCG_SC_FCRDIV_SHIFT 1
4691 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
4692 /* HCTRIM Bit Fields */
4693 #define MCG_HCTRIM_COARSE_TRIM_MASK 0x3Fu
4694 #define MCG_HCTRIM_COARSE_TRIM_SHIFT 0
4695 #define MCG_HCTRIM_COARSE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HCTRIM_COARSE_TRIM_SHIFT))&MCG_HCTRIM_COARSE_TRIM_MASK)
4696 /* HTTRIM Bit Fields */
4697 #define MCG_HTTRIM_TEMPCO_TRIM_MASK 0x1Fu
4698 #define MCG_HTTRIM_TEMPCO_TRIM_SHIFT 0
4699 #define MCG_HTTRIM_TEMPCO_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HTTRIM_TEMPCO_TRIM_SHIFT))&MCG_HTTRIM_TEMPCO_TRIM_MASK)
4700 /* HFTRIM Bit Fields */
4701 #define MCG_HFTRIM_FINE_TRIM_MASK 0x7Fu
4702 #define MCG_HFTRIM_FINE_TRIM_SHIFT 0
4703 #define MCG_HFTRIM_FINE_TRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_HFTRIM_FINE_TRIM_SHIFT))&MCG_HFTRIM_FINE_TRIM_MASK)
4704 /* MC Bit Fields */
4705 #define MCG_MC_LIRC_DIV2_MASK 0x7u
4706 #define MCG_MC_LIRC_DIV2_SHIFT 0
4707 #define MCG_MC_LIRC_DIV2(x) (((uint8_t)(((uint8_t)(x))<<MCG_MC_LIRC_DIV2_SHIFT))&MCG_MC_LIRC_DIV2_MASK)
4708 #define MCG_MC_HIRCEN_MASK 0x80u
4709 #define MCG_MC_HIRCEN_SHIFT 7
4710 /* LTRIMRNG Bit Fields */
4711 #define MCG_LTRIMRNG_STRIMRNG_MASK 0x3u
4712 #define MCG_LTRIMRNG_STRIMRNG_SHIFT 0
4713 #define MCG_LTRIMRNG_STRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_STRIMRNG_SHIFT))&MCG_LTRIMRNG_STRIMRNG_MASK)
4714 #define MCG_LTRIMRNG_FTRIMRNG_MASK 0xCu
4715 #define MCG_LTRIMRNG_FTRIMRNG_SHIFT 2
4716 #define MCG_LTRIMRNG_FTRIMRNG(x) (((uint8_t)(((uint8_t)(x))<<MCG_LTRIMRNG_FTRIMRNG_SHIFT))&MCG_LTRIMRNG_FTRIMRNG_MASK)
4717 /* LFTRIM Bit Fields */
4718 #define MCG_LFTRIM_LIRC_FTRIM_MASK 0x7Fu
4719 #define MCG_LFTRIM_LIRC_FTRIM_SHIFT 0
4720 #define MCG_LFTRIM_LIRC_FTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LFTRIM_LIRC_FTRIM_SHIFT))&MCG_LFTRIM_LIRC_FTRIM_MASK)
4721 /* LSTRIM Bit Fields */
4722 #define MCG_LSTRIM_LIRC_STRIM_MASK 0x7Fu
4723 #define MCG_LSTRIM_LIRC_STRIM_SHIFT 0
4724 #define MCG_LSTRIM_LIRC_STRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_LSTRIM_LIRC_STRIM_SHIFT))&MCG_LSTRIM_LIRC_STRIM_MASK)
4725
4726 /*!
4727 * @}
4728 */ /* end of group MCG_Register_Masks */
4729
4730
4731 /* MCG - Peripheral instance base addresses */
4732 /** Peripheral MCG base address */
4733 #define MCG_BASE (0x40064000u)
4734 /** Peripheral MCG base pointer */
4735 #define MCG ((MCG_Type *)MCG_BASE)
4736 #define MCG_BASE_PTR (MCG)
4737 /** Array initializer of MCG peripheral base addresses */
4738 #define MCG_BASE_ADDRS { MCG_BASE }
4739 /** Array initializer of MCG peripheral base pointers */
4740 #define MCG_BASE_PTRS { MCG }
4741
4742 /* ----------------------------------------------------------------------------
4743 -- MCG - Register accessor macros
4744 ---------------------------------------------------------------------------- */
4745
4746 /*!
4747 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
4748 * @{
4749 */
4750
4751
4752 /* MCG - Register instance definitions */
4753 /* MCG */
4754 #define MCG_C1 MCG_C1_REG(MCG)
4755 #define MCG_C2 MCG_C2_REG(MCG)
4756 #define MCG_S MCG_S_REG(MCG)
4757 #define MCG_SC MCG_SC_REG(MCG)
4758 #define MCG_HCTRIM MCG_HCTRIM_REG(MCG)
4759 #define MCG_HTTRIM MCG_HTTRIM_REG(MCG)
4760 #define MCG_HFTRIM MCG_HFTRIM_REG(MCG)
4761 #define MCG_MC MCG_MC_REG(MCG)
4762 #define MCG_LTRIMRNG MCG_LTRIMRNG_REG(MCG)
4763 #define MCG_LFTRIM MCG_LFTRIM_REG(MCG)
4764 #define MCG_LSTRIM MCG_LSTRIM_REG(MCG)
4765
4766 /*!
4767 * @}
4768 */ /* end of group MCG_Register_Accessor_Macros */
4769
4770
4771 /*!
4772 * @}
4773 */ /* end of group MCG_Peripheral_Access_Layer */
4774
4775
4776 /* ----------------------------------------------------------------------------
4777 -- MCM Peripheral Access Layer
4778 ---------------------------------------------------------------------------- */
4779
4780 /*!
4781 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
4782 * @{
4783 */
4784
4785 /** MCM - Register Layout Typedef */
4786 typedef struct {
4787 uint8_t RESERVED_0[8];
4788 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
4789 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
4790 __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */
4791 uint8_t RESERVED_1[48];
4792 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
4793 } MCM_Type, *MCM_MemMapPtr;
4794
4795 /* ----------------------------------------------------------------------------
4796 -- MCM - Register accessor macros
4797 ---------------------------------------------------------------------------- */
4798
4799 /*!
4800 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
4801 * @{
4802 */
4803
4804
4805 /* MCM - Register accessors */
4806 #define MCM_PLASC_REG(base) ((base)->PLASC)
4807 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
4808 #define MCM_PLACR_REG(base) ((base)->PLACR)
4809 #define MCM_CPO_REG(base) ((base)->CPO)
4810
4811 /*!
4812 * @}
4813 */ /* end of group MCM_Register_Accessor_Macros */
4814
4815
4816 /* ----------------------------------------------------------------------------
4817 -- MCM Register Masks
4818 ---------------------------------------------------------------------------- */
4819
4820 /*!
4821 * @addtogroup MCM_Register_Masks MCM Register Masks
4822 * @{
4823 */
4824
4825 /* PLASC Bit Fields */
4826 #define MCM_PLASC_ASC_MASK 0xFFu
4827 #define MCM_PLASC_ASC_SHIFT 0
4828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
4829 /* PLAMC Bit Fields */
4830 #define MCM_PLAMC_AMC_MASK 0xFFu
4831 #define MCM_PLAMC_AMC_SHIFT 0
4832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
4833 /* PLACR Bit Fields */
4834 #define MCM_PLACR_ARB_MASK 0x200u
4835 #define MCM_PLACR_ARB_SHIFT 9
4836 #define MCM_PLACR_CFCC_MASK 0x400u
4837 #define MCM_PLACR_CFCC_SHIFT 10
4838 #define MCM_PLACR_DFCDA_MASK 0x800u
4839 #define MCM_PLACR_DFCDA_SHIFT 11
4840 #define MCM_PLACR_DFCIC_MASK 0x1000u
4841 #define MCM_PLACR_DFCIC_SHIFT 12
4842 #define MCM_PLACR_DFCC_MASK 0x2000u
4843 #define MCM_PLACR_DFCC_SHIFT 13
4844 #define MCM_PLACR_EFDS_MASK 0x4000u
4845 #define MCM_PLACR_EFDS_SHIFT 14
4846 #define MCM_PLACR_DFCS_MASK 0x8000u
4847 #define MCM_PLACR_DFCS_SHIFT 15
4848 #define MCM_PLACR_ESFC_MASK 0x10000u
4849 #define MCM_PLACR_ESFC_SHIFT 16
4850 /* CPO Bit Fields */
4851 #define MCM_CPO_CPOREQ_MASK 0x1u
4852 #define MCM_CPO_CPOREQ_SHIFT 0
4853 #define MCM_CPO_CPOACK_MASK 0x2u
4854 #define MCM_CPO_CPOACK_SHIFT 1
4855 #define MCM_CPO_CPOWOI_MASK 0x4u
4856 #define MCM_CPO_CPOWOI_SHIFT 2
4857
4858 /*!
4859 * @}
4860 */ /* end of group MCM_Register_Masks */
4861
4862
4863 /* MCM - Peripheral instance base addresses */
4864 /** Peripheral MCM base address */
4865 #define MCM_BASE (0xF0003000u)
4866 /** Peripheral MCM base pointer */
4867 #define MCM ((MCM_Type *)MCM_BASE)
4868 #define MCM_BASE_PTR (MCM)
4869 /** Array initializer of MCM peripheral base addresses */
4870 #define MCM_BASE_ADDRS { MCM_BASE }
4871 /** Array initializer of MCM peripheral base pointers */
4872 #define MCM_BASE_PTRS { MCM }
4873
4874 /* ----------------------------------------------------------------------------
4875 -- MCM - Register accessor macros
4876 ---------------------------------------------------------------------------- */
4877
4878 /*!
4879 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
4880 * @{
4881 */
4882
4883
4884 /* MCM - Register instance definitions */
4885 /* MCM */
4886 #define MCM_PLASC MCM_PLASC_REG(MCM)
4887 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
4888 #define MCM_PLACR MCM_PLACR_REG(MCM)
4889 #define MCM_CPO MCM_CPO_REG(MCM)
4890
4891 /*!
4892 * @}
4893 */ /* end of group MCM_Register_Accessor_Macros */
4894
4895
4896 /*!
4897 * @}
4898 */ /* end of group MCM_Peripheral_Access_Layer */
4899
4900
4901 /* ----------------------------------------------------------------------------
4902 -- MTB Peripheral Access Layer
4903 ---------------------------------------------------------------------------- */
4904
4905 /*!
4906 * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
4907 * @{
4908 */
4909
4910 /** MTB - Register Layout Typedef */
4911 typedef struct {
4912 __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */
4913 __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */
4914 __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */
4915 __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */
4916 uint8_t RESERVED_0[3824];
4917 __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */
4918 uint8_t RESERVED_1[156];
4919 __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */
4920 __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */
4921 uint8_t RESERVED_2[8];
4922 __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */
4923 __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */
4924 __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */
4925 __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */
4926 uint8_t RESERVED_3[8];
4927 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
4928 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
4929 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
4930 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
4931 } MTB_Type, *MTB_MemMapPtr;
4932
4933 /* ----------------------------------------------------------------------------
4934 -- MTB - Register accessor macros
4935 ---------------------------------------------------------------------------- */
4936
4937 /*!
4938 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
4939 * @{
4940 */
4941
4942
4943 /* MTB - Register accessors */
4944 #define MTB_POSITION_REG(base) ((base)->POSITION)
4945 #define MTB_MASTER_REG(base) ((base)->MASTER)
4946 #define MTB_FLOW_REG(base) ((base)->FLOW)
4947 #define MTB_BASE_REG(base) ((base)->BASE)
4948 #define MTB_MODECTRL_REG(base) ((base)->MODECTRL)
4949 #define MTB_TAGSET_REG(base) ((base)->TAGSET)
4950 #define MTB_TAGCLEAR_REG(base) ((base)->TAGCLEAR)
4951 #define MTB_LOCKACCESS_REG(base) ((base)->LOCKACCESS)
4952 #define MTB_LOCKSTAT_REG(base) ((base)->LOCKSTAT)
4953 #define MTB_AUTHSTAT_REG(base) ((base)->AUTHSTAT)
4954 #define MTB_DEVICEARCH_REG(base) ((base)->DEVICEARCH)
4955 #define MTB_DEVICECFG_REG(base) ((base)->DEVICECFG)
4956 #define MTB_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
4957 #define MTB_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
4958 #define MTB_COMPID_REG(base,index) ((base)->COMPID[index])
4959
4960 /*!
4961 * @}
4962 */ /* end of group MTB_Register_Accessor_Macros */
4963
4964
4965 /* ----------------------------------------------------------------------------
4966 -- MTB Register Masks
4967 ---------------------------------------------------------------------------- */
4968
4969 /*!
4970 * @addtogroup MTB_Register_Masks MTB Register Masks
4971 * @{
4972 */
4973
4974 /* POSITION Bit Fields */
4975 #define MTB_POSITION_WRAP_MASK 0x4u
4976 #define MTB_POSITION_WRAP_SHIFT 2
4977 #define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
4978 #define MTB_POSITION_POINTER_SHIFT 3
4979 #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
4980 /* MASTER Bit Fields */
4981 #define MTB_MASTER_MASK_MASK 0x1Fu
4982 #define MTB_MASTER_MASK_SHIFT 0
4983 #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
4984 #define MTB_MASTER_TSTARTEN_MASK 0x20u
4985 #define MTB_MASTER_TSTARTEN_SHIFT 5
4986 #define MTB_MASTER_TSTOPEN_MASK 0x40u
4987 #define MTB_MASTER_TSTOPEN_SHIFT 6
4988 #define MTB_MASTER_SFRWPRIV_MASK 0x80u
4989 #define MTB_MASTER_SFRWPRIV_SHIFT 7
4990 #define MTB_MASTER_RAMPRIV_MASK 0x100u
4991 #define MTB_MASTER_RAMPRIV_SHIFT 8
4992 #define MTB_MASTER_HALTREQ_MASK 0x200u
4993 #define MTB_MASTER_HALTREQ_SHIFT 9
4994 #define MTB_MASTER_EN_MASK 0x80000000u
4995 #define MTB_MASTER_EN_SHIFT 31
4996 /* FLOW Bit Fields */
4997 #define MTB_FLOW_AUTOSTOP_MASK 0x1u
4998 #define MTB_FLOW_AUTOSTOP_SHIFT 0
4999 #define MTB_FLOW_AUTOHALT_MASK 0x2u
5000 #define MTB_FLOW_AUTOHALT_SHIFT 1
5001 #define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
5002 #define MTB_FLOW_WATERMARK_SHIFT 3
5003 #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
5004 /* BASE Bit Fields */
5005 #define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
5006 #define MTB_BASE_BASEADDR_SHIFT 0
5007 #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
5008 /* MODECTRL Bit Fields */
5009 #define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
5010 #define MTB_MODECTRL_MODECTRL_SHIFT 0
5011 #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
5012 /* TAGSET Bit Fields */
5013 #define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
5014 #define MTB_TAGSET_TAGSET_SHIFT 0
5015 #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
5016 /* TAGCLEAR Bit Fields */
5017 #define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
5018 #define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
5019 #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
5020 /* LOCKACCESS Bit Fields */
5021 #define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
5022 #define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
5023 #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
5024 /* LOCKSTAT Bit Fields */
5025 #define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
5026 #define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
5027 #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
5028 /* AUTHSTAT Bit Fields */
5029 #define MTB_AUTHSTAT_BIT0_MASK 0x1u
5030 #define MTB_AUTHSTAT_BIT0_SHIFT 0
5031 #define MTB_AUTHSTAT_BIT1_MASK 0x2u
5032 #define MTB_AUTHSTAT_BIT1_SHIFT 1
5033 #define MTB_AUTHSTAT_BIT2_MASK 0x4u
5034 #define MTB_AUTHSTAT_BIT2_SHIFT 2
5035 #define MTB_AUTHSTAT_BIT3_MASK 0x8u
5036 #define MTB_AUTHSTAT_BIT3_SHIFT 3
5037 /* DEVICEARCH Bit Fields */
5038 #define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
5039 #define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
5040 #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
5041 /* DEVICECFG Bit Fields */
5042 #define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
5043 #define MTB_DEVICECFG_DEVICECFG_SHIFT 0
5044 #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
5045 /* DEVICETYPID Bit Fields */
5046 #define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
5047 #define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
5048 #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
5049 /* PERIPHID Bit Fields */
5050 #define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
5051 #define MTB_PERIPHID_PERIPHID_SHIFT 0
5052 #define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
5053 /* COMPID Bit Fields */
5054 #define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
5055 #define MTB_COMPID_COMPID_SHIFT 0
5056 #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
5057
5058 /*!
5059 * @}
5060 */ /* end of group MTB_Register_Masks */
5061
5062
5063 /* MTB - Peripheral instance base addresses */
5064 /** Peripheral MTB base address */
5065 #define MTB_BASE (0xF0000000u)
5066 /** Peripheral MTB base pointer */
5067 #define MTB ((MTB_Type *)MTB_BASE)
5068 #define MTB_BASE_PTR (MTB)
5069 /** Array initializer of MTB peripheral base addresses */
5070 #define MTB_BASE_ADDRS { MTB_BASE }
5071 /** Array initializer of MTB peripheral base pointers */
5072 #define MTB_BASE_PTRS { MTB }
5073
5074 /* ----------------------------------------------------------------------------
5075 -- MTB - Register accessor macros
5076 ---------------------------------------------------------------------------- */
5077
5078 /*!
5079 * @addtogroup MTB_Register_Accessor_Macros MTB - Register accessor macros
5080 * @{
5081 */
5082
5083
5084 /* MTB - Register instance definitions */
5085 /* MTB */
5086 #define MTB_POSITION MTB_POSITION_REG(MTB)
5087 #define MTB_MASTER MTB_MASTER_REG(MTB)
5088 #define MTB_FLOW MTB_FLOW_REG(MTB)
5089 #define MTB_BASEr MTB_BASE_REG(MTB)
5090 #define MTB_MODECTRL MTB_MODECTRL_REG(MTB)
5091 #define MTB_TAGSET MTB_TAGSET_REG(MTB)
5092 #define MTB_TAGCLEAR MTB_TAGCLEAR_REG(MTB)
5093 #define MTB_LOCKACCESS MTB_LOCKACCESS_REG(MTB)
5094 #define MTB_LOCKSTAT MTB_LOCKSTAT_REG(MTB)
5095 #define MTB_AUTHSTAT MTB_AUTHSTAT_REG(MTB)
5096 #define MTB_DEVICEARCH MTB_DEVICEARCH_REG(MTB)
5097 #define MTB_DEVICECFG MTB_DEVICECFG_REG(MTB)
5098 #define MTB_DEVICETYPID MTB_DEVICETYPID_REG(MTB)
5099 #define MTB_PERIPHID4 MTB_PERIPHID_REG(MTB,0)
5100 #define MTB_PERIPHID5 MTB_PERIPHID_REG(MTB,1)
5101 #define MTB_PERIPHID6 MTB_PERIPHID_REG(MTB,2)
5102 #define MTB_PERIPHID7 MTB_PERIPHID_REG(MTB,3)
5103 #define MTB_PERIPHID0 MTB_PERIPHID_REG(MTB,4)
5104 #define MTB_PERIPHID1 MTB_PERIPHID_REG(MTB,5)
5105 #define MTB_PERIPHID2 MTB_PERIPHID_REG(MTB,6)
5106 #define MTB_PERIPHID3 MTB_PERIPHID_REG(MTB,7)
5107 #define MTB_COMPID0 MTB_COMPID_REG(MTB,0)
5108 #define MTB_COMPID1 MTB_COMPID_REG(MTB,1)
5109 #define MTB_COMPID2 MTB_COMPID_REG(MTB,2)
5110 #define MTB_COMPID3 MTB_COMPID_REG(MTB,3)
5111
5112 /* MTB - Register array accessors */
5113 #define MTB_PERIPHID(index) MTB_PERIPHID_REG(MTB,index)
5114 #define MTB_COMPID(index) MTB_COMPID_REG(MTB,index)
5115
5116 /*!
5117 * @}
5118 */ /* end of group MTB_Register_Accessor_Macros */
5119
5120
5121 /*!
5122 * @}
5123 */ /* end of group MTB_Peripheral_Access_Layer */
5124
5125
5126 /* ----------------------------------------------------------------------------
5127 -- MTBDWT Peripheral Access Layer
5128 ---------------------------------------------------------------------------- */
5129
5130 /*!
5131 * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
5132 * @{
5133 */
5134
5135 /** MTBDWT - Register Layout Typedef */
5136 typedef struct {
5137 __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */
5138 uint8_t RESERVED_0[28];
5139 struct { /* offset: 0x20, array step: 0x10 */
5140 __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */
5141 __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */
5142 __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */
5143 uint8_t RESERVED_0[4];
5144 } COMPARATOR[2];
5145 uint8_t RESERVED_1[448];
5146 __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */
5147 uint8_t RESERVED_2[3524];
5148 __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */
5149 __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */
5150 __I uint32_t PERIPHID[8]; /**< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 */
5151 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
5152 } MTBDWT_Type, *MTBDWT_MemMapPtr;
5153
5154 /* ----------------------------------------------------------------------------
5155 -- MTBDWT - Register accessor macros
5156 ---------------------------------------------------------------------------- */
5157
5158 /*!
5159 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
5160 * @{
5161 */
5162
5163
5164 /* MTBDWT - Register accessors */
5165 #define MTBDWT_CTRL_REG(base) ((base)->CTRL)
5166 #define MTBDWT_COMP_REG(base,index) ((base)->COMPARATOR[index].COMP)
5167 #define MTBDWT_MASK_REG(base,index) ((base)->COMPARATOR[index].MASK)
5168 #define MTBDWT_FCT_REG(base,index) ((base)->COMPARATOR[index].FCT)
5169 #define MTBDWT_TBCTRL_REG(base) ((base)->TBCTRL)
5170 #define MTBDWT_DEVICECFG_REG(base) ((base)->DEVICECFG)
5171 #define MTBDWT_DEVICETYPID_REG(base) ((base)->DEVICETYPID)
5172 #define MTBDWT_PERIPHID_REG(base,index) ((base)->PERIPHID[index])
5173 #define MTBDWT_COMPID_REG(base,index) ((base)->COMPID[index])
5174
5175 /*!
5176 * @}
5177 */ /* end of group MTBDWT_Register_Accessor_Macros */
5178
5179
5180 /* ----------------------------------------------------------------------------
5181 -- MTBDWT Register Masks
5182 ---------------------------------------------------------------------------- */
5183
5184 /*!
5185 * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
5186 * @{
5187 */
5188
5189 /* CTRL Bit Fields */
5190 #define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
5191 #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
5192 #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
5193 #define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
5194 #define MTBDWT_CTRL_NUMCMP_SHIFT 28
5195 #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
5196 /* COMP Bit Fields */
5197 #define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
5198 #define MTBDWT_COMP_COMP_SHIFT 0
5199 #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
5200 /* MASK Bit Fields */
5201 #define MTBDWT_MASK_MASK_MASK 0x1Fu
5202 #define MTBDWT_MASK_MASK_SHIFT 0
5203 #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
5204 /* FCT Bit Fields */
5205 #define MTBDWT_FCT_FUNCTION_MASK 0xFu
5206 #define MTBDWT_FCT_FUNCTION_SHIFT 0
5207 #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
5208 #define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
5209 #define MTBDWT_FCT_DATAVMATCH_SHIFT 8
5210 #define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
5211 #define MTBDWT_FCT_DATAVSIZE_SHIFT 10
5212 #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
5213 #define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
5214 #define MTBDWT_FCT_DATAVADDR0_SHIFT 12
5215 #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
5216 #define MTBDWT_FCT_MATCHED_MASK 0x1000000u
5217 #define MTBDWT_FCT_MATCHED_SHIFT 24
5218 /* TBCTRL Bit Fields */
5219 #define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
5220 #define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
5221 #define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
5222 #define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
5223 #define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
5224 #define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
5225 #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
5226 /* DEVICECFG Bit Fields */
5227 #define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
5228 #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
5229 #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
5230 /* DEVICETYPID Bit Fields */
5231 #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
5232 #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
5233 #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
5234 /* PERIPHID Bit Fields */
5235 #define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
5236 #define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
5237 #define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
5238 /* COMPID Bit Fields */
5239 #define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
5240 #define MTBDWT_COMPID_COMPID_SHIFT 0
5241 #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
5242
5243 /*!
5244 * @}
5245 */ /* end of group MTBDWT_Register_Masks */
5246
5247
5248 /* MTBDWT - Peripheral instance base addresses */
5249 /** Peripheral MTBDWT base address */
5250 #define MTBDWT_BASE (0xF0001000u)
5251 /** Peripheral MTBDWT base pointer */
5252 #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
5253 #define MTBDWT_BASE_PTR (MTBDWT)
5254 /** Array initializer of MTBDWT peripheral base addresses */
5255 #define MTBDWT_BASE_ADDRS { MTBDWT_BASE }
5256 /** Array initializer of MTBDWT peripheral base pointers */
5257 #define MTBDWT_BASE_PTRS { MTBDWT }
5258
5259 /* ----------------------------------------------------------------------------
5260 -- MTBDWT - Register accessor macros
5261 ---------------------------------------------------------------------------- */
5262
5263 /*!
5264 * @addtogroup MTBDWT_Register_Accessor_Macros MTBDWT - Register accessor macros
5265 * @{
5266 */
5267
5268
5269 /* MTBDWT - Register instance definitions */
5270 /* MTBDWT */
5271 #define MTBDWT_CTRL MTBDWT_CTRL_REG(MTBDWT)
5272 #define MTBDWT_COMP0 MTBDWT_COMP_REG(MTBDWT,0)
5273 #define MTBDWT_MASK0 MTBDWT_MASK_REG(MTBDWT,0)
5274 #define MTBDWT_FCT0 MTBDWT_FCT_REG(MTBDWT,0)
5275 #define MTBDWT_COMP1 MTBDWT_COMP_REG(MTBDWT,1)
5276 #define MTBDWT_MASK1 MTBDWT_MASK_REG(MTBDWT,1)
5277 #define MTBDWT_FCT1 MTBDWT_FCT_REG(MTBDWT,1)
5278 #define MTBDWT_TBCTRL MTBDWT_TBCTRL_REG(MTBDWT)
5279 #define MTBDWT_DEVICECFG MTBDWT_DEVICECFG_REG(MTBDWT)
5280 #define MTBDWT_DEVICETYPID MTBDWT_DEVICETYPID_REG(MTBDWT)
5281 #define MTBDWT_PERIPHID4 MTBDWT_PERIPHID_REG(MTBDWT,0)
5282 #define MTBDWT_PERIPHID5 MTBDWT_PERIPHID_REG(MTBDWT,1)
5283 #define MTBDWT_PERIPHID6 MTBDWT_PERIPHID_REG(MTBDWT,2)
5284 #define MTBDWT_PERIPHID7 MTBDWT_PERIPHID_REG(MTBDWT,3)
5285 #define MTBDWT_PERIPHID0 MTBDWT_PERIPHID_REG(MTBDWT,4)
5286 #define MTBDWT_PERIPHID1 MTBDWT_PERIPHID_REG(MTBDWT,5)
5287 #define MTBDWT_PERIPHID2 MTBDWT_PERIPHID_REG(MTBDWT,6)
5288 #define MTBDWT_PERIPHID3 MTBDWT_PERIPHID_REG(MTBDWT,7)
5289 #define MTBDWT_COMPID0 MTBDWT_COMPID_REG(MTBDWT,0)
5290 #define MTBDWT_COMPID1 MTBDWT_COMPID_REG(MTBDWT,1)
5291 #define MTBDWT_COMPID2 MTBDWT_COMPID_REG(MTBDWT,2)
5292 #define MTBDWT_COMPID3 MTBDWT_COMPID_REG(MTBDWT,3)
5293
5294 /* MTBDWT - Register array accessors */
5295 #define MTBDWT_COMP(index) MTBDWT_COMP_REG(MTBDWT,index)
5296 #define MTBDWT_MASK(index) MTBDWT_MASK_REG(MTBDWT,index)
5297 #define MTBDWT_FCT(index) MTBDWT_FCT_REG(MTBDWT,index)
5298 #define MTBDWT_PERIPHID(index) MTBDWT_PERIPHID_REG(MTBDWT,index)
5299 #define MTBDWT_COMPID(index) MTBDWT_COMPID_REG(MTBDWT,index)
5300
5301 /*!
5302 * @}
5303 */ /* end of group MTBDWT_Register_Accessor_Macros */
5304
5305
5306 /*!
5307 * @}
5308 */ /* end of group MTBDWT_Peripheral_Access_Layer */
5309
5310
5311 /* ----------------------------------------------------------------------------
5312 -- NV Peripheral Access Layer
5313 ---------------------------------------------------------------------------- */
5314
5315 /*!
5316 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
5317 * @{
5318 */
5319
5320 /** NV - Register Layout Typedef */
5321 typedef struct {
5322 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
5323 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
5324 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
5325 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
5326 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
5327 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
5328 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
5329 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
5330 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
5331 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
5332 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
5333 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
5334 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
5335 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
5336 } NV_Type, *NV_MemMapPtr;
5337
5338 /* ----------------------------------------------------------------------------
5339 -- NV - Register accessor macros
5340 ---------------------------------------------------------------------------- */
5341
5342 /*!
5343 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
5344 * @{
5345 */
5346
5347
5348 /* NV - Register accessors */
5349 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
5350 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
5351 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
5352 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
5353 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
5354 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
5355 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
5356 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
5357 #define NV_FPROT3_REG(base) ((base)->FPROT3)
5358 #define NV_FPROT2_REG(base) ((base)->FPROT2)
5359 #define NV_FPROT1_REG(base) ((base)->FPROT1)
5360 #define NV_FPROT0_REG(base) ((base)->FPROT0)
5361 #define NV_FSEC_REG(base) ((base)->FSEC)
5362 #define NV_FOPT_REG(base) ((base)->FOPT)
5363
5364 /*!
5365 * @}
5366 */ /* end of group NV_Register_Accessor_Macros */
5367
5368
5369 /* ----------------------------------------------------------------------------
5370 -- NV Register Masks
5371 ---------------------------------------------------------------------------- */
5372
5373 /*!
5374 * @addtogroup NV_Register_Masks NV Register Masks
5375 * @{
5376 */
5377
5378 /* BACKKEY3 Bit Fields */
5379 #define NV_BACKKEY3_KEY_MASK 0xFFu
5380 #define NV_BACKKEY3_KEY_SHIFT 0
5381 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
5382 /* BACKKEY2 Bit Fields */
5383 #define NV_BACKKEY2_KEY_MASK 0xFFu
5384 #define NV_BACKKEY2_KEY_SHIFT 0
5385 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
5386 /* BACKKEY1 Bit Fields */
5387 #define NV_BACKKEY1_KEY_MASK 0xFFu
5388 #define NV_BACKKEY1_KEY_SHIFT 0
5389 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
5390 /* BACKKEY0 Bit Fields */
5391 #define NV_BACKKEY0_KEY_MASK 0xFFu
5392 #define NV_BACKKEY0_KEY_SHIFT 0
5393 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
5394 /* BACKKEY7 Bit Fields */
5395 #define NV_BACKKEY7_KEY_MASK 0xFFu
5396 #define NV_BACKKEY7_KEY_SHIFT 0
5397 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
5398 /* BACKKEY6 Bit Fields */
5399 #define NV_BACKKEY6_KEY_MASK 0xFFu
5400 #define NV_BACKKEY6_KEY_SHIFT 0
5401 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
5402 /* BACKKEY5 Bit Fields */
5403 #define NV_BACKKEY5_KEY_MASK 0xFFu
5404 #define NV_BACKKEY5_KEY_SHIFT 0
5405 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
5406 /* BACKKEY4 Bit Fields */
5407 #define NV_BACKKEY4_KEY_MASK 0xFFu
5408 #define NV_BACKKEY4_KEY_SHIFT 0
5409 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
5410 /* FPROT3 Bit Fields */
5411 #define NV_FPROT3_PROT_MASK 0xFFu
5412 #define NV_FPROT3_PROT_SHIFT 0
5413 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
5414 /* FPROT2 Bit Fields */
5415 #define NV_FPROT2_PROT_MASK 0xFFu
5416 #define NV_FPROT2_PROT_SHIFT 0
5417 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
5418 /* FPROT1 Bit Fields */
5419 #define NV_FPROT1_PROT_MASK 0xFFu
5420 #define NV_FPROT1_PROT_SHIFT 0
5421 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
5422 /* FPROT0 Bit Fields */
5423 #define NV_FPROT0_PROT_MASK 0xFFu
5424 #define NV_FPROT0_PROT_SHIFT 0
5425 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
5426 /* FSEC Bit Fields */
5427 #define NV_FSEC_SEC_MASK 0x3u
5428 #define NV_FSEC_SEC_SHIFT 0
5429 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
5430 #define NV_FSEC_FSLACC_MASK 0xCu
5431 #define NV_FSEC_FSLACC_SHIFT 2
5432 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
5433 #define NV_FSEC_MEEN_MASK 0x30u
5434 #define NV_FSEC_MEEN_SHIFT 4
5435 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
5436 #define NV_FSEC_KEYEN_MASK 0xC0u
5437 #define NV_FSEC_KEYEN_SHIFT 6
5438 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
5439 /* FOPT Bit Fields */
5440 #define NV_FOPT_LPBOOT0_MASK 0x1u
5441 #define NV_FOPT_LPBOOT0_SHIFT 0
5442 #define NV_FOPT_BOOTPIN_OPT_MASK 0x2u
5443 #define NV_FOPT_BOOTPIN_OPT_SHIFT 1
5444 #define NV_FOPT_NMI_DIS_MASK 0x4u
5445 #define NV_FOPT_NMI_DIS_SHIFT 2
5446 #define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
5447 #define NV_FOPT_RESET_PIN_CFG_SHIFT 3
5448 #define NV_FOPT_LPBOOT1_MASK 0x10u
5449 #define NV_FOPT_LPBOOT1_SHIFT 4
5450 #define NV_FOPT_FAST_INIT_MASK 0x20u
5451 #define NV_FOPT_FAST_INIT_SHIFT 5
5452 #define NV_FOPT_BOOTSRC_SEL_MASK 0xC0u
5453 #define NV_FOPT_BOOTSRC_SEL_SHIFT 6
5454 #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x))<<NV_FOPT_BOOTSRC_SEL_SHIFT))&NV_FOPT_BOOTSRC_SEL_MASK)
5455
5456 /*!
5457 * @}
5458 */ /* end of group NV_Register_Masks */
5459
5460
5461 /* NV - Peripheral instance base addresses */
5462 /** Peripheral FTFA_FlashConfig base address */
5463 #define FTFA_FlashConfig_BASE (0x400u)
5464 /** Peripheral FTFA_FlashConfig base pointer */
5465 #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
5466 #define FTFA_FlashConfig_BASE_PTR (FTFA_FlashConfig)
5467 /** Array initializer of NV peripheral base addresses */
5468 #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
5469 /** Array initializer of NV peripheral base pointers */
5470 #define NV_BASE_PTRS { FTFA_FlashConfig }
5471
5472 /* ----------------------------------------------------------------------------
5473 -- NV - Register accessor macros
5474 ---------------------------------------------------------------------------- */
5475
5476 /*!
5477 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
5478 * @{
5479 */
5480
5481
5482 /* NV - Register instance definitions */
5483 /* FTFA_FlashConfig */
5484 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFA_FlashConfig)
5485 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFA_FlashConfig)
5486 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFA_FlashConfig)
5487 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFA_FlashConfig)
5488 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFA_FlashConfig)
5489 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFA_FlashConfig)
5490 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFA_FlashConfig)
5491 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFA_FlashConfig)
5492 #define NV_FPROT3 NV_FPROT3_REG(FTFA_FlashConfig)
5493 #define NV_FPROT2 NV_FPROT2_REG(FTFA_FlashConfig)
5494 #define NV_FPROT1 NV_FPROT1_REG(FTFA_FlashConfig)
5495 #define NV_FPROT0 NV_FPROT0_REG(FTFA_FlashConfig)
5496 #define NV_FSEC NV_FSEC_REG(FTFA_FlashConfig)
5497 #define NV_FOPT NV_FOPT_REG(FTFA_FlashConfig)
5498
5499 /*!
5500 * @}
5501 */ /* end of group NV_Register_Accessor_Macros */
5502
5503
5504 /*!
5505 * @}
5506 */ /* end of group NV_Peripheral_Access_Layer */
5507
5508
5509 /* ----------------------------------------------------------------------------
5510 -- OSC Peripheral Access Layer
5511 ---------------------------------------------------------------------------- */
5512
5513 /*!
5514 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
5515 * @{
5516 */
5517
5518 /** OSC - Register Layout Typedef */
5519 typedef struct {
5520 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
5521 } OSC_Type, *OSC_MemMapPtr;
5522
5523 /* ----------------------------------------------------------------------------
5524 -- OSC - Register accessor macros
5525 ---------------------------------------------------------------------------- */
5526
5527 /*!
5528 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
5529 * @{
5530 */
5531
5532
5533 /* OSC - Register accessors */
5534 #define OSC_CR_REG(base) ((base)->CR)
5535
5536 /*!
5537 * @}
5538 */ /* end of group OSC_Register_Accessor_Macros */
5539
5540
5541 /* ----------------------------------------------------------------------------
5542 -- OSC Register Masks
5543 ---------------------------------------------------------------------------- */
5544
5545 /*!
5546 * @addtogroup OSC_Register_Masks OSC Register Masks
5547 * @{
5548 */
5549
5550 /* CR Bit Fields */
5551 #define OSC_CR_SC16P_MASK 0x1u
5552 #define OSC_CR_SC16P_SHIFT 0
5553 #define OSC_CR_SC8P_MASK 0x2u
5554 #define OSC_CR_SC8P_SHIFT 1
5555 #define OSC_CR_SC4P_MASK 0x4u
5556 #define OSC_CR_SC4P_SHIFT 2
5557 #define OSC_CR_SC2P_MASK 0x8u
5558 #define OSC_CR_SC2P_SHIFT 3
5559 #define OSC_CR_EREFSTEN_MASK 0x20u
5560 #define OSC_CR_EREFSTEN_SHIFT 5
5561 #define OSC_CR_ERCLKEN_MASK 0x80u
5562 #define OSC_CR_ERCLKEN_SHIFT 7
5563
5564 /*!
5565 * @}
5566 */ /* end of group OSC_Register_Masks */
5567
5568
5569 /* OSC - Peripheral instance base addresses */
5570 /** Peripheral OSC0 base address */
5571 #define OSC0_BASE (0x40065000u)
5572 /** Peripheral OSC0 base pointer */
5573 #define OSC0 ((OSC_Type *)OSC0_BASE)
5574 #define OSC0_BASE_PTR (OSC0)
5575 /** Array initializer of OSC peripheral base addresses */
5576 #define OSC_BASE_ADDRS { OSC0_BASE }
5577 /** Array initializer of OSC peripheral base pointers */
5578 #define OSC_BASE_PTRS { OSC0 }
5579
5580 /* ----------------------------------------------------------------------------
5581 -- OSC - Register accessor macros
5582 ---------------------------------------------------------------------------- */
5583
5584 /*!
5585 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
5586 * @{
5587 */
5588
5589
5590 /* OSC - Register instance definitions */
5591 /* OSC0 */
5592 #define OSC0_CR OSC_CR_REG(OSC0)
5593
5594 /*!
5595 * @}
5596 */ /* end of group OSC_Register_Accessor_Macros */
5597
5598
5599 /*!
5600 * @}
5601 */ /* end of group OSC_Peripheral_Access_Layer */
5602
5603
5604 /* ----------------------------------------------------------------------------
5605 -- PIT Peripheral Access Layer
5606 ---------------------------------------------------------------------------- */
5607
5608 /*!
5609 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
5610 * @{
5611 */
5612
5613 /** PIT - Register Layout Typedef */
5614 typedef struct {
5615 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
5616 uint8_t RESERVED_0[220];
5617 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
5618 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
5619 uint8_t RESERVED_1[24];
5620 struct { /* offset: 0x100, array step: 0x10 */
5621 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
5622 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
5623 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
5624 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
5625 } CHANNEL[2];
5626 } PIT_Type, *PIT_MemMapPtr;
5627
5628 /* ----------------------------------------------------------------------------
5629 -- PIT - Register accessor macros
5630 ---------------------------------------------------------------------------- */
5631
5632 /*!
5633 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
5634 * @{
5635 */
5636
5637
5638 /* PIT - Register accessors */
5639 #define PIT_MCR_REG(base) ((base)->MCR)
5640 #define PIT_LTMR64H_REG(base) ((base)->LTMR64H)
5641 #define PIT_LTMR64L_REG(base) ((base)->LTMR64L)
5642 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
5643 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
5644 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
5645 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
5646
5647 /*!
5648 * @}
5649 */ /* end of group PIT_Register_Accessor_Macros */
5650
5651
5652 /* ----------------------------------------------------------------------------
5653 -- PIT Register Masks
5654 ---------------------------------------------------------------------------- */
5655
5656 /*!
5657 * @addtogroup PIT_Register_Masks PIT Register Masks
5658 * @{
5659 */
5660
5661 /* MCR Bit Fields */
5662 #define PIT_MCR_FRZ_MASK 0x1u
5663 #define PIT_MCR_FRZ_SHIFT 0
5664 #define PIT_MCR_MDIS_MASK 0x2u
5665 #define PIT_MCR_MDIS_SHIFT 1
5666 /* LTMR64H Bit Fields */
5667 #define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
5668 #define PIT_LTMR64H_LTH_SHIFT 0
5669 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
5670 /* LTMR64L Bit Fields */
5671 #define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
5672 #define PIT_LTMR64L_LTL_SHIFT 0
5673 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
5674 /* LDVAL Bit Fields */
5675 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
5676 #define PIT_LDVAL_TSV_SHIFT 0
5677 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
5678 /* CVAL Bit Fields */
5679 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
5680 #define PIT_CVAL_TVL_SHIFT 0
5681 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
5682 /* TCTRL Bit Fields */
5683 #define PIT_TCTRL_TEN_MASK 0x1u
5684 #define PIT_TCTRL_TEN_SHIFT 0
5685 #define PIT_TCTRL_TIE_MASK 0x2u
5686 #define PIT_TCTRL_TIE_SHIFT 1
5687 #define PIT_TCTRL_CHN_MASK 0x4u
5688 #define PIT_TCTRL_CHN_SHIFT 2
5689 /* TFLG Bit Fields */
5690 #define PIT_TFLG_TIF_MASK 0x1u
5691 #define PIT_TFLG_TIF_SHIFT 0
5692
5693 /*!
5694 * @}
5695 */ /* end of group PIT_Register_Masks */
5696
5697
5698 /* PIT - Peripheral instance base addresses */
5699 /** Peripheral PIT base address */
5700 #define PIT_BASE (0x40037000u)
5701 /** Peripheral PIT base pointer */
5702 #define PIT ((PIT_Type *)PIT_BASE)
5703 #define PIT_BASE_PTR (PIT)
5704 /** Array initializer of PIT peripheral base addresses */
5705 #define PIT_BASE_ADDRS { PIT_BASE }
5706 /** Array initializer of PIT peripheral base pointers */
5707 #define PIT_BASE_PTRS { PIT }
5708 /** Interrupt vectors for the PIT peripheral type */
5709 #define PIT_IRQS { PIT_IRQn, PIT_IRQn }
5710
5711 /* ----------------------------------------------------------------------------
5712 -- PIT - Register accessor macros
5713 ---------------------------------------------------------------------------- */
5714
5715 /*!
5716 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
5717 * @{
5718 */
5719
5720
5721 /* PIT - Register instance definitions */
5722 /* PIT */
5723 #define PIT_MCR PIT_MCR_REG(PIT)
5724 #define PIT_LTMR64H PIT_LTMR64H_REG(PIT)
5725 #define PIT_LTMR64L PIT_LTMR64L_REG(PIT)
5726 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
5727 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
5728 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
5729 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
5730 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
5731 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
5732 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
5733 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
5734
5735 /* PIT - Register array accessors */
5736 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
5737 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
5738 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
5739 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
5740
5741 /*!
5742 * @}
5743 */ /* end of group PIT_Register_Accessor_Macros */
5744
5745
5746 /*!
5747 * @}
5748 */ /* end of group PIT_Peripheral_Access_Layer */
5749
5750
5751 /* ----------------------------------------------------------------------------
5752 -- PMC Peripheral Access Layer
5753 ---------------------------------------------------------------------------- */
5754
5755 /*!
5756 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
5757 * @{
5758 */
5759
5760 /** PMC - Register Layout Typedef */
5761 typedef struct {
5762 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
5763 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
5764 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
5765 } PMC_Type, *PMC_MemMapPtr;
5766
5767 /* ----------------------------------------------------------------------------
5768 -- PMC - Register accessor macros
5769 ---------------------------------------------------------------------------- */
5770
5771 /*!
5772 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
5773 * @{
5774 */
5775
5776
5777 /* PMC - Register accessors */
5778 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
5779 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
5780 #define PMC_REGSC_REG(base) ((base)->REGSC)
5781
5782 /*!
5783 * @}
5784 */ /* end of group PMC_Register_Accessor_Macros */
5785
5786
5787 /* ----------------------------------------------------------------------------
5788 -- PMC Register Masks
5789 ---------------------------------------------------------------------------- */
5790
5791 /*!
5792 * @addtogroup PMC_Register_Masks PMC Register Masks
5793 * @{
5794 */
5795
5796 /* LVDSC1 Bit Fields */
5797 #define PMC_LVDSC1_LVDV_MASK 0x3u
5798 #define PMC_LVDSC1_LVDV_SHIFT 0
5799 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
5800 #define PMC_LVDSC1_LVDRE_MASK 0x10u
5801 #define PMC_LVDSC1_LVDRE_SHIFT 4
5802 #define PMC_LVDSC1_LVDIE_MASK 0x20u
5803 #define PMC_LVDSC1_LVDIE_SHIFT 5
5804 #define PMC_LVDSC1_LVDACK_MASK 0x40u
5805 #define PMC_LVDSC1_LVDACK_SHIFT 6
5806 #define PMC_LVDSC1_LVDF_MASK 0x80u
5807 #define PMC_LVDSC1_LVDF_SHIFT 7
5808 /* LVDSC2 Bit Fields */
5809 #define PMC_LVDSC2_LVWV_MASK 0x3u
5810 #define PMC_LVDSC2_LVWV_SHIFT 0
5811 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
5812 #define PMC_LVDSC2_LVWIE_MASK 0x20u
5813 #define PMC_LVDSC2_LVWIE_SHIFT 5
5814 #define PMC_LVDSC2_LVWACK_MASK 0x40u
5815 #define PMC_LVDSC2_LVWACK_SHIFT 6
5816 #define PMC_LVDSC2_LVWF_MASK 0x80u
5817 #define PMC_LVDSC2_LVWF_SHIFT 7
5818 /* REGSC Bit Fields */
5819 #define PMC_REGSC_BGBE_MASK 0x1u
5820 #define PMC_REGSC_BGBE_SHIFT 0
5821 #define PMC_REGSC_REGONS_MASK 0x4u
5822 #define PMC_REGSC_REGONS_SHIFT 2
5823 #define PMC_REGSC_ACKISO_MASK 0x8u
5824 #define PMC_REGSC_ACKISO_SHIFT 3
5825 #define PMC_REGSC_BGEN_MASK 0x10u
5826 #define PMC_REGSC_BGEN_SHIFT 4
5827
5828 /*!
5829 * @}
5830 */ /* end of group PMC_Register_Masks */
5831
5832
5833 /* PMC - Peripheral instance base addresses */
5834 /** Peripheral PMC base address */
5835 #define PMC_BASE (0x4007D000u)
5836 /** Peripheral PMC base pointer */
5837 #define PMC ((PMC_Type *)PMC_BASE)
5838 #define PMC_BASE_PTR (PMC)
5839 /** Array initializer of PMC peripheral base addresses */
5840 #define PMC_BASE_ADDRS { PMC_BASE }
5841 /** Array initializer of PMC peripheral base pointers */
5842 #define PMC_BASE_PTRS { PMC }
5843 /** Interrupt vectors for the PMC peripheral type */
5844 #define PMC_IRQS { PMC_IRQn }
5845
5846 /* ----------------------------------------------------------------------------
5847 -- PMC - Register accessor macros
5848 ---------------------------------------------------------------------------- */
5849
5850 /*!
5851 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
5852 * @{
5853 */
5854
5855
5856 /* PMC - Register instance definitions */
5857 /* PMC */
5858 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
5859 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
5860 #define PMC_REGSC PMC_REGSC_REG(PMC)
5861
5862 /*!
5863 * @}
5864 */ /* end of group PMC_Register_Accessor_Macros */
5865
5866
5867 /*!
5868 * @}
5869 */ /* end of group PMC_Peripheral_Access_Layer */
5870
5871
5872 /* ----------------------------------------------------------------------------
5873 -- PORT Peripheral Access Layer
5874 ---------------------------------------------------------------------------- */
5875
5876 /*!
5877 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
5878 * @{
5879 */
5880
5881 /** PORT - Register Layout Typedef */
5882 typedef struct {
5883 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
5884 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
5885 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
5886 uint8_t RESERVED_0[24];
5887 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
5888 } PORT_Type, *PORT_MemMapPtr;
5889
5890 /* ----------------------------------------------------------------------------
5891 -- PORT - Register accessor macros
5892 ---------------------------------------------------------------------------- */
5893
5894 /*!
5895 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
5896 * @{
5897 */
5898
5899
5900 /* PORT - Register accessors */
5901 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
5902 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
5903 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
5904 #define PORT_ISFR_REG(base) ((base)->ISFR)
5905
5906 /*!
5907 * @}
5908 */ /* end of group PORT_Register_Accessor_Macros */
5909
5910
5911 /* ----------------------------------------------------------------------------
5912 -- PORT Register Masks
5913 ---------------------------------------------------------------------------- */
5914
5915 /*!
5916 * @addtogroup PORT_Register_Masks PORT Register Masks
5917 * @{
5918 */
5919
5920 /* PCR Bit Fields */
5921 #define PORT_PCR_PS_MASK 0x1u
5922 #define PORT_PCR_PS_SHIFT 0
5923 #define PORT_PCR_PE_MASK 0x2u
5924 #define PORT_PCR_PE_SHIFT 1
5925 #define PORT_PCR_SRE_MASK 0x4u
5926 #define PORT_PCR_SRE_SHIFT 2
5927 #define PORT_PCR_PFE_MASK 0x10u
5928 #define PORT_PCR_PFE_SHIFT 4
5929 #define PORT_PCR_DSE_MASK 0x40u
5930 #define PORT_PCR_DSE_SHIFT 6
5931 #define PORT_PCR_MUX_MASK 0x700u
5932 #define PORT_PCR_MUX_SHIFT 8
5933 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
5934 #define PORT_PCR_IRQC_MASK 0xF0000u
5935 #define PORT_PCR_IRQC_SHIFT 16
5936 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
5937 #define PORT_PCR_ISF_MASK 0x1000000u
5938 #define PORT_PCR_ISF_SHIFT 24
5939 /* GPCLR Bit Fields */
5940 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
5941 #define PORT_GPCLR_GPWD_SHIFT 0
5942 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
5943 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
5944 #define PORT_GPCLR_GPWE_SHIFT 16
5945 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
5946 /* GPCHR Bit Fields */
5947 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
5948 #define PORT_GPCHR_GPWD_SHIFT 0
5949 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
5950 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
5951 #define PORT_GPCHR_GPWE_SHIFT 16
5952 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
5953 /* ISFR Bit Fields */
5954 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
5955 #define PORT_ISFR_ISF_SHIFT 0
5956 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
5957
5958 /*!
5959 * @}
5960 */ /* end of group PORT_Register_Masks */
5961
5962
5963 /* PORT - Peripheral instance base addresses */
5964 /** Peripheral PORTA base address */
5965 #define PORTA_BASE (0x40049000u)
5966 /** Peripheral PORTA base pointer */
5967 #define PORTA ((PORT_Type *)PORTA_BASE)
5968 #define PORTA_BASE_PTR (PORTA)
5969 /** Peripheral PORTB base address */
5970 #define PORTB_BASE (0x4004A000u)
5971 /** Peripheral PORTB base pointer */
5972 #define PORTB ((PORT_Type *)PORTB_BASE)
5973 #define PORTB_BASE_PTR (PORTB)
5974 /** Peripheral PORTC base address */
5975 #define PORTC_BASE (0x4004B000u)
5976 /** Peripheral PORTC base pointer */
5977 #define PORTC ((PORT_Type *)PORTC_BASE)
5978 #define PORTC_BASE_PTR (PORTC)
5979 /** Peripheral PORTD base address */
5980 #define PORTD_BASE (0x4004C000u)
5981 /** Peripheral PORTD base pointer */
5982 #define PORTD ((PORT_Type *)PORTD_BASE)
5983 #define PORTD_BASE_PTR (PORTD)
5984 /** Peripheral PORTE base address */
5985 #define PORTE_BASE (0x4004D000u)
5986 /** Peripheral PORTE base pointer */
5987 #define PORTE ((PORT_Type *)PORTE_BASE)
5988 #define PORTE_BASE_PTR (PORTE)
5989 /** Array initializer of PORT peripheral base addresses */
5990 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
5991 /** Array initializer of PORT peripheral base pointers */
5992 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
5993 /** Interrupt vectors for the PORT peripheral type */
5994 #define PORT_IRQS { PORTA_IRQn, NotAvail_IRQn, PORTCD_IRQn, PORTCD_IRQn, NotAvail_IRQn }
5995
5996 /* ----------------------------------------------------------------------------
5997 -- PORT - Register accessor macros
5998 ---------------------------------------------------------------------------- */
5999
6000 /*!
6001 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
6002 * @{
6003 */
6004
6005
6006 /* PORT - Register instance definitions */
6007 /* PORTA */
6008 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
6009 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
6010 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
6011 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
6012 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
6013 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
6014 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
6015 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
6016 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
6017 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
6018 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
6019 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
6020 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
6021 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
6022 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
6023 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
6024 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
6025 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
6026 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
6027 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
6028 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
6029 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
6030 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
6031 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
6032 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
6033 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
6034 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
6035 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
6036 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
6037 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
6038 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
6039 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
6040 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
6041 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
6042 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
6043 /* PORTB */
6044 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
6045 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
6046 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
6047 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
6048 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
6049 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
6050 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
6051 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
6052 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
6053 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
6054 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
6055 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
6056 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
6057 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
6058 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
6059 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
6060 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
6061 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
6062 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
6063 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
6064 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
6065 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
6066 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
6067 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
6068 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
6069 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
6070 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
6071 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
6072 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
6073 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
6074 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
6075 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
6076 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
6077 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
6078 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
6079 /* PORTC */
6080 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
6081 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
6082 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
6083 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
6084 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
6085 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
6086 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
6087 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
6088 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
6089 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
6090 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
6091 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
6092 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
6093 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
6094 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
6095 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
6096 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
6097 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
6098 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
6099 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
6100 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
6101 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
6102 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
6103 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
6104 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
6105 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
6106 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
6107 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
6108 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
6109 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
6110 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
6111 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
6112 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
6113 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
6114 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
6115 /* PORTD */
6116 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
6117 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
6118 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
6119 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
6120 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
6121 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
6122 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
6123 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
6124 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
6125 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
6126 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
6127 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
6128 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
6129 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
6130 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
6131 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
6132 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
6133 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
6134 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
6135 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
6136 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
6137 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
6138 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
6139 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
6140 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
6141 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
6142 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
6143 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
6144 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
6145 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
6146 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
6147 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
6148 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
6149 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
6150 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
6151 /* PORTE */
6152 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
6153 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
6154 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
6155 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
6156 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
6157 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
6158 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
6159 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
6160 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
6161 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
6162 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
6163 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
6164 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
6165 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
6166 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
6167 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
6168 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
6169 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
6170 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
6171 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
6172 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
6173 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
6174 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
6175 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
6176 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
6177 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
6178 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
6179 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
6180 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
6181 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
6182 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
6183 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
6184 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
6185 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
6186 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
6187
6188 /* PORT - Register array accessors */
6189 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
6190 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
6191 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
6192 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
6193 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
6194
6195 /*!
6196 * @}
6197 */ /* end of group PORT_Register_Accessor_Macros */
6198
6199
6200 /*!
6201 * @}
6202 */ /* end of group PORT_Peripheral_Access_Layer */
6203
6204
6205 /* ----------------------------------------------------------------------------
6206 -- RCM Peripheral Access Layer
6207 ---------------------------------------------------------------------------- */
6208
6209 /*!
6210 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
6211 * @{
6212 */
6213
6214 /** RCM - Register Layout Typedef */
6215 typedef struct {
6216 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
6217 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
6218 uint8_t RESERVED_0[2];
6219 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
6220 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
6221 __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */
6222 __IO uint8_t MR; /**< Mode Register, offset: 0x7 */
6223 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
6224 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
6225 } RCM_Type, *RCM_MemMapPtr;
6226
6227 /* ----------------------------------------------------------------------------
6228 -- RCM - Register accessor macros
6229 ---------------------------------------------------------------------------- */
6230
6231 /*!
6232 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
6233 * @{
6234 */
6235
6236
6237 /* RCM - Register accessors */
6238 #define RCM_SRS0_REG(base) ((base)->SRS0)
6239 #define RCM_SRS1_REG(base) ((base)->SRS1)
6240 #define RCM_RPFC_REG(base) ((base)->RPFC)
6241 #define RCM_RPFW_REG(base) ((base)->RPFW)
6242 #define RCM_FM_REG(base) ((base)->FM)
6243 #define RCM_MR_REG(base) ((base)->MR)
6244 #define RCM_SSRS0_REG(base) ((base)->SSRS0)
6245 #define RCM_SSRS1_REG(base) ((base)->SSRS1)
6246
6247 /*!
6248 * @}
6249 */ /* end of group RCM_Register_Accessor_Macros */
6250
6251
6252 /* ----------------------------------------------------------------------------
6253 -- RCM Register Masks
6254 ---------------------------------------------------------------------------- */
6255
6256 /*!
6257 * @addtogroup RCM_Register_Masks RCM Register Masks
6258 * @{
6259 */
6260
6261 /* SRS0 Bit Fields */
6262 #define RCM_SRS0_WAKEUP_MASK 0x1u
6263 #define RCM_SRS0_WAKEUP_SHIFT 0
6264 #define RCM_SRS0_LVD_MASK 0x2u
6265 #define RCM_SRS0_LVD_SHIFT 1
6266 #define RCM_SRS0_WDOG_MASK 0x20u
6267 #define RCM_SRS0_WDOG_SHIFT 5
6268 #define RCM_SRS0_PIN_MASK 0x40u
6269 #define RCM_SRS0_PIN_SHIFT 6
6270 #define RCM_SRS0_POR_MASK 0x80u
6271 #define RCM_SRS0_POR_SHIFT 7
6272 /* SRS1 Bit Fields */
6273 #define RCM_SRS1_LOCKUP_MASK 0x2u
6274 #define RCM_SRS1_LOCKUP_SHIFT 1
6275 #define RCM_SRS1_SW_MASK 0x4u
6276 #define RCM_SRS1_SW_SHIFT 2
6277 #define RCM_SRS1_MDM_AP_MASK 0x8u
6278 #define RCM_SRS1_MDM_AP_SHIFT 3
6279 #define RCM_SRS1_SACKERR_MASK 0x20u
6280 #define RCM_SRS1_SACKERR_SHIFT 5
6281 /* RPFC Bit Fields */
6282 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
6283 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
6284 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
6285 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
6286 #define RCM_RPFC_RSTFLTSS_SHIFT 2
6287 /* RPFW Bit Fields */
6288 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
6289 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
6290 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
6291 /* FM Bit Fields */
6292 #define RCM_FM_FORCEROM_MASK 0x6u
6293 #define RCM_FM_FORCEROM_SHIFT 1
6294 #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_FM_FORCEROM_SHIFT))&RCM_FM_FORCEROM_MASK)
6295 /* MR Bit Fields */
6296 #define RCM_MR_BOOTROM_MASK 0x6u
6297 #define RCM_MR_BOOTROM_SHIFT 1
6298 #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x))<<RCM_MR_BOOTROM_SHIFT))&RCM_MR_BOOTROM_MASK)
6299 /* SSRS0 Bit Fields */
6300 #define RCM_SSRS0_SWAKEUP_MASK 0x1u
6301 #define RCM_SSRS0_SWAKEUP_SHIFT 0
6302 #define RCM_SSRS0_SLVD_MASK 0x2u
6303 #define RCM_SSRS0_SLVD_SHIFT 1
6304 #define RCM_SSRS0_SWDOG_MASK 0x20u
6305 #define RCM_SSRS0_SWDOG_SHIFT 5
6306 #define RCM_SSRS0_SPIN_MASK 0x40u
6307 #define RCM_SSRS0_SPIN_SHIFT 6
6308 #define RCM_SSRS0_SPOR_MASK 0x80u
6309 #define RCM_SSRS0_SPOR_SHIFT 7
6310 /* SSRS1 Bit Fields */
6311 #define RCM_SSRS1_SLOCKUP_MASK 0x2u
6312 #define RCM_SSRS1_SLOCKUP_SHIFT 1
6313 #define RCM_SSRS1_SSW_MASK 0x4u
6314 #define RCM_SSRS1_SSW_SHIFT 2
6315 #define RCM_SSRS1_SMDM_AP_MASK 0x8u
6316 #define RCM_SSRS1_SMDM_AP_SHIFT 3
6317 #define RCM_SSRS1_SSACKERR_MASK 0x20u
6318 #define RCM_SSRS1_SSACKERR_SHIFT 5
6319
6320 /*!
6321 * @}
6322 */ /* end of group RCM_Register_Masks */
6323
6324
6325 /* RCM - Peripheral instance base addresses */
6326 /** Peripheral RCM base address */
6327 #define RCM_BASE (0x4007F000u)
6328 /** Peripheral RCM base pointer */
6329 #define RCM ((RCM_Type *)RCM_BASE)
6330 #define RCM_BASE_PTR (RCM)
6331 /** Array initializer of RCM peripheral base addresses */
6332 #define RCM_BASE_ADDRS { RCM_BASE }
6333 /** Array initializer of RCM peripheral base pointers */
6334 #define RCM_BASE_PTRS { RCM }
6335
6336 /* ----------------------------------------------------------------------------
6337 -- RCM - Register accessor macros
6338 ---------------------------------------------------------------------------- */
6339
6340 /*!
6341 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
6342 * @{
6343 */
6344
6345
6346 /* RCM - Register instance definitions */
6347 /* RCM */
6348 #define RCM_SRS0 RCM_SRS0_REG(RCM)
6349 #define RCM_SRS1 RCM_SRS1_REG(RCM)
6350 #define RCM_RPFC RCM_RPFC_REG(RCM)
6351 #define RCM_RPFW RCM_RPFW_REG(RCM)
6352 #define RCM_FM RCM_FM_REG(RCM)
6353 #define RCM_MR RCM_MR_REG(RCM)
6354 #define RCM_SSRS0 RCM_SSRS0_REG(RCM)
6355 #define RCM_SSRS1 RCM_SSRS1_REG(RCM)
6356
6357 /*!
6358 * @}
6359 */ /* end of group RCM_Register_Accessor_Macros */
6360
6361
6362 /*!
6363 * @}
6364 */ /* end of group RCM_Peripheral_Access_Layer */
6365
6366
6367 /* ----------------------------------------------------------------------------
6368 -- RFSYS Peripheral Access Layer
6369 ---------------------------------------------------------------------------- */
6370
6371 /*!
6372 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
6373 * @{
6374 */
6375
6376 /** RFSYS - Register Layout Typedef */
6377 typedef struct {
6378 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
6379 } RFSYS_Type, *RFSYS_MemMapPtr;
6380
6381 /* ----------------------------------------------------------------------------
6382 -- RFSYS - Register accessor macros
6383 ---------------------------------------------------------------------------- */
6384
6385 /*!
6386 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
6387 * @{
6388 */
6389
6390
6391 /* RFSYS - Register accessors */
6392 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
6393
6394 /*!
6395 * @}
6396 */ /* end of group RFSYS_Register_Accessor_Macros */
6397
6398
6399 /* ----------------------------------------------------------------------------
6400 -- RFSYS Register Masks
6401 ---------------------------------------------------------------------------- */
6402
6403 /*!
6404 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
6405 * @{
6406 */
6407
6408 /* REG Bit Fields */
6409 #define RFSYS_REG_LL_MASK 0xFFu
6410 #define RFSYS_REG_LL_SHIFT 0
6411 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
6412 #define RFSYS_REG_LH_MASK 0xFF00u
6413 #define RFSYS_REG_LH_SHIFT 8
6414 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
6415 #define RFSYS_REG_HL_MASK 0xFF0000u
6416 #define RFSYS_REG_HL_SHIFT 16
6417 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
6418 #define RFSYS_REG_HH_MASK 0xFF000000u
6419 #define RFSYS_REG_HH_SHIFT 24
6420 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
6421
6422 /*!
6423 * @}
6424 */ /* end of group RFSYS_Register_Masks */
6425
6426
6427 /* RFSYS - Peripheral instance base addresses */
6428 /** Peripheral RFSYS base address */
6429 #define RFSYS_BASE (0x40041000u)
6430 /** Peripheral RFSYS base pointer */
6431 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
6432 #define RFSYS_BASE_PTR (RFSYS)
6433 /** Array initializer of RFSYS peripheral base addresses */
6434 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
6435 /** Array initializer of RFSYS peripheral base pointers */
6436 #define RFSYS_BASE_PTRS { RFSYS }
6437
6438 /* ----------------------------------------------------------------------------
6439 -- RFSYS - Register accessor macros
6440 ---------------------------------------------------------------------------- */
6441
6442 /*!
6443 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
6444 * @{
6445 */
6446
6447
6448 /* RFSYS - Register instance definitions */
6449 /* RFSYS */
6450 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
6451 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
6452 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
6453 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
6454 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
6455 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
6456 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
6457 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
6458
6459 /* RFSYS - Register array accessors */
6460 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
6461
6462 /*!
6463 * @}
6464 */ /* end of group RFSYS_Register_Accessor_Macros */
6465
6466
6467 /*!
6468 * @}
6469 */ /* end of group RFSYS_Peripheral_Access_Layer */
6470
6471
6472 /* ----------------------------------------------------------------------------
6473 -- ROM Peripheral Access Layer
6474 ---------------------------------------------------------------------------- */
6475
6476 /*!
6477 * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
6478 * @{
6479 */
6480
6481 /** ROM - Register Layout Typedef */
6482 typedef struct {
6483 __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */
6484 __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */
6485 uint8_t RESERVED_0[4028];
6486 __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */
6487 __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */
6488 __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */
6489 __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */
6490 __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */
6491 __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */
6492 __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */
6493 __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */
6494 __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */
6495 __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */
6496 } ROM_Type, *ROM_MemMapPtr;
6497
6498 /* ----------------------------------------------------------------------------
6499 -- ROM - Register accessor macros
6500 ---------------------------------------------------------------------------- */
6501
6502 /*!
6503 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
6504 * @{
6505 */
6506
6507
6508 /* ROM - Register accessors */
6509 #define ROM_ENTRY_REG(base,index) ((base)->ENTRY[index])
6510 #define ROM_TABLEMARK_REG(base) ((base)->TABLEMARK)
6511 #define ROM_SYSACCESS_REG(base) ((base)->SYSACCESS)
6512 #define ROM_PERIPHID4_REG(base) ((base)->PERIPHID4)
6513 #define ROM_PERIPHID5_REG(base) ((base)->PERIPHID5)
6514 #define ROM_PERIPHID6_REG(base) ((base)->PERIPHID6)
6515 #define ROM_PERIPHID7_REG(base) ((base)->PERIPHID7)
6516 #define ROM_PERIPHID0_REG(base) ((base)->PERIPHID0)
6517 #define ROM_PERIPHID1_REG(base) ((base)->PERIPHID1)
6518 #define ROM_PERIPHID2_REG(base) ((base)->PERIPHID2)
6519 #define ROM_PERIPHID3_REG(base) ((base)->PERIPHID3)
6520 #define ROM_COMPID_REG(base,index) ((base)->COMPID[index])
6521
6522 /*!
6523 * @}
6524 */ /* end of group ROM_Register_Accessor_Macros */
6525
6526
6527 /* ----------------------------------------------------------------------------
6528 -- ROM Register Masks
6529 ---------------------------------------------------------------------------- */
6530
6531 /*!
6532 * @addtogroup ROM_Register_Masks ROM Register Masks
6533 * @{
6534 */
6535
6536 /* ENTRY Bit Fields */
6537 #define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
6538 #define ROM_ENTRY_ENTRY_SHIFT 0
6539 #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
6540 /* TABLEMARK Bit Fields */
6541 #define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
6542 #define ROM_TABLEMARK_MARK_SHIFT 0
6543 #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
6544 /* SYSACCESS Bit Fields */
6545 #define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
6546 #define ROM_SYSACCESS_SYSACCESS_SHIFT 0
6547 #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
6548 /* PERIPHID4 Bit Fields */
6549 #define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
6550 #define ROM_PERIPHID4_PERIPHID_SHIFT 0
6551 #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
6552 /* PERIPHID5 Bit Fields */
6553 #define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
6554 #define ROM_PERIPHID5_PERIPHID_SHIFT 0
6555 #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
6556 /* PERIPHID6 Bit Fields */
6557 #define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
6558 #define ROM_PERIPHID6_PERIPHID_SHIFT 0
6559 #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
6560 /* PERIPHID7 Bit Fields */
6561 #define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
6562 #define ROM_PERIPHID7_PERIPHID_SHIFT 0
6563 #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
6564 /* PERIPHID0 Bit Fields */
6565 #define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
6566 #define ROM_PERIPHID0_PERIPHID_SHIFT 0
6567 #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
6568 /* PERIPHID1 Bit Fields */
6569 #define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
6570 #define ROM_PERIPHID1_PERIPHID_SHIFT 0
6571 #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
6572 /* PERIPHID2 Bit Fields */
6573 #define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
6574 #define ROM_PERIPHID2_PERIPHID_SHIFT 0
6575 #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
6576 /* PERIPHID3 Bit Fields */
6577 #define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
6578 #define ROM_PERIPHID3_PERIPHID_SHIFT 0
6579 #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
6580 /* COMPID Bit Fields */
6581 #define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
6582 #define ROM_COMPID_COMPID_SHIFT 0
6583 #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
6584
6585 /*!
6586 * @}
6587 */ /* end of group ROM_Register_Masks */
6588
6589
6590 /* ROM - Peripheral instance base addresses */
6591 /** Peripheral ROM base address */
6592 #define ROM_BASE (0xF0002000u)
6593 /** Peripheral ROM base pointer */
6594 #define ROM ((ROM_Type *)ROM_BASE)
6595 #define ROM_BASE_PTR (ROM)
6596 /** Array initializer of ROM peripheral base addresses */
6597 #define ROM_BASE_ADDRS { ROM_BASE }
6598 /** Array initializer of ROM peripheral base pointers */
6599 #define ROM_BASE_PTRS { ROM }
6600
6601 /* ----------------------------------------------------------------------------
6602 -- ROM - Register accessor macros
6603 ---------------------------------------------------------------------------- */
6604
6605 /*!
6606 * @addtogroup ROM_Register_Accessor_Macros ROM - Register accessor macros
6607 * @{
6608 */
6609
6610
6611 /* ROM - Register instance definitions */
6612 /* ROM */
6613 #define ROM_ENTRY0 ROM_ENTRY_REG(ROM,0)
6614 #define ROM_ENTRY1 ROM_ENTRY_REG(ROM,1)
6615 #define ROM_ENTRY2 ROM_ENTRY_REG(ROM,2)
6616 #define ROM_TABLEMARK ROM_TABLEMARK_REG(ROM)
6617 #define ROM_SYSACCESS ROM_SYSACCESS_REG(ROM)
6618 #define ROM_PERIPHID4 ROM_PERIPHID4_REG(ROM)
6619 #define ROM_PERIPHID5 ROM_PERIPHID5_REG(ROM)
6620 #define ROM_PERIPHID6 ROM_PERIPHID6_REG(ROM)
6621 #define ROM_PERIPHID7 ROM_PERIPHID7_REG(ROM)
6622 #define ROM_PERIPHID0 ROM_PERIPHID0_REG(ROM)
6623 #define ROM_PERIPHID1 ROM_PERIPHID1_REG(ROM)
6624 #define ROM_PERIPHID2 ROM_PERIPHID2_REG(ROM)
6625 #define ROM_PERIPHID3 ROM_PERIPHID3_REG(ROM)
6626 #define ROM_COMPID0 ROM_COMPID_REG(ROM,0)
6627 #define ROM_COMPID1 ROM_COMPID_REG(ROM,1)
6628 #define ROM_COMPID2 ROM_COMPID_REG(ROM,2)
6629 #define ROM_COMPID3 ROM_COMPID_REG(ROM,3)
6630
6631 /* ROM - Register array accessors */
6632 #define ROM_ENTRY(index) ROM_ENTRY_REG(ROM,index)
6633 #define ROM_COMPID(index) ROM_COMPID_REG(ROM,index)
6634
6635 /*!
6636 * @}
6637 */ /* end of group ROM_Register_Accessor_Macros */
6638
6639
6640 /*!
6641 * @}
6642 */ /* end of group ROM_Peripheral_Access_Layer */
6643
6644
6645 /* ----------------------------------------------------------------------------
6646 -- RTC Peripheral Access Layer
6647 ---------------------------------------------------------------------------- */
6648
6649 /*!
6650 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
6651 * @{
6652 */
6653
6654 /** RTC - Register Layout Typedef */
6655 typedef struct {
6656 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
6657 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
6658 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
6659 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
6660 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
6661 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
6662 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
6663 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
6664 } RTC_Type, *RTC_MemMapPtr;
6665
6666 /* ----------------------------------------------------------------------------
6667 -- RTC - Register accessor macros
6668 ---------------------------------------------------------------------------- */
6669
6670 /*!
6671 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
6672 * @{
6673 */
6674
6675
6676 /* RTC - Register accessors */
6677 #define RTC_TSR_REG(base) ((base)->TSR)
6678 #define RTC_TPR_REG(base) ((base)->TPR)
6679 #define RTC_TAR_REG(base) ((base)->TAR)
6680 #define RTC_TCR_REG(base) ((base)->TCR)
6681 #define RTC_CR_REG(base) ((base)->CR)
6682 #define RTC_SR_REG(base) ((base)->SR)
6683 #define RTC_LR_REG(base) ((base)->LR)
6684 #define RTC_IER_REG(base) ((base)->IER)
6685
6686 /*!
6687 * @}
6688 */ /* end of group RTC_Register_Accessor_Macros */
6689
6690
6691 /* ----------------------------------------------------------------------------
6692 -- RTC Register Masks
6693 ---------------------------------------------------------------------------- */
6694
6695 /*!
6696 * @addtogroup RTC_Register_Masks RTC Register Masks
6697 * @{
6698 */
6699
6700 /* TSR Bit Fields */
6701 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
6702 #define RTC_TSR_TSR_SHIFT 0
6703 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
6704 /* TPR Bit Fields */
6705 #define RTC_TPR_TPR_MASK 0xFFFFu
6706 #define RTC_TPR_TPR_SHIFT 0
6707 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
6708 /* TAR Bit Fields */
6709 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
6710 #define RTC_TAR_TAR_SHIFT 0
6711 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
6712 /* TCR Bit Fields */
6713 #define RTC_TCR_TCR_MASK 0xFFu
6714 #define RTC_TCR_TCR_SHIFT 0
6715 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
6716 #define RTC_TCR_CIR_MASK 0xFF00u
6717 #define RTC_TCR_CIR_SHIFT 8
6718 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
6719 #define RTC_TCR_TCV_MASK 0xFF0000u
6720 #define RTC_TCR_TCV_SHIFT 16
6721 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
6722 #define RTC_TCR_CIC_MASK 0xFF000000u
6723 #define RTC_TCR_CIC_SHIFT 24
6724 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
6725 /* CR Bit Fields */
6726 #define RTC_CR_SWR_MASK 0x1u
6727 #define RTC_CR_SWR_SHIFT 0
6728 #define RTC_CR_WPE_MASK 0x2u
6729 #define RTC_CR_WPE_SHIFT 1
6730 #define RTC_CR_SUP_MASK 0x4u
6731 #define RTC_CR_SUP_SHIFT 2
6732 #define RTC_CR_UM_MASK 0x8u
6733 #define RTC_CR_UM_SHIFT 3
6734 #define RTC_CR_WPS_MASK 0x10u
6735 #define RTC_CR_WPS_SHIFT 4
6736 #define RTC_CR_OSCE_MASK 0x100u
6737 #define RTC_CR_OSCE_SHIFT 8
6738 #define RTC_CR_CLKO_MASK 0x200u
6739 #define RTC_CR_CLKO_SHIFT 9
6740 #define RTC_CR_SC16P_MASK 0x400u
6741 #define RTC_CR_SC16P_SHIFT 10
6742 #define RTC_CR_SC8P_MASK 0x800u
6743 #define RTC_CR_SC8P_SHIFT 11
6744 #define RTC_CR_SC4P_MASK 0x1000u
6745 #define RTC_CR_SC4P_SHIFT 12
6746 #define RTC_CR_SC2P_MASK 0x2000u
6747 #define RTC_CR_SC2P_SHIFT 13
6748 /* SR Bit Fields */
6749 #define RTC_SR_TIF_MASK 0x1u
6750 #define RTC_SR_TIF_SHIFT 0
6751 #define RTC_SR_TOF_MASK 0x2u
6752 #define RTC_SR_TOF_SHIFT 1
6753 #define RTC_SR_TAF_MASK 0x4u
6754 #define RTC_SR_TAF_SHIFT 2
6755 #define RTC_SR_TCE_MASK 0x10u
6756 #define RTC_SR_TCE_SHIFT 4
6757 /* LR Bit Fields */
6758 #define RTC_LR_TCL_MASK 0x8u
6759 #define RTC_LR_TCL_SHIFT 3
6760 #define RTC_LR_CRL_MASK 0x10u
6761 #define RTC_LR_CRL_SHIFT 4
6762 #define RTC_LR_SRL_MASK 0x20u
6763 #define RTC_LR_SRL_SHIFT 5
6764 #define RTC_LR_LRL_MASK 0x40u
6765 #define RTC_LR_LRL_SHIFT 6
6766 /* IER Bit Fields */
6767 #define RTC_IER_TIIE_MASK 0x1u
6768 #define RTC_IER_TIIE_SHIFT 0
6769 #define RTC_IER_TOIE_MASK 0x2u
6770 #define RTC_IER_TOIE_SHIFT 1
6771 #define RTC_IER_TAIE_MASK 0x4u
6772 #define RTC_IER_TAIE_SHIFT 2
6773 #define RTC_IER_TSIE_MASK 0x10u
6774 #define RTC_IER_TSIE_SHIFT 4
6775 #define RTC_IER_WPON_MASK 0x80u
6776 #define RTC_IER_WPON_SHIFT 7
6777
6778 /*!
6779 * @}
6780 */ /* end of group RTC_Register_Masks */
6781
6782
6783 /* RTC - Peripheral instance base addresses */
6784 /** Peripheral RTC base address */
6785 #define RTC_BASE (0x4003D000u)
6786 /** Peripheral RTC base pointer */
6787 #define RTC ((RTC_Type *)RTC_BASE)
6788 #define RTC_BASE_PTR (RTC)
6789 /** Array initializer of RTC peripheral base addresses */
6790 #define RTC_BASE_ADDRS { RTC_BASE }
6791 /** Array initializer of RTC peripheral base pointers */
6792 #define RTC_BASE_PTRS { RTC }
6793 /** Interrupt vectors for the RTC peripheral type */
6794 #define RTC_IRQS { RTC_IRQn }
6795 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
6796
6797 /* ----------------------------------------------------------------------------
6798 -- RTC - Register accessor macros
6799 ---------------------------------------------------------------------------- */
6800
6801 /*!
6802 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
6803 * @{
6804 */
6805
6806
6807 /* RTC - Register instance definitions */
6808 /* RTC */
6809 #define RTC_TSR RTC_TSR_REG(RTC)
6810 #define RTC_TPR RTC_TPR_REG(RTC)
6811 #define RTC_TAR RTC_TAR_REG(RTC)
6812 #define RTC_TCR RTC_TCR_REG(RTC)
6813 #define RTC_CR RTC_CR_REG(RTC)
6814 #define RTC_SR RTC_SR_REG(RTC)
6815 #define RTC_LR RTC_LR_REG(RTC)
6816 #define RTC_IER RTC_IER_REG(RTC)
6817
6818 /*!
6819 * @}
6820 */ /* end of group RTC_Register_Accessor_Macros */
6821
6822
6823 /*!
6824 * @}
6825 */ /* end of group RTC_Peripheral_Access_Layer */
6826
6827
6828 /* ----------------------------------------------------------------------------
6829 -- SIM Peripheral Access Layer
6830 ---------------------------------------------------------------------------- */
6831
6832 /*!
6833 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
6834 * @{
6835 */
6836
6837 /** SIM - Register Layout Typedef */
6838 typedef struct {
6839 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
6840 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
6841 uint8_t RESERVED_0[4092];
6842 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
6843 uint8_t RESERVED_1[4];
6844 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
6845 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
6846 uint8_t RESERVED_2[4];
6847 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
6848 uint8_t RESERVED_3[8];
6849 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
6850 uint8_t RESERVED_4[12];
6851 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
6852 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
6853 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
6854 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
6855 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
6856 uint8_t RESERVED_5[4];
6857 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
6858 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
6859 uint8_t RESERVED_6[4];
6860 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
6861 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
6862 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
6863 uint8_t RESERVED_7[156];
6864 __IO uint32_t COPC; /**< COP Control Register, offset: 0x1100 */
6865 __O uint32_t SRVCOP; /**< Service COP, offset: 0x1104 */
6866 } SIM_Type, *SIM_MemMapPtr;
6867
6868 /* ----------------------------------------------------------------------------
6869 -- SIM - Register accessor macros
6870 ---------------------------------------------------------------------------- */
6871
6872 /*!
6873 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
6874 * @{
6875 */
6876
6877
6878 /* SIM - Register accessors */
6879 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
6880 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
6881 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
6882 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
6883 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
6884 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
6885 #define SIM_SDID_REG(base) ((base)->SDID)
6886 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
6887 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
6888 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
6889 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
6890 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
6891 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
6892 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
6893 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
6894 #define SIM_UIDML_REG(base) ((base)->UIDML)
6895 #define SIM_UIDL_REG(base) ((base)->UIDL)
6896 #define SIM_COPC_REG(base) ((base)->COPC)
6897 #define SIM_SRVCOP_REG(base) ((base)->SRVCOP)
6898
6899 /*!
6900 * @}
6901 */ /* end of group SIM_Register_Accessor_Macros */
6902
6903
6904 /* ----------------------------------------------------------------------------
6905 -- SIM Register Masks
6906 ---------------------------------------------------------------------------- */
6907
6908 /*!
6909 * @addtogroup SIM_Register_Masks SIM Register Masks
6910 * @{
6911 */
6912
6913 /* SOPT1 Bit Fields */
6914 #define SIM_SOPT1_OSC32KOUT_MASK 0x30000u
6915 #define SIM_SOPT1_OSC32KOUT_SHIFT 16
6916 #define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KOUT_SHIFT))&SIM_SOPT1_OSC32KOUT_MASK)
6917 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
6918 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
6919 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
6920 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
6921 #define SIM_SOPT1_USBVSTBY_SHIFT 29
6922 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
6923 #define SIM_SOPT1_USBSSTBY_SHIFT 30
6924 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
6925 #define SIM_SOPT1_USBREGEN_SHIFT 31
6926 /* SOPT1CFG Bit Fields */
6927 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
6928 #define SIM_SOPT1CFG_URWE_SHIFT 24
6929 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
6930 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
6931 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
6932 #define SIM_SOPT1CFG_USSWE_SHIFT 26
6933 /* SOPT2 Bit Fields */
6934 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
6935 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
6936 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
6937 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
6938 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
6939 #define SIM_SOPT2_USBSRC_MASK 0x40000u
6940 #define SIM_SOPT2_USBSRC_SHIFT 18
6941 #define SIM_SOPT2_FLEXIOSRC_MASK 0xC00000u
6942 #define SIM_SOPT2_FLEXIOSRC_SHIFT 22
6943 #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FLEXIOSRC_SHIFT))&SIM_SOPT2_FLEXIOSRC_MASK)
6944 #define SIM_SOPT2_TPMSRC_MASK 0x3000000u
6945 #define SIM_SOPT2_TPMSRC_SHIFT 24
6946 #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
6947 #define SIM_SOPT2_LPUART0SRC_MASK 0xC000000u
6948 #define SIM_SOPT2_LPUART0SRC_SHIFT 26
6949 #define SIM_SOPT2_LPUART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART0SRC_SHIFT))&SIM_SOPT2_LPUART0SRC_MASK)
6950 #define SIM_SOPT2_LPUART1SRC_MASK 0x30000000u
6951 #define SIM_SOPT2_LPUART1SRC_SHIFT 28
6952 #define SIM_SOPT2_LPUART1SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_LPUART1SRC_SHIFT))&SIM_SOPT2_LPUART1SRC_MASK)
6953 /* SOPT4 Bit Fields */
6954 #define SIM_SOPT4_TPM1CH0SRC_MASK 0xC0000u
6955 #define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
6956 #define SIM_SOPT4_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_TPM1CH0SRC_SHIFT))&SIM_SOPT4_TPM1CH0SRC_MASK)
6957 #define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
6958 #define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
6959 #define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
6960 #define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
6961 #define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
6962 #define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
6963 #define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
6964 #define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
6965 /* SOPT5 Bit Fields */
6966 #define SIM_SOPT5_LPUART0TXSRC_MASK 0x3u
6967 #define SIM_SOPT5_LPUART0TXSRC_SHIFT 0
6968 #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART0TXSRC_SHIFT))&SIM_SOPT5_LPUART0TXSRC_MASK)
6969 #define SIM_SOPT5_LPUART0RXSRC_MASK 0x4u
6970 #define SIM_SOPT5_LPUART0RXSRC_SHIFT 2
6971 #define SIM_SOPT5_LPUART1TXSRC_MASK 0x30u
6972 #define SIM_SOPT5_LPUART1TXSRC_SHIFT 4
6973 #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_LPUART1TXSRC_SHIFT))&SIM_SOPT5_LPUART1TXSRC_MASK)
6974 #define SIM_SOPT5_LPUART1RXSRC_MASK 0x40u
6975 #define SIM_SOPT5_LPUART1RXSRC_SHIFT 6
6976 #define SIM_SOPT5_LPUART0ODE_MASK 0x10000u
6977 #define SIM_SOPT5_LPUART0ODE_SHIFT 16
6978 #define SIM_SOPT5_LPUART1ODE_MASK 0x20000u
6979 #define SIM_SOPT5_LPUART1ODE_SHIFT 17
6980 #define SIM_SOPT5_UART2ODE_MASK 0x40000u
6981 #define SIM_SOPT5_UART2ODE_SHIFT 18
6982 /* SOPT7 Bit Fields */
6983 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
6984 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
6985 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
6986 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
6987 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
6988 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
6989 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
6990 /* SDID Bit Fields */
6991 #define SIM_SDID_PINID_MASK 0xFu
6992 #define SIM_SDID_PINID_SHIFT 0
6993 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
6994 #define SIM_SDID_REVID_MASK 0xF000u
6995 #define SIM_SDID_REVID_SHIFT 12
6996 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
6997 #define SIM_SDID_SRAMSIZE_MASK 0xF0000u
6998 #define SIM_SDID_SRAMSIZE_SHIFT 16
6999 #define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
7000 #define SIM_SDID_SERIESID_MASK 0xF00000u
7001 #define SIM_SDID_SERIESID_SHIFT 20
7002 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
7003 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
7004 #define SIM_SDID_SUBFAMID_SHIFT 24
7005 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
7006 #define SIM_SDID_FAMID_MASK 0xF0000000u
7007 #define SIM_SDID_FAMID_SHIFT 28
7008 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
7009 /* SCGC4 Bit Fields */
7010 #define SIM_SCGC4_I2C0_MASK 0x40u
7011 #define SIM_SCGC4_I2C0_SHIFT 6
7012 #define SIM_SCGC4_I2C1_MASK 0x80u
7013 #define SIM_SCGC4_I2C1_SHIFT 7
7014 #define SIM_SCGC4_UART2_MASK 0x1000u
7015 #define SIM_SCGC4_UART2_SHIFT 12
7016 #define SIM_SCGC4_USBFS_MASK 0x40000u
7017 #define SIM_SCGC4_USBFS_SHIFT 18
7018 #define SIM_SCGC4_CMP0_MASK 0x80000u
7019 #define SIM_SCGC4_CMP0_SHIFT 19
7020 #define SIM_SCGC4_VREF_MASK 0x100000u
7021 #define SIM_SCGC4_VREF_SHIFT 20
7022 #define SIM_SCGC4_SPI0_MASK 0x400000u
7023 #define SIM_SCGC4_SPI0_SHIFT 22
7024 #define SIM_SCGC4_SPI1_MASK 0x800000u
7025 #define SIM_SCGC4_SPI1_SHIFT 23
7026 /* SCGC5 Bit Fields */
7027 #define SIM_SCGC5_LPTMR_MASK 0x1u
7028 #define SIM_SCGC5_LPTMR_SHIFT 0
7029 #define SIM_SCGC5_PORTA_MASK 0x200u
7030 #define SIM_SCGC5_PORTA_SHIFT 9
7031 #define SIM_SCGC5_PORTB_MASK 0x400u
7032 #define SIM_SCGC5_PORTB_SHIFT 10
7033 #define SIM_SCGC5_PORTC_MASK 0x800u
7034 #define SIM_SCGC5_PORTC_SHIFT 11
7035 #define SIM_SCGC5_PORTD_MASK 0x1000u
7036 #define SIM_SCGC5_PORTD_SHIFT 12
7037 #define SIM_SCGC5_PORTE_MASK 0x2000u
7038 #define SIM_SCGC5_PORTE_SHIFT 13
7039 #define SIM_SCGC5_SLCD_MASK 0x80000u
7040 #define SIM_SCGC5_SLCD_SHIFT 19
7041 #define SIM_SCGC5_LPUART0_MASK 0x100000u
7042 #define SIM_SCGC5_LPUART0_SHIFT 20
7043 #define SIM_SCGC5_LPUART1_MASK 0x200000u
7044 #define SIM_SCGC5_LPUART1_SHIFT 21
7045 #define SIM_SCGC5_FLEXIO_MASK 0x80000000u
7046 #define SIM_SCGC5_FLEXIO_SHIFT 31
7047 /* SCGC6 Bit Fields */
7048 #define SIM_SCGC6_FTF_MASK 0x1u
7049 #define SIM_SCGC6_FTF_SHIFT 0
7050 #define SIM_SCGC6_DMAMUX_MASK 0x2u
7051 #define SIM_SCGC6_DMAMUX_SHIFT 1
7052 #define SIM_SCGC6_I2S_MASK 0x8000u
7053 #define SIM_SCGC6_I2S_SHIFT 15
7054 #define SIM_SCGC6_PIT_MASK 0x800000u
7055 #define SIM_SCGC6_PIT_SHIFT 23
7056 #define SIM_SCGC6_TPM0_MASK 0x1000000u
7057 #define SIM_SCGC6_TPM0_SHIFT 24
7058 #define SIM_SCGC6_TPM1_MASK 0x2000000u
7059 #define SIM_SCGC6_TPM1_SHIFT 25
7060 #define SIM_SCGC6_TPM2_MASK 0x4000000u
7061 #define SIM_SCGC6_TPM2_SHIFT 26
7062 #define SIM_SCGC6_ADC0_MASK 0x8000000u
7063 #define SIM_SCGC6_ADC0_SHIFT 27
7064 #define SIM_SCGC6_RTC_MASK 0x20000000u
7065 #define SIM_SCGC6_RTC_SHIFT 29
7066 #define SIM_SCGC6_DAC0_MASK 0x80000000u
7067 #define SIM_SCGC6_DAC0_SHIFT 31
7068 /* SCGC7 Bit Fields */
7069 #define SIM_SCGC7_DMA_MASK 0x100u
7070 #define SIM_SCGC7_DMA_SHIFT 8
7071 /* CLKDIV1 Bit Fields */
7072 #define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
7073 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
7074 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
7075 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
7076 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
7077 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
7078 /* FCFG1 Bit Fields */
7079 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
7080 #define SIM_FCFG1_FLASHDIS_SHIFT 0
7081 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
7082 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
7083 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
7084 #define SIM_FCFG1_PFSIZE_SHIFT 24
7085 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
7086 /* FCFG2 Bit Fields */
7087 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
7088 #define SIM_FCFG2_MAXADDR1_SHIFT 16
7089 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
7090 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
7091 #define SIM_FCFG2_MAXADDR0_SHIFT 24
7092 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
7093 /* UIDMH Bit Fields */
7094 #define SIM_UIDMH_UID_MASK 0xFFFFu
7095 #define SIM_UIDMH_UID_SHIFT 0
7096 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
7097 /* UIDML Bit Fields */
7098 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
7099 #define SIM_UIDML_UID_SHIFT 0
7100 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
7101 /* UIDL Bit Fields */
7102 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
7103 #define SIM_UIDL_UID_SHIFT 0
7104 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
7105 /* COPC Bit Fields */
7106 #define SIM_COPC_COPW_MASK 0x1u
7107 #define SIM_COPC_COPW_SHIFT 0
7108 #define SIM_COPC_COPCLKS_MASK 0x2u
7109 #define SIM_COPC_COPCLKS_SHIFT 1
7110 #define SIM_COPC_COPT_MASK 0xCu
7111 #define SIM_COPC_COPT_SHIFT 2
7112 #define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
7113 #define SIM_COPC_COPSTPEN_MASK 0x10u
7114 #define SIM_COPC_COPSTPEN_SHIFT 4
7115 #define SIM_COPC_COPDBGEN_MASK 0x20u
7116 #define SIM_COPC_COPDBGEN_SHIFT 5
7117 #define SIM_COPC_COPCLKSEL_MASK 0xC0u
7118 #define SIM_COPC_COPCLKSEL_SHIFT 6
7119 #define SIM_COPC_COPCLKSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPCLKSEL_SHIFT))&SIM_COPC_COPCLKSEL_MASK)
7120 /* SRVCOP Bit Fields */
7121 #define SIM_SRVCOP_SRVCOP_MASK 0xFFu
7122 #define SIM_SRVCOP_SRVCOP_SHIFT 0
7123 #define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
7124
7125 /*!
7126 * @}
7127 */ /* end of group SIM_Register_Masks */
7128
7129
7130 /* SIM - Peripheral instance base addresses */
7131 /** Peripheral SIM base address */
7132 #define SIM_BASE (0x40047000u)
7133 /** Peripheral SIM base pointer */
7134 #define SIM ((SIM_Type *)SIM_BASE)
7135 #define SIM_BASE_PTR (SIM)
7136 /** Array initializer of SIM peripheral base addresses */
7137 #define SIM_BASE_ADDRS { SIM_BASE }
7138 /** Array initializer of SIM peripheral base pointers */
7139 #define SIM_BASE_PTRS { SIM }
7140
7141 /* ----------------------------------------------------------------------------
7142 -- SIM - Register accessor macros
7143 ---------------------------------------------------------------------------- */
7144
7145 /*!
7146 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
7147 * @{
7148 */
7149
7150
7151 /* SIM - Register instance definitions */
7152 /* SIM */
7153 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
7154 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
7155 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
7156 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
7157 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
7158 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
7159 #define SIM_SDID SIM_SDID_REG(SIM)
7160 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
7161 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
7162 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
7163 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
7164 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
7165 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
7166 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
7167 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
7168 #define SIM_UIDML SIM_UIDML_REG(SIM)
7169 #define SIM_UIDL SIM_UIDL_REG(SIM)
7170 #define SIM_COPC SIM_COPC_REG(SIM)
7171 #define SIM_SRVCOP SIM_SRVCOP_REG(SIM)
7172
7173 /*!
7174 * @}
7175 */ /* end of group SIM_Register_Accessor_Macros */
7176
7177
7178 /*!
7179 * @}
7180 */ /* end of group SIM_Peripheral_Access_Layer */
7181
7182
7183 /* ----------------------------------------------------------------------------
7184 -- SMC Peripheral Access Layer
7185 ---------------------------------------------------------------------------- */
7186
7187 /*!
7188 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
7189 * @{
7190 */
7191
7192 /** SMC - Register Layout Typedef */
7193 typedef struct {
7194 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
7195 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
7196 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
7197 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
7198 } SMC_Type, *SMC_MemMapPtr;
7199
7200 /* ----------------------------------------------------------------------------
7201 -- SMC - Register accessor macros
7202 ---------------------------------------------------------------------------- */
7203
7204 /*!
7205 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
7206 * @{
7207 */
7208
7209
7210 /* SMC - Register accessors */
7211 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
7212 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
7213 #define SMC_STOPCTRL_REG(base) ((base)->STOPCTRL)
7214 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
7215
7216 /*!
7217 * @}
7218 */ /* end of group SMC_Register_Accessor_Macros */
7219
7220
7221 /* ----------------------------------------------------------------------------
7222 -- SMC Register Masks
7223 ---------------------------------------------------------------------------- */
7224
7225 /*!
7226 * @addtogroup SMC_Register_Masks SMC Register Masks
7227 * @{
7228 */
7229
7230 /* PMPROT Bit Fields */
7231 #define SMC_PMPROT_AVLLS_MASK 0x2u
7232 #define SMC_PMPROT_AVLLS_SHIFT 1
7233 #define SMC_PMPROT_ALLS_MASK 0x8u
7234 #define SMC_PMPROT_ALLS_SHIFT 3
7235 #define SMC_PMPROT_AVLP_MASK 0x20u
7236 #define SMC_PMPROT_AVLP_SHIFT 5
7237 /* PMCTRL Bit Fields */
7238 #define SMC_PMCTRL_STOPM_MASK 0x7u
7239 #define SMC_PMCTRL_STOPM_SHIFT 0
7240 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
7241 #define SMC_PMCTRL_STOPA_MASK 0x8u
7242 #define SMC_PMCTRL_STOPA_SHIFT 3
7243 #define SMC_PMCTRL_RUNM_MASK 0x60u
7244 #define SMC_PMCTRL_RUNM_SHIFT 5
7245 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
7246 /* STOPCTRL Bit Fields */
7247 #define SMC_STOPCTRL_VLLSM_MASK 0x7u
7248 #define SMC_STOPCTRL_VLLSM_SHIFT 0
7249 #define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
7250 #define SMC_STOPCTRL_PORPO_MASK 0x20u
7251 #define SMC_STOPCTRL_PORPO_SHIFT 5
7252 #define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
7253 #define SMC_STOPCTRL_PSTOPO_SHIFT 6
7254 #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
7255 /* PMSTAT Bit Fields */
7256 #define SMC_PMSTAT_PMSTAT_MASK 0xFFu
7257 #define SMC_PMSTAT_PMSTAT_SHIFT 0
7258 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
7259
7260 /*!
7261 * @}
7262 */ /* end of group SMC_Register_Masks */
7263
7264
7265 /* SMC - Peripheral instance base addresses */
7266 /** Peripheral SMC base address */
7267 #define SMC_BASE (0x4007E000u)
7268 /** Peripheral SMC base pointer */
7269 #define SMC ((SMC_Type *)SMC_BASE)
7270 #define SMC_BASE_PTR (SMC)
7271 /** Array initializer of SMC peripheral base addresses */
7272 #define SMC_BASE_ADDRS { SMC_BASE }
7273 /** Array initializer of SMC peripheral base pointers */
7274 #define SMC_BASE_PTRS { SMC }
7275
7276 /* ----------------------------------------------------------------------------
7277 -- SMC - Register accessor macros
7278 ---------------------------------------------------------------------------- */
7279
7280 /*!
7281 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
7282 * @{
7283 */
7284
7285
7286 /* SMC - Register instance definitions */
7287 /* SMC */
7288 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
7289 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
7290 #define SMC_STOPCTRL SMC_STOPCTRL_REG(SMC)
7291 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
7292
7293 /*!
7294 * @}
7295 */ /* end of group SMC_Register_Accessor_Macros */
7296
7297
7298 /*!
7299 * @}
7300 */ /* end of group SMC_Peripheral_Access_Layer */
7301
7302
7303 /* ----------------------------------------------------------------------------
7304 -- SPI Peripheral Access Layer
7305 ---------------------------------------------------------------------------- */
7306
7307 /*!
7308 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
7309 * @{
7310 */
7311
7312 /** SPI - Register Layout Typedef */
7313 typedef struct {
7314 __I uint8_t S; /**< SPI Status Register, offset: 0x0 */
7315 __IO uint8_t BR; /**< SPI Baud Rate Register, offset: 0x1 */
7316 __IO uint8_t C2; /**< SPI Control Register 2, offset: 0x2 */
7317 __IO uint8_t C1; /**< SPI Control Register 1, offset: 0x3 */
7318 __IO uint8_t ML; /**< SPI Match Register low, offset: 0x4 */
7319 __IO uint8_t MH; /**< SPI match register high, offset: 0x5 */
7320 __IO uint8_t DL; /**< SPI Data Register low, offset: 0x6 */
7321 __IO uint8_t DH; /**< SPI data register high, offset: 0x7 */
7322 uint8_t RESERVED_0[2];
7323 __IO uint8_t CI; /**< SPI clear interrupt register, offset: 0xA */
7324 __IO uint8_t C3; /**< SPI control register 3, offset: 0xB */
7325 } SPI_Type, *SPI_MemMapPtr;
7326
7327 /* ----------------------------------------------------------------------------
7328 -- SPI - Register accessor macros
7329 ---------------------------------------------------------------------------- */
7330
7331 /*!
7332 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
7333 * @{
7334 */
7335
7336
7337 /* SPI - Register accessors */
7338 #define SPI_S_REG(base) ((base)->S)
7339 #define SPI_BR_REG(base) ((base)->BR)
7340 #define SPI_C2_REG(base) ((base)->C2)
7341 #define SPI_C1_REG(base) ((base)->C1)
7342 #define SPI_ML_REG(base) ((base)->ML)
7343 #define SPI_MH_REG(base) ((base)->MH)
7344 #define SPI_DL_REG(base) ((base)->DL)
7345 #define SPI_DH_REG(base) ((base)->DH)
7346 #define SPI_CI_REG(base) ((base)->CI)
7347 #define SPI_C3_REG(base) ((base)->C3)
7348
7349 /*!
7350 * @}
7351 */ /* end of group SPI_Register_Accessor_Macros */
7352
7353
7354 /* ----------------------------------------------------------------------------
7355 -- SPI Register Masks
7356 ---------------------------------------------------------------------------- */
7357
7358 /*!
7359 * @addtogroup SPI_Register_Masks SPI Register Masks
7360 * @{
7361 */
7362
7363 /* S Bit Fields */
7364 #define SPI_S_RFIFOEF_MASK 0x1u
7365 #define SPI_S_RFIFOEF_SHIFT 0
7366 #define SPI_S_TXFULLF_MASK 0x2u
7367 #define SPI_S_TXFULLF_SHIFT 1
7368 #define SPI_S_TNEAREF_MASK 0x4u
7369 #define SPI_S_TNEAREF_SHIFT 2
7370 #define SPI_S_RNFULLF_MASK 0x8u
7371 #define SPI_S_RNFULLF_SHIFT 3
7372 #define SPI_S_MODF_MASK 0x10u
7373 #define SPI_S_MODF_SHIFT 4
7374 #define SPI_S_SPTEF_MASK 0x20u
7375 #define SPI_S_SPTEF_SHIFT 5
7376 #define SPI_S_SPMF_MASK 0x40u
7377 #define SPI_S_SPMF_SHIFT 6
7378 #define SPI_S_SPRF_MASK 0x80u
7379 #define SPI_S_SPRF_SHIFT 7
7380 /* BR Bit Fields */
7381 #define SPI_BR_SPR_MASK 0xFu
7382 #define SPI_BR_SPR_SHIFT 0
7383 #define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
7384 #define SPI_BR_SPPR_MASK 0x70u
7385 #define SPI_BR_SPPR_SHIFT 4
7386 #define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
7387 /* C2 Bit Fields */
7388 #define SPI_C2_SPC0_MASK 0x1u
7389 #define SPI_C2_SPC0_SHIFT 0
7390 #define SPI_C2_SPISWAI_MASK 0x2u
7391 #define SPI_C2_SPISWAI_SHIFT 1
7392 #define SPI_C2_RXDMAE_MASK 0x4u
7393 #define SPI_C2_RXDMAE_SHIFT 2
7394 #define SPI_C2_BIDIROE_MASK 0x8u
7395 #define SPI_C2_BIDIROE_SHIFT 3
7396 #define SPI_C2_MODFEN_MASK 0x10u
7397 #define SPI_C2_MODFEN_SHIFT 4
7398 #define SPI_C2_TXDMAE_MASK 0x20u
7399 #define SPI_C2_TXDMAE_SHIFT 5
7400 #define SPI_C2_SPIMODE_MASK 0x40u
7401 #define SPI_C2_SPIMODE_SHIFT 6
7402 #define SPI_C2_SPMIE_MASK 0x80u
7403 #define SPI_C2_SPMIE_SHIFT 7
7404 /* C1 Bit Fields */
7405 #define SPI_C1_LSBFE_MASK 0x1u
7406 #define SPI_C1_LSBFE_SHIFT 0
7407 #define SPI_C1_SSOE_MASK 0x2u
7408 #define SPI_C1_SSOE_SHIFT 1
7409 #define SPI_C1_CPHA_MASK 0x4u
7410 #define SPI_C1_CPHA_SHIFT 2
7411 #define SPI_C1_CPOL_MASK 0x8u
7412 #define SPI_C1_CPOL_SHIFT 3
7413 #define SPI_C1_MSTR_MASK 0x10u
7414 #define SPI_C1_MSTR_SHIFT 4
7415 #define SPI_C1_SPTIE_MASK 0x20u
7416 #define SPI_C1_SPTIE_SHIFT 5
7417 #define SPI_C1_SPE_MASK 0x40u
7418 #define SPI_C1_SPE_SHIFT 6
7419 #define SPI_C1_SPIE_MASK 0x80u
7420 #define SPI_C1_SPIE_SHIFT 7
7421 /* ML Bit Fields */
7422 #define SPI_ML_Bits_MASK 0xFFu
7423 #define SPI_ML_Bits_SHIFT 0
7424 #define SPI_ML_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_ML_Bits_SHIFT))&SPI_ML_Bits_MASK)
7425 /* MH Bit Fields */
7426 #define SPI_MH_Bits_MASK 0xFFu
7427 #define SPI_MH_Bits_SHIFT 0
7428 #define SPI_MH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_MH_Bits_SHIFT))&SPI_MH_Bits_MASK)
7429 /* DL Bit Fields */
7430 #define SPI_DL_Bits_MASK 0xFFu
7431 #define SPI_DL_Bits_SHIFT 0
7432 #define SPI_DL_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DL_Bits_SHIFT))&SPI_DL_Bits_MASK)
7433 /* DH Bit Fields */
7434 #define SPI_DH_Bits_MASK 0xFFu
7435 #define SPI_DH_Bits_SHIFT 0
7436 #define SPI_DH_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_DH_Bits_SHIFT))&SPI_DH_Bits_MASK)
7437 /* CI Bit Fields */
7438 #define SPI_CI_SPRFCI_MASK 0x1u
7439 #define SPI_CI_SPRFCI_SHIFT 0
7440 #define SPI_CI_SPTEFCI_MASK 0x2u
7441 #define SPI_CI_SPTEFCI_SHIFT 1
7442 #define SPI_CI_RNFULLFCI_MASK 0x4u
7443 #define SPI_CI_RNFULLFCI_SHIFT 2
7444 #define SPI_CI_TNEAREFCI_MASK 0x8u
7445 #define SPI_CI_TNEAREFCI_SHIFT 3
7446 #define SPI_CI_RXFOF_MASK 0x10u
7447 #define SPI_CI_RXFOF_SHIFT 4
7448 #define SPI_CI_TXFOF_MASK 0x20u
7449 #define SPI_CI_TXFOF_SHIFT 5
7450 #define SPI_CI_RXFERR_MASK 0x40u
7451 #define SPI_CI_RXFERR_SHIFT 6
7452 #define SPI_CI_TXFERR_MASK 0x80u
7453 #define SPI_CI_TXFERR_SHIFT 7
7454 /* C3 Bit Fields */
7455 #define SPI_C3_FIFOMODE_MASK 0x1u
7456 #define SPI_C3_FIFOMODE_SHIFT 0
7457 #define SPI_C3_RNFULLIEN_MASK 0x2u
7458 #define SPI_C3_RNFULLIEN_SHIFT 1
7459 #define SPI_C3_TNEARIEN_MASK 0x4u
7460 #define SPI_C3_TNEARIEN_SHIFT 2
7461 #define SPI_C3_INTCLR_MASK 0x8u
7462 #define SPI_C3_INTCLR_SHIFT 3
7463 #define SPI_C3_RNFULLF_MARK_MASK 0x10u
7464 #define SPI_C3_RNFULLF_MARK_SHIFT 4
7465 #define SPI_C3_TNEAREF_MARK_MASK 0x20u
7466 #define SPI_C3_TNEAREF_MARK_SHIFT 5
7467
7468 /*!
7469 * @}
7470 */ /* end of group SPI_Register_Masks */
7471
7472
7473 /* SPI - Peripheral instance base addresses */
7474 /** Peripheral SPI0 base address */
7475 #define SPI0_BASE (0x40076000u)
7476 /** Peripheral SPI0 base pointer */
7477 #define SPI0 ((SPI_Type *)SPI0_BASE)
7478 #define SPI0_BASE_PTR (SPI0)
7479 /** Peripheral SPI1 base address */
7480 #define SPI1_BASE (0x40077000u)
7481 /** Peripheral SPI1 base pointer */
7482 #define SPI1 ((SPI_Type *)SPI1_BASE)
7483 #define SPI1_BASE_PTR (SPI1)
7484 /** Array initializer of SPI peripheral base addresses */
7485 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
7486 /** Array initializer of SPI peripheral base pointers */
7487 #define SPI_BASE_PTRS { SPI0, SPI1 }
7488 /** Interrupt vectors for the SPI peripheral type */
7489 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
7490
7491 /* ----------------------------------------------------------------------------
7492 -- SPI - Register accessor macros
7493 ---------------------------------------------------------------------------- */
7494
7495 /*!
7496 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
7497 * @{
7498 */
7499
7500
7501 /* SPI - Register instance definitions */
7502 /* SPI0 */
7503 #define SPI0_S SPI_S_REG(SPI0)
7504 #define SPI0_BR SPI_BR_REG(SPI0)
7505 #define SPI0_C2 SPI_C2_REG(SPI0)
7506 #define SPI0_C1 SPI_C1_REG(SPI0)
7507 #define SPI0_ML SPI_ML_REG(SPI0)
7508 #define SPI0_MH SPI_MH_REG(SPI0)
7509 #define SPI0_DL SPI_DL_REG(SPI0)
7510 #define SPI0_DH SPI_DH_REG(SPI0)
7511 /* SPI1 */
7512 #define SPI1_S SPI_S_REG(SPI1)
7513 #define SPI1_BR SPI_BR_REG(SPI1)
7514 #define SPI1_C2 SPI_C2_REG(SPI1)
7515 #define SPI1_C1 SPI_C1_REG(SPI1)
7516 #define SPI1_ML SPI_ML_REG(SPI1)
7517 #define SPI1_MH SPI_MH_REG(SPI1)
7518 #define SPI1_DL SPI_DL_REG(SPI1)
7519 #define SPI1_DH SPI_DH_REG(SPI1)
7520 #define SPI1_CI SPI_CI_REG(SPI1)
7521 #define SPI1_C3 SPI_C3_REG(SPI1)
7522
7523 /*!
7524 * @}
7525 */ /* end of group SPI_Register_Accessor_Macros */
7526
7527
7528 /*!
7529 * @}
7530 */ /* end of group SPI_Peripheral_Access_Layer */
7531
7532
7533 /* ----------------------------------------------------------------------------
7534 -- TPM Peripheral Access Layer
7535 ---------------------------------------------------------------------------- */
7536
7537 /*!
7538 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
7539 * @{
7540 */
7541
7542 /** TPM - Register Layout Typedef */
7543 typedef struct {
7544 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
7545 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
7546 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
7547 struct { /* offset: 0xC, array step: 0x8 */
7548 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
7549 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
7550 } CONTROLS[6];
7551 uint8_t RESERVED_0[20];
7552 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
7553 uint8_t RESERVED_1[28];
7554 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
7555 uint8_t RESERVED_2[16];
7556 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
7557 } TPM_Type, *TPM_MemMapPtr;
7558
7559 /* ----------------------------------------------------------------------------
7560 -- TPM - Register accessor macros
7561 ---------------------------------------------------------------------------- */
7562
7563 /*!
7564 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
7565 * @{
7566 */
7567
7568
7569 /* TPM - Register accessors */
7570 #define TPM_SC_REG(base) ((base)->SC)
7571 #define TPM_CNT_REG(base) ((base)->CNT)
7572 #define TPM_MOD_REG(base) ((base)->MOD)
7573 #define TPM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
7574 #define TPM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
7575 #define TPM_STATUS_REG(base) ((base)->STATUS)
7576 #define TPM_POL_REG(base) ((base)->POL)
7577 #define TPM_CONF_REG(base) ((base)->CONF)
7578
7579 /*!
7580 * @}
7581 */ /* end of group TPM_Register_Accessor_Macros */
7582
7583
7584 /* ----------------------------------------------------------------------------
7585 -- TPM Register Masks
7586 ---------------------------------------------------------------------------- */
7587
7588 /*!
7589 * @addtogroup TPM_Register_Masks TPM Register Masks
7590 * @{
7591 */
7592
7593 /* SC Bit Fields */
7594 #define TPM_SC_PS_MASK 0x7u
7595 #define TPM_SC_PS_SHIFT 0
7596 #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
7597 #define TPM_SC_CMOD_MASK 0x18u
7598 #define TPM_SC_CMOD_SHIFT 3
7599 #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
7600 #define TPM_SC_CPWMS_MASK 0x20u
7601 #define TPM_SC_CPWMS_SHIFT 5
7602 #define TPM_SC_TOIE_MASK 0x40u
7603 #define TPM_SC_TOIE_SHIFT 6
7604 #define TPM_SC_TOF_MASK 0x80u
7605 #define TPM_SC_TOF_SHIFT 7
7606 #define TPM_SC_DMA_MASK 0x100u
7607 #define TPM_SC_DMA_SHIFT 8
7608 /* CNT Bit Fields */
7609 #define TPM_CNT_COUNT_MASK 0xFFFFu
7610 #define TPM_CNT_COUNT_SHIFT 0
7611 #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
7612 /* MOD Bit Fields */
7613 #define TPM_MOD_MOD_MASK 0xFFFFu
7614 #define TPM_MOD_MOD_SHIFT 0
7615 #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
7616 /* CnSC Bit Fields */
7617 #define TPM_CnSC_DMA_MASK 0x1u
7618 #define TPM_CnSC_DMA_SHIFT 0
7619 #define TPM_CnSC_ELSA_MASK 0x4u
7620 #define TPM_CnSC_ELSA_SHIFT 2
7621 #define TPM_CnSC_ELSB_MASK 0x8u
7622 #define TPM_CnSC_ELSB_SHIFT 3
7623 #define TPM_CnSC_MSA_MASK 0x10u
7624 #define TPM_CnSC_MSA_SHIFT 4
7625 #define TPM_CnSC_MSB_MASK 0x20u
7626 #define TPM_CnSC_MSB_SHIFT 5
7627 #define TPM_CnSC_CHIE_MASK 0x40u
7628 #define TPM_CnSC_CHIE_SHIFT 6
7629 #define TPM_CnSC_CHF_MASK 0x80u
7630 #define TPM_CnSC_CHF_SHIFT 7
7631 /* CnV Bit Fields */
7632 #define TPM_CnV_VAL_MASK 0xFFFFu
7633 #define TPM_CnV_VAL_SHIFT 0
7634 #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
7635 /* STATUS Bit Fields */
7636 #define TPM_STATUS_CH0F_MASK 0x1u
7637 #define TPM_STATUS_CH0F_SHIFT 0
7638 #define TPM_STATUS_CH1F_MASK 0x2u
7639 #define TPM_STATUS_CH1F_SHIFT 1
7640 #define TPM_STATUS_CH2F_MASK 0x4u
7641 #define TPM_STATUS_CH2F_SHIFT 2
7642 #define TPM_STATUS_CH3F_MASK 0x8u
7643 #define TPM_STATUS_CH3F_SHIFT 3
7644 #define TPM_STATUS_CH4F_MASK 0x10u
7645 #define TPM_STATUS_CH4F_SHIFT 4
7646 #define TPM_STATUS_CH5F_MASK 0x20u
7647 #define TPM_STATUS_CH5F_SHIFT 5
7648 #define TPM_STATUS_TOF_MASK 0x100u
7649 #define TPM_STATUS_TOF_SHIFT 8
7650 /* POL Bit Fields */
7651 #define TPM_POL_POL0_MASK 0x1u
7652 #define TPM_POL_POL0_SHIFT 0
7653 #define TPM_POL_POL1_MASK 0x2u
7654 #define TPM_POL_POL1_SHIFT 1
7655 #define TPM_POL_POL2_MASK 0x4u
7656 #define TPM_POL_POL2_SHIFT 2
7657 #define TPM_POL_POL3_MASK 0x8u
7658 #define TPM_POL_POL3_SHIFT 3
7659 #define TPM_POL_POL4_MASK 0x10u
7660 #define TPM_POL_POL4_SHIFT 4
7661 #define TPM_POL_POL5_MASK 0x20u
7662 #define TPM_POL_POL5_SHIFT 5
7663 /* CONF Bit Fields */
7664 #define TPM_CONF_DOZEEN_MASK 0x20u
7665 #define TPM_CONF_DOZEEN_SHIFT 5
7666 #define TPM_CONF_DBGMODE_MASK 0xC0u
7667 #define TPM_CONF_DBGMODE_SHIFT 6
7668 #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
7669 #define TPM_CONF_GTBSYNC_MASK 0x100u
7670 #define TPM_CONF_GTBSYNC_SHIFT 8
7671 #define TPM_CONF_GTBEEN_MASK 0x200u
7672 #define TPM_CONF_GTBEEN_SHIFT 9
7673 #define TPM_CONF_CSOT_MASK 0x10000u
7674 #define TPM_CONF_CSOT_SHIFT 16
7675 #define TPM_CONF_CSOO_MASK 0x20000u
7676 #define TPM_CONF_CSOO_SHIFT 17
7677 #define TPM_CONF_CROT_MASK 0x40000u
7678 #define TPM_CONF_CROT_SHIFT 18
7679 #define TPM_CONF_CPOT_MASK 0x80000u
7680 #define TPM_CONF_CPOT_SHIFT 19
7681 #define TPM_CONF_TRGPOL_MASK 0x400000u
7682 #define TPM_CONF_TRGPOL_SHIFT 22
7683 #define TPM_CONF_TRGSRC_MASK 0x800000u
7684 #define TPM_CONF_TRGSRC_SHIFT 23
7685 #define TPM_CONF_TRGSEL_MASK 0xF000000u
7686 #define TPM_CONF_TRGSEL_SHIFT 24
7687 #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
7688
7689 /*!
7690 * @}
7691 */ /* end of group TPM_Register_Masks */
7692
7693
7694 /* TPM - Peripheral instance base addresses */
7695 /** Peripheral TPM0 base address */
7696 #define TPM0_BASE (0x40038000u)
7697 /** Peripheral TPM0 base pointer */
7698 #define TPM0 ((TPM_Type *)TPM0_BASE)
7699 #define TPM0_BASE_PTR (TPM0)
7700 /** Peripheral TPM1 base address */
7701 #define TPM1_BASE (0x40039000u)
7702 /** Peripheral TPM1 base pointer */
7703 #define TPM1 ((TPM_Type *)TPM1_BASE)
7704 #define TPM1_BASE_PTR (TPM1)
7705 /** Peripheral TPM2 base address */
7706 #define TPM2_BASE (0x4003A000u)
7707 /** Peripheral TPM2 base pointer */
7708 #define TPM2 ((TPM_Type *)TPM2_BASE)
7709 #define TPM2_BASE_PTR (TPM2)
7710 /** Array initializer of TPM peripheral base addresses */
7711 #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE }
7712 /** Array initializer of TPM peripheral base pointers */
7713 #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 }
7714 /** Interrupt vectors for the TPM peripheral type */
7715 #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn }
7716
7717 /* ----------------------------------------------------------------------------
7718 -- TPM - Register accessor macros
7719 ---------------------------------------------------------------------------- */
7720
7721 /*!
7722 * @addtogroup TPM_Register_Accessor_Macros TPM - Register accessor macros
7723 * @{
7724 */
7725
7726
7727 /* TPM - Register instance definitions */
7728 /* TPM0 */
7729 #define TPM0_SC TPM_SC_REG(TPM0)
7730 #define TPM0_CNT TPM_CNT_REG(TPM0)
7731 #define TPM0_MOD TPM_MOD_REG(TPM0)
7732 #define TPM0_C0SC TPM_CnSC_REG(TPM0,0)
7733 #define TPM0_C0V TPM_CnV_REG(TPM0,0)
7734 #define TPM0_C1SC TPM_CnSC_REG(TPM0,1)
7735 #define TPM0_C1V TPM_CnV_REG(TPM0,1)
7736 #define TPM0_C2SC TPM_CnSC_REG(TPM0,2)
7737 #define TPM0_C2V TPM_CnV_REG(TPM0,2)
7738 #define TPM0_C3SC TPM_CnSC_REG(TPM0,3)
7739 #define TPM0_C3V TPM_CnV_REG(TPM0,3)
7740 #define TPM0_C4SC TPM_CnSC_REG(TPM0,4)
7741 #define TPM0_C4V TPM_CnV_REG(TPM0,4)
7742 #define TPM0_C5SC TPM_CnSC_REG(TPM0,5)
7743 #define TPM0_C5V TPM_CnV_REG(TPM0,5)
7744 #define TPM0_STATUS TPM_STATUS_REG(TPM0)
7745 #define TPM0_POL TPM_POL_REG(TPM0)
7746 #define TPM0_CONF TPM_CONF_REG(TPM0)
7747 /* TPM1 */
7748 #define TPM1_SC TPM_SC_REG(TPM1)
7749 #define TPM1_CNT TPM_CNT_REG(TPM1)
7750 #define TPM1_MOD TPM_MOD_REG(TPM1)
7751 #define TPM1_C0SC TPM_CnSC_REG(TPM1,0)
7752 #define TPM1_C0V TPM_CnV_REG(TPM1,0)
7753 #define TPM1_C1SC TPM_CnSC_REG(TPM1,1)
7754 #define TPM1_C1V TPM_CnV_REG(TPM1,1)
7755 #define TPM1_STATUS TPM_STATUS_REG(TPM1)
7756 #define TPM1_POL TPM_POL_REG(TPM1)
7757 #define TPM1_CONF TPM_CONF_REG(TPM1)
7758 /* TPM2 */
7759 #define TPM2_SC TPM_SC_REG(TPM2)
7760 #define TPM2_CNT TPM_CNT_REG(TPM2)
7761 #define TPM2_MOD TPM_MOD_REG(TPM2)
7762 #define TPM2_C0SC TPM_CnSC_REG(TPM2,0)
7763 #define TPM2_C0V TPM_CnV_REG(TPM2,0)
7764 #define TPM2_C1SC TPM_CnSC_REG(TPM2,1)
7765 #define TPM2_C1V TPM_CnV_REG(TPM2,1)
7766 #define TPM2_STATUS TPM_STATUS_REG(TPM2)
7767 #define TPM2_POL TPM_POL_REG(TPM2)
7768 #define TPM2_CONF TPM_CONF_REG(TPM2)
7769
7770 /* TPM - Register array accessors */
7771 #define TPM0_CnSC(index) TPM_CnSC_REG(TPM0,index)
7772 #define TPM1_CnSC(index) TPM_CnSC_REG(TPM1,index)
7773 #define TPM2_CnSC(index) TPM_CnSC_REG(TPM2,index)
7774 #define TPM0_CnV(index) TPM_CnV_REG(TPM0,index)
7775 #define TPM1_CnV(index) TPM_CnV_REG(TPM1,index)
7776 #define TPM2_CnV(index) TPM_CnV_REG(TPM2,index)
7777
7778 /*!
7779 * @}
7780 */ /* end of group TPM_Register_Accessor_Macros */
7781
7782
7783 /*!
7784 * @}
7785 */ /* end of group TPM_Peripheral_Access_Layer */
7786
7787
7788 /* ----------------------------------------------------------------------------
7789 -- UART Peripheral Access Layer
7790 ---------------------------------------------------------------------------- */
7791
7792 /*!
7793 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
7794 * @{
7795 */
7796
7797 /** UART - Register Layout Typedef */
7798 typedef struct {
7799 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
7800 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
7801 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
7802 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
7803 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
7804 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
7805 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
7806 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
7807 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
7808 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
7809 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
7810 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
7811 uint8_t RESERVED_0[12];
7812 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
7813 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
7814 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
7815 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
7816 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
7817 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
7818 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
7819 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
7820 uint8_t RESERVED_1[26];
7821 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
7822 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
7823 union { /* offset: 0x3C */
7824 struct { /* offset: 0x3C */
7825 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
7826 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
7827 } TYPE0;
7828 struct { /* offset: 0x3C */
7829 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
7830 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
7831 } TYPE1;
7832 };
7833 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
7834 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
7835 } UART_Type, *UART_MemMapPtr;
7836
7837 /* ----------------------------------------------------------------------------
7838 -- UART - Register accessor macros
7839 ---------------------------------------------------------------------------- */
7840
7841 /*!
7842 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
7843 * @{
7844 */
7845
7846
7847 /* UART - Register accessors */
7848 #define UART_BDH_REG(base) ((base)->BDH)
7849 #define UART_BDL_REG(base) ((base)->BDL)
7850 #define UART_C1_REG(base) ((base)->C1)
7851 #define UART_C2_REG(base) ((base)->C2)
7852 #define UART_S1_REG(base) ((base)->S1)
7853 #define UART_S2_REG(base) ((base)->S2)
7854 #define UART_C3_REG(base) ((base)->C3)
7855 #define UART_D_REG(base) ((base)->D)
7856 #define UART_MA1_REG(base) ((base)->MA1)
7857 #define UART_MA2_REG(base) ((base)->MA2)
7858 #define UART_C4_REG(base) ((base)->C4)
7859 #define UART_C5_REG(base) ((base)->C5)
7860 #define UART_C7816_REG(base) ((base)->C7816)
7861 #define UART_IE7816_REG(base) ((base)->IE7816)
7862 #define UART_IS7816_REG(base) ((base)->IS7816)
7863 #define UART_WP7816_REG(base) ((base)->WP7816)
7864 #define UART_WN7816_REG(base) ((base)->WN7816)
7865 #define UART_WF7816_REG(base) ((base)->WF7816)
7866 #define UART_ET7816_REG(base) ((base)->ET7816)
7867 #define UART_TL7816_REG(base) ((base)->TL7816)
7868 #define UART_AP7816A_T0_REG(base) ((base)->AP7816A_T0)
7869 #define UART_AP7816B_T0_REG(base) ((base)->AP7816B_T0)
7870 #define UART_WP7816A_T0_REG(base) ((base)->TYPE0.WP7816A_T0)
7871 #define UART_WP7816B_T0_REG(base) ((base)->TYPE0.WP7816B_T0)
7872 #define UART_WP7816A_T1_REG(base) ((base)->TYPE1.WP7816A_T1)
7873 #define UART_WP7816B_T1_REG(base) ((base)->TYPE1.WP7816B_T1)
7874 #define UART_WGP7816_T1_REG(base) ((base)->WGP7816_T1)
7875 #define UART_WP7816C_T1_REG(base) ((base)->WP7816C_T1)
7876
7877 /*!
7878 * @}
7879 */ /* end of group UART_Register_Accessor_Macros */
7880
7881
7882 /* ----------------------------------------------------------------------------
7883 -- UART Register Masks
7884 ---------------------------------------------------------------------------- */
7885
7886 /*!
7887 * @addtogroup UART_Register_Masks UART Register Masks
7888 * @{
7889 */
7890
7891 /* BDH Bit Fields */
7892 #define UART_BDH_SBR_MASK 0x1Fu
7893 #define UART_BDH_SBR_SHIFT 0
7894 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
7895 #define UART_BDH_RXEDGIE_MASK 0x40u
7896 #define UART_BDH_RXEDGIE_SHIFT 6
7897 /* BDL Bit Fields */
7898 #define UART_BDL_SBR_MASK 0xFFu
7899 #define UART_BDL_SBR_SHIFT 0
7900 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
7901 /* C1 Bit Fields */
7902 #define UART_C1_PT_MASK 0x1u
7903 #define UART_C1_PT_SHIFT 0
7904 #define UART_C1_PE_MASK 0x2u
7905 #define UART_C1_PE_SHIFT 1
7906 #define UART_C1_ILT_MASK 0x4u
7907 #define UART_C1_ILT_SHIFT 2
7908 #define UART_C1_WAKE_MASK 0x8u
7909 #define UART_C1_WAKE_SHIFT 3
7910 #define UART_C1_M_MASK 0x10u
7911 #define UART_C1_M_SHIFT 4
7912 #define UART_C1_RSRC_MASK 0x20u
7913 #define UART_C1_RSRC_SHIFT 5
7914 #define UART_C1_LOOPS_MASK 0x80u
7915 #define UART_C1_LOOPS_SHIFT 7
7916 /* C2 Bit Fields */
7917 #define UART_C2_SBK_MASK 0x1u
7918 #define UART_C2_SBK_SHIFT 0
7919 #define UART_C2_RWU_MASK 0x2u
7920 #define UART_C2_RWU_SHIFT 1
7921 #define UART_C2_RE_MASK 0x4u
7922 #define UART_C2_RE_SHIFT 2
7923 #define UART_C2_TE_MASK 0x8u
7924 #define UART_C2_TE_SHIFT 3
7925 #define UART_C2_ILIE_MASK 0x10u
7926 #define UART_C2_ILIE_SHIFT 4
7927 #define UART_C2_RIE_MASK 0x20u
7928 #define UART_C2_RIE_SHIFT 5
7929 #define UART_C2_TCIE_MASK 0x40u
7930 #define UART_C2_TCIE_SHIFT 6
7931 #define UART_C2_TIE_MASK 0x80u
7932 #define UART_C2_TIE_SHIFT 7
7933 /* S1 Bit Fields */
7934 #define UART_S1_PF_MASK 0x1u
7935 #define UART_S1_PF_SHIFT 0
7936 #define UART_S1_FE_MASK 0x2u
7937 #define UART_S1_FE_SHIFT 1
7938 #define UART_S1_NF_MASK 0x4u
7939 #define UART_S1_NF_SHIFT 2
7940 #define UART_S1_OR_MASK 0x8u
7941 #define UART_S1_OR_SHIFT 3
7942 #define UART_S1_IDLE_MASK 0x10u
7943 #define UART_S1_IDLE_SHIFT 4
7944 #define UART_S1_RDRF_MASK 0x20u
7945 #define UART_S1_RDRF_SHIFT 5
7946 #define UART_S1_TC_MASK 0x40u
7947 #define UART_S1_TC_SHIFT 6
7948 #define UART_S1_TDRE_MASK 0x80u
7949 #define UART_S1_TDRE_SHIFT 7
7950 /* S2 Bit Fields */
7951 #define UART_S2_RAF_MASK 0x1u
7952 #define UART_S2_RAF_SHIFT 0
7953 #define UART_S2_BRK13_MASK 0x4u
7954 #define UART_S2_BRK13_SHIFT 2
7955 #define UART_S2_RWUID_MASK 0x8u
7956 #define UART_S2_RWUID_SHIFT 3
7957 #define UART_S2_RXINV_MASK 0x10u
7958 #define UART_S2_RXINV_SHIFT 4
7959 #define UART_S2_MSBF_MASK 0x20u
7960 #define UART_S2_MSBF_SHIFT 5
7961 #define UART_S2_RXEDGIF_MASK 0x40u
7962 #define UART_S2_RXEDGIF_SHIFT 6
7963 /* C3 Bit Fields */
7964 #define UART_C3_PEIE_MASK 0x1u
7965 #define UART_C3_PEIE_SHIFT 0
7966 #define UART_C3_FEIE_MASK 0x2u
7967 #define UART_C3_FEIE_SHIFT 1
7968 #define UART_C3_NEIE_MASK 0x4u
7969 #define UART_C3_NEIE_SHIFT 2
7970 #define UART_C3_ORIE_MASK 0x8u
7971 #define UART_C3_ORIE_SHIFT 3
7972 #define UART_C3_TXINV_MASK 0x10u
7973 #define UART_C3_TXINV_SHIFT 4
7974 #define UART_C3_TXDIR_MASK 0x20u
7975 #define UART_C3_TXDIR_SHIFT 5
7976 #define UART_C3_T8_MASK 0x40u
7977 #define UART_C3_T8_SHIFT 6
7978 #define UART_C3_R8_MASK 0x80u
7979 #define UART_C3_R8_SHIFT 7
7980 /* D Bit Fields */
7981 #define UART_D_RT_MASK 0xFFu
7982 #define UART_D_RT_SHIFT 0
7983 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
7984 /* MA1 Bit Fields */
7985 #define UART_MA1_MA_MASK 0xFFu
7986 #define UART_MA1_MA_SHIFT 0
7987 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
7988 /* MA2 Bit Fields */
7989 #define UART_MA2_MA_MASK 0xFFu
7990 #define UART_MA2_MA_SHIFT 0
7991 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
7992 /* C4 Bit Fields */
7993 #define UART_C4_BRFA_MASK 0x1Fu
7994 #define UART_C4_BRFA_SHIFT 0
7995 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
7996 #define UART_C4_M10_MASK 0x20u
7997 #define UART_C4_M10_SHIFT 5
7998 #define UART_C4_MAEN2_MASK 0x40u
7999 #define UART_C4_MAEN2_SHIFT 6
8000 #define UART_C4_MAEN1_MASK 0x80u
8001 #define UART_C4_MAEN1_SHIFT 7
8002 /* C5 Bit Fields */
8003 #define UART_C5_RDMAS_MASK 0x20u
8004 #define UART_C5_RDMAS_SHIFT 5
8005 #define UART_C5_TDMAS_MASK 0x80u
8006 #define UART_C5_TDMAS_SHIFT 7
8007 /* C7816 Bit Fields */
8008 #define UART_C7816_ISO_7816E_MASK 0x1u
8009 #define UART_C7816_ISO_7816E_SHIFT 0
8010 #define UART_C7816_TTYPE_MASK 0x2u
8011 #define UART_C7816_TTYPE_SHIFT 1
8012 #define UART_C7816_INIT_MASK 0x4u
8013 #define UART_C7816_INIT_SHIFT 2
8014 #define UART_C7816_ANACK_MASK 0x8u
8015 #define UART_C7816_ANACK_SHIFT 3
8016 #define UART_C7816_ONACK_MASK 0x10u
8017 #define UART_C7816_ONACK_SHIFT 4
8018 /* IE7816 Bit Fields */
8019 #define UART_IE7816_RXTE_MASK 0x1u
8020 #define UART_IE7816_RXTE_SHIFT 0
8021 #define UART_IE7816_TXTE_MASK 0x2u
8022 #define UART_IE7816_TXTE_SHIFT 1
8023 #define UART_IE7816_GTVE_MASK 0x4u
8024 #define UART_IE7816_GTVE_SHIFT 2
8025 #define UART_IE7816_ADTE_MASK 0x8u
8026 #define UART_IE7816_ADTE_SHIFT 3
8027 #define UART_IE7816_INITDE_MASK 0x10u
8028 #define UART_IE7816_INITDE_SHIFT 4
8029 #define UART_IE7816_BWTE_MASK 0x20u
8030 #define UART_IE7816_BWTE_SHIFT 5
8031 #define UART_IE7816_CWTE_MASK 0x40u
8032 #define UART_IE7816_CWTE_SHIFT 6
8033 #define UART_IE7816_WTE_MASK 0x80u
8034 #define UART_IE7816_WTE_SHIFT 7
8035 /* IS7816 Bit Fields */
8036 #define UART_IS7816_RXT_MASK 0x1u
8037 #define UART_IS7816_RXT_SHIFT 0
8038 #define UART_IS7816_TXT_MASK 0x2u
8039 #define UART_IS7816_TXT_SHIFT 1
8040 #define UART_IS7816_GTV_MASK 0x4u
8041 #define UART_IS7816_GTV_SHIFT 2
8042 #define UART_IS7816_ADT_MASK 0x8u
8043 #define UART_IS7816_ADT_SHIFT 3
8044 #define UART_IS7816_INITD_MASK 0x10u
8045 #define UART_IS7816_INITD_SHIFT 4
8046 #define UART_IS7816_BWT_MASK 0x20u
8047 #define UART_IS7816_BWT_SHIFT 5
8048 #define UART_IS7816_CWT_MASK 0x40u
8049 #define UART_IS7816_CWT_SHIFT 6
8050 #define UART_IS7816_WT_MASK 0x80u
8051 #define UART_IS7816_WT_SHIFT 7
8052 /* WP7816 Bit Fields */
8053 #define UART_WP7816_WTX_MASK 0xFFu
8054 #define UART_WP7816_WTX_SHIFT 0
8055 #define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816_WTX_SHIFT))&UART_WP7816_WTX_MASK)
8056 /* WN7816 Bit Fields */
8057 #define UART_WN7816_GTN_MASK 0xFFu
8058 #define UART_WN7816_GTN_SHIFT 0
8059 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
8060 /* WF7816 Bit Fields */
8061 #define UART_WF7816_GTFD_MASK 0xFFu
8062 #define UART_WF7816_GTFD_SHIFT 0
8063 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
8064 /* ET7816 Bit Fields */
8065 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
8066 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
8067 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
8068 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
8069 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
8070 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
8071 /* TL7816 Bit Fields */
8072 #define UART_TL7816_TLEN_MASK 0xFFu
8073 #define UART_TL7816_TLEN_SHIFT 0
8074 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
8075 /* AP7816A_T0 Bit Fields */
8076 #define UART_AP7816A_T0_ADTI_H_MASK 0xFFu
8077 #define UART_AP7816A_T0_ADTI_H_SHIFT 0
8078 #define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816A_T0_ADTI_H_SHIFT))&UART_AP7816A_T0_ADTI_H_MASK)
8079 /* AP7816B_T0 Bit Fields */
8080 #define UART_AP7816B_T0_ADTI_L_MASK 0xFFu
8081 #define UART_AP7816B_T0_ADTI_L_SHIFT 0
8082 #define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_AP7816B_T0_ADTI_L_SHIFT))&UART_AP7816B_T0_ADTI_L_MASK)
8083 /* WP7816A_T0 Bit Fields */
8084 #define UART_WP7816A_T0_WI_H_MASK 0xFFu
8085 #define UART_WP7816A_T0_WI_H_SHIFT 0
8086 #define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T0_WI_H_SHIFT))&UART_WP7816A_T0_WI_H_MASK)
8087 /* WP7816B_T0 Bit Fields */
8088 #define UART_WP7816B_T0_WI_L_MASK 0xFFu
8089 #define UART_WP7816B_T0_WI_L_SHIFT 0
8090 #define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T0_WI_L_SHIFT))&UART_WP7816B_T0_WI_L_MASK)
8091 /* WP7816A_T1 Bit Fields */
8092 #define UART_WP7816A_T1_BWI_H_MASK 0xFFu
8093 #define UART_WP7816A_T1_BWI_H_SHIFT 0
8094 #define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816A_T1_BWI_H_SHIFT))&UART_WP7816A_T1_BWI_H_MASK)
8095 /* WP7816B_T1 Bit Fields */
8096 #define UART_WP7816B_T1_BWI_L_MASK 0xFFu
8097 #define UART_WP7816B_T1_BWI_L_SHIFT 0
8098 #define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816B_T1_BWI_L_SHIFT))&UART_WP7816B_T1_BWI_L_MASK)
8099 /* WGP7816_T1 Bit Fields */
8100 #define UART_WGP7816_T1_BGI_MASK 0xFu
8101 #define UART_WGP7816_T1_BGI_SHIFT 0
8102 #define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_BGI_SHIFT))&UART_WGP7816_T1_BGI_MASK)
8103 #define UART_WGP7816_T1_CWI1_MASK 0xF0u
8104 #define UART_WGP7816_T1_CWI1_SHIFT 4
8105 #define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x))<<UART_WGP7816_T1_CWI1_SHIFT))&UART_WGP7816_T1_CWI1_MASK)
8106 /* WP7816C_T1 Bit Fields */
8107 #define UART_WP7816C_T1_CWI2_MASK 0x1Fu
8108 #define UART_WP7816C_T1_CWI2_SHIFT 0
8109 #define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816C_T1_CWI2_SHIFT))&UART_WP7816C_T1_CWI2_MASK)
8110
8111 /*!
8112 * @}
8113 */ /* end of group UART_Register_Masks */
8114
8115
8116 /* UART - Peripheral instance base addresses */
8117 /** Peripheral UART2 base address */
8118 #define UART2_BASE (0x4006C000u)
8119 /** Peripheral UART2 base pointer */
8120 #define UART2 ((UART_Type *)UART2_BASE)
8121 #define UART2_BASE_PTR (UART2)
8122 /** Array initializer of UART peripheral base addresses */
8123 #define UART_BASE_ADDRS { UART2_BASE }
8124 /** Array initializer of UART peripheral base pointers */
8125 #define UART_BASE_PTRS { UART2 }
8126 /** Interrupt vectors for the UART peripheral type */
8127 #define UART_RX_TX_IRQS { UART2_FLEXIO_IRQn }
8128 #define UART_ERR_IRQS { UART2_FLEXIO_IRQn }
8129
8130 /* ----------------------------------------------------------------------------
8131 -- UART - Register accessor macros
8132 ---------------------------------------------------------------------------- */
8133
8134 /*!
8135 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
8136 * @{
8137 */
8138
8139
8140 /* UART - Register instance definitions */
8141 /* UART2 */
8142 #define UART2_BDH UART_BDH_REG(UART2)
8143 #define UART2_BDL UART_BDL_REG(UART2)
8144 #define UART2_C1 UART_C1_REG(UART2)
8145 #define UART2_C2 UART_C2_REG(UART2)
8146 #define UART2_S1 UART_S1_REG(UART2)
8147 #define UART2_S2 UART_S2_REG(UART2)
8148 #define UART2_C3 UART_C3_REG(UART2)
8149 #define UART2_D UART_D_REG(UART2)
8150 #define UART2_MA1 UART_MA1_REG(UART2)
8151 #define UART2_MA2 UART_MA2_REG(UART2)
8152 #define UART2_C4 UART_C4_REG(UART2)
8153 #define UART2_C5 UART_C5_REG(UART2)
8154 #define UART2_C7816 UART_C7816_REG(UART2)
8155 #define UART2_IE7816 UART_IE7816_REG(UART2)
8156 #define UART2_IS7816 UART_IS7816_REG(UART2)
8157 #define UART2_WP7816 UART_WP7816_REG(UART2)
8158 #define UART2_WN7816 UART_WN7816_REG(UART2)
8159 #define UART2_WF7816 UART_WF7816_REG(UART2)
8160 #define UART2_ET7816 UART_ET7816_REG(UART2)
8161 #define UART2_TL7816 UART_TL7816_REG(UART2)
8162 #define UART2_AP7816A_T0 UART_AP7816A_T0_REG(UART2)
8163 #define UART2_AP7816B_T0 UART_AP7816B_T0_REG(UART2)
8164 #define UART2_WP7816A_T0 UART_WP7816A_T0_REG(UART2)
8165 #define UART2_WP7816A_T1 UART_WP7816A_T1_REG(UART2)
8166 #define UART2_WP7816B_T0 UART_WP7816B_T0_REG(UART2)
8167 #define UART2_WP7816B_T1 UART_WP7816B_T1_REG(UART2)
8168 #define UART2_WGP7816_T1 UART_WGP7816_T1_REG(UART2)
8169 #define UART2_WP7816C_T1 UART_WP7816C_T1_REG(UART2)
8170
8171 /*!
8172 * @}
8173 */ /* end of group UART_Register_Accessor_Macros */
8174
8175
8176 /*!
8177 * @}
8178 */ /* end of group UART_Peripheral_Access_Layer */
8179
8180
8181 /* ----------------------------------------------------------------------------
8182 -- USB Peripheral Access Layer
8183 ---------------------------------------------------------------------------- */
8184
8185 /*!
8186 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
8187 * @{
8188 */
8189
8190 /** USB - Register Layout Typedef */
8191 typedef struct {
8192 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
8193 uint8_t RESERVED_0[3];
8194 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
8195 uint8_t RESERVED_1[3];
8196 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
8197 uint8_t RESERVED_2[3];
8198 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
8199 uint8_t RESERVED_3[15];
8200 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
8201 uint8_t RESERVED_4[99];
8202 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
8203 uint8_t RESERVED_5[3];
8204 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
8205 uint8_t RESERVED_6[3];
8206 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
8207 uint8_t RESERVED_7[3];
8208 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
8209 uint8_t RESERVED_8[3];
8210 __I uint8_t STAT; /**< Status register, offset: 0x90 */
8211 uint8_t RESERVED_9[3];
8212 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
8213 uint8_t RESERVED_10[3];
8214 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
8215 uint8_t RESERVED_11[3];
8216 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
8217 uint8_t RESERVED_12[3];
8218 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
8219 uint8_t RESERVED_13[3];
8220 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
8221 uint8_t RESERVED_14[11];
8222 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
8223 uint8_t RESERVED_15[3];
8224 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
8225 uint8_t RESERVED_16[11];
8226 struct { /* offset: 0xC0, array step: 0x4 */
8227 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
8228 uint8_t RESERVED_0[3];
8229 } ENDPOINT[16];
8230 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
8231 uint8_t RESERVED_17[3];
8232 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
8233 uint8_t RESERVED_18[3];
8234 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
8235 uint8_t RESERVED_19[3];
8236 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
8237 uint8_t RESERVED_20[7];
8238 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
8239 uint8_t RESERVED_21[43];
8240 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
8241 uint8_t RESERVED_22[3];
8242 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
8243 uint8_t RESERVED_23[15];
8244 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
8245 uint8_t RESERVED_24[7];
8246 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
8247 } USB_Type, *USB_MemMapPtr;
8248
8249 /* ----------------------------------------------------------------------------
8250 -- USB - Register accessor macros
8251 ---------------------------------------------------------------------------- */
8252
8253 /*!
8254 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
8255 * @{
8256 */
8257
8258
8259 /* USB - Register accessors */
8260 #define USB_PERID_REG(base) ((base)->PERID)
8261 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
8262 #define USB_REV_REG(base) ((base)->REV)
8263 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
8264 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
8265 #define USB_ISTAT_REG(base) ((base)->ISTAT)
8266 #define USB_INTEN_REG(base) ((base)->INTEN)
8267 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
8268 #define USB_ERREN_REG(base) ((base)->ERREN)
8269 #define USB_STAT_REG(base) ((base)->STAT)
8270 #define USB_CTL_REG(base) ((base)->CTL)
8271 #define USB_ADDR_REG(base) ((base)->ADDR)
8272 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
8273 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
8274 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
8275 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
8276 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
8277 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
8278 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
8279 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
8280 #define USB_CONTROL_REG(base) ((base)->CONTROL)
8281 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
8282 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
8283 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
8284 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
8285 #define USB_CLK_RECOVER_INT_EN_REG(base) ((base)->CLK_RECOVER_INT_EN)
8286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
8287
8288 /*!
8289 * @}
8290 */ /* end of group USB_Register_Accessor_Macros */
8291
8292
8293 /* ----------------------------------------------------------------------------
8294 -- USB Register Masks
8295 ---------------------------------------------------------------------------- */
8296
8297 /*!
8298 * @addtogroup USB_Register_Masks USB Register Masks
8299 * @{
8300 */
8301
8302 /* PERID Bit Fields */
8303 #define USB_PERID_ID_MASK 0x3Fu
8304 #define USB_PERID_ID_SHIFT 0
8305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
8306 /* IDCOMP Bit Fields */
8307 #define USB_IDCOMP_NID_MASK 0x3Fu
8308 #define USB_IDCOMP_NID_SHIFT 0
8309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
8310 /* REV Bit Fields */
8311 #define USB_REV_REV_MASK 0xFFu
8312 #define USB_REV_REV_SHIFT 0
8313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
8314 /* ADDINFO Bit Fields */
8315 #define USB_ADDINFO_IEHOST_MASK 0x1u
8316 #define USB_ADDINFO_IEHOST_SHIFT 0
8317 /* OTGCTL Bit Fields */
8318 #define USB_OTGCTL_DPHIGH_MASK 0x80u
8319 #define USB_OTGCTL_DPHIGH_SHIFT 7
8320 /* ISTAT Bit Fields */
8321 #define USB_ISTAT_USBRST_MASK 0x1u
8322 #define USB_ISTAT_USBRST_SHIFT 0
8323 #define USB_ISTAT_ERROR_MASK 0x2u
8324 #define USB_ISTAT_ERROR_SHIFT 1
8325 #define USB_ISTAT_SOFTOK_MASK 0x4u
8326 #define USB_ISTAT_SOFTOK_SHIFT 2
8327 #define USB_ISTAT_TOKDNE_MASK 0x8u
8328 #define USB_ISTAT_TOKDNE_SHIFT 3
8329 #define USB_ISTAT_SLEEP_MASK 0x10u
8330 #define USB_ISTAT_SLEEP_SHIFT 4
8331 #define USB_ISTAT_RESUME_MASK 0x20u
8332 #define USB_ISTAT_RESUME_SHIFT 5
8333 #define USB_ISTAT_STALL_MASK 0x80u
8334 #define USB_ISTAT_STALL_SHIFT 7
8335 /* INTEN Bit Fields */
8336 #define USB_INTEN_USBRSTEN_MASK 0x1u
8337 #define USB_INTEN_USBRSTEN_SHIFT 0
8338 #define USB_INTEN_ERROREN_MASK 0x2u
8339 #define USB_INTEN_ERROREN_SHIFT 1
8340 #define USB_INTEN_SOFTOKEN_MASK 0x4u
8341 #define USB_INTEN_SOFTOKEN_SHIFT 2
8342 #define USB_INTEN_TOKDNEEN_MASK 0x8u
8343 #define USB_INTEN_TOKDNEEN_SHIFT 3
8344 #define USB_INTEN_SLEEPEN_MASK 0x10u
8345 #define USB_INTEN_SLEEPEN_SHIFT 4
8346 #define USB_INTEN_RESUMEEN_MASK 0x20u
8347 #define USB_INTEN_RESUMEEN_SHIFT 5
8348 #define USB_INTEN_STALLEN_MASK 0x80u
8349 #define USB_INTEN_STALLEN_SHIFT 7
8350 /* ERRSTAT Bit Fields */
8351 #define USB_ERRSTAT_PIDERR_MASK 0x1u
8352 #define USB_ERRSTAT_PIDERR_SHIFT 0
8353 #define USB_ERRSTAT_CRC5_MASK 0x2u
8354 #define USB_ERRSTAT_CRC5_SHIFT 1
8355 #define USB_ERRSTAT_CRC16_MASK 0x4u
8356 #define USB_ERRSTAT_CRC16_SHIFT 2
8357 #define USB_ERRSTAT_DFN8_MASK 0x8u
8358 #define USB_ERRSTAT_DFN8_SHIFT 3
8359 #define USB_ERRSTAT_BTOERR_MASK 0x10u
8360 #define USB_ERRSTAT_BTOERR_SHIFT 4
8361 #define USB_ERRSTAT_DMAERR_MASK 0x20u
8362 #define USB_ERRSTAT_DMAERR_SHIFT 5
8363 #define USB_ERRSTAT_BTSERR_MASK 0x80u
8364 #define USB_ERRSTAT_BTSERR_SHIFT 7
8365 /* ERREN Bit Fields */
8366 #define USB_ERREN_PIDERREN_MASK 0x1u
8367 #define USB_ERREN_PIDERREN_SHIFT 0
8368 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
8369 #define USB_ERREN_CRC5EOFEN_SHIFT 1
8370 #define USB_ERREN_CRC16EN_MASK 0x4u
8371 #define USB_ERREN_CRC16EN_SHIFT 2
8372 #define USB_ERREN_DFN8EN_MASK 0x8u
8373 #define USB_ERREN_DFN8EN_SHIFT 3
8374 #define USB_ERREN_BTOERREN_MASK 0x10u
8375 #define USB_ERREN_BTOERREN_SHIFT 4
8376 #define USB_ERREN_DMAERREN_MASK 0x20u
8377 #define USB_ERREN_DMAERREN_SHIFT 5
8378 #define USB_ERREN_BTSERREN_MASK 0x80u
8379 #define USB_ERREN_BTSERREN_SHIFT 7
8380 /* STAT Bit Fields */
8381 #define USB_STAT_ODD_MASK 0x4u
8382 #define USB_STAT_ODD_SHIFT 2
8383 #define USB_STAT_TX_MASK 0x8u
8384 #define USB_STAT_TX_SHIFT 3
8385 #define USB_STAT_ENDP_MASK 0xF0u
8386 #define USB_STAT_ENDP_SHIFT 4
8387 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
8388 /* CTL Bit Fields */
8389 #define USB_CTL_USBENSOFEN_MASK 0x1u
8390 #define USB_CTL_USBENSOFEN_SHIFT 0
8391 #define USB_CTL_ODDRST_MASK 0x2u
8392 #define USB_CTL_ODDRST_SHIFT 1
8393 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
8394 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
8395 #define USB_CTL_SE0_MASK 0x40u
8396 #define USB_CTL_SE0_SHIFT 6
8397 #define USB_CTL_JSTATE_MASK 0x80u
8398 #define USB_CTL_JSTATE_SHIFT 7
8399 /* ADDR Bit Fields */
8400 #define USB_ADDR_ADDR_MASK 0x7Fu
8401 #define USB_ADDR_ADDR_SHIFT 0
8402 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
8403 /* BDTPAGE1 Bit Fields */
8404 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
8405 #define USB_BDTPAGE1_BDTBA_SHIFT 1
8406 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
8407 /* FRMNUML Bit Fields */
8408 #define USB_FRMNUML_FRM_MASK 0xFFu
8409 #define USB_FRMNUML_FRM_SHIFT 0
8410 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
8411 /* FRMNUMH Bit Fields */
8412 #define USB_FRMNUMH_FRM_MASK 0x7u
8413 #define USB_FRMNUMH_FRM_SHIFT 0
8414 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
8415 /* BDTPAGE2 Bit Fields */
8416 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
8417 #define USB_BDTPAGE2_BDTBA_SHIFT 0
8418 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
8419 /* BDTPAGE3 Bit Fields */
8420 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
8421 #define USB_BDTPAGE3_BDTBA_SHIFT 0
8422 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
8423 /* ENDPT Bit Fields */
8424 #define USB_ENDPT_EPHSHK_MASK 0x1u
8425 #define USB_ENDPT_EPHSHK_SHIFT 0
8426 #define USB_ENDPT_EPSTALL_MASK 0x2u
8427 #define USB_ENDPT_EPSTALL_SHIFT 1
8428 #define USB_ENDPT_EPTXEN_MASK 0x4u
8429 #define USB_ENDPT_EPTXEN_SHIFT 2
8430 #define USB_ENDPT_EPRXEN_MASK 0x8u
8431 #define USB_ENDPT_EPRXEN_SHIFT 3
8432 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
8433 #define USB_ENDPT_EPCTLDIS_SHIFT 4
8434 /* USBCTRL Bit Fields */
8435 #define USB_USBCTRL_PDE_MASK 0x40u
8436 #define USB_USBCTRL_PDE_SHIFT 6
8437 #define USB_USBCTRL_SUSP_MASK 0x80u
8438 #define USB_USBCTRL_SUSP_SHIFT 7
8439 /* OBSERVE Bit Fields */
8440 #define USB_OBSERVE_DMPD_MASK 0x10u
8441 #define USB_OBSERVE_DMPD_SHIFT 4
8442 #define USB_OBSERVE_DPPD_MASK 0x40u
8443 #define USB_OBSERVE_DPPD_SHIFT 6
8444 #define USB_OBSERVE_DPPU_MASK 0x80u
8445 #define USB_OBSERVE_DPPU_SHIFT 7
8446 /* CONTROL Bit Fields */
8447 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
8448 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
8449 /* USBTRC0 Bit Fields */
8450 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
8451 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
8452 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
8453 #define USB_USBTRC0_SYNC_DET_SHIFT 1
8454 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
8455 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
8456 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
8457 #define USB_USBTRC0_USBRESMEN_SHIFT 5
8458 #define USB_USBTRC0_USBRESET_MASK 0x80u
8459 #define USB_USBTRC0_USBRESET_SHIFT 7
8460 /* USBFRMADJUST Bit Fields */
8461 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
8462 #define USB_USBFRMADJUST_ADJ_SHIFT 0
8463 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
8464 /* CLK_RECOVER_CTRL Bit Fields */
8465 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
8466 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
8467 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
8468 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
8469 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
8470 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
8471 /* CLK_RECOVER_IRC_EN Bit Fields */
8472 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
8473 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
8474 /* CLK_RECOVER_INT_EN Bit Fields */
8475 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK 0x10u
8476 #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT 4
8477 /* CLK_RECOVER_INT_STATUS Bit Fields */
8478 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
8479 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
8480
8481 /*!
8482 * @}
8483 */ /* end of group USB_Register_Masks */
8484
8485
8486 /* USB - Peripheral instance base addresses */
8487 /** Peripheral USB0 base address */
8488 #define USB0_BASE (0x40072000u)
8489 /** Peripheral USB0 base pointer */
8490 #define USB0 ((USB_Type *)USB0_BASE)
8491 #define USB0_BASE_PTR (USB0)
8492 /** Array initializer of USB peripheral base addresses */
8493 #define USB_BASE_ADDRS { USB0_BASE }
8494 /** Array initializer of USB peripheral base pointers */
8495 #define USB_BASE_PTRS { USB0 }
8496 /** Interrupt vectors for the USB peripheral type */
8497 #define USB_IRQS { USB0_IRQn }
8498
8499 /* ----------------------------------------------------------------------------
8500 -- USB - Register accessor macros
8501 ---------------------------------------------------------------------------- */
8502
8503 /*!
8504 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
8505 * @{
8506 */
8507
8508
8509 /* USB - Register instance definitions */
8510 /* USB0 */
8511 #define USB0_PERID USB_PERID_REG(USB0)
8512 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
8513 #define USB0_REV USB_REV_REG(USB0)
8514 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
8515 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
8516 #define USB0_ISTAT USB_ISTAT_REG(USB0)
8517 #define USB0_INTEN USB_INTEN_REG(USB0)
8518 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
8519 #define USB0_ERREN USB_ERREN_REG(USB0)
8520 #define USB0_STAT USB_STAT_REG(USB0)
8521 #define USB0_CTL USB_CTL_REG(USB0)
8522 #define USB0_ADDR USB_ADDR_REG(USB0)
8523 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
8524 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
8525 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
8526 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
8527 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
8528 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
8529 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
8530 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
8531 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
8532 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
8533 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
8534 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
8535 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
8536 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
8537 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
8538 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
8539 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
8540 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
8541 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
8542 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
8543 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
8544 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
8545 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
8546 #define USB0_CONTROL USB_CONTROL_REG(USB0)
8547 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
8548 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
8549 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
8550 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
8551 #define USB0_CLK_RECOVER_INT_EN USB_CLK_RECOVER_INT_EN_REG(USB0)
8552 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
8553
8554 /* USB - Register array accessors */
8555 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
8556
8557 /*!
8558 * @}
8559 */ /* end of group USB_Register_Accessor_Macros */
8560
8561
8562 /*!
8563 * @}
8564 */ /* end of group USB_Peripheral_Access_Layer */
8565
8566
8567 /* ----------------------------------------------------------------------------
8568 -- VREF Peripheral Access Layer
8569 ---------------------------------------------------------------------------- */
8570
8571 /*!
8572 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
8573 * @{
8574 */
8575
8576 /** VREF - Register Layout Typedef */
8577 typedef struct {
8578 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
8579 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
8580 } VREF_Type, *VREF_MemMapPtr;
8581
8582 /* ----------------------------------------------------------------------------
8583 -- VREF - Register accessor macros
8584 ---------------------------------------------------------------------------- */
8585
8586 /*!
8587 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
8588 * @{
8589 */
8590
8591
8592 /* VREF - Register accessors */
8593 #define VREF_TRM_REG(base) ((base)->TRM)
8594 #define VREF_SC_REG(base) ((base)->SC)
8595
8596 /*!
8597 * @}
8598 */ /* end of group VREF_Register_Accessor_Macros */
8599
8600
8601 /* ----------------------------------------------------------------------------
8602 -- VREF Register Masks
8603 ---------------------------------------------------------------------------- */
8604
8605 /*!
8606 * @addtogroup VREF_Register_Masks VREF Register Masks
8607 * @{
8608 */
8609
8610 /* TRM Bit Fields */
8611 #define VREF_TRM_TRIM_MASK 0x3Fu
8612 #define VREF_TRM_TRIM_SHIFT 0
8613 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
8614 #define VREF_TRM_CHOPEN_MASK 0x40u
8615 #define VREF_TRM_CHOPEN_SHIFT 6
8616 /* SC Bit Fields */
8617 #define VREF_SC_MODE_LV_MASK 0x3u
8618 #define VREF_SC_MODE_LV_SHIFT 0
8619 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
8620 #define VREF_SC_VREFST_MASK 0x4u
8621 #define VREF_SC_VREFST_SHIFT 2
8622 #define VREF_SC_ICOMPEN_MASK 0x20u
8623 #define VREF_SC_ICOMPEN_SHIFT 5
8624 #define VREF_SC_REGEN_MASK 0x40u
8625 #define VREF_SC_REGEN_SHIFT 6
8626 #define VREF_SC_VREFEN_MASK 0x80u
8627 #define VREF_SC_VREFEN_SHIFT 7
8628
8629 /*!
8630 * @}
8631 */ /* end of group VREF_Register_Masks */
8632
8633
8634 /* VREF - Peripheral instance base addresses */
8635 /** Peripheral VREF base address */
8636 #define VREF_BASE (0x40074000u)
8637 /** Peripheral VREF base pointer */
8638 #define VREF ((VREF_Type *)VREF_BASE)
8639 #define VREF_BASE_PTR (VREF)
8640 /** Array initializer of VREF peripheral base addresses */
8641 #define VREF_BASE_ADDRS { VREF_BASE }
8642 /** Array initializer of VREF peripheral base pointers */
8643 #define VREF_BASE_PTRS { VREF }
8644
8645 /* ----------------------------------------------------------------------------
8646 -- VREF - Register accessor macros
8647 ---------------------------------------------------------------------------- */
8648
8649 /*!
8650 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
8651 * @{
8652 */
8653
8654
8655 /* VREF - Register instance definitions */
8656 /* VREF */
8657 #define VREF_TRM VREF_TRM_REG(VREF)
8658 #define VREF_SC VREF_SC_REG(VREF)
8659
8660 /*!
8661 * @}
8662 */ /* end of group VREF_Register_Accessor_Macros */
8663
8664
8665 /*!
8666 * @}
8667 */ /* end of group VREF_Peripheral_Access_Layer */
8668
8669
8670 /*
8671 ** End of section using anonymous unions
8672 */
8673
8674 #if defined(__ARMCC_VERSION)
8675 #pragma pop
8676 #elif defined(__CWCC__)
8677 #pragma pop
8678 #elif defined(__GNUC__)
8679 /* leave anonymous unions enabled */
8680 #elif defined(__IAR_SYSTEMS_ICC__)
8681 #pragma language=default
8682 #else
8683 #error Not supported compiler type
8684 #endif
8685
8686 /*!
8687 * @}
8688 */ /* end of group Peripheral_access_layer */
8689
8690
8691 /* ----------------------------------------------------------------------------
8692 -- Backward Compatibility
8693 ---------------------------------------------------------------------------- */
8694
8695 /*!
8696 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
8697 * @{
8698 */
8699
8700 #define I2C_S1_RXAK_MASK I2C_S_RXAK_MASK
8701 #define I2C_S1_RXAK_SHIFT I2C_S_RXAK_SHIFT
8702 #define I2C_S1_IICIF_MASK I2C_S_IICIF_MASK
8703 #define I2C_S1_IICIF_SHIFT I2C_S_IICIF_SHIFTFT
8704 #define I2C_S1_SRW_MASK I2C_S_SRW_MASK
8705 #define I2C_S1_SRW_SHIFT I2C_S_SRW_SHIFT
8706 #define I2C_S1_RAM_MASK I2C_S_RAM_MASK
8707 #define I2C_S1_RAM_SHIFT I2C_S_RAM_SHIFT
8708 #define I2C_S1_ARBL_MASK I2C_S_ARBL_MASK
8709 #define I2C_S1_ARBL_SHIFT I2C_S_ARBL_SHIFT
8710 #define I2C_S1_BUSY_MASK I2C_S_BUSY_MASK
8711 #define I2C_S1_BUSY_SHIFT I2C_S_BUSY_SHIFT
8712 #define I2C_S1_IAAS_MASK I2C_S_IAAS_MASK
8713 #define I2C_S1_IAAS_SHIFT I2C_S_IAAS_SHIFT
8714 #define I2C_S1_TCF_MASK I2C_S_TCF_MASK
8715 #define I2C_S1_TCF_SHIFT I2C_S_TCF_SHIFT
8716 #define I2C_S1_REG(base) I2C_S_REG(base)
8717 #define I2C0_S1 I2C0_S
8718 #define I2C1_S1 I2C1_S
8719 #define ADC_BASES ADC_BASE_PTRS
8720 #define CMP_BASES CMP_BASE_PTRS
8721 #define DAC_BASES DAC_BASE_PTRS
8722 #define DMA_BASES DMA_BASE_PTRS
8723 #define DMAMUX_BASES DMAMUX_BASE_PTRS
8724 #define FLEXIO_BASES FLEXIO_BASE_PTRS
8725 #define FTFA_BASES FTFA_BASE_PTRS
8726 #define GPIO_BASES GPIO_BASE_PTRS
8727 #define I2C_BASES I2C_BASE_PTRS
8728 #define I2S_BASES I2S_BASE_PTRS
8729 #define LCD_BASES LCD_BASE_PTRS
8730 #define LLWU_BASES LLWU_BASE_PTRS
8731 #define LPTMR_BASES LPTMR_BASE_PTRS
8732 #define LPUART_BASES LPUART_BASE_PTRS
8733 #define MCG_BASES MCG_BASE_PTRS
8734 #define MCM_BASES MCM_BASE_PTRS
8735 #define MTB_BASES MTB_BASE_PTRS
8736 #define MTBDWT_BASES MTBDWT_BASE_PTRS
8737 #define NV_BASES NV_BASE_PTRS
8738 #define OSC_BASES OSC_BASE_PTRS
8739 #define PIT_BASES PIT_BASE_PTRS
8740 #define PMC_BASES PMC_BASE_PTRS
8741 #define PORT_BASES PORT_BASE_PTRS
8742 #define RCM_BASES RCM_BASE_PTRS
8743 #define ROM_BASES ROM_BASE_PTRS
8744 #define RTC_BASES RTC_BASE_PTRS
8745 #define SIM_BASES SIM_BASE_PTRS
8746 #define SMC_BASES SMC_BASE_PTRS
8747 #define SPI_BASES SPI_BASE_PTRS
8748 #define TPM_BASES TPM_BASE_PTRS
8749 #define UART_BASES UART_BASE_PTRS
8750 #define USB_BASES USB_BASE_PTRS
8751 #define VREF_BASES VREF_BASE_PTRS
8752 #define PTA_BASE_PTR GPIOA_BASE_PTR
8753 #define PTB_BASE_PTR GPIOB_BASE_PTR
8754 #define PTC_BASE_PTR GPIOC_BASE_PTR
8755 #define PTD_BASE_PTR GPIOD_BASE_PTR
8756 #define PTE_BASE_PTR GPIOE_BASE_PTR
8757 #define PTA_BASE GPIOA_BASE
8758 #define PTB_BASE GPIOB_BASE
8759 #define PTC_BASE GPIOC_BASE
8760 #define PTD_BASE GPIOD_BASE
8761 #define PTE_BASE GPIOE_BASE
8762 #define PTA GPIOA
8763 #define PTB GPIOB
8764 #define PTC GPIOC
8765 #define PTD GPIOD
8766 #define PTE GPIOE
8767 #define UART0_FLEXIO_IRQn UART2_FLEXIO_IRQn
8768 #define SIM_SOPT5_UART0ODE_MASK SIM_SOPT5_UART2ODE_MASK
8769 #define SIM_SOPT5_UART0ODE_SHIFT SIM_SOPT5_UART2ODE_SHIFT
8770 #define SIM_SCGC4_UART0_MASK SIM_SCGC4_UART2_MASK
8771 #define SIM_SCGC4_UART0_SHIFT SIM_SCGC4_UART2_SHIFT
8772 #define UART0_BASE UART2_BASE
8773 #define UART0 UART2
8774 #define UART0_BASE_PTR UART2_BASE_PTR
8775 #define UART0_BDH UART2_BDH
8776 #define UART0_BDL UART2_BDL
8777 #define UART0_C1 UART2_C1
8778 #define UART0_C2 UART2_C2
8779 #define UART0_S1 UART2_S1
8780 #define UART0_S2 UART2_S2
8781 #define UART0_C3 UART2_C3
8782 #define UART0_D UART2_D
8783 #define UART0_MA1 UART2_MA1
8784 #define UART0_MA2 UART2_MA2
8785 #define UART0_C4 UART2_C4
8786 #define UART0_C5 UART2_C5
8787 #define UART0_ED UART2_ED
8788 #define UART0_MODEM UART2_MODEM
8789 #define UART0_IR UART2_IR
8790 #define UART0_PFIFO UART2_PFIFO
8791 #define UART0_CFIFO UART2_CFIFO
8792 #define UART0_SFIFO UART2_SFIFO
8793 #define UART0_TWFIFO UART2_TWFIFO
8794 #define UART0_TCFIFO UART2_TCFIFO
8795 #define UART0_RWFIFO UART2_RWFIFO
8796 #define UART0_RCFIFO UART2_RCFIFO
8797 #define UART0_C7816 UART2_C7816
8798 #define UART0_IE7816 UART2_IE7816
8799 #define UART0_IS7816 UART2_IS7816
8800 #define UART0_WP7816 UART2_WP7816
8801 #define UART0_WN7816 UART2_WN7816
8802 #define UART0_WF7816 UART2_WF7816
8803 #define UART0_ET7816 UART2_ET7816
8804 #define UART0_TL7816 UART2_TL7816
8805 #define UART0_AP7816A_T0 UART2_AP7816A_T0
8806 #define UART0_AP7816B_T0 UART2_AP7816B_T0
8807 #define UART0_WP7816A_T0 UART2_WP7816A_T0
8808 #define UART0_WP7816A_T1 UART2_WP7816A_T1
8809 #define UART0_WP7816B_T0 UART2_WP7816B_T0
8810 #define UART0_WP7816B_T1 UART2_WP7816B_T1
8811 #define UART0_WGP7816_T1 UART2_WGP7816_T1
8812 #define UART0_WP7816C_T1 UART2_WP7816C_T1
8813 #define I2S0_MDR This_symb_has_been_deprecated
8814 #define I2S_MDR_DIVIDE_MASK This_symb_has_been_deprecated
8815 #define I2S_MDR_DIVIDE_SHIFT This_symb_has_been_deprecated
8816 #define I2S_MDR_DIVIDE(x) This_symb_has_been_deprecated
8817 #define I2S_MDR_FRACT_MASK This_symb_has_been_deprecated
8818 #define I2S_MDR_FRACT_SHIFT This_symb_has_been_deprecated
8819 #define I2S_MDR_FRACT(x) This_symb_has_been_deprecated
8820 #define I2S_MDR_REG(base) This_symb_has_been_deprecated
8821 #define CTL0 OTGCTL
8822 #define USB0_CTL0 USB0_OTGCTL
8823 #define USB_CTL0_REG(base) USB_OTGCTL_REG(base)
8824 #define USB_CTL0_DPHIGH_MASK USB_OTGCTL_DPHIGH_MASK
8825 #define USB_CTL0_DPHIGH_SHIFT USB_OTGCTL_DPHIGH_SHIFT
8826 #define CTL1 CTL
8827 #define USB0_CTL1 USB0_CTL
8828 #define USB_CTL1_REG(base) USB_CTL_REG(base)
8829 #define USB_CTL1_USBEN_MASK USB_CTL_USBEN_MASK
8830 #define USB_CTL1_USBEN_SHIFT USB_CTL_USBEN_SHIFT
8831 #define USB_CTL1_ODDRST_MASK USB_CTL_ODDRST_MASK
8832 #define USB_CTL1_ODDRST_SHIFT USB_CTL_ODDRST_SHIFT
8833 #define USB_CTL1_TXSUSPENDTOKENBUSY_MASK USB_CTL_TXSUSPENDTOKENBUSY_MASK
8834 #define USB_CTL1_TXSUSPENDTOKENBUSY_SHIFT USB_CTL_TXSUSPENDTOKENBUSY_SHIFT
8835 #define USB_CTL1_SE0_MASK USB_CTL_SE0_MASK
8836 #define USB_CTL1_SE0_SHIFT USB_CTL_SE0_SHIFT
8837 #define USB_CTL1_JSTATE_MASK USB_CTL_JSTATE_MASK
8838 #define USB_CTL1_JSTATE_SHIFT USB_CTL_JSTATE_SHIFT
8839 #define USB_CTL_USBEN_MASK USB_CTL_USBENSOFEN_MASK
8840 #define USB_CTL_USBEN_SHIFT USB_CTL_USBENSOFEN_SHIFT
8841
8842 /*!
8843 * @}
8844 */ /* end of group Backward_Compatibility_Symbols */
8845
8846
8847 #else /* #if !defined(MKL43Z4_H_) */
8848 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
8849 #if (MCU_MEM_MAP_VERSION != 0x0100u)
8850 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
8851 #warning There are included two not compatible versions of memory maps. Please check possible differences.
8852 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
8853 #endif /* (MCU_MEM_MAP_VERSION != 0x0100u) */
8854 #endif /* #if !defined(MKL43Z4_H_) */
8855
8856 /* MKL43Z4.h, eof. */
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum