tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL43Z/system_MKL43Z4.h

   1 /*
   2 ** ###################################################################
   3 **     Processors:          MKL43Z256VLH4
   4 **                          MKL43Z128VLH4
   5 **                          MKL43Z64VLH4
   6 **                          MKL43Z256VMP4
   7 **                          MKL43Z128VMP4
   8 **                          MKL43Z64VMP4
   9 **
  10 **     Compilers:           Keil ARM C/C++ Compiler
  11 **                          Freescale C/C++ for Embedded ARM
  12 **                          GNU C Compiler
  13 **                          GNU C Compiler - CodeSourcery Sourcery G++
  14 **                          IAR ANSI C/C++ Compiler for ARM
  15 **
  16 **     Reference manual:    KL43P64M48SF6RM, Rev.3, Aug 2014
  17 **     Version:             rev. 1.4, 2014-09-01
  18 **     Build:               b140904
  19 **
  20 **     Abstract:
  21 **         Provides a system configuration function and a global variable that
  22 **         contains the system frequency. It configures the device and initializes
  23 **         the oscillator (PLL) that is part of the microcontroller device.
  24 **
  25 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  26 **     All rights reserved.
  27 **
  28 **     Redistribution and use in source and binary forms, with or without modification,
  29 **     are permitted provided that the following conditions are met:
  30 **
  31 **     o Redistributions of source code must retain the above copyright notice, this list
  32 **       of conditions and the following disclaimer.
  33 **
  34 **     o Redistributions in binary form must reproduce the above copyright notice, this
  35 **       list of conditions and the following disclaimer in the documentation and/or
  36 **       other materials provided with the distribution.
  37 **
  38 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  39 **       contributors may be used to endorse or promote products derived from this
  40 **       software without specific prior written permission.
  41 **
  42 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  43 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  44 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  45 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  46 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  47 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  48 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  49 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  50 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  51 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  52 **
  53 **     http:                 www.freescale.com
  54 **     mail:                 support@freescale.com
  55 **
  56 **     Revisions:
  57 **     - rev. 1.0 (2014-03-27)
  58 **         Initial version.
  59 **     - rev. 1.1 (2014-05-26)
  60 **         I2S registers TCR2/RCR2 and others were changed.
  61 **         FLEXIO register FLEXIO_VERID has now bitfields: FEATURE, MINOR, MAJOR.
  62 **         Names of the bitfields of the FLEXIO_SHIFTBUF have been changed to the appropriate register name e.g.: FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS.
  63 **         Peripheral_BASES macros has been changed to Peripheral_BASE_PTRS, e.g.: ADC_BASES to ADC_BASE_PTRS.
  64 **         Clock configuration for high range external oscillator has been added.
  65 **         RFSYS module access has been added.
  66 **     - rev. 1.2 (2014-07-10)
  67 **         GPIO - Renamed modules PTA,PTB,PTC,PTD,PTE to GPIOA,GPIOB,GPIOC,GPIOD,GPIOE.
  68 **         UART0 - UART0 module renamed to UART2.
  69 **         I2S - removed MDR register.
  70 **     - rev. 1.3 (2014-08-21)
  71 **         UART2 - Removed ED register.
  72 **         UART2 - Removed MODEM register.
  73 **         UART2 - Removed IR register.
  74 **         UART2 - Removed PFIFO register.
  75 **         UART2 - Removed CFIFO register.
  76 **         UART2 - Removed SFIFO register.
  77 **         UART2 - Removed TWFIFO register.
  78 **         UART2 - Removed TCFIFO register.
  79 **         UART2 - Removed RWFIFO register.
  80 **         UART2 - Removed RCFIFO register.
  81 **         USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
  82 **         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
  83 **         SIM - Removed bitfield DIEID in SDID register.
  84 **     - rev. 1.4 (2014-09-01)
  85 **         USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
  86 **         USB - USB0_CTL1 was renamed to USB0_CTL register.
  87 **
  88 ** ###################################################################
  89 */
  90
  91 /*!
  92  * @file MKL43Z4
  93  * @version 1.4
  94  * @date 2014-09-01
  95  * @brief Device specific configuration file for MKL43Z4 (header file)
  96  *
  97  * Provides a system configuration function and a global variable that contains
  98  * the system frequency. It configures the device and initializes the oscillator
  99  * (PLL) that is part of the microcontroller device.
 100  */
 101
 102 #ifndef SYSTEM_MKL43Z4_H_
 103 #define SYSTEM_MKL43Z4_H_                        /**< Symbol preventing repeated inclusion */
 104
 105 #ifdef __cplusplus
 106 extern "C" {
 107 #endif
 108
 109 #include <stdint.h>
 110
 111
 112 #ifndef DISABLE_WDOG
 113   #define DISABLE_WDOG  1
 114 #endif
 115
 116 #define ACK_ISOLATION   1
 117
 118 #ifndef CLOCK_SETUP
 119   #define CLOCK_SETUP   1
 120 #endif
 121
 122 /* MCG_Lite mode constants */
 123
 124 #define MCG_MODE_LIRC_8M               0U
 125 #define MCG_MODE_HIRC                  1U
 126 #define MCG_MODE_LIRC_2M               2U
 127 #define MCG_MODE_EXT                   3U
 128
 129 /* Predefined clock setups
 130    0 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 8 MHz (LIRC 8 MHz) mode
 131          Default part configuration.
 132          Core clock/Bus clock derived from the internal clock source 8 MHz
 133          Core clock = 4MHz, BusClock = 2MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
 134    1 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
 135          Maximum achievable clock frequency configuration using internal clock.
 136          Core clock/Bus clock derived from the internal clock source 48MHz
 137          Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
 138    2 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
 139          Core clock/Bus clock derived directly from the external crystal 32.768kHz
 140          The clock settings is ready for Very Low Power Run mode.
 141          Core clock = 32.768kHz, BusClock = 32.768kHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
 142    3 ... Multipurpose Clock Generator Lite (MCG_Lite) in Low-frequency Internal Reference Clock 2 MHz (LIRC 2 MHz) mode
 143          Core clock/Bus clock derived from the internal clock source 2 MHz
 144          The clock settings is ready for Very Low Power Run mode.
 145          Core clock = 2MHz, BusClock = 1MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
 146    4 ... Multipurpose Clock Generator Lite (MCG_Lite) in High-frequency Internal Reference Clock (HIRC) mode
 147          USB clock setup - for USB to receive internal 48MHz clock derived from HIRC.
 148          Core clock/Bus clock derived from the internal clock source 48MHz
 149          Core clock = 48MHz, BusClock = 24MHz, USB FS clock derived from HIRC (MCGPCLK)
 150    5 ... Multipurpose Clock Generator Lite (MCG_Lite) in External Oscillator (EXT) mode
 151          Core clock/Bus clock derived directly from the external crystal 8 MHz
 152          Core clock = 8MHz, BusClock = 4MHz, USB FS clock derived from external clock USB_CLKIN (applicable only for derivatived with USB)
 153 */
 154
 155 /* Define clock source values */
 156
 157 #define CPU_XTAL_CLK_HZ                32768u              /* Value of the external crystal or oscillator clock frequency in Hz */
 158 #define CPU_INT_FAST_CLK_HZ            48000000u           /* Value of the fast internal oscillator clock frequency in Hz  */
 159 #define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
 160
 161 /* Low power mode enable */
 162 /* SMC_PMPROT: AVLP=1,AVLLS=1 */
 163 #define SMC_PMPROT_VALUE               0x22u               /* SMC_PMPROT */
 164
 165 #if (CLOCK_SETUP == 0)
 166   #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
 167   #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 168   #define MCG_MODE                     MCG_MODE_LIRC_8M    /* Clock generator mode */
 169   /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
 170   #define MCG_C1_VALUE                 0x42u               /* MCG_C1 */
 171   /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
 172   #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
 173   /* MCG_SC: FCRDIV=0 */
 174   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 175   /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
 176   #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
 177   /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 178   #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
 179   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 180   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 181   /* SIM_CLKDIV1: OUTDIV1=1,OUTDIV4=1 */
 182   #define SYSTEM_SIM_CLKDIV1_VALUE     0x10010000u         /* SIM_CLKDIV1 */
 183   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 184   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 185   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 186   #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
 187 #elif (CLOCK_SETUP == 1)
 188   #define DEFAULT_SYSTEM_CLOCK         48000000u           /* Default System clock value */
 189   #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 190   #define MCG_MODE                     MCG_MODE_HIRC       /* Clock generator mode */
 191   /* MCG_C1: CLKS=0,IRCLKEN=0,IREFSTEN=0 */
 192   #define MCG_C1_VALUE                 0x00u               /* MCG_C1 */
 193   /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
 194   #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
 195   /* MCG_SC: FCRDIV=0 */
 196   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 197   /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
 198   #define MCG_MC_VALUE                 0x80u               /* MCG_MC */
 199   /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 200   #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
 201   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 202   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 203   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
 204   #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
 205   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 206   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 207   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 208   #define SYSTEM_SIM_SOPT2_VALUE       0x03000000U         /* SIM_SOPT2 */
 209 #elif (CLOCK_SETUP == 2)
 210   #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
 211   #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 212   #define MCG_MODE                     MCG_MODE_EXT        /* Clock generator mode */
 213   /* MCG_C1: CLKS=2,IRCLKEN=1,IREFSTEN=0 */
 214   #define MCG_C1_VALUE                 0x82u               /* MCG_C1 */
 215   /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=1,IRCS=1 */
 216   #define MCG_C2_VALUE                 0x05u               /* MCG_C2 */
 217   /* MCG_SC: FCRDIV=0 */
 218   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 219   /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
 220   #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
 221   /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 222   #define OSC0_CR_VALUE                0x80u               /* OSC0_CR */
 223   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 224   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 225   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=0 */
 226   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00u               /* SIM_CLKDIV1 */
 227   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 228   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 229   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=2,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 230   #define SYSTEM_SIM_SOPT2_VALUE       0x02000000u         /* SIM_SOPT2 */
 231 #elif (CLOCK_SETUP == 3)
 232   #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
 233   #define CPU_INT_SLOW_CLK_HZ          2000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 234   #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
 235   /* MCG_C1: CLKS=1,IRCLKEN=1,IREFSTEN=0 */
 236   #define MCG_C1_VALUE                 0x42u               /* MCG_C1 */
 237   /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=0 */
 238   #define MCG_C2_VALUE                 0x00u               /* MCG_C2 */
 239   /* MCG_SC: FCRDIV=0 */
 240   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 241   /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
 242   #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
 243   /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 244   #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
 245   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 246   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 247   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
 248   #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
 249   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 250   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 251   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 252   #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
 253 #elif (CLOCK_SETUP == 4)
 254   #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
 255   #define CPU_INT_SLOW_CLK_HZ          8000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 256   #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
 257   /* MCG_C1: CLKS=0,IRCLKEN=1,IREFSTEN=0 */
 258   #define MCG_C1_VALUE                 0x02u               /* MCG_C1 */
 259   /* MCG_C2: RANGE0=0,HGO0=0,EREFS0=0,IRCS=1 */
 260   #define MCG_C2_VALUE                 0x01u               /* MCG_C2 */
 261   /* MCG_SC: FCRDIV=0 */
 262   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 263   /* MCG_MC: HIRCEN=1 LIRC_DIV2=0 */
 264   #define MCG_MC_VALUE                 0x80u               /* MCG_MC */
 265   /* OSC0_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 266   #define OSC0_CR_VALUE                0x00u               /* OSC0_CR */
 267   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 268   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 269   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
 270   #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
 271   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 272   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 273   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=1,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 274   #define SYSTEM_SIM_SOPT2_VALUE       0x03040000u         /* SIM_SOPT2 */
 275 #elif (CLOCK_SETUP == 5)
 276   #define DEFAULT_SYSTEM_CLOCK         2000000u            /* Default System clock value */
 277   #define CPU_INT_SLOW_CLK_HZ          2000000u            /* Value of the slow internal oscillator clock frequency in Hz  */
 278   #define MCG_MODE                     MCG_MODE_LIRC_2M    /* Clock generator mode */
 279   /* MCG_C1: CLKS=2,IRCLKEN=0,IREFSTEN=0 */
 280   #define MCG_C1_VALUE                 0x80u               /* MCG_C1 */
 281   /* MCG_C2: RANGE0=1,HGO0=0,EREFS0=1,IRCS=1 */
 282   #define MCG_C2_VALUE                 0x15u               /* MCG_C2 */
 283   /* MCG_SC: FCRDIV=0 */
 284   #define MCG_SC_VALUE                 0x00u               /* MCG_SC */
 285   /* MCG_MC: HIRCEN=0 LIRC_DIV2=0 */
 286   #define MCG_MC_VALUE                 0x00u               /* MCG_MC */
 287   /* OSC0_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 288   #define OSC0_CR_VALUE                0x80u               /* OSC0_CR */
 289   /* SMC_PMCTRL: RUNM=0,STOPA=0,STOPM=0 */
 290   #define SMC_PMCTRL_VALUE             0x00u               /* SMC_PMCTRL */
 291   /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV4=1 */
 292   #define SYSTEM_SIM_CLKDIV1_VALUE     0x10000u            /* SIM_CLKDIV1 */
 293   /* SIM_SOPT1: OSC32KSEL=0,OSC32KOUT=0 */
 294   #define SYSTEM_SIM_SOPT1_VALUE       0x00000000u         /* SIM_SOPT1 */
 295   /* SIM_SOPT2: LPUART1SRC=0,LPUART0SRC=0,TPMSRC=3,FLEXIOSRC=0,USBSRC=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 296   #define SYSTEM_SIM_SOPT2_VALUE       0x03000000u         /* SIM_SOPT2 */
 297 #else
 298   #error The selected clock setup is not supported.
 299 #endif /* (CLOCK_SETUP == 5) */
 300
 301
 302 /**
 303  * @brief System clock frequency (core clock)
 304  *
 305  * The system clock frequency supplied to the SysTick timer and the processor
 306  * core clock. This variable can be used by the user application to setup the
 307  * SysTick timer or configure other parameters. It may also be used by debugger to
 308  * query the frequency of the debug timer or configure the trace clock speed
 309  * SystemCoreClock is initialized with a correct predefined value.
 310  */
 311 extern uint32_t SystemCoreClock;
 312
 313 /**
 314  * @brief Setup the microcontroller system.
 315  *
 316  * Typically this function configures the oscillator (PLL) that is part of the
 317  * microcontroller device. For systems with variable clock speed it also updates
 318  * the variable SystemCoreClock. SystemInit is called from startup_device file.
 319  */
 320 void SystemInit (void);
 321
 322 /**
 323  * @brief Updates the SystemCoreClock variable.
 324  *
 325  * It must be called whenever the core clock is changed during program
 326  * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
 327  * the current core clock.
 328  */
 329 void SystemCoreClockUpdate (void);
 330
 331 #ifdef __cplusplus
 332 }
 333 #endif
 334
 335 #endif  /* #if !defined(SYSTEM_MKL43Z4_H_) */