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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_Freescale / TARGET_MCU_K64F / MK64F12.h
1 /*
2 ** ###################################################################
3 ** Processors: MK64FN1M0VDC12
4 ** MK64FN1M0VLL12
5 ** MK64FN1M0VLQ12
6 ** MK64FN1M0VMD12
7 **
8 ** Compilers: Keil ARM C/C++ Compiler
9 ** Freescale C/C++ for Embedded ARM
10 ** GNU C Compiler
11 ** GNU C Compiler - CodeSourcery Sourcery G++
12 ** IAR ANSI C/C++ Compiler for ARM
13 **
14 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
15 ** Version: rev. 2.5, 2014-02-10
16 ** Build: b140604
17 **
18 ** Abstract:
19 ** CMSIS Peripheral Access Layer for MK64F12
20 **
21 ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc.
22 ** All rights reserved.
23 **
24 ** Redistribution and use in source and binary forms, with or without modification,
25 ** are permitted provided that the following conditions are met:
26 **
27 ** o Redistributions of source code must retain the above copyright notice, this list
28 ** of conditions and the following disclaimer.
29 **
30 ** o Redistributions in binary form must reproduce the above copyright notice, this
31 ** list of conditions and the following disclaimer in the documentation and/or
32 ** other materials provided with the distribution.
33 **
34 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
35 ** contributors may be used to endorse or promote products derived from this
36 ** software without specific prior written permission.
37 **
38 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
39 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
40 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
41 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
42 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
43 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
44 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
45 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
46 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
47 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
48 **
49 ** http: www.freescale.com
50 ** mail: support@freescale.com
51 **
52 ** Revisions:
53 ** - rev. 1.0 (2013-08-12)
54 ** Initial version.
55 ** - rev. 2.0 (2013-10-29)
56 ** Register accessor macros added to the memory map.
57 ** Symbols for Processor Expert memory map compatibility added to the memory map.
58 ** Startup file for gcc has been updated according to CMSIS 3.2.
59 ** System initialization updated.
60 ** MCG - registers updated.
61 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
62 ** - rev. 2.1 (2013-10-30)
63 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
64 ** - rev. 2.2 (2013-12-09)
65 ** DMA - EARS register removed.
66 ** AIPS0, AIPS1 - MPRA register updated.
67 ** - rev. 2.3 (2014-01-24)
68 ** Update according to reference manual rev. 2
69 ** ENET, MCG, MCM, SIM, USB - registers updated
70 ** - rev. 2.4 (2014-02-10)
71 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
72 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
73 ** - rev. 2.5 (2014-02-10)
74 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
75 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
76 ** Module access macro module_BASES replaced by module_BASE_PTRS.
77 **
78 ** ###################################################################
79 */
80
81 /*!
82 * @file MK64F12.h
83 * @version 2.5
84 * @date 2014-02-10
85 * @brief CMSIS Peripheral Access Layer for MK64F12
86 *
87 * CMSIS Peripheral Access Layer for MK64F12
88 */
89
90
91 /* ----------------------------------------------------------------------------
92 -- MCU activation
93 ---------------------------------------------------------------------------- */
94
95 /* Prevention from multiple including the same memory map */
96 #if !defined(MK64F12_H_) /* Check if memory map has not been already included */
97 #define MK64F12_H_
98 #define MCU_MK64F12
99
100 /* Check if another memory map has not been also included */
101 #if (defined(MCU_ACTIVE))
102 #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included.
103 #endif /* (defined(MCU_ACTIVE)) */
104 #define MCU_ACTIVE
105
106 #include <stdint.h>
107
108 /** Memory map major version (memory maps with equal major version number are
109 * compatible) */
110 #define MCU_MEM_MAP_VERSION 0x0200u
111 /** Memory map minor version */
112 #define MCU_MEM_MAP_VERSION_MINOR 0x0005u
113
114 /**
115 * @brief Macro to calculate address of an aliased word in the peripheral
116 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
117 * 0x400FFFFF).
118 * @param Reg Register to access.
119 * @param Bit Bit number to access.
120 * @return Address of the aliased word in the peripheral bitband area.
121 */
122 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
123 /**
124 * @brief Macro to access a single bit of a peripheral register (bit band region
125 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
126 * be used for peripherals with 32bit access allowed.
127 * @param Reg Register to access.
128 * @param Bit Bit number to access.
129 * @return Value of the targeted bit in the bit band region.
130 */
131 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
132 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit))
133 /**
134 * @brief Macro to access a single bit of a peripheral register (bit band region
135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
136 * be used for peripherals with 16bit access allowed.
137 * @param Reg Register to access.
138 * @param Bit Bit number to access.
139 * @return Value of the targeted bit in the bit band region.
140 */
141 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
142 /**
143 * @brief Macro to access a single bit of a peripheral register (bit band region
144 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
145 * be used for peripherals with 8bit access allowed.
146 * @param Reg Register to access.
147 * @param Bit Bit number to access.
148 * @return Value of the targeted bit in the bit band region.
149 */
150 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit))))
151
152 /* ----------------------------------------------------------------------------
153 -- Interrupt vector numbers
154 ---------------------------------------------------------------------------- */
155
156 /*!
157 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
158 * @{
159 */
160
161 /** Interrupt Number Definitions */
162 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
163
164 typedef enum IRQn {
165 /* Core interrupts */
166 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
167 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
168 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
169 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
170 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
171 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
172 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
173 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
174 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
175
176 /* Device specific interrupts */
177 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
178 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
179 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
180 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
181 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
182 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
183 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
184 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
185 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
186 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
187 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
188 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
189 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
190 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
191 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
192 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
193 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
194 MCM_IRQn = 17, /**< Normal Interrupt */
195 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
196 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
197 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
198 LLW_IRQn = 21, /**< Low Leakage Wakeup */
199 Watchdog_IRQn = 22, /**< WDOG Interrupt */
200 RNG_IRQn = 23, /**< RNG Interrupt */
201 I2C0_IRQn = 24, /**< I2C0 interrupt */
202 I2C1_IRQn = 25, /**< I2C1 interrupt */
203 SPI0_IRQn = 26, /**< SPI0 Interrupt */
204 SPI1_IRQn = 27, /**< SPI1 Interrupt */
205 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
206 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
207 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
208 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
209 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
210 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
211 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
212 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
213 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
214 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
215 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
216 ADC0_IRQn = 39, /**< ADC0 interrupt */
217 CMP0_IRQn = 40, /**< CMP0 interrupt */
218 CMP1_IRQn = 41, /**< CMP1 interrupt */
219 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
220 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
221 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
222 CMT_IRQn = 45, /**< CMT interrupt */
223 RTC_IRQn = 46, /**< RTC interrupt */
224 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
225 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
226 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
227 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
228 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
229 PDB0_IRQn = 52, /**< PDB0 Interrupt */
230 USB0_IRQn = 53, /**< USB0 interrupt */
231 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
232 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
233 DAC0_IRQn = 56, /**< DAC0 interrupt */
234 MCG_IRQn = 57, /**< MCG Interrupt */
235 LPTimer_IRQn = 58, /**< LPTimer interrupt */
236 PORTA_IRQn = 59, /**< Port A interrupt */
237 PORTB_IRQn = 60, /**< Port B interrupt */
238 PORTC_IRQn = 61, /**< Port C interrupt */
239 PORTD_IRQn = 62, /**< Port D interrupt */
240 PORTE_IRQn = 63, /**< Port E interrupt */
241 SWI_IRQn = 64, /**< Software interrupt */
242 SPI2_IRQn = 65, /**< SPI2 Interrupt */
243 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
244 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
245 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
246 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
247 CMP2_IRQn = 70, /**< CMP2 interrupt */
248 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
249 DAC1_IRQn = 72, /**< DAC1 interrupt */
250 ADC1_IRQn = 73, /**< ADC1 interrupt */
251 I2C2_IRQn = 74, /**< I2C2 interrupt */
252 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
253 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
254 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
255 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
256 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
257 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
258 SDHC_IRQn = 81, /**< SDHC interrupt */
259 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
260 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
261 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
262 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
263 } IRQn_Type;
264
265 /*!
266 * @}
267 */ /* end of group Interrupt_vector_numbers */
268
269
270 /* ----------------------------------------------------------------------------
271 -- Cortex M4 Core Configuration
272 ---------------------------------------------------------------------------- */
273
274 /*!
275 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
276 * @{
277 */
278
279 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
280 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
281 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
282 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
283
284 #include "core_cm4.h" /* Core Peripheral Access Layer */
285 #include "system_MK64F12.h" /* Device specific configuration file */
286
287 /*!
288 * @}
289 */ /* end of group Cortex_Core_Configuration */
290
291
292 /* ----------------------------------------------------------------------------
293 -- Device Peripheral Access Layer
294 ---------------------------------------------------------------------------- */
295
296 /*!
297 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
298 * @{
299 */
300
301
302 /*
303 ** Start of section using anonymous unions
304 */
305
306 #if defined(__ARMCC_VERSION)
307 #pragma push
308 #pragma anon_unions
309 #elif defined(__CWCC__)
310 #pragma push
311 #pragma cpp_extensions on
312 #elif defined(__GNUC__)
313 /* anonymous unions are enabled by default */
314 #elif defined(__IAR_SYSTEMS_ICC__)
315 #pragma language=extended
316 #else
317 #error Not supported compiler type
318 #endif
319
320 /* ----------------------------------------------------------------------------
321 -- ADC Peripheral Access Layer
322 ---------------------------------------------------------------------------- */
323
324 /*!
325 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
326 * @{
327 */
328
329 /** ADC - Register Layout Typedef */
330 typedef struct {
331 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
332 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
333 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
334 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
335 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
336 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
337 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
338 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
339 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
340 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
341 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
342 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
343 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
344 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
345 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
346 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
347 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
348 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
349 uint8_t RESERVED_0[4];
350 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
351 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
352 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
353 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
354 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
355 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
356 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
357 } ADC_Type, *ADC_MemMapPtr;
358
359 /* ----------------------------------------------------------------------------
360 -- ADC - Register accessor macros
361 ---------------------------------------------------------------------------- */
362
363 /*!
364 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
365 * @{
366 */
367
368
369 /* ADC - Register accessors */
370 #define ADC_SC1_REG(base,index) ((base)->SC1[index])
371 #define ADC_CFG1_REG(base) ((base)->CFG1)
372 #define ADC_CFG2_REG(base) ((base)->CFG2)
373 #define ADC_R_REG(base,index) ((base)->R[index])
374 #define ADC_CV1_REG(base) ((base)->CV1)
375 #define ADC_CV2_REG(base) ((base)->CV2)
376 #define ADC_SC2_REG(base) ((base)->SC2)
377 #define ADC_SC3_REG(base) ((base)->SC3)
378 #define ADC_OFS_REG(base) ((base)->OFS)
379 #define ADC_PG_REG(base) ((base)->PG)
380 #define ADC_MG_REG(base) ((base)->MG)
381 #define ADC_CLPD_REG(base) ((base)->CLPD)
382 #define ADC_CLPS_REG(base) ((base)->CLPS)
383 #define ADC_CLP4_REG(base) ((base)->CLP4)
384 #define ADC_CLP3_REG(base) ((base)->CLP3)
385 #define ADC_CLP2_REG(base) ((base)->CLP2)
386 #define ADC_CLP1_REG(base) ((base)->CLP1)
387 #define ADC_CLP0_REG(base) ((base)->CLP0)
388 #define ADC_CLMD_REG(base) ((base)->CLMD)
389 #define ADC_CLMS_REG(base) ((base)->CLMS)
390 #define ADC_CLM4_REG(base) ((base)->CLM4)
391 #define ADC_CLM3_REG(base) ((base)->CLM3)
392 #define ADC_CLM2_REG(base) ((base)->CLM2)
393 #define ADC_CLM1_REG(base) ((base)->CLM1)
394 #define ADC_CLM0_REG(base) ((base)->CLM0)
395
396 /*!
397 * @}
398 */ /* end of group ADC_Register_Accessor_Macros */
399
400
401 /* ----------------------------------------------------------------------------
402 -- ADC Register Masks
403 ---------------------------------------------------------------------------- */
404
405 /*!
406 * @addtogroup ADC_Register_Masks ADC Register Masks
407 * @{
408 */
409
410 /* SC1 Bit Fields */
411 #define ADC_SC1_ADCH_MASK 0x1Fu
412 #define ADC_SC1_ADCH_SHIFT 0
413 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
414 #define ADC_SC1_DIFF_MASK 0x20u
415 #define ADC_SC1_DIFF_SHIFT 5
416 #define ADC_SC1_AIEN_MASK 0x40u
417 #define ADC_SC1_AIEN_SHIFT 6
418 #define ADC_SC1_COCO_MASK 0x80u
419 #define ADC_SC1_COCO_SHIFT 7
420 /* CFG1 Bit Fields */
421 #define ADC_CFG1_ADICLK_MASK 0x3u
422 #define ADC_CFG1_ADICLK_SHIFT 0
423 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
424 #define ADC_CFG1_MODE_MASK 0xCu
425 #define ADC_CFG1_MODE_SHIFT 2
426 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
427 #define ADC_CFG1_ADLSMP_MASK 0x10u
428 #define ADC_CFG1_ADLSMP_SHIFT 4
429 #define ADC_CFG1_ADIV_MASK 0x60u
430 #define ADC_CFG1_ADIV_SHIFT 5
431 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
432 #define ADC_CFG1_ADLPC_MASK 0x80u
433 #define ADC_CFG1_ADLPC_SHIFT 7
434 /* CFG2 Bit Fields */
435 #define ADC_CFG2_ADLSTS_MASK 0x3u
436 #define ADC_CFG2_ADLSTS_SHIFT 0
437 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
438 #define ADC_CFG2_ADHSC_MASK 0x4u
439 #define ADC_CFG2_ADHSC_SHIFT 2
440 #define ADC_CFG2_ADACKEN_MASK 0x8u
441 #define ADC_CFG2_ADACKEN_SHIFT 3
442 #define ADC_CFG2_MUXSEL_MASK 0x10u
443 #define ADC_CFG2_MUXSEL_SHIFT 4
444 /* R Bit Fields */
445 #define ADC_R_D_MASK 0xFFFFu
446 #define ADC_R_D_SHIFT 0
447 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
448 /* CV1 Bit Fields */
449 #define ADC_CV1_CV_MASK 0xFFFFu
450 #define ADC_CV1_CV_SHIFT 0
451 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
452 /* CV2 Bit Fields */
453 #define ADC_CV2_CV_MASK 0xFFFFu
454 #define ADC_CV2_CV_SHIFT 0
455 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
456 /* SC2 Bit Fields */
457 #define ADC_SC2_REFSEL_MASK 0x3u
458 #define ADC_SC2_REFSEL_SHIFT 0
459 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
460 #define ADC_SC2_DMAEN_MASK 0x4u
461 #define ADC_SC2_DMAEN_SHIFT 2
462 #define ADC_SC2_ACREN_MASK 0x8u
463 #define ADC_SC2_ACREN_SHIFT 3
464 #define ADC_SC2_ACFGT_MASK 0x10u
465 #define ADC_SC2_ACFGT_SHIFT 4
466 #define ADC_SC2_ACFE_MASK 0x20u
467 #define ADC_SC2_ACFE_SHIFT 5
468 #define ADC_SC2_ADTRG_MASK 0x40u
469 #define ADC_SC2_ADTRG_SHIFT 6
470 #define ADC_SC2_ADACT_MASK 0x80u
471 #define ADC_SC2_ADACT_SHIFT 7
472 /* SC3 Bit Fields */
473 #define ADC_SC3_AVGS_MASK 0x3u
474 #define ADC_SC3_AVGS_SHIFT 0
475 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
476 #define ADC_SC3_AVGE_MASK 0x4u
477 #define ADC_SC3_AVGE_SHIFT 2
478 #define ADC_SC3_ADCO_MASK 0x8u
479 #define ADC_SC3_ADCO_SHIFT 3
480 #define ADC_SC3_CALF_MASK 0x40u
481 #define ADC_SC3_CALF_SHIFT 6
482 #define ADC_SC3_CAL_MASK 0x80u
483 #define ADC_SC3_CAL_SHIFT 7
484 /* OFS Bit Fields */
485 #define ADC_OFS_OFS_MASK 0xFFFFu
486 #define ADC_OFS_OFS_SHIFT 0
487 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
488 /* PG Bit Fields */
489 #define ADC_PG_PG_MASK 0xFFFFu
490 #define ADC_PG_PG_SHIFT 0
491 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
492 /* MG Bit Fields */
493 #define ADC_MG_MG_MASK 0xFFFFu
494 #define ADC_MG_MG_SHIFT 0
495 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
496 /* CLPD Bit Fields */
497 #define ADC_CLPD_CLPD_MASK 0x3Fu
498 #define ADC_CLPD_CLPD_SHIFT 0
499 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
500 /* CLPS Bit Fields */
501 #define ADC_CLPS_CLPS_MASK 0x3Fu
502 #define ADC_CLPS_CLPS_SHIFT 0
503 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
504 /* CLP4 Bit Fields */
505 #define ADC_CLP4_CLP4_MASK 0x3FFu
506 #define ADC_CLP4_CLP4_SHIFT 0
507 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
508 /* CLP3 Bit Fields */
509 #define ADC_CLP3_CLP3_MASK 0x1FFu
510 #define ADC_CLP3_CLP3_SHIFT 0
511 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
512 /* CLP2 Bit Fields */
513 #define ADC_CLP2_CLP2_MASK 0xFFu
514 #define ADC_CLP2_CLP2_SHIFT 0
515 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
516 /* CLP1 Bit Fields */
517 #define ADC_CLP1_CLP1_MASK 0x7Fu
518 #define ADC_CLP1_CLP1_SHIFT 0
519 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
520 /* CLP0 Bit Fields */
521 #define ADC_CLP0_CLP0_MASK 0x3Fu
522 #define ADC_CLP0_CLP0_SHIFT 0
523 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
524 /* CLMD Bit Fields */
525 #define ADC_CLMD_CLMD_MASK 0x3Fu
526 #define ADC_CLMD_CLMD_SHIFT 0
527 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
528 /* CLMS Bit Fields */
529 #define ADC_CLMS_CLMS_MASK 0x3Fu
530 #define ADC_CLMS_CLMS_SHIFT 0
531 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
532 /* CLM4 Bit Fields */
533 #define ADC_CLM4_CLM4_MASK 0x3FFu
534 #define ADC_CLM4_CLM4_SHIFT 0
535 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
536 /* CLM3 Bit Fields */
537 #define ADC_CLM3_CLM3_MASK 0x1FFu
538 #define ADC_CLM3_CLM3_SHIFT 0
539 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
540 /* CLM2 Bit Fields */
541 #define ADC_CLM2_CLM2_MASK 0xFFu
542 #define ADC_CLM2_CLM2_SHIFT 0
543 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
544 /* CLM1 Bit Fields */
545 #define ADC_CLM1_CLM1_MASK 0x7Fu
546 #define ADC_CLM1_CLM1_SHIFT 0
547 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
548 /* CLM0 Bit Fields */
549 #define ADC_CLM0_CLM0_MASK 0x3Fu
550 #define ADC_CLM0_CLM0_SHIFT 0
551 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
552
553 /*!
554 * @}
555 */ /* end of group ADC_Register_Masks */
556
557
558 /* ADC - Peripheral instance base addresses */
559 /** Peripheral ADC0 base address */
560 #define ADC0_BASE (0x4003B000u)
561 /** Peripheral ADC0 base pointer */
562 #define ADC0 ((ADC_Type *)ADC0_BASE)
563 #define ADC0_BASE_PTR (ADC0)
564 /** Peripheral ADC1 base address */
565 #define ADC1_BASE (0x400BB000u)
566 /** Peripheral ADC1 base pointer */
567 #define ADC1 ((ADC_Type *)ADC1_BASE)
568 #define ADC1_BASE_PTR (ADC1)
569 /** Array initializer of ADC peripheral base addresses */
570 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
571 /** Array initializer of ADC peripheral base pointers */
572 #define ADC_BASE_PTRS { ADC0, ADC1 }
573 /** Interrupt vectors for the ADC peripheral type */
574 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
575
576 /* ----------------------------------------------------------------------------
577 -- ADC - Register accessor macros
578 ---------------------------------------------------------------------------- */
579
580 /*!
581 * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros
582 * @{
583 */
584
585
586 /* ADC - Register instance definitions */
587 /* ADC0 */
588 #define ADC0_SC1A ADC_SC1_REG(ADC0,0)
589 #define ADC0_SC1B ADC_SC1_REG(ADC0,1)
590 #define ADC0_CFG1 ADC_CFG1_REG(ADC0)
591 #define ADC0_CFG2 ADC_CFG2_REG(ADC0)
592 #define ADC0_RA ADC_R_REG(ADC0,0)
593 #define ADC0_RB ADC_R_REG(ADC0,1)
594 #define ADC0_CV1 ADC_CV1_REG(ADC0)
595 #define ADC0_CV2 ADC_CV2_REG(ADC0)
596 #define ADC0_SC2 ADC_SC2_REG(ADC0)
597 #define ADC0_SC3 ADC_SC3_REG(ADC0)
598 #define ADC0_OFS ADC_OFS_REG(ADC0)
599 #define ADC0_PG ADC_PG_REG(ADC0)
600 #define ADC0_MG ADC_MG_REG(ADC0)
601 #define ADC0_CLPD ADC_CLPD_REG(ADC0)
602 #define ADC0_CLPS ADC_CLPS_REG(ADC0)
603 #define ADC0_CLP4 ADC_CLP4_REG(ADC0)
604 #define ADC0_CLP3 ADC_CLP3_REG(ADC0)
605 #define ADC0_CLP2 ADC_CLP2_REG(ADC0)
606 #define ADC0_CLP1 ADC_CLP1_REG(ADC0)
607 #define ADC0_CLP0 ADC_CLP0_REG(ADC0)
608 #define ADC0_CLMD ADC_CLMD_REG(ADC0)
609 #define ADC0_CLMS ADC_CLMS_REG(ADC0)
610 #define ADC0_CLM4 ADC_CLM4_REG(ADC0)
611 #define ADC0_CLM3 ADC_CLM3_REG(ADC0)
612 #define ADC0_CLM2 ADC_CLM2_REG(ADC0)
613 #define ADC0_CLM1 ADC_CLM1_REG(ADC0)
614 #define ADC0_CLM0 ADC_CLM0_REG(ADC0)
615 /* ADC1 */
616 #define ADC1_SC1A ADC_SC1_REG(ADC1,0)
617 #define ADC1_SC1B ADC_SC1_REG(ADC1,1)
618 #define ADC1_CFG1 ADC_CFG1_REG(ADC1)
619 #define ADC1_CFG2 ADC_CFG2_REG(ADC1)
620 #define ADC1_RA ADC_R_REG(ADC1,0)
621 #define ADC1_RB ADC_R_REG(ADC1,1)
622 #define ADC1_CV1 ADC_CV1_REG(ADC1)
623 #define ADC1_CV2 ADC_CV2_REG(ADC1)
624 #define ADC1_SC2 ADC_SC2_REG(ADC1)
625 #define ADC1_SC3 ADC_SC3_REG(ADC1)
626 #define ADC1_OFS ADC_OFS_REG(ADC1)
627 #define ADC1_PG ADC_PG_REG(ADC1)
628 #define ADC1_MG ADC_MG_REG(ADC1)
629 #define ADC1_CLPD ADC_CLPD_REG(ADC1)
630 #define ADC1_CLPS ADC_CLPS_REG(ADC1)
631 #define ADC1_CLP4 ADC_CLP4_REG(ADC1)
632 #define ADC1_CLP3 ADC_CLP3_REG(ADC1)
633 #define ADC1_CLP2 ADC_CLP2_REG(ADC1)
634 #define ADC1_CLP1 ADC_CLP1_REG(ADC1)
635 #define ADC1_CLP0 ADC_CLP0_REG(ADC1)
636 #define ADC1_CLMD ADC_CLMD_REG(ADC1)
637 #define ADC1_CLMS ADC_CLMS_REG(ADC1)
638 #define ADC1_CLM4 ADC_CLM4_REG(ADC1)
639 #define ADC1_CLM3 ADC_CLM3_REG(ADC1)
640 #define ADC1_CLM2 ADC_CLM2_REG(ADC1)
641 #define ADC1_CLM1 ADC_CLM1_REG(ADC1)
642 #define ADC1_CLM0 ADC_CLM0_REG(ADC1)
643
644 /* ADC - Register array accessors */
645 #define ADC0_SC1(index) ADC_SC1_REG(ADC0,index)
646 #define ADC1_SC1(index) ADC_SC1_REG(ADC1,index)
647 #define ADC0_R(index) ADC_R_REG(ADC0,index)
648 #define ADC1_R(index) ADC_R_REG(ADC1,index)
649
650 /*!
651 * @}
652 */ /* end of group ADC_Register_Accessor_Macros */
653
654
655 /*!
656 * @}
657 */ /* end of group ADC_Peripheral_Access_Layer */
658
659
660 /* ----------------------------------------------------------------------------
661 -- AIPS Peripheral Access Layer
662 ---------------------------------------------------------------------------- */
663
664 /*!
665 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
666 * @{
667 */
668
669 /** AIPS - Register Layout Typedef */
670 typedef struct {
671 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
672 uint8_t RESERVED_0[28];
673 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
674 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
675 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
676 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
677 uint8_t RESERVED_1[16];
678 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
679 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
680 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
681 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
682 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
683 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
684 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
685 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
686 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
687 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
688 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
689 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
690 uint8_t RESERVED_2[16];
691 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
692 } AIPS_Type, *AIPS_MemMapPtr;
693
694 /* ----------------------------------------------------------------------------
695 -- AIPS - Register accessor macros
696 ---------------------------------------------------------------------------- */
697
698 /*!
699 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
700 * @{
701 */
702
703
704 /* AIPS - Register accessors */
705 #define AIPS_MPRA_REG(base) ((base)->MPRA)
706 #define AIPS_PACRA_REG(base) ((base)->PACRA)
707 #define AIPS_PACRB_REG(base) ((base)->PACRB)
708 #define AIPS_PACRC_REG(base) ((base)->PACRC)
709 #define AIPS_PACRD_REG(base) ((base)->PACRD)
710 #define AIPS_PACRE_REG(base) ((base)->PACRE)
711 #define AIPS_PACRF_REG(base) ((base)->PACRF)
712 #define AIPS_PACRG_REG(base) ((base)->PACRG)
713 #define AIPS_PACRH_REG(base) ((base)->PACRH)
714 #define AIPS_PACRI_REG(base) ((base)->PACRI)
715 #define AIPS_PACRJ_REG(base) ((base)->PACRJ)
716 #define AIPS_PACRK_REG(base) ((base)->PACRK)
717 #define AIPS_PACRL_REG(base) ((base)->PACRL)
718 #define AIPS_PACRM_REG(base) ((base)->PACRM)
719 #define AIPS_PACRN_REG(base) ((base)->PACRN)
720 #define AIPS_PACRO_REG(base) ((base)->PACRO)
721 #define AIPS_PACRP_REG(base) ((base)->PACRP)
722 #define AIPS_PACRU_REG(base) ((base)->PACRU)
723
724 /*!
725 * @}
726 */ /* end of group AIPS_Register_Accessor_Macros */
727
728
729 /* ----------------------------------------------------------------------------
730 -- AIPS Register Masks
731 ---------------------------------------------------------------------------- */
732
733 /*!
734 * @addtogroup AIPS_Register_Masks AIPS Register Masks
735 * @{
736 */
737
738 /* MPRA Bit Fields */
739 #define AIPS_MPRA_MPL5_MASK 0x100u
740 #define AIPS_MPRA_MPL5_SHIFT 8
741 #define AIPS_MPRA_MTW5_MASK 0x200u
742 #define AIPS_MPRA_MTW5_SHIFT 9
743 #define AIPS_MPRA_MTR5_MASK 0x400u
744 #define AIPS_MPRA_MTR5_SHIFT 10
745 #define AIPS_MPRA_MPL4_MASK 0x1000u
746 #define AIPS_MPRA_MPL4_SHIFT 12
747 #define AIPS_MPRA_MTW4_MASK 0x2000u
748 #define AIPS_MPRA_MTW4_SHIFT 13
749 #define AIPS_MPRA_MTR4_MASK 0x4000u
750 #define AIPS_MPRA_MTR4_SHIFT 14
751 #define AIPS_MPRA_MPL3_MASK 0x10000u
752 #define AIPS_MPRA_MPL3_SHIFT 16
753 #define AIPS_MPRA_MTW3_MASK 0x20000u
754 #define AIPS_MPRA_MTW3_SHIFT 17
755 #define AIPS_MPRA_MTR3_MASK 0x40000u
756 #define AIPS_MPRA_MTR3_SHIFT 18
757 #define AIPS_MPRA_MPL2_MASK 0x100000u
758 #define AIPS_MPRA_MPL2_SHIFT 20
759 #define AIPS_MPRA_MTW2_MASK 0x200000u
760 #define AIPS_MPRA_MTW2_SHIFT 21
761 #define AIPS_MPRA_MTR2_MASK 0x400000u
762 #define AIPS_MPRA_MTR2_SHIFT 22
763 #define AIPS_MPRA_MPL1_MASK 0x1000000u
764 #define AIPS_MPRA_MPL1_SHIFT 24
765 #define AIPS_MPRA_MTW1_MASK 0x2000000u
766 #define AIPS_MPRA_MTW1_SHIFT 25
767 #define AIPS_MPRA_MTR1_MASK 0x4000000u
768 #define AIPS_MPRA_MTR1_SHIFT 26
769 #define AIPS_MPRA_MPL0_MASK 0x10000000u
770 #define AIPS_MPRA_MPL0_SHIFT 28
771 #define AIPS_MPRA_MTW0_MASK 0x20000000u
772 #define AIPS_MPRA_MTW0_SHIFT 29
773 #define AIPS_MPRA_MTR0_MASK 0x40000000u
774 #define AIPS_MPRA_MTR0_SHIFT 30
775 /* PACRA Bit Fields */
776 #define AIPS_PACRA_TP7_MASK 0x1u
777 #define AIPS_PACRA_TP7_SHIFT 0
778 #define AIPS_PACRA_WP7_MASK 0x2u
779 #define AIPS_PACRA_WP7_SHIFT 1
780 #define AIPS_PACRA_SP7_MASK 0x4u
781 #define AIPS_PACRA_SP7_SHIFT 2
782 #define AIPS_PACRA_TP6_MASK 0x10u
783 #define AIPS_PACRA_TP6_SHIFT 4
784 #define AIPS_PACRA_WP6_MASK 0x20u
785 #define AIPS_PACRA_WP6_SHIFT 5
786 #define AIPS_PACRA_SP6_MASK 0x40u
787 #define AIPS_PACRA_SP6_SHIFT 6
788 #define AIPS_PACRA_TP5_MASK 0x100u
789 #define AIPS_PACRA_TP5_SHIFT 8
790 #define AIPS_PACRA_WP5_MASK 0x200u
791 #define AIPS_PACRA_WP5_SHIFT 9
792 #define AIPS_PACRA_SP5_MASK 0x400u
793 #define AIPS_PACRA_SP5_SHIFT 10
794 #define AIPS_PACRA_TP4_MASK 0x1000u
795 #define AIPS_PACRA_TP4_SHIFT 12
796 #define AIPS_PACRA_WP4_MASK 0x2000u
797 #define AIPS_PACRA_WP4_SHIFT 13
798 #define AIPS_PACRA_SP4_MASK 0x4000u
799 #define AIPS_PACRA_SP4_SHIFT 14
800 #define AIPS_PACRA_TP3_MASK 0x10000u
801 #define AIPS_PACRA_TP3_SHIFT 16
802 #define AIPS_PACRA_WP3_MASK 0x20000u
803 #define AIPS_PACRA_WP3_SHIFT 17
804 #define AIPS_PACRA_SP3_MASK 0x40000u
805 #define AIPS_PACRA_SP3_SHIFT 18
806 #define AIPS_PACRA_TP2_MASK 0x100000u
807 #define AIPS_PACRA_TP2_SHIFT 20
808 #define AIPS_PACRA_WP2_MASK 0x200000u
809 #define AIPS_PACRA_WP2_SHIFT 21
810 #define AIPS_PACRA_SP2_MASK 0x400000u
811 #define AIPS_PACRA_SP2_SHIFT 22
812 #define AIPS_PACRA_TP1_MASK 0x1000000u
813 #define AIPS_PACRA_TP1_SHIFT 24
814 #define AIPS_PACRA_WP1_MASK 0x2000000u
815 #define AIPS_PACRA_WP1_SHIFT 25
816 #define AIPS_PACRA_SP1_MASK 0x4000000u
817 #define AIPS_PACRA_SP1_SHIFT 26
818 #define AIPS_PACRA_TP0_MASK 0x10000000u
819 #define AIPS_PACRA_TP0_SHIFT 28
820 #define AIPS_PACRA_WP0_MASK 0x20000000u
821 #define AIPS_PACRA_WP0_SHIFT 29
822 #define AIPS_PACRA_SP0_MASK 0x40000000u
823 #define AIPS_PACRA_SP0_SHIFT 30
824 /* PACRB Bit Fields */
825 #define AIPS_PACRB_TP7_MASK 0x1u
826 #define AIPS_PACRB_TP7_SHIFT 0
827 #define AIPS_PACRB_WP7_MASK 0x2u
828 #define AIPS_PACRB_WP7_SHIFT 1
829 #define AIPS_PACRB_SP7_MASK 0x4u
830 #define AIPS_PACRB_SP7_SHIFT 2
831 #define AIPS_PACRB_TP6_MASK 0x10u
832 #define AIPS_PACRB_TP6_SHIFT 4
833 #define AIPS_PACRB_WP6_MASK 0x20u
834 #define AIPS_PACRB_WP6_SHIFT 5
835 #define AIPS_PACRB_SP6_MASK 0x40u
836 #define AIPS_PACRB_SP6_SHIFT 6
837 #define AIPS_PACRB_TP5_MASK 0x100u
838 #define AIPS_PACRB_TP5_SHIFT 8
839 #define AIPS_PACRB_WP5_MASK 0x200u
840 #define AIPS_PACRB_WP5_SHIFT 9
841 #define AIPS_PACRB_SP5_MASK 0x400u
842 #define AIPS_PACRB_SP5_SHIFT 10
843 #define AIPS_PACRB_TP4_MASK 0x1000u
844 #define AIPS_PACRB_TP4_SHIFT 12
845 #define AIPS_PACRB_WP4_MASK 0x2000u
846 #define AIPS_PACRB_WP4_SHIFT 13
847 #define AIPS_PACRB_SP4_MASK 0x4000u
848 #define AIPS_PACRB_SP4_SHIFT 14
849 #define AIPS_PACRB_TP3_MASK 0x10000u
850 #define AIPS_PACRB_TP3_SHIFT 16
851 #define AIPS_PACRB_WP3_MASK 0x20000u
852 #define AIPS_PACRB_WP3_SHIFT 17
853 #define AIPS_PACRB_SP3_MASK 0x40000u
854 #define AIPS_PACRB_SP3_SHIFT 18
855 #define AIPS_PACRB_TP2_MASK 0x100000u
856 #define AIPS_PACRB_TP2_SHIFT 20
857 #define AIPS_PACRB_WP2_MASK 0x200000u
858 #define AIPS_PACRB_WP2_SHIFT 21
859 #define AIPS_PACRB_SP2_MASK 0x400000u
860 #define AIPS_PACRB_SP2_SHIFT 22
861 #define AIPS_PACRB_TP1_MASK 0x1000000u
862 #define AIPS_PACRB_TP1_SHIFT 24
863 #define AIPS_PACRB_WP1_MASK 0x2000000u
864 #define AIPS_PACRB_WP1_SHIFT 25
865 #define AIPS_PACRB_SP1_MASK 0x4000000u
866 #define AIPS_PACRB_SP1_SHIFT 26
867 #define AIPS_PACRB_TP0_MASK 0x10000000u
868 #define AIPS_PACRB_TP0_SHIFT 28
869 #define AIPS_PACRB_WP0_MASK 0x20000000u
870 #define AIPS_PACRB_WP0_SHIFT 29
871 #define AIPS_PACRB_SP0_MASK 0x40000000u
872 #define AIPS_PACRB_SP0_SHIFT 30
873 /* PACRC Bit Fields */
874 #define AIPS_PACRC_TP7_MASK 0x1u
875 #define AIPS_PACRC_TP7_SHIFT 0
876 #define AIPS_PACRC_WP7_MASK 0x2u
877 #define AIPS_PACRC_WP7_SHIFT 1
878 #define AIPS_PACRC_SP7_MASK 0x4u
879 #define AIPS_PACRC_SP7_SHIFT 2
880 #define AIPS_PACRC_TP6_MASK 0x10u
881 #define AIPS_PACRC_TP6_SHIFT 4
882 #define AIPS_PACRC_WP6_MASK 0x20u
883 #define AIPS_PACRC_WP6_SHIFT 5
884 #define AIPS_PACRC_SP6_MASK 0x40u
885 #define AIPS_PACRC_SP6_SHIFT 6
886 #define AIPS_PACRC_TP5_MASK 0x100u
887 #define AIPS_PACRC_TP5_SHIFT 8
888 #define AIPS_PACRC_WP5_MASK 0x200u
889 #define AIPS_PACRC_WP5_SHIFT 9
890 #define AIPS_PACRC_SP5_MASK 0x400u
891 #define AIPS_PACRC_SP5_SHIFT 10
892 #define AIPS_PACRC_TP4_MASK 0x1000u
893 #define AIPS_PACRC_TP4_SHIFT 12
894 #define AIPS_PACRC_WP4_MASK 0x2000u
895 #define AIPS_PACRC_WP4_SHIFT 13
896 #define AIPS_PACRC_SP4_MASK 0x4000u
897 #define AIPS_PACRC_SP4_SHIFT 14
898 #define AIPS_PACRC_TP3_MASK 0x10000u
899 #define AIPS_PACRC_TP3_SHIFT 16
900 #define AIPS_PACRC_WP3_MASK 0x20000u
901 #define AIPS_PACRC_WP3_SHIFT 17
902 #define AIPS_PACRC_SP3_MASK 0x40000u
903 #define AIPS_PACRC_SP3_SHIFT 18
904 #define AIPS_PACRC_TP2_MASK 0x100000u
905 #define AIPS_PACRC_TP2_SHIFT 20
906 #define AIPS_PACRC_WP2_MASK 0x200000u
907 #define AIPS_PACRC_WP2_SHIFT 21
908 #define AIPS_PACRC_SP2_MASK 0x400000u
909 #define AIPS_PACRC_SP2_SHIFT 22
910 #define AIPS_PACRC_TP1_MASK 0x1000000u
911 #define AIPS_PACRC_TP1_SHIFT 24
912 #define AIPS_PACRC_WP1_MASK 0x2000000u
913 #define AIPS_PACRC_WP1_SHIFT 25
914 #define AIPS_PACRC_SP1_MASK 0x4000000u
915 #define AIPS_PACRC_SP1_SHIFT 26
916 #define AIPS_PACRC_TP0_MASK 0x10000000u
917 #define AIPS_PACRC_TP0_SHIFT 28
918 #define AIPS_PACRC_WP0_MASK 0x20000000u
919 #define AIPS_PACRC_WP0_SHIFT 29
920 #define AIPS_PACRC_SP0_MASK 0x40000000u
921 #define AIPS_PACRC_SP0_SHIFT 30
922 /* PACRD Bit Fields */
923 #define AIPS_PACRD_TP7_MASK 0x1u
924 #define AIPS_PACRD_TP7_SHIFT 0
925 #define AIPS_PACRD_WP7_MASK 0x2u
926 #define AIPS_PACRD_WP7_SHIFT 1
927 #define AIPS_PACRD_SP7_MASK 0x4u
928 #define AIPS_PACRD_SP7_SHIFT 2
929 #define AIPS_PACRD_TP6_MASK 0x10u
930 #define AIPS_PACRD_TP6_SHIFT 4
931 #define AIPS_PACRD_WP6_MASK 0x20u
932 #define AIPS_PACRD_WP6_SHIFT 5
933 #define AIPS_PACRD_SP6_MASK 0x40u
934 #define AIPS_PACRD_SP6_SHIFT 6
935 #define AIPS_PACRD_TP5_MASK 0x100u
936 #define AIPS_PACRD_TP5_SHIFT 8
937 #define AIPS_PACRD_WP5_MASK 0x200u
938 #define AIPS_PACRD_WP5_SHIFT 9
939 #define AIPS_PACRD_SP5_MASK 0x400u
940 #define AIPS_PACRD_SP5_SHIFT 10
941 #define AIPS_PACRD_TP4_MASK 0x1000u
942 #define AIPS_PACRD_TP4_SHIFT 12
943 #define AIPS_PACRD_WP4_MASK 0x2000u
944 #define AIPS_PACRD_WP4_SHIFT 13
945 #define AIPS_PACRD_SP4_MASK 0x4000u
946 #define AIPS_PACRD_SP4_SHIFT 14
947 #define AIPS_PACRD_TP3_MASK 0x10000u
948 #define AIPS_PACRD_TP3_SHIFT 16
949 #define AIPS_PACRD_WP3_MASK 0x20000u
950 #define AIPS_PACRD_WP3_SHIFT 17
951 #define AIPS_PACRD_SP3_MASK 0x40000u
952 #define AIPS_PACRD_SP3_SHIFT 18
953 #define AIPS_PACRD_TP2_MASK 0x100000u
954 #define AIPS_PACRD_TP2_SHIFT 20
955 #define AIPS_PACRD_WP2_MASK 0x200000u
956 #define AIPS_PACRD_WP2_SHIFT 21
957 #define AIPS_PACRD_SP2_MASK 0x400000u
958 #define AIPS_PACRD_SP2_SHIFT 22
959 #define AIPS_PACRD_TP1_MASK 0x1000000u
960 #define AIPS_PACRD_TP1_SHIFT 24
961 #define AIPS_PACRD_WP1_MASK 0x2000000u
962 #define AIPS_PACRD_WP1_SHIFT 25
963 #define AIPS_PACRD_SP1_MASK 0x4000000u
964 #define AIPS_PACRD_SP1_SHIFT 26
965 #define AIPS_PACRD_TP0_MASK 0x10000000u
966 #define AIPS_PACRD_TP0_SHIFT 28
967 #define AIPS_PACRD_WP0_MASK 0x20000000u
968 #define AIPS_PACRD_WP0_SHIFT 29
969 #define AIPS_PACRD_SP0_MASK 0x40000000u
970 #define AIPS_PACRD_SP0_SHIFT 30
971 /* PACRE Bit Fields */
972 #define AIPS_PACRE_TP7_MASK 0x1u
973 #define AIPS_PACRE_TP7_SHIFT 0
974 #define AIPS_PACRE_WP7_MASK 0x2u
975 #define AIPS_PACRE_WP7_SHIFT 1
976 #define AIPS_PACRE_SP7_MASK 0x4u
977 #define AIPS_PACRE_SP7_SHIFT 2
978 #define AIPS_PACRE_TP6_MASK 0x10u
979 #define AIPS_PACRE_TP6_SHIFT 4
980 #define AIPS_PACRE_WP6_MASK 0x20u
981 #define AIPS_PACRE_WP6_SHIFT 5
982 #define AIPS_PACRE_SP6_MASK 0x40u
983 #define AIPS_PACRE_SP6_SHIFT 6
984 #define AIPS_PACRE_TP5_MASK 0x100u
985 #define AIPS_PACRE_TP5_SHIFT 8
986 #define AIPS_PACRE_WP5_MASK 0x200u
987 #define AIPS_PACRE_WP5_SHIFT 9
988 #define AIPS_PACRE_SP5_MASK 0x400u
989 #define AIPS_PACRE_SP5_SHIFT 10
990 #define AIPS_PACRE_TP4_MASK 0x1000u
991 #define AIPS_PACRE_TP4_SHIFT 12
992 #define AIPS_PACRE_WP4_MASK 0x2000u
993 #define AIPS_PACRE_WP4_SHIFT 13
994 #define AIPS_PACRE_SP4_MASK 0x4000u
995 #define AIPS_PACRE_SP4_SHIFT 14
996 #define AIPS_PACRE_TP3_MASK 0x10000u
997 #define AIPS_PACRE_TP3_SHIFT 16
998 #define AIPS_PACRE_WP3_MASK 0x20000u
999 #define AIPS_PACRE_WP3_SHIFT 17
1000 #define AIPS_PACRE_SP3_MASK 0x40000u
1001 #define AIPS_PACRE_SP3_SHIFT 18
1002 #define AIPS_PACRE_TP2_MASK 0x100000u
1003 #define AIPS_PACRE_TP2_SHIFT 20
1004 #define AIPS_PACRE_WP2_MASK 0x200000u
1005 #define AIPS_PACRE_WP2_SHIFT 21
1006 #define AIPS_PACRE_SP2_MASK 0x400000u
1007 #define AIPS_PACRE_SP2_SHIFT 22
1008 #define AIPS_PACRE_TP1_MASK 0x1000000u
1009 #define AIPS_PACRE_TP1_SHIFT 24
1010 #define AIPS_PACRE_WP1_MASK 0x2000000u
1011 #define AIPS_PACRE_WP1_SHIFT 25
1012 #define AIPS_PACRE_SP1_MASK 0x4000000u
1013 #define AIPS_PACRE_SP1_SHIFT 26
1014 #define AIPS_PACRE_TP0_MASK 0x10000000u
1015 #define AIPS_PACRE_TP0_SHIFT 28
1016 #define AIPS_PACRE_WP0_MASK 0x20000000u
1017 #define AIPS_PACRE_WP0_SHIFT 29
1018 #define AIPS_PACRE_SP0_MASK 0x40000000u
1019 #define AIPS_PACRE_SP0_SHIFT 30
1020 /* PACRF Bit Fields */
1021 #define AIPS_PACRF_TP7_MASK 0x1u
1022 #define AIPS_PACRF_TP7_SHIFT 0
1023 #define AIPS_PACRF_WP7_MASK 0x2u
1024 #define AIPS_PACRF_WP7_SHIFT 1
1025 #define AIPS_PACRF_SP7_MASK 0x4u
1026 #define AIPS_PACRF_SP7_SHIFT 2
1027 #define AIPS_PACRF_TP6_MASK 0x10u
1028 #define AIPS_PACRF_TP6_SHIFT 4
1029 #define AIPS_PACRF_WP6_MASK 0x20u
1030 #define AIPS_PACRF_WP6_SHIFT 5
1031 #define AIPS_PACRF_SP6_MASK 0x40u
1032 #define AIPS_PACRF_SP6_SHIFT 6
1033 #define AIPS_PACRF_TP5_MASK 0x100u
1034 #define AIPS_PACRF_TP5_SHIFT 8
1035 #define AIPS_PACRF_WP5_MASK 0x200u
1036 #define AIPS_PACRF_WP5_SHIFT 9
1037 #define AIPS_PACRF_SP5_MASK 0x400u
1038 #define AIPS_PACRF_SP5_SHIFT 10
1039 #define AIPS_PACRF_TP4_MASK 0x1000u
1040 #define AIPS_PACRF_TP4_SHIFT 12
1041 #define AIPS_PACRF_WP4_MASK 0x2000u
1042 #define AIPS_PACRF_WP4_SHIFT 13
1043 #define AIPS_PACRF_SP4_MASK 0x4000u
1044 #define AIPS_PACRF_SP4_SHIFT 14
1045 #define AIPS_PACRF_TP3_MASK 0x10000u
1046 #define AIPS_PACRF_TP3_SHIFT 16
1047 #define AIPS_PACRF_WP3_MASK 0x20000u
1048 #define AIPS_PACRF_WP3_SHIFT 17
1049 #define AIPS_PACRF_SP3_MASK 0x40000u
1050 #define AIPS_PACRF_SP3_SHIFT 18
1051 #define AIPS_PACRF_TP2_MASK 0x100000u
1052 #define AIPS_PACRF_TP2_SHIFT 20
1053 #define AIPS_PACRF_WP2_MASK 0x200000u
1054 #define AIPS_PACRF_WP2_SHIFT 21
1055 #define AIPS_PACRF_SP2_MASK 0x400000u
1056 #define AIPS_PACRF_SP2_SHIFT 22
1057 #define AIPS_PACRF_TP1_MASK 0x1000000u
1058 #define AIPS_PACRF_TP1_SHIFT 24
1059 #define AIPS_PACRF_WP1_MASK 0x2000000u
1060 #define AIPS_PACRF_WP1_SHIFT 25
1061 #define AIPS_PACRF_SP1_MASK 0x4000000u
1062 #define AIPS_PACRF_SP1_SHIFT 26
1063 #define AIPS_PACRF_TP0_MASK 0x10000000u
1064 #define AIPS_PACRF_TP0_SHIFT 28
1065 #define AIPS_PACRF_WP0_MASK 0x20000000u
1066 #define AIPS_PACRF_WP0_SHIFT 29
1067 #define AIPS_PACRF_SP0_MASK 0x40000000u
1068 #define AIPS_PACRF_SP0_SHIFT 30
1069 /* PACRG Bit Fields */
1070 #define AIPS_PACRG_TP7_MASK 0x1u
1071 #define AIPS_PACRG_TP7_SHIFT 0
1072 #define AIPS_PACRG_WP7_MASK 0x2u
1073 #define AIPS_PACRG_WP7_SHIFT 1
1074 #define AIPS_PACRG_SP7_MASK 0x4u
1075 #define AIPS_PACRG_SP7_SHIFT 2
1076 #define AIPS_PACRG_TP6_MASK 0x10u
1077 #define AIPS_PACRG_TP6_SHIFT 4
1078 #define AIPS_PACRG_WP6_MASK 0x20u
1079 #define AIPS_PACRG_WP6_SHIFT 5
1080 #define AIPS_PACRG_SP6_MASK 0x40u
1081 #define AIPS_PACRG_SP6_SHIFT 6
1082 #define AIPS_PACRG_TP5_MASK 0x100u
1083 #define AIPS_PACRG_TP5_SHIFT 8
1084 #define AIPS_PACRG_WP5_MASK 0x200u
1085 #define AIPS_PACRG_WP5_SHIFT 9
1086 #define AIPS_PACRG_SP5_MASK 0x400u
1087 #define AIPS_PACRG_SP5_SHIFT 10
1088 #define AIPS_PACRG_TP4_MASK 0x1000u
1089 #define AIPS_PACRG_TP4_SHIFT 12
1090 #define AIPS_PACRG_WP4_MASK 0x2000u
1091 #define AIPS_PACRG_WP4_SHIFT 13
1092 #define AIPS_PACRG_SP4_MASK 0x4000u
1093 #define AIPS_PACRG_SP4_SHIFT 14
1094 #define AIPS_PACRG_TP3_MASK 0x10000u
1095 #define AIPS_PACRG_TP3_SHIFT 16
1096 #define AIPS_PACRG_WP3_MASK 0x20000u
1097 #define AIPS_PACRG_WP3_SHIFT 17
1098 #define AIPS_PACRG_SP3_MASK 0x40000u
1099 #define AIPS_PACRG_SP3_SHIFT 18
1100 #define AIPS_PACRG_TP2_MASK 0x100000u
1101 #define AIPS_PACRG_TP2_SHIFT 20
1102 #define AIPS_PACRG_WP2_MASK 0x200000u
1103 #define AIPS_PACRG_WP2_SHIFT 21
1104 #define AIPS_PACRG_SP2_MASK 0x400000u
1105 #define AIPS_PACRG_SP2_SHIFT 22
1106 #define AIPS_PACRG_TP1_MASK 0x1000000u
1107 #define AIPS_PACRG_TP1_SHIFT 24
1108 #define AIPS_PACRG_WP1_MASK 0x2000000u
1109 #define AIPS_PACRG_WP1_SHIFT 25
1110 #define AIPS_PACRG_SP1_MASK 0x4000000u
1111 #define AIPS_PACRG_SP1_SHIFT 26
1112 #define AIPS_PACRG_TP0_MASK 0x10000000u
1113 #define AIPS_PACRG_TP0_SHIFT 28
1114 #define AIPS_PACRG_WP0_MASK 0x20000000u
1115 #define AIPS_PACRG_WP0_SHIFT 29
1116 #define AIPS_PACRG_SP0_MASK 0x40000000u
1117 #define AIPS_PACRG_SP0_SHIFT 30
1118 /* PACRH Bit Fields */
1119 #define AIPS_PACRH_TP7_MASK 0x1u
1120 #define AIPS_PACRH_TP7_SHIFT 0
1121 #define AIPS_PACRH_WP7_MASK 0x2u
1122 #define AIPS_PACRH_WP7_SHIFT 1
1123 #define AIPS_PACRH_SP7_MASK 0x4u
1124 #define AIPS_PACRH_SP7_SHIFT 2
1125 #define AIPS_PACRH_TP6_MASK 0x10u
1126 #define AIPS_PACRH_TP6_SHIFT 4
1127 #define AIPS_PACRH_WP6_MASK 0x20u
1128 #define AIPS_PACRH_WP6_SHIFT 5
1129 #define AIPS_PACRH_SP6_MASK 0x40u
1130 #define AIPS_PACRH_SP6_SHIFT 6
1131 #define AIPS_PACRH_TP5_MASK 0x100u
1132 #define AIPS_PACRH_TP5_SHIFT 8
1133 #define AIPS_PACRH_WP5_MASK 0x200u
1134 #define AIPS_PACRH_WP5_SHIFT 9
1135 #define AIPS_PACRH_SP5_MASK 0x400u
1136 #define AIPS_PACRH_SP5_SHIFT 10
1137 #define AIPS_PACRH_TP4_MASK 0x1000u
1138 #define AIPS_PACRH_TP4_SHIFT 12
1139 #define AIPS_PACRH_WP4_MASK 0x2000u
1140 #define AIPS_PACRH_WP4_SHIFT 13
1141 #define AIPS_PACRH_SP4_MASK 0x4000u
1142 #define AIPS_PACRH_SP4_SHIFT 14
1143 #define AIPS_PACRH_TP3_MASK 0x10000u
1144 #define AIPS_PACRH_TP3_SHIFT 16
1145 #define AIPS_PACRH_WP3_MASK 0x20000u
1146 #define AIPS_PACRH_WP3_SHIFT 17
1147 #define AIPS_PACRH_SP3_MASK 0x40000u
1148 #define AIPS_PACRH_SP3_SHIFT 18
1149 #define AIPS_PACRH_TP2_MASK 0x100000u
1150 #define AIPS_PACRH_TP2_SHIFT 20
1151 #define AIPS_PACRH_WP2_MASK 0x200000u
1152 #define AIPS_PACRH_WP2_SHIFT 21
1153 #define AIPS_PACRH_SP2_MASK 0x400000u
1154 #define AIPS_PACRH_SP2_SHIFT 22
1155 #define AIPS_PACRH_TP1_MASK 0x1000000u
1156 #define AIPS_PACRH_TP1_SHIFT 24
1157 #define AIPS_PACRH_WP1_MASK 0x2000000u
1158 #define AIPS_PACRH_WP1_SHIFT 25
1159 #define AIPS_PACRH_SP1_MASK 0x4000000u
1160 #define AIPS_PACRH_SP1_SHIFT 26
1161 #define AIPS_PACRH_TP0_MASK 0x10000000u
1162 #define AIPS_PACRH_TP0_SHIFT 28
1163 #define AIPS_PACRH_WP0_MASK 0x20000000u
1164 #define AIPS_PACRH_WP0_SHIFT 29
1165 #define AIPS_PACRH_SP0_MASK 0x40000000u
1166 #define AIPS_PACRH_SP0_SHIFT 30
1167 /* PACRI Bit Fields */
1168 #define AIPS_PACRI_TP7_MASK 0x1u
1169 #define AIPS_PACRI_TP7_SHIFT 0
1170 #define AIPS_PACRI_WP7_MASK 0x2u
1171 #define AIPS_PACRI_WP7_SHIFT 1
1172 #define AIPS_PACRI_SP7_MASK 0x4u
1173 #define AIPS_PACRI_SP7_SHIFT 2
1174 #define AIPS_PACRI_TP6_MASK 0x10u
1175 #define AIPS_PACRI_TP6_SHIFT 4
1176 #define AIPS_PACRI_WP6_MASK 0x20u
1177 #define AIPS_PACRI_WP6_SHIFT 5
1178 #define AIPS_PACRI_SP6_MASK 0x40u
1179 #define AIPS_PACRI_SP6_SHIFT 6
1180 #define AIPS_PACRI_TP5_MASK 0x100u
1181 #define AIPS_PACRI_TP5_SHIFT 8
1182 #define AIPS_PACRI_WP5_MASK 0x200u
1183 #define AIPS_PACRI_WP5_SHIFT 9
1184 #define AIPS_PACRI_SP5_MASK 0x400u
1185 #define AIPS_PACRI_SP5_SHIFT 10
1186 #define AIPS_PACRI_TP4_MASK 0x1000u
1187 #define AIPS_PACRI_TP4_SHIFT 12
1188 #define AIPS_PACRI_WP4_MASK 0x2000u
1189 #define AIPS_PACRI_WP4_SHIFT 13
1190 #define AIPS_PACRI_SP4_MASK 0x4000u
1191 #define AIPS_PACRI_SP4_SHIFT 14
1192 #define AIPS_PACRI_TP3_MASK 0x10000u
1193 #define AIPS_PACRI_TP3_SHIFT 16
1194 #define AIPS_PACRI_WP3_MASK 0x20000u
1195 #define AIPS_PACRI_WP3_SHIFT 17
1196 #define AIPS_PACRI_SP3_MASK 0x40000u
1197 #define AIPS_PACRI_SP3_SHIFT 18
1198 #define AIPS_PACRI_TP2_MASK 0x100000u
1199 #define AIPS_PACRI_TP2_SHIFT 20
1200 #define AIPS_PACRI_WP2_MASK 0x200000u
1201 #define AIPS_PACRI_WP2_SHIFT 21
1202 #define AIPS_PACRI_SP2_MASK 0x400000u
1203 #define AIPS_PACRI_SP2_SHIFT 22
1204 #define AIPS_PACRI_TP1_MASK 0x1000000u
1205 #define AIPS_PACRI_TP1_SHIFT 24
1206 #define AIPS_PACRI_WP1_MASK 0x2000000u
1207 #define AIPS_PACRI_WP1_SHIFT 25
1208 #define AIPS_PACRI_SP1_MASK 0x4000000u
1209 #define AIPS_PACRI_SP1_SHIFT 26
1210 #define AIPS_PACRI_TP0_MASK 0x10000000u
1211 #define AIPS_PACRI_TP0_SHIFT 28
1212 #define AIPS_PACRI_WP0_MASK 0x20000000u
1213 #define AIPS_PACRI_WP0_SHIFT 29
1214 #define AIPS_PACRI_SP0_MASK 0x40000000u
1215 #define AIPS_PACRI_SP0_SHIFT 30
1216 /* PACRJ Bit Fields */
1217 #define AIPS_PACRJ_TP7_MASK 0x1u
1218 #define AIPS_PACRJ_TP7_SHIFT 0
1219 #define AIPS_PACRJ_WP7_MASK 0x2u
1220 #define AIPS_PACRJ_WP7_SHIFT 1
1221 #define AIPS_PACRJ_SP7_MASK 0x4u
1222 #define AIPS_PACRJ_SP7_SHIFT 2
1223 #define AIPS_PACRJ_TP6_MASK 0x10u
1224 #define AIPS_PACRJ_TP6_SHIFT 4
1225 #define AIPS_PACRJ_WP6_MASK 0x20u
1226 #define AIPS_PACRJ_WP6_SHIFT 5
1227 #define AIPS_PACRJ_SP6_MASK 0x40u
1228 #define AIPS_PACRJ_SP6_SHIFT 6
1229 #define AIPS_PACRJ_TP5_MASK 0x100u
1230 #define AIPS_PACRJ_TP5_SHIFT 8
1231 #define AIPS_PACRJ_WP5_MASK 0x200u
1232 #define AIPS_PACRJ_WP5_SHIFT 9
1233 #define AIPS_PACRJ_SP5_MASK 0x400u
1234 #define AIPS_PACRJ_SP5_SHIFT 10
1235 #define AIPS_PACRJ_TP4_MASK 0x1000u
1236 #define AIPS_PACRJ_TP4_SHIFT 12
1237 #define AIPS_PACRJ_WP4_MASK 0x2000u
1238 #define AIPS_PACRJ_WP4_SHIFT 13
1239 #define AIPS_PACRJ_SP4_MASK 0x4000u
1240 #define AIPS_PACRJ_SP4_SHIFT 14
1241 #define AIPS_PACRJ_TP3_MASK 0x10000u
1242 #define AIPS_PACRJ_TP3_SHIFT 16
1243 #define AIPS_PACRJ_WP3_MASK 0x20000u
1244 #define AIPS_PACRJ_WP3_SHIFT 17
1245 #define AIPS_PACRJ_SP3_MASK 0x40000u
1246 #define AIPS_PACRJ_SP3_SHIFT 18
1247 #define AIPS_PACRJ_TP2_MASK 0x100000u
1248 #define AIPS_PACRJ_TP2_SHIFT 20
1249 #define AIPS_PACRJ_WP2_MASK 0x200000u
1250 #define AIPS_PACRJ_WP2_SHIFT 21
1251 #define AIPS_PACRJ_SP2_MASK 0x400000u
1252 #define AIPS_PACRJ_SP2_SHIFT 22
1253 #define AIPS_PACRJ_TP1_MASK 0x1000000u
1254 #define AIPS_PACRJ_TP1_SHIFT 24
1255 #define AIPS_PACRJ_WP1_MASK 0x2000000u
1256 #define AIPS_PACRJ_WP1_SHIFT 25
1257 #define AIPS_PACRJ_SP1_MASK 0x4000000u
1258 #define AIPS_PACRJ_SP1_SHIFT 26
1259 #define AIPS_PACRJ_TP0_MASK 0x10000000u
1260 #define AIPS_PACRJ_TP0_SHIFT 28
1261 #define AIPS_PACRJ_WP0_MASK 0x20000000u
1262 #define AIPS_PACRJ_WP0_SHIFT 29
1263 #define AIPS_PACRJ_SP0_MASK 0x40000000u
1264 #define AIPS_PACRJ_SP0_SHIFT 30
1265 /* PACRK Bit Fields */
1266 #define AIPS_PACRK_TP7_MASK 0x1u
1267 #define AIPS_PACRK_TP7_SHIFT 0
1268 #define AIPS_PACRK_WP7_MASK 0x2u
1269 #define AIPS_PACRK_WP7_SHIFT 1
1270 #define AIPS_PACRK_SP7_MASK 0x4u
1271 #define AIPS_PACRK_SP7_SHIFT 2
1272 #define AIPS_PACRK_TP6_MASK 0x10u
1273 #define AIPS_PACRK_TP6_SHIFT 4
1274 #define AIPS_PACRK_WP6_MASK 0x20u
1275 #define AIPS_PACRK_WP6_SHIFT 5
1276 #define AIPS_PACRK_SP6_MASK 0x40u
1277 #define AIPS_PACRK_SP6_SHIFT 6
1278 #define AIPS_PACRK_TP5_MASK 0x100u
1279 #define AIPS_PACRK_TP5_SHIFT 8
1280 #define AIPS_PACRK_WP5_MASK 0x200u
1281 #define AIPS_PACRK_WP5_SHIFT 9
1282 #define AIPS_PACRK_SP5_MASK 0x400u
1283 #define AIPS_PACRK_SP5_SHIFT 10
1284 #define AIPS_PACRK_TP4_MASK 0x1000u
1285 #define AIPS_PACRK_TP4_SHIFT 12
1286 #define AIPS_PACRK_WP4_MASK 0x2000u
1287 #define AIPS_PACRK_WP4_SHIFT 13
1288 #define AIPS_PACRK_SP4_MASK 0x4000u
1289 #define AIPS_PACRK_SP4_SHIFT 14
1290 #define AIPS_PACRK_TP3_MASK 0x10000u
1291 #define AIPS_PACRK_TP3_SHIFT 16
1292 #define AIPS_PACRK_WP3_MASK 0x20000u
1293 #define AIPS_PACRK_WP3_SHIFT 17
1294 #define AIPS_PACRK_SP3_MASK 0x40000u
1295 #define AIPS_PACRK_SP3_SHIFT 18
1296 #define AIPS_PACRK_TP2_MASK 0x100000u
1297 #define AIPS_PACRK_TP2_SHIFT 20
1298 #define AIPS_PACRK_WP2_MASK 0x200000u
1299 #define AIPS_PACRK_WP2_SHIFT 21
1300 #define AIPS_PACRK_SP2_MASK 0x400000u
1301 #define AIPS_PACRK_SP2_SHIFT 22
1302 #define AIPS_PACRK_TP1_MASK 0x1000000u
1303 #define AIPS_PACRK_TP1_SHIFT 24
1304 #define AIPS_PACRK_WP1_MASK 0x2000000u
1305 #define AIPS_PACRK_WP1_SHIFT 25
1306 #define AIPS_PACRK_SP1_MASK 0x4000000u
1307 #define AIPS_PACRK_SP1_SHIFT 26
1308 #define AIPS_PACRK_TP0_MASK 0x10000000u
1309 #define AIPS_PACRK_TP0_SHIFT 28
1310 #define AIPS_PACRK_WP0_MASK 0x20000000u
1311 #define AIPS_PACRK_WP0_SHIFT 29
1312 #define AIPS_PACRK_SP0_MASK 0x40000000u
1313 #define AIPS_PACRK_SP0_SHIFT 30
1314 /* PACRL Bit Fields */
1315 #define AIPS_PACRL_TP7_MASK 0x1u
1316 #define AIPS_PACRL_TP7_SHIFT 0
1317 #define AIPS_PACRL_WP7_MASK 0x2u
1318 #define AIPS_PACRL_WP7_SHIFT 1
1319 #define AIPS_PACRL_SP7_MASK 0x4u
1320 #define AIPS_PACRL_SP7_SHIFT 2
1321 #define AIPS_PACRL_TP6_MASK 0x10u
1322 #define AIPS_PACRL_TP6_SHIFT 4
1323 #define AIPS_PACRL_WP6_MASK 0x20u
1324 #define AIPS_PACRL_WP6_SHIFT 5
1325 #define AIPS_PACRL_SP6_MASK 0x40u
1326 #define AIPS_PACRL_SP6_SHIFT 6
1327 #define AIPS_PACRL_TP5_MASK 0x100u
1328 #define AIPS_PACRL_TP5_SHIFT 8
1329 #define AIPS_PACRL_WP5_MASK 0x200u
1330 #define AIPS_PACRL_WP5_SHIFT 9
1331 #define AIPS_PACRL_SP5_MASK 0x400u
1332 #define AIPS_PACRL_SP5_SHIFT 10
1333 #define AIPS_PACRL_TP4_MASK 0x1000u
1334 #define AIPS_PACRL_TP4_SHIFT 12
1335 #define AIPS_PACRL_WP4_MASK 0x2000u
1336 #define AIPS_PACRL_WP4_SHIFT 13
1337 #define AIPS_PACRL_SP4_MASK 0x4000u
1338 #define AIPS_PACRL_SP4_SHIFT 14
1339 #define AIPS_PACRL_TP3_MASK 0x10000u
1340 #define AIPS_PACRL_TP3_SHIFT 16
1341 #define AIPS_PACRL_WP3_MASK 0x20000u
1342 #define AIPS_PACRL_WP3_SHIFT 17
1343 #define AIPS_PACRL_SP3_MASK 0x40000u
1344 #define AIPS_PACRL_SP3_SHIFT 18
1345 #define AIPS_PACRL_TP2_MASK 0x100000u
1346 #define AIPS_PACRL_TP2_SHIFT 20
1347 #define AIPS_PACRL_WP2_MASK 0x200000u
1348 #define AIPS_PACRL_WP2_SHIFT 21
1349 #define AIPS_PACRL_SP2_MASK 0x400000u
1350 #define AIPS_PACRL_SP2_SHIFT 22
1351 #define AIPS_PACRL_TP1_MASK 0x1000000u
1352 #define AIPS_PACRL_TP1_SHIFT 24
1353 #define AIPS_PACRL_WP1_MASK 0x2000000u
1354 #define AIPS_PACRL_WP1_SHIFT 25
1355 #define AIPS_PACRL_SP1_MASK 0x4000000u
1356 #define AIPS_PACRL_SP1_SHIFT 26
1357 #define AIPS_PACRL_TP0_MASK 0x10000000u
1358 #define AIPS_PACRL_TP0_SHIFT 28
1359 #define AIPS_PACRL_WP0_MASK 0x20000000u
1360 #define AIPS_PACRL_WP0_SHIFT 29
1361 #define AIPS_PACRL_SP0_MASK 0x40000000u
1362 #define AIPS_PACRL_SP0_SHIFT 30
1363 /* PACRM Bit Fields */
1364 #define AIPS_PACRM_TP7_MASK 0x1u
1365 #define AIPS_PACRM_TP7_SHIFT 0
1366 #define AIPS_PACRM_WP7_MASK 0x2u
1367 #define AIPS_PACRM_WP7_SHIFT 1
1368 #define AIPS_PACRM_SP7_MASK 0x4u
1369 #define AIPS_PACRM_SP7_SHIFT 2
1370 #define AIPS_PACRM_TP6_MASK 0x10u
1371 #define AIPS_PACRM_TP6_SHIFT 4
1372 #define AIPS_PACRM_WP6_MASK 0x20u
1373 #define AIPS_PACRM_WP6_SHIFT 5
1374 #define AIPS_PACRM_SP6_MASK 0x40u
1375 #define AIPS_PACRM_SP6_SHIFT 6
1376 #define AIPS_PACRM_TP5_MASK 0x100u
1377 #define AIPS_PACRM_TP5_SHIFT 8
1378 #define AIPS_PACRM_WP5_MASK 0x200u
1379 #define AIPS_PACRM_WP5_SHIFT 9
1380 #define AIPS_PACRM_SP5_MASK 0x400u
1381 #define AIPS_PACRM_SP5_SHIFT 10
1382 #define AIPS_PACRM_TP4_MASK 0x1000u
1383 #define AIPS_PACRM_TP4_SHIFT 12
1384 #define AIPS_PACRM_WP4_MASK 0x2000u
1385 #define AIPS_PACRM_WP4_SHIFT 13
1386 #define AIPS_PACRM_SP4_MASK 0x4000u
1387 #define AIPS_PACRM_SP4_SHIFT 14
1388 #define AIPS_PACRM_TP3_MASK 0x10000u
1389 #define AIPS_PACRM_TP3_SHIFT 16
1390 #define AIPS_PACRM_WP3_MASK 0x20000u
1391 #define AIPS_PACRM_WP3_SHIFT 17
1392 #define AIPS_PACRM_SP3_MASK 0x40000u
1393 #define AIPS_PACRM_SP3_SHIFT 18
1394 #define AIPS_PACRM_TP2_MASK 0x100000u
1395 #define AIPS_PACRM_TP2_SHIFT 20
1396 #define AIPS_PACRM_WP2_MASK 0x200000u
1397 #define AIPS_PACRM_WP2_SHIFT 21
1398 #define AIPS_PACRM_SP2_MASK 0x400000u
1399 #define AIPS_PACRM_SP2_SHIFT 22
1400 #define AIPS_PACRM_TP1_MASK 0x1000000u
1401 #define AIPS_PACRM_TP1_SHIFT 24
1402 #define AIPS_PACRM_WP1_MASK 0x2000000u
1403 #define AIPS_PACRM_WP1_SHIFT 25
1404 #define AIPS_PACRM_SP1_MASK 0x4000000u
1405 #define AIPS_PACRM_SP1_SHIFT 26
1406 #define AIPS_PACRM_TP0_MASK 0x10000000u
1407 #define AIPS_PACRM_TP0_SHIFT 28
1408 #define AIPS_PACRM_WP0_MASK 0x20000000u
1409 #define AIPS_PACRM_WP0_SHIFT 29
1410 #define AIPS_PACRM_SP0_MASK 0x40000000u
1411 #define AIPS_PACRM_SP0_SHIFT 30
1412 /* PACRN Bit Fields */
1413 #define AIPS_PACRN_TP7_MASK 0x1u
1414 #define AIPS_PACRN_TP7_SHIFT 0
1415 #define AIPS_PACRN_WP7_MASK 0x2u
1416 #define AIPS_PACRN_WP7_SHIFT 1
1417 #define AIPS_PACRN_SP7_MASK 0x4u
1418 #define AIPS_PACRN_SP7_SHIFT 2
1419 #define AIPS_PACRN_TP6_MASK 0x10u
1420 #define AIPS_PACRN_TP6_SHIFT 4
1421 #define AIPS_PACRN_WP6_MASK 0x20u
1422 #define AIPS_PACRN_WP6_SHIFT 5
1423 #define AIPS_PACRN_SP6_MASK 0x40u
1424 #define AIPS_PACRN_SP6_SHIFT 6
1425 #define AIPS_PACRN_TP5_MASK 0x100u
1426 #define AIPS_PACRN_TP5_SHIFT 8
1427 #define AIPS_PACRN_WP5_MASK 0x200u
1428 #define AIPS_PACRN_WP5_SHIFT 9
1429 #define AIPS_PACRN_SP5_MASK 0x400u
1430 #define AIPS_PACRN_SP5_SHIFT 10
1431 #define AIPS_PACRN_TP4_MASK 0x1000u
1432 #define AIPS_PACRN_TP4_SHIFT 12
1433 #define AIPS_PACRN_WP4_MASK 0x2000u
1434 #define AIPS_PACRN_WP4_SHIFT 13
1435 #define AIPS_PACRN_SP4_MASK 0x4000u
1436 #define AIPS_PACRN_SP4_SHIFT 14
1437 #define AIPS_PACRN_TP3_MASK 0x10000u
1438 #define AIPS_PACRN_TP3_SHIFT 16
1439 #define AIPS_PACRN_WP3_MASK 0x20000u
1440 #define AIPS_PACRN_WP3_SHIFT 17
1441 #define AIPS_PACRN_SP3_MASK 0x40000u
1442 #define AIPS_PACRN_SP3_SHIFT 18
1443 #define AIPS_PACRN_TP2_MASK 0x100000u
1444 #define AIPS_PACRN_TP2_SHIFT 20
1445 #define AIPS_PACRN_WP2_MASK 0x200000u
1446 #define AIPS_PACRN_WP2_SHIFT 21
1447 #define AIPS_PACRN_SP2_MASK 0x400000u
1448 #define AIPS_PACRN_SP2_SHIFT 22
1449 #define AIPS_PACRN_TP1_MASK 0x1000000u
1450 #define AIPS_PACRN_TP1_SHIFT 24
1451 #define AIPS_PACRN_WP1_MASK 0x2000000u
1452 #define AIPS_PACRN_WP1_SHIFT 25
1453 #define AIPS_PACRN_SP1_MASK 0x4000000u
1454 #define AIPS_PACRN_SP1_SHIFT 26
1455 #define AIPS_PACRN_TP0_MASK 0x10000000u
1456 #define AIPS_PACRN_TP0_SHIFT 28
1457 #define AIPS_PACRN_WP0_MASK 0x20000000u
1458 #define AIPS_PACRN_WP0_SHIFT 29
1459 #define AIPS_PACRN_SP0_MASK 0x40000000u
1460 #define AIPS_PACRN_SP0_SHIFT 30
1461 /* PACRO Bit Fields */
1462 #define AIPS_PACRO_TP7_MASK 0x1u
1463 #define AIPS_PACRO_TP7_SHIFT 0
1464 #define AIPS_PACRO_WP7_MASK 0x2u
1465 #define AIPS_PACRO_WP7_SHIFT 1
1466 #define AIPS_PACRO_SP7_MASK 0x4u
1467 #define AIPS_PACRO_SP7_SHIFT 2
1468 #define AIPS_PACRO_TP6_MASK 0x10u
1469 #define AIPS_PACRO_TP6_SHIFT 4
1470 #define AIPS_PACRO_WP6_MASK 0x20u
1471 #define AIPS_PACRO_WP6_SHIFT 5
1472 #define AIPS_PACRO_SP6_MASK 0x40u
1473 #define AIPS_PACRO_SP6_SHIFT 6
1474 #define AIPS_PACRO_TP5_MASK 0x100u
1475 #define AIPS_PACRO_TP5_SHIFT 8
1476 #define AIPS_PACRO_WP5_MASK 0x200u
1477 #define AIPS_PACRO_WP5_SHIFT 9
1478 #define AIPS_PACRO_SP5_MASK 0x400u
1479 #define AIPS_PACRO_SP5_SHIFT 10
1480 #define AIPS_PACRO_TP4_MASK 0x1000u
1481 #define AIPS_PACRO_TP4_SHIFT 12
1482 #define AIPS_PACRO_WP4_MASK 0x2000u
1483 #define AIPS_PACRO_WP4_SHIFT 13
1484 #define AIPS_PACRO_SP4_MASK 0x4000u
1485 #define AIPS_PACRO_SP4_SHIFT 14
1486 #define AIPS_PACRO_TP3_MASK 0x10000u
1487 #define AIPS_PACRO_TP3_SHIFT 16
1488 #define AIPS_PACRO_WP3_MASK 0x20000u
1489 #define AIPS_PACRO_WP3_SHIFT 17
1490 #define AIPS_PACRO_SP3_MASK 0x40000u
1491 #define AIPS_PACRO_SP3_SHIFT 18
1492 #define AIPS_PACRO_TP2_MASK 0x100000u
1493 #define AIPS_PACRO_TP2_SHIFT 20
1494 #define AIPS_PACRO_WP2_MASK 0x200000u
1495 #define AIPS_PACRO_WP2_SHIFT 21
1496 #define AIPS_PACRO_SP2_MASK 0x400000u
1497 #define AIPS_PACRO_SP2_SHIFT 22
1498 #define AIPS_PACRO_TP1_MASK 0x1000000u
1499 #define AIPS_PACRO_TP1_SHIFT 24
1500 #define AIPS_PACRO_WP1_MASK 0x2000000u
1501 #define AIPS_PACRO_WP1_SHIFT 25
1502 #define AIPS_PACRO_SP1_MASK 0x4000000u
1503 #define AIPS_PACRO_SP1_SHIFT 26
1504 #define AIPS_PACRO_TP0_MASK 0x10000000u
1505 #define AIPS_PACRO_TP0_SHIFT 28
1506 #define AIPS_PACRO_WP0_MASK 0x20000000u
1507 #define AIPS_PACRO_WP0_SHIFT 29
1508 #define AIPS_PACRO_SP0_MASK 0x40000000u
1509 #define AIPS_PACRO_SP0_SHIFT 30
1510 /* PACRP Bit Fields */
1511 #define AIPS_PACRP_TP7_MASK 0x1u
1512 #define AIPS_PACRP_TP7_SHIFT 0
1513 #define AIPS_PACRP_WP7_MASK 0x2u
1514 #define AIPS_PACRP_WP7_SHIFT 1
1515 #define AIPS_PACRP_SP7_MASK 0x4u
1516 #define AIPS_PACRP_SP7_SHIFT 2
1517 #define AIPS_PACRP_TP6_MASK 0x10u
1518 #define AIPS_PACRP_TP6_SHIFT 4
1519 #define AIPS_PACRP_WP6_MASK 0x20u
1520 #define AIPS_PACRP_WP6_SHIFT 5
1521 #define AIPS_PACRP_SP6_MASK 0x40u
1522 #define AIPS_PACRP_SP6_SHIFT 6
1523 #define AIPS_PACRP_TP5_MASK 0x100u
1524 #define AIPS_PACRP_TP5_SHIFT 8
1525 #define AIPS_PACRP_WP5_MASK 0x200u
1526 #define AIPS_PACRP_WP5_SHIFT 9
1527 #define AIPS_PACRP_SP5_MASK 0x400u
1528 #define AIPS_PACRP_SP5_SHIFT 10
1529 #define AIPS_PACRP_TP4_MASK 0x1000u
1530 #define AIPS_PACRP_TP4_SHIFT 12
1531 #define AIPS_PACRP_WP4_MASK 0x2000u
1532 #define AIPS_PACRP_WP4_SHIFT 13
1533 #define AIPS_PACRP_SP4_MASK 0x4000u
1534 #define AIPS_PACRP_SP4_SHIFT 14
1535 #define AIPS_PACRP_TP3_MASK 0x10000u
1536 #define AIPS_PACRP_TP3_SHIFT 16
1537 #define AIPS_PACRP_WP3_MASK 0x20000u
1538 #define AIPS_PACRP_WP3_SHIFT 17
1539 #define AIPS_PACRP_SP3_MASK 0x40000u
1540 #define AIPS_PACRP_SP3_SHIFT 18
1541 #define AIPS_PACRP_TP2_MASK 0x100000u
1542 #define AIPS_PACRP_TP2_SHIFT 20
1543 #define AIPS_PACRP_WP2_MASK 0x200000u
1544 #define AIPS_PACRP_WP2_SHIFT 21
1545 #define AIPS_PACRP_SP2_MASK 0x400000u
1546 #define AIPS_PACRP_SP2_SHIFT 22
1547 #define AIPS_PACRP_TP1_MASK 0x1000000u
1548 #define AIPS_PACRP_TP1_SHIFT 24
1549 #define AIPS_PACRP_WP1_MASK 0x2000000u
1550 #define AIPS_PACRP_WP1_SHIFT 25
1551 #define AIPS_PACRP_SP1_MASK 0x4000000u
1552 #define AIPS_PACRP_SP1_SHIFT 26
1553 #define AIPS_PACRP_TP0_MASK 0x10000000u
1554 #define AIPS_PACRP_TP0_SHIFT 28
1555 #define AIPS_PACRP_WP0_MASK 0x20000000u
1556 #define AIPS_PACRP_WP0_SHIFT 29
1557 #define AIPS_PACRP_SP0_MASK 0x40000000u
1558 #define AIPS_PACRP_SP0_SHIFT 30
1559 /* PACRU Bit Fields */
1560 #define AIPS_PACRU_TP1_MASK 0x1000000u
1561 #define AIPS_PACRU_TP1_SHIFT 24
1562 #define AIPS_PACRU_WP1_MASK 0x2000000u
1563 #define AIPS_PACRU_WP1_SHIFT 25
1564 #define AIPS_PACRU_SP1_MASK 0x4000000u
1565 #define AIPS_PACRU_SP1_SHIFT 26
1566 #define AIPS_PACRU_TP0_MASK 0x10000000u
1567 #define AIPS_PACRU_TP0_SHIFT 28
1568 #define AIPS_PACRU_WP0_MASK 0x20000000u
1569 #define AIPS_PACRU_WP0_SHIFT 29
1570 #define AIPS_PACRU_SP0_MASK 0x40000000u
1571 #define AIPS_PACRU_SP0_SHIFT 30
1572
1573 /*!
1574 * @}
1575 */ /* end of group AIPS_Register_Masks */
1576
1577
1578 /* AIPS - Peripheral instance base addresses */
1579 /** Peripheral AIPS0 base address */
1580 #define AIPS0_BASE (0x40000000u)
1581 /** Peripheral AIPS0 base pointer */
1582 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
1583 #define AIPS0_BASE_PTR (AIPS0)
1584 /** Peripheral AIPS1 base address */
1585 #define AIPS1_BASE (0x40080000u)
1586 /** Peripheral AIPS1 base pointer */
1587 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
1588 #define AIPS1_BASE_PTR (AIPS1)
1589 /** Array initializer of AIPS peripheral base addresses */
1590 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
1591 /** Array initializer of AIPS peripheral base pointers */
1592 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
1593
1594 /* ----------------------------------------------------------------------------
1595 -- AIPS - Register accessor macros
1596 ---------------------------------------------------------------------------- */
1597
1598 /*!
1599 * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros
1600 * @{
1601 */
1602
1603
1604 /* AIPS - Register instance definitions */
1605 /* AIPS0 */
1606 #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0)
1607 #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0)
1608 #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0)
1609 #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0)
1610 #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0)
1611 #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0)
1612 #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0)
1613 #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0)
1614 #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0)
1615 #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0)
1616 #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0)
1617 #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0)
1618 #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0)
1619 #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0)
1620 #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0)
1621 #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0)
1622 #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0)
1623 #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0)
1624 /* AIPS1 */
1625 #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1)
1626 #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1)
1627 #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1)
1628 #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1)
1629 #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1)
1630 #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1)
1631 #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1)
1632 #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1)
1633 #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1)
1634 #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1)
1635 #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1)
1636 #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1)
1637 #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1)
1638 #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1)
1639 #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1)
1640 #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1)
1641 #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1)
1642 #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1)
1643
1644 /*!
1645 * @}
1646 */ /* end of group AIPS_Register_Accessor_Macros */
1647
1648
1649 /*!
1650 * @}
1651 */ /* end of group AIPS_Peripheral_Access_Layer */
1652
1653
1654 /* ----------------------------------------------------------------------------
1655 -- AXBS Peripheral Access Layer
1656 ---------------------------------------------------------------------------- */
1657
1658 /*!
1659 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
1660 * @{
1661 */
1662
1663 /** AXBS - Register Layout Typedef */
1664 typedef struct {
1665 struct { /* offset: 0x0, array step: 0x100 */
1666 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
1667 uint8_t RESERVED_0[12];
1668 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
1669 uint8_t RESERVED_1[236];
1670 } SLAVE[5];
1671 uint8_t RESERVED_0[768];
1672 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
1673 uint8_t RESERVED_1[252];
1674 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
1675 uint8_t RESERVED_2[252];
1676 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
1677 uint8_t RESERVED_3[252];
1678 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
1679 uint8_t RESERVED_4[252];
1680 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
1681 uint8_t RESERVED_5[252];
1682 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
1683 } AXBS_Type, *AXBS_MemMapPtr;
1684
1685 /* ----------------------------------------------------------------------------
1686 -- AXBS - Register accessor macros
1687 ---------------------------------------------------------------------------- */
1688
1689 /*!
1690 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
1691 * @{
1692 */
1693
1694
1695 /* AXBS - Register accessors */
1696 #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS)
1697 #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS)
1698 #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0)
1699 #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1)
1700 #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2)
1701 #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3)
1702 #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4)
1703 #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5)
1704
1705 /*!
1706 * @}
1707 */ /* end of group AXBS_Register_Accessor_Macros */
1708
1709
1710 /* ----------------------------------------------------------------------------
1711 -- AXBS Register Masks
1712 ---------------------------------------------------------------------------- */
1713
1714 /*!
1715 * @addtogroup AXBS_Register_Masks AXBS Register Masks
1716 * @{
1717 */
1718
1719 /* PRS Bit Fields */
1720 #define AXBS_PRS_M0_MASK 0x7u
1721 #define AXBS_PRS_M0_SHIFT 0
1722 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M0_SHIFT))&AXBS_PRS_M0_MASK)
1723 #define AXBS_PRS_M1_MASK 0x70u
1724 #define AXBS_PRS_M1_SHIFT 4
1725 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M1_SHIFT))&AXBS_PRS_M1_MASK)
1726 #define AXBS_PRS_M2_MASK 0x700u
1727 #define AXBS_PRS_M2_SHIFT 8
1728 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M2_SHIFT))&AXBS_PRS_M2_MASK)
1729 #define AXBS_PRS_M3_MASK 0x7000u
1730 #define AXBS_PRS_M3_SHIFT 12
1731 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M3_SHIFT))&AXBS_PRS_M3_MASK)
1732 #define AXBS_PRS_M4_MASK 0x70000u
1733 #define AXBS_PRS_M4_SHIFT 16
1734 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M4_SHIFT))&AXBS_PRS_M4_MASK)
1735 #define AXBS_PRS_M5_MASK 0x700000u
1736 #define AXBS_PRS_M5_SHIFT 20
1737 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x))<<AXBS_PRS_M5_SHIFT))&AXBS_PRS_M5_MASK)
1738 /* CRS Bit Fields */
1739 #define AXBS_CRS_PARK_MASK 0x7u
1740 #define AXBS_CRS_PARK_SHIFT 0
1741 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PARK_SHIFT))&AXBS_CRS_PARK_MASK)
1742 #define AXBS_CRS_PCTL_MASK 0x30u
1743 #define AXBS_CRS_PCTL_SHIFT 4
1744 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_PCTL_SHIFT))&AXBS_CRS_PCTL_MASK)
1745 #define AXBS_CRS_ARB_MASK 0x300u
1746 #define AXBS_CRS_ARB_SHIFT 8
1747 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_CRS_ARB_SHIFT))&AXBS_CRS_ARB_MASK)
1748 #define AXBS_CRS_HLP_MASK 0x40000000u
1749 #define AXBS_CRS_HLP_SHIFT 30
1750 #define AXBS_CRS_RO_MASK 0x80000000u
1751 #define AXBS_CRS_RO_SHIFT 31
1752 /* MGPCR0 Bit Fields */
1753 #define AXBS_MGPCR0_AULB_MASK 0x7u
1754 #define AXBS_MGPCR0_AULB_SHIFT 0
1755 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR0_AULB_SHIFT))&AXBS_MGPCR0_AULB_MASK)
1756 /* MGPCR1 Bit Fields */
1757 #define AXBS_MGPCR1_AULB_MASK 0x7u
1758 #define AXBS_MGPCR1_AULB_SHIFT 0
1759 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR1_AULB_SHIFT))&AXBS_MGPCR1_AULB_MASK)
1760 /* MGPCR2 Bit Fields */
1761 #define AXBS_MGPCR2_AULB_MASK 0x7u
1762 #define AXBS_MGPCR2_AULB_SHIFT 0
1763 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR2_AULB_SHIFT))&AXBS_MGPCR2_AULB_MASK)
1764 /* MGPCR3 Bit Fields */
1765 #define AXBS_MGPCR3_AULB_MASK 0x7u
1766 #define AXBS_MGPCR3_AULB_SHIFT 0
1767 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR3_AULB_SHIFT))&AXBS_MGPCR3_AULB_MASK)
1768 /* MGPCR4 Bit Fields */
1769 #define AXBS_MGPCR4_AULB_MASK 0x7u
1770 #define AXBS_MGPCR4_AULB_SHIFT 0
1771 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR4_AULB_SHIFT))&AXBS_MGPCR4_AULB_MASK)
1772 /* MGPCR5 Bit Fields */
1773 #define AXBS_MGPCR5_AULB_MASK 0x7u
1774 #define AXBS_MGPCR5_AULB_SHIFT 0
1775 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x))<<AXBS_MGPCR5_AULB_SHIFT))&AXBS_MGPCR5_AULB_MASK)
1776
1777 /*!
1778 * @}
1779 */ /* end of group AXBS_Register_Masks */
1780
1781
1782 /* AXBS - Peripheral instance base addresses */
1783 /** Peripheral AXBS base address */
1784 #define AXBS_BASE (0x40004000u)
1785 /** Peripheral AXBS base pointer */
1786 #define AXBS ((AXBS_Type *)AXBS_BASE)
1787 #define AXBS_BASE_PTR (AXBS)
1788 /** Array initializer of AXBS peripheral base addresses */
1789 #define AXBS_BASE_ADDRS { AXBS_BASE }
1790 /** Array initializer of AXBS peripheral base pointers */
1791 #define AXBS_BASE_PTRS { AXBS }
1792
1793 /* ----------------------------------------------------------------------------
1794 -- AXBS - Register accessor macros
1795 ---------------------------------------------------------------------------- */
1796
1797 /*!
1798 * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros
1799 * @{
1800 */
1801
1802
1803 /* AXBS - Register instance definitions */
1804 /* AXBS */
1805 #define AXBS_PRS0 AXBS_PRS_REG(AXBS,0)
1806 #define AXBS_CRS0 AXBS_CRS_REG(AXBS,0)
1807 #define AXBS_PRS1 AXBS_PRS_REG(AXBS,1)
1808 #define AXBS_CRS1 AXBS_CRS_REG(AXBS,1)
1809 #define AXBS_PRS2 AXBS_PRS_REG(AXBS,2)
1810 #define AXBS_CRS2 AXBS_CRS_REG(AXBS,2)
1811 #define AXBS_PRS3 AXBS_PRS_REG(AXBS,3)
1812 #define AXBS_CRS3 AXBS_CRS_REG(AXBS,3)
1813 #define AXBS_PRS4 AXBS_PRS_REG(AXBS,4)
1814 #define AXBS_CRS4 AXBS_CRS_REG(AXBS,4)
1815 #define AXBS_MGPCR0 AXBS_MGPCR0_REG(AXBS)
1816 #define AXBS_MGPCR1 AXBS_MGPCR1_REG(AXBS)
1817 #define AXBS_MGPCR2 AXBS_MGPCR2_REG(AXBS)
1818 #define AXBS_MGPCR3 AXBS_MGPCR3_REG(AXBS)
1819 #define AXBS_MGPCR4 AXBS_MGPCR4_REG(AXBS)
1820 #define AXBS_MGPCR5 AXBS_MGPCR5_REG(AXBS)
1821
1822 /* AXBS - Register array accessors */
1823 #define AXBS_PRS(index) AXBS_PRS_REG(AXBS,index)
1824 #define AXBS_CRS(index) AXBS_CRS_REG(AXBS,index)
1825
1826 /*!
1827 * @}
1828 */ /* end of group AXBS_Register_Accessor_Macros */
1829
1830
1831 /*!
1832 * @}
1833 */ /* end of group AXBS_Peripheral_Access_Layer */
1834
1835
1836 /* ----------------------------------------------------------------------------
1837 -- CAN Peripheral Access Layer
1838 ---------------------------------------------------------------------------- */
1839
1840 /*!
1841 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
1842 * @{
1843 */
1844
1845 /** CAN - Register Layout Typedef */
1846 typedef struct {
1847 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
1848 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
1849 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
1850 uint8_t RESERVED_0[4];
1851 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
1852 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
1853 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
1854 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
1855 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
1856 uint8_t RESERVED_1[4];
1857 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
1858 uint8_t RESERVED_2[4];
1859 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
1860 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
1861 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
1862 uint8_t RESERVED_3[8];
1863 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
1864 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
1865 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
1866 uint8_t RESERVED_4[48];
1867 struct { /* offset: 0x80, array step: 0x10 */
1868 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
1869 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
1870 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
1871 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
1872 } MB[16];
1873 uint8_t RESERVED_5[1792];
1874 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
1875 } CAN_Type, *CAN_MemMapPtr;
1876
1877 /* ----------------------------------------------------------------------------
1878 -- CAN - Register accessor macros
1879 ---------------------------------------------------------------------------- */
1880
1881 /*!
1882 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
1883 * @{
1884 */
1885
1886
1887 /* CAN - Register accessors */
1888 #define CAN_MCR_REG(base) ((base)->MCR)
1889 #define CAN_CTRL1_REG(base) ((base)->CTRL1)
1890 #define CAN_TIMER_REG(base) ((base)->TIMER)
1891 #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK)
1892 #define CAN_RX14MASK_REG(base) ((base)->RX14MASK)
1893 #define CAN_RX15MASK_REG(base) ((base)->RX15MASK)
1894 #define CAN_ECR_REG(base) ((base)->ECR)
1895 #define CAN_ESR1_REG(base) ((base)->ESR1)
1896 #define CAN_IMASK1_REG(base) ((base)->IMASK1)
1897 #define CAN_IFLAG1_REG(base) ((base)->IFLAG1)
1898 #define CAN_CTRL2_REG(base) ((base)->CTRL2)
1899 #define CAN_ESR2_REG(base) ((base)->ESR2)
1900 #define CAN_CRCR_REG(base) ((base)->CRCR)
1901 #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK)
1902 #define CAN_RXFIR_REG(base) ((base)->RXFIR)
1903 #define CAN_CS_REG(base,index) ((base)->MB[index].CS)
1904 #define CAN_ID_REG(base,index) ((base)->MB[index].ID)
1905 #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0)
1906 #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1)
1907 #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index])
1908
1909 /*!
1910 * @}
1911 */ /* end of group CAN_Register_Accessor_Macros */
1912
1913
1914 /* ----------------------------------------------------------------------------
1915 -- CAN Register Masks
1916 ---------------------------------------------------------------------------- */
1917
1918 /*!
1919 * @addtogroup CAN_Register_Masks CAN Register Masks
1920 * @{
1921 */
1922
1923 /* MCR Bit Fields */
1924 #define CAN_MCR_MAXMB_MASK 0x7Fu
1925 #define CAN_MCR_MAXMB_SHIFT 0
1926 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_MAXMB_SHIFT))&CAN_MCR_MAXMB_MASK)
1927 #define CAN_MCR_IDAM_MASK 0x300u
1928 #define CAN_MCR_IDAM_SHIFT 8
1929 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x))<<CAN_MCR_IDAM_SHIFT))&CAN_MCR_IDAM_MASK)
1930 #define CAN_MCR_AEN_MASK 0x1000u
1931 #define CAN_MCR_AEN_SHIFT 12
1932 #define CAN_MCR_LPRIOEN_MASK 0x2000u
1933 #define CAN_MCR_LPRIOEN_SHIFT 13
1934 #define CAN_MCR_IRMQ_MASK 0x10000u
1935 #define CAN_MCR_IRMQ_SHIFT 16
1936 #define CAN_MCR_SRXDIS_MASK 0x20000u
1937 #define CAN_MCR_SRXDIS_SHIFT 17
1938 #define CAN_MCR_WAKSRC_MASK 0x80000u
1939 #define CAN_MCR_WAKSRC_SHIFT 19
1940 #define CAN_MCR_LPMACK_MASK 0x100000u
1941 #define CAN_MCR_LPMACK_SHIFT 20
1942 #define CAN_MCR_WRNEN_MASK 0x200000u
1943 #define CAN_MCR_WRNEN_SHIFT 21
1944 #define CAN_MCR_SLFWAK_MASK 0x400000u
1945 #define CAN_MCR_SLFWAK_SHIFT 22
1946 #define CAN_MCR_SUPV_MASK 0x800000u
1947 #define CAN_MCR_SUPV_SHIFT 23
1948 #define CAN_MCR_FRZACK_MASK 0x1000000u
1949 #define CAN_MCR_FRZACK_SHIFT 24
1950 #define CAN_MCR_SOFTRST_MASK 0x2000000u
1951 #define CAN_MCR_SOFTRST_SHIFT 25
1952 #define CAN_MCR_WAKMSK_MASK 0x4000000u
1953 #define CAN_MCR_WAKMSK_SHIFT 26
1954 #define CAN_MCR_NOTRDY_MASK 0x8000000u
1955 #define CAN_MCR_NOTRDY_SHIFT 27
1956 #define CAN_MCR_HALT_MASK 0x10000000u
1957 #define CAN_MCR_HALT_SHIFT 28
1958 #define CAN_MCR_RFEN_MASK 0x20000000u
1959 #define CAN_MCR_RFEN_SHIFT 29
1960 #define CAN_MCR_FRZ_MASK 0x40000000u
1961 #define CAN_MCR_FRZ_SHIFT 30
1962 #define CAN_MCR_MDIS_MASK 0x80000000u
1963 #define CAN_MCR_MDIS_SHIFT 31
1964 /* CTRL1 Bit Fields */
1965 #define CAN_CTRL1_PROPSEG_MASK 0x7u
1966 #define CAN_CTRL1_PROPSEG_SHIFT 0
1967 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PROPSEG_SHIFT))&CAN_CTRL1_PROPSEG_MASK)
1968 #define CAN_CTRL1_LOM_MASK 0x8u
1969 #define CAN_CTRL1_LOM_SHIFT 3
1970 #define CAN_CTRL1_LBUF_MASK 0x10u
1971 #define CAN_CTRL1_LBUF_SHIFT 4
1972 #define CAN_CTRL1_TSYN_MASK 0x20u
1973 #define CAN_CTRL1_TSYN_SHIFT 5
1974 #define CAN_CTRL1_BOFFREC_MASK 0x40u
1975 #define CAN_CTRL1_BOFFREC_SHIFT 6
1976 #define CAN_CTRL1_SMP_MASK 0x80u
1977 #define CAN_CTRL1_SMP_SHIFT 7
1978 #define CAN_CTRL1_RWRNMSK_MASK 0x400u
1979 #define CAN_CTRL1_RWRNMSK_SHIFT 10
1980 #define CAN_CTRL1_TWRNMSK_MASK 0x800u
1981 #define CAN_CTRL1_TWRNMSK_SHIFT 11
1982 #define CAN_CTRL1_LPB_MASK 0x1000u
1983 #define CAN_CTRL1_LPB_SHIFT 12
1984 #define CAN_CTRL1_CLKSRC_MASK 0x2000u
1985 #define CAN_CTRL1_CLKSRC_SHIFT 13
1986 #define CAN_CTRL1_ERRMSK_MASK 0x4000u
1987 #define CAN_CTRL1_ERRMSK_SHIFT 14
1988 #define CAN_CTRL1_BOFFMSK_MASK 0x8000u
1989 #define CAN_CTRL1_BOFFMSK_SHIFT 15
1990 #define CAN_CTRL1_PSEG2_MASK 0x70000u
1991 #define CAN_CTRL1_PSEG2_SHIFT 16
1992 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG2_SHIFT))&CAN_CTRL1_PSEG2_MASK)
1993 #define CAN_CTRL1_PSEG1_MASK 0x380000u
1994 #define CAN_CTRL1_PSEG1_SHIFT 19
1995 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PSEG1_SHIFT))&CAN_CTRL1_PSEG1_MASK)
1996 #define CAN_CTRL1_RJW_MASK 0xC00000u
1997 #define CAN_CTRL1_RJW_SHIFT 22
1998 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_RJW_SHIFT))&CAN_CTRL1_RJW_MASK)
1999 #define CAN_CTRL1_PRESDIV_MASK 0xFF000000u
2000 #define CAN_CTRL1_PRESDIV_SHIFT 24
2001 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL1_PRESDIV_SHIFT))&CAN_CTRL1_PRESDIV_MASK)
2002 /* TIMER Bit Fields */
2003 #define CAN_TIMER_TIMER_MASK 0xFFFFu
2004 #define CAN_TIMER_TIMER_SHIFT 0
2005 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x))<<CAN_TIMER_TIMER_SHIFT))&CAN_TIMER_TIMER_MASK)
2006 /* RXMGMASK Bit Fields */
2007 #define CAN_RXMGMASK_MG_MASK 0xFFFFFFFFu
2008 #define CAN_RXMGMASK_MG_SHIFT 0
2009 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXMGMASK_MG_SHIFT))&CAN_RXMGMASK_MG_MASK)
2010 /* RX14MASK Bit Fields */
2011 #define CAN_RX14MASK_RX14M_MASK 0xFFFFFFFFu
2012 #define CAN_RX14MASK_RX14M_SHIFT 0
2013 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX14MASK_RX14M_SHIFT))&CAN_RX14MASK_RX14M_MASK)
2014 /* RX15MASK Bit Fields */
2015 #define CAN_RX15MASK_RX15M_MASK 0xFFFFFFFFu
2016 #define CAN_RX15MASK_RX15M_SHIFT 0
2017 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x))<<CAN_RX15MASK_RX15M_SHIFT))&CAN_RX15MASK_RX15M_MASK)
2018 /* ECR Bit Fields */
2019 #define CAN_ECR_TXERRCNT_MASK 0xFFu
2020 #define CAN_ECR_TXERRCNT_SHIFT 0
2021 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_TXERRCNT_SHIFT))&CAN_ECR_TXERRCNT_MASK)
2022 #define CAN_ECR_RXERRCNT_MASK 0xFF00u
2023 #define CAN_ECR_RXERRCNT_SHIFT 8
2024 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ECR_RXERRCNT_SHIFT))&CAN_ECR_RXERRCNT_MASK)
2025 /* ESR1 Bit Fields */
2026 #define CAN_ESR1_WAKINT_MASK 0x1u
2027 #define CAN_ESR1_WAKINT_SHIFT 0
2028 #define CAN_ESR1_ERRINT_MASK 0x2u
2029 #define CAN_ESR1_ERRINT_SHIFT 1
2030 #define CAN_ESR1_BOFFINT_MASK 0x4u
2031 #define CAN_ESR1_BOFFINT_SHIFT 2
2032 #define CAN_ESR1_RX_MASK 0x8u
2033 #define CAN_ESR1_RX_SHIFT 3
2034 #define CAN_ESR1_FLTCONF_MASK 0x30u
2035 #define CAN_ESR1_FLTCONF_SHIFT 4
2036 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR1_FLTCONF_SHIFT))&CAN_ESR1_FLTCONF_MASK)
2037 #define CAN_ESR1_TX_MASK 0x40u
2038 #define CAN_ESR1_TX_SHIFT 6
2039 #define CAN_ESR1_IDLE_MASK 0x80u
2040 #define CAN_ESR1_IDLE_SHIFT 7
2041 #define CAN_ESR1_RXWRN_MASK 0x100u
2042 #define CAN_ESR1_RXWRN_SHIFT 8
2043 #define CAN_ESR1_TXWRN_MASK 0x200u
2044 #define CAN_ESR1_TXWRN_SHIFT 9
2045 #define CAN_ESR1_STFERR_MASK 0x400u
2046 #define CAN_ESR1_STFERR_SHIFT 10
2047 #define CAN_ESR1_FRMERR_MASK 0x800u
2048 #define CAN_ESR1_FRMERR_SHIFT 11
2049 #define CAN_ESR1_CRCERR_MASK 0x1000u
2050 #define CAN_ESR1_CRCERR_SHIFT 12
2051 #define CAN_ESR1_ACKERR_MASK 0x2000u
2052 #define CAN_ESR1_ACKERR_SHIFT 13
2053 #define CAN_ESR1_BIT0ERR_MASK 0x4000u
2054 #define CAN_ESR1_BIT0ERR_SHIFT 14
2055 #define CAN_ESR1_BIT1ERR_MASK 0x8000u
2056 #define CAN_ESR1_BIT1ERR_SHIFT 15
2057 #define CAN_ESR1_RWRNINT_MASK 0x10000u
2058 #define CAN_ESR1_RWRNINT_SHIFT 16
2059 #define CAN_ESR1_TWRNINT_MASK 0x20000u
2060 #define CAN_ESR1_TWRNINT_SHIFT 17
2061 #define CAN_ESR1_SYNCH_MASK 0x40000u
2062 #define CAN_ESR1_SYNCH_SHIFT 18
2063 /* IMASK1 Bit Fields */
2064 #define CAN_IMASK1_BUFLM_MASK 0xFFFFFFFFu
2065 #define CAN_IMASK1_BUFLM_SHIFT 0
2066 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x))<<CAN_IMASK1_BUFLM_SHIFT))&CAN_IMASK1_BUFLM_MASK)
2067 /* IFLAG1 Bit Fields */
2068 #define CAN_IFLAG1_BUF0I_MASK 0x1u
2069 #define CAN_IFLAG1_BUF0I_SHIFT 0
2070 #define CAN_IFLAG1_BUF4TO1I_MASK 0x1Eu
2071 #define CAN_IFLAG1_BUF4TO1I_SHIFT 1
2072 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF4TO1I_SHIFT))&CAN_IFLAG1_BUF4TO1I_MASK)
2073 #define CAN_IFLAG1_BUF5I_MASK 0x20u
2074 #define CAN_IFLAG1_BUF5I_SHIFT 5
2075 #define CAN_IFLAG1_BUF6I_MASK 0x40u
2076 #define CAN_IFLAG1_BUF6I_SHIFT 6
2077 #define CAN_IFLAG1_BUF7I_MASK 0x80u
2078 #define CAN_IFLAG1_BUF7I_SHIFT 7
2079 #define CAN_IFLAG1_BUF31TO8I_MASK 0xFFFFFF00u
2080 #define CAN_IFLAG1_BUF31TO8I_SHIFT 8
2081 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x))<<CAN_IFLAG1_BUF31TO8I_SHIFT))&CAN_IFLAG1_BUF31TO8I_MASK)
2082 /* CTRL2 Bit Fields */
2083 #define CAN_CTRL2_EACEN_MASK 0x10000u
2084 #define CAN_CTRL2_EACEN_SHIFT 16
2085 #define CAN_CTRL2_RRS_MASK 0x20000u
2086 #define CAN_CTRL2_RRS_SHIFT 17
2087 #define CAN_CTRL2_MRP_MASK 0x40000u
2088 #define CAN_CTRL2_MRP_SHIFT 18
2089 #define CAN_CTRL2_TASD_MASK 0xF80000u
2090 #define CAN_CTRL2_TASD_SHIFT 19
2091 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_TASD_SHIFT))&CAN_CTRL2_TASD_MASK)
2092 #define CAN_CTRL2_RFFN_MASK 0xF000000u
2093 #define CAN_CTRL2_RFFN_SHIFT 24
2094 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x))<<CAN_CTRL2_RFFN_SHIFT))&CAN_CTRL2_RFFN_MASK)
2095 #define CAN_CTRL2_WRMFRZ_MASK 0x10000000u
2096 #define CAN_CTRL2_WRMFRZ_SHIFT 28
2097 /* ESR2 Bit Fields */
2098 #define CAN_ESR2_IMB_MASK 0x2000u
2099 #define CAN_ESR2_IMB_SHIFT 13
2100 #define CAN_ESR2_VPS_MASK 0x4000u
2101 #define CAN_ESR2_VPS_SHIFT 14
2102 #define CAN_ESR2_LPTM_MASK 0x7F0000u
2103 #define CAN_ESR2_LPTM_SHIFT 16
2104 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x))<<CAN_ESR2_LPTM_SHIFT))&CAN_ESR2_LPTM_MASK)
2105 /* CRCR Bit Fields */
2106 #define CAN_CRCR_TXCRC_MASK 0x7FFFu
2107 #define CAN_CRCR_TXCRC_SHIFT 0
2108 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_TXCRC_SHIFT))&CAN_CRCR_TXCRC_MASK)
2109 #define CAN_CRCR_MBCRC_MASK 0x7F0000u
2110 #define CAN_CRCR_MBCRC_SHIFT 16
2111 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CRCR_MBCRC_SHIFT))&CAN_CRCR_MBCRC_MASK)
2112 /* RXFGMASK Bit Fields */
2113 #define CAN_RXFGMASK_FGM_MASK 0xFFFFFFFFu
2114 #define CAN_RXFGMASK_FGM_SHIFT 0
2115 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFGMASK_FGM_SHIFT))&CAN_RXFGMASK_FGM_MASK)
2116 /* RXFIR Bit Fields */
2117 #define CAN_RXFIR_IDHIT_MASK 0x1FFu
2118 #define CAN_RXFIR_IDHIT_SHIFT 0
2119 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXFIR_IDHIT_SHIFT))&CAN_RXFIR_IDHIT_MASK)
2120 /* CS Bit Fields */
2121 #define CAN_CS_TIME_STAMP_MASK 0xFFFFu
2122 #define CAN_CS_TIME_STAMP_SHIFT 0
2123 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_TIME_STAMP_SHIFT))&CAN_CS_TIME_STAMP_MASK)
2124 #define CAN_CS_DLC_MASK 0xF0000u
2125 #define CAN_CS_DLC_SHIFT 16
2126 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_DLC_SHIFT))&CAN_CS_DLC_MASK)
2127 #define CAN_CS_RTR_MASK 0x100000u
2128 #define CAN_CS_RTR_SHIFT 20
2129 #define CAN_CS_IDE_MASK 0x200000u
2130 #define CAN_CS_IDE_SHIFT 21
2131 #define CAN_CS_SRR_MASK 0x400000u
2132 #define CAN_CS_SRR_SHIFT 22
2133 #define CAN_CS_CODE_MASK 0xF000000u
2134 #define CAN_CS_CODE_SHIFT 24
2135 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x))<<CAN_CS_CODE_SHIFT))&CAN_CS_CODE_MASK)
2136 /* ID Bit Fields */
2137 #define CAN_ID_EXT_MASK 0x3FFFFu
2138 #define CAN_ID_EXT_SHIFT 0
2139 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_EXT_SHIFT))&CAN_ID_EXT_MASK)
2140 #define CAN_ID_STD_MASK 0x1FFC0000u
2141 #define CAN_ID_STD_SHIFT 18
2142 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_STD_SHIFT))&CAN_ID_STD_MASK)
2143 #define CAN_ID_PRIO_MASK 0xE0000000u
2144 #define CAN_ID_PRIO_SHIFT 29
2145 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x))<<CAN_ID_PRIO_SHIFT))&CAN_ID_PRIO_MASK)
2146 /* WORD0 Bit Fields */
2147 #define CAN_WORD0_DATA_BYTE_3_MASK 0xFFu
2148 #define CAN_WORD0_DATA_BYTE_3_SHIFT 0
2149 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_3_SHIFT))&CAN_WORD0_DATA_BYTE_3_MASK)
2150 #define CAN_WORD0_DATA_BYTE_2_MASK 0xFF00u
2151 #define CAN_WORD0_DATA_BYTE_2_SHIFT 8
2152 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_2_SHIFT))&CAN_WORD0_DATA_BYTE_2_MASK)
2153 #define CAN_WORD0_DATA_BYTE_1_MASK 0xFF0000u
2154 #define CAN_WORD0_DATA_BYTE_1_SHIFT 16
2155 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_1_SHIFT))&CAN_WORD0_DATA_BYTE_1_MASK)
2156 #define CAN_WORD0_DATA_BYTE_0_MASK 0xFF000000u
2157 #define CAN_WORD0_DATA_BYTE_0_SHIFT 24
2158 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD0_DATA_BYTE_0_SHIFT))&CAN_WORD0_DATA_BYTE_0_MASK)
2159 /* WORD1 Bit Fields */
2160 #define CAN_WORD1_DATA_BYTE_7_MASK 0xFFu
2161 #define CAN_WORD1_DATA_BYTE_7_SHIFT 0
2162 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_7_SHIFT))&CAN_WORD1_DATA_BYTE_7_MASK)
2163 #define CAN_WORD1_DATA_BYTE_6_MASK 0xFF00u
2164 #define CAN_WORD1_DATA_BYTE_6_SHIFT 8
2165 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_6_SHIFT))&CAN_WORD1_DATA_BYTE_6_MASK)
2166 #define CAN_WORD1_DATA_BYTE_5_MASK 0xFF0000u
2167 #define CAN_WORD1_DATA_BYTE_5_SHIFT 16
2168 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_5_SHIFT))&CAN_WORD1_DATA_BYTE_5_MASK)
2169 #define CAN_WORD1_DATA_BYTE_4_MASK 0xFF000000u
2170 #define CAN_WORD1_DATA_BYTE_4_SHIFT 24
2171 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x))<<CAN_WORD1_DATA_BYTE_4_SHIFT))&CAN_WORD1_DATA_BYTE_4_MASK)
2172 /* RXIMR Bit Fields */
2173 #define CAN_RXIMR_MI_MASK 0xFFFFFFFFu
2174 #define CAN_RXIMR_MI_SHIFT 0
2175 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x))<<CAN_RXIMR_MI_SHIFT))&CAN_RXIMR_MI_MASK)
2176
2177 /*!
2178 * @}
2179 */ /* end of group CAN_Register_Masks */
2180
2181
2182 /* CAN - Peripheral instance base addresses */
2183 /** Peripheral CAN0 base address */
2184 #define CAN0_BASE (0x40024000u)
2185 /** Peripheral CAN0 base pointer */
2186 #define CAN0 ((CAN_Type *)CAN0_BASE)
2187 #define CAN0_BASE_PTR (CAN0)
2188 /** Array initializer of CAN peripheral base addresses */
2189 #define CAN_BASE_ADDRS { CAN0_BASE }
2190 /** Array initializer of CAN peripheral base pointers */
2191 #define CAN_BASE_PTRS { CAN0 }
2192 /** Interrupt vectors for the CAN peripheral type */
2193 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
2194 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
2195 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
2196 #define CAN_Error_IRQS { CAN0_Error_IRQn }
2197 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
2198 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
2199
2200 /* ----------------------------------------------------------------------------
2201 -- CAN - Register accessor macros
2202 ---------------------------------------------------------------------------- */
2203
2204 /*!
2205 * @addtogroup CAN_Register_Accessor_Macros CAN - Register accessor macros
2206 * @{
2207 */
2208
2209
2210 /* CAN - Register instance definitions */
2211 /* CAN0 */
2212 #define CAN0_MCR CAN_MCR_REG(CAN0)
2213 #define CAN0_CTRL1 CAN_CTRL1_REG(CAN0)
2214 #define CAN0_TIMER CAN_TIMER_REG(CAN0)
2215 #define CAN0_RXMGMASK CAN_RXMGMASK_REG(CAN0)
2216 #define CAN0_RX14MASK CAN_RX14MASK_REG(CAN0)
2217 #define CAN0_RX15MASK CAN_RX15MASK_REG(CAN0)
2218 #define CAN0_ECR CAN_ECR_REG(CAN0)
2219 #define CAN0_ESR1 CAN_ESR1_REG(CAN0)
2220 #define CAN0_IMASK1 CAN_IMASK1_REG(CAN0)
2221 #define CAN0_IFLAG1 CAN_IFLAG1_REG(CAN0)
2222 #define CAN0_CTRL2 CAN_CTRL2_REG(CAN0)
2223 #define CAN0_ESR2 CAN_ESR2_REG(CAN0)
2224 #define CAN0_CRCR CAN_CRCR_REG(CAN0)
2225 #define CAN0_RXFGMASK CAN_RXFGMASK_REG(CAN0)
2226 #define CAN0_RXFIR CAN_RXFIR_REG(CAN0)
2227 #define CAN0_CS0 CAN_CS_REG(CAN0,0)
2228 #define CAN0_ID0 CAN_ID_REG(CAN0,0)
2229 #define CAN0_WORD00 CAN_WORD0_REG(CAN0,0)
2230 #define CAN0_WORD10 CAN_WORD1_REG(CAN0,0)
2231 #define CAN0_CS1 CAN_CS_REG(CAN0,1)
2232 #define CAN0_ID1 CAN_ID_REG(CAN0,1)
2233 #define CAN0_WORD01 CAN_WORD0_REG(CAN0,1)
2234 #define CAN0_WORD11 CAN_WORD1_REG(CAN0,1)
2235 #define CAN0_CS2 CAN_CS_REG(CAN0,2)
2236 #define CAN0_ID2 CAN_ID_REG(CAN0,2)
2237 #define CAN0_WORD02 CAN_WORD0_REG(CAN0,2)
2238 #define CAN0_WORD12 CAN_WORD1_REG(CAN0,2)
2239 #define CAN0_CS3 CAN_CS_REG(CAN0,3)
2240 #define CAN0_ID3 CAN_ID_REG(CAN0,3)
2241 #define CAN0_WORD03 CAN_WORD0_REG(CAN0,3)
2242 #define CAN0_WORD13 CAN_WORD1_REG(CAN0,3)
2243 #define CAN0_CS4 CAN_CS_REG(CAN0,4)
2244 #define CAN0_ID4 CAN_ID_REG(CAN0,4)
2245 #define CAN0_WORD04 CAN_WORD0_REG(CAN0,4)
2246 #define CAN0_WORD14 CAN_WORD1_REG(CAN0,4)
2247 #define CAN0_CS5 CAN_CS_REG(CAN0,5)
2248 #define CAN0_ID5 CAN_ID_REG(CAN0,5)
2249 #define CAN0_WORD05 CAN_WORD0_REG(CAN0,5)
2250 #define CAN0_WORD15 CAN_WORD1_REG(CAN0,5)
2251 #define CAN0_CS6 CAN_CS_REG(CAN0,6)
2252 #define CAN0_ID6 CAN_ID_REG(CAN0,6)
2253 #define CAN0_WORD06 CAN_WORD0_REG(CAN0,6)
2254 #define CAN0_WORD16 CAN_WORD1_REG(CAN0,6)
2255 #define CAN0_CS7 CAN_CS_REG(CAN0,7)
2256 #define CAN0_ID7 CAN_ID_REG(CAN0,7)
2257 #define CAN0_WORD07 CAN_WORD0_REG(CAN0,7)
2258 #define CAN0_WORD17 CAN_WORD1_REG(CAN0,7)
2259 #define CAN0_CS8 CAN_CS_REG(CAN0,8)
2260 #define CAN0_ID8 CAN_ID_REG(CAN0,8)
2261 #define CAN0_WORD08 CAN_WORD0_REG(CAN0,8)
2262 #define CAN0_WORD18 CAN_WORD1_REG(CAN0,8)
2263 #define CAN0_CS9 CAN_CS_REG(CAN0,9)
2264 #define CAN0_ID9 CAN_ID_REG(CAN0,9)
2265 #define CAN0_WORD09 CAN_WORD0_REG(CAN0,9)
2266 #define CAN0_WORD19 CAN_WORD1_REG(CAN0,9)
2267 #define CAN0_CS10 CAN_CS_REG(CAN0,10)
2268 #define CAN0_ID10 CAN_ID_REG(CAN0,10)
2269 #define CAN0_WORD010 CAN_WORD0_REG(CAN0,10)
2270 #define CAN0_WORD110 CAN_WORD1_REG(CAN0,10)
2271 #define CAN0_CS11 CAN_CS_REG(CAN0,11)
2272 #define CAN0_ID11 CAN_ID_REG(CAN0,11)
2273 #define CAN0_WORD011 CAN_WORD0_REG(CAN0,11)
2274 #define CAN0_WORD111 CAN_WORD1_REG(CAN0,11)
2275 #define CAN0_CS12 CAN_CS_REG(CAN0,12)
2276 #define CAN0_ID12 CAN_ID_REG(CAN0,12)
2277 #define CAN0_WORD012 CAN_WORD0_REG(CAN0,12)
2278 #define CAN0_WORD112 CAN_WORD1_REG(CAN0,12)
2279 #define CAN0_CS13 CAN_CS_REG(CAN0,13)
2280 #define CAN0_ID13 CAN_ID_REG(CAN0,13)
2281 #define CAN0_WORD013 CAN_WORD0_REG(CAN0,13)
2282 #define CAN0_WORD113 CAN_WORD1_REG(CAN0,13)
2283 #define CAN0_CS14 CAN_CS_REG(CAN0,14)
2284 #define CAN0_ID14 CAN_ID_REG(CAN0,14)
2285 #define CAN0_WORD014 CAN_WORD0_REG(CAN0,14)
2286 #define CAN0_WORD114 CAN_WORD1_REG(CAN0,14)
2287 #define CAN0_CS15 CAN_CS_REG(CAN0,15)
2288 #define CAN0_ID15 CAN_ID_REG(CAN0,15)
2289 #define CAN0_WORD015 CAN_WORD0_REG(CAN0,15)
2290 #define CAN0_WORD115 CAN_WORD1_REG(CAN0,15)
2291 #define CAN0_RXIMR0 CAN_RXIMR_REG(CAN0,0)
2292 #define CAN0_RXIMR1 CAN_RXIMR_REG(CAN0,1)
2293 #define CAN0_RXIMR2 CAN_RXIMR_REG(CAN0,2)
2294 #define CAN0_RXIMR3 CAN_RXIMR_REG(CAN0,3)
2295 #define CAN0_RXIMR4 CAN_RXIMR_REG(CAN0,4)
2296 #define CAN0_RXIMR5 CAN_RXIMR_REG(CAN0,5)
2297 #define CAN0_RXIMR6 CAN_RXIMR_REG(CAN0,6)
2298 #define CAN0_RXIMR7 CAN_RXIMR_REG(CAN0,7)
2299 #define CAN0_RXIMR8 CAN_RXIMR_REG(CAN0,8)
2300 #define CAN0_RXIMR9 CAN_RXIMR_REG(CAN0,9)
2301 #define CAN0_RXIMR10 CAN_RXIMR_REG(CAN0,10)
2302 #define CAN0_RXIMR11 CAN_RXIMR_REG(CAN0,11)
2303 #define CAN0_RXIMR12 CAN_RXIMR_REG(CAN0,12)
2304 #define CAN0_RXIMR13 CAN_RXIMR_REG(CAN0,13)
2305 #define CAN0_RXIMR14 CAN_RXIMR_REG(CAN0,14)
2306 #define CAN0_RXIMR15 CAN_RXIMR_REG(CAN0,15)
2307
2308 /* CAN - Register array accessors */
2309 #define CAN0_CS(index) CAN_CS_REG(CAN0,index)
2310 #define CAN0_ID(index) CAN_ID_REG(CAN0,index)
2311 #define CAN0_WORD0(index) CAN_WORD0_REG(CAN0,index)
2312 #define CAN0_WORD1(index) CAN_WORD1_REG(CAN0,index)
2313 #define CAN0_RXIMR(index) CAN_RXIMR_REG(CAN0,index)
2314
2315 /*!
2316 * @}
2317 */ /* end of group CAN_Register_Accessor_Macros */
2318
2319
2320 /*!
2321 * @}
2322 */ /* end of group CAN_Peripheral_Access_Layer */
2323
2324
2325 /* ----------------------------------------------------------------------------
2326 -- CAU Peripheral Access Layer
2327 ---------------------------------------------------------------------------- */
2328
2329 /*!
2330 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
2331 * @{
2332 */
2333
2334 /** CAU - Register Layout Typedef */
2335 typedef struct {
2336 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
2337 uint8_t RESERVED_0[2048];
2338 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
2339 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
2340 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
2341 uint8_t RESERVED_1[20];
2342 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
2343 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
2344 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
2345 uint8_t RESERVED_2[20];
2346 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
2347 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
2348 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
2349 uint8_t RESERVED_3[20];
2350 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
2351 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
2352 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
2353 uint8_t RESERVED_4[84];
2354 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
2355 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
2356 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
2357 uint8_t RESERVED_5[20];
2358 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
2359 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
2360 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
2361 uint8_t RESERVED_6[276];
2362 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
2363 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
2364 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
2365 uint8_t RESERVED_7[20];
2366 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
2367 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
2368 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
2369 } CAU_Type, *CAU_MemMapPtr;
2370
2371 /* ----------------------------------------------------------------------------
2372 -- CAU - Register accessor macros
2373 ---------------------------------------------------------------------------- */
2374
2375 /*!
2376 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
2377 * @{
2378 */
2379
2380
2381 /* CAU - Register accessors */
2382 #define CAU_DIRECT_REG(base,index) ((base)->DIRECT[index])
2383 #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR)
2384 #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA)
2385 #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index])
2386 #define CAU_STR_CASR_REG(base) ((base)->STR_CASR)
2387 #define CAU_STR_CAA_REG(base) ((base)->STR_CAA)
2388 #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index])
2389 #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR)
2390 #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA)
2391 #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index])
2392 #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR)
2393 #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA)
2394 #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index])
2395 #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR)
2396 #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA)
2397 #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index])
2398 #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR)
2399 #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA)
2400 #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index])
2401 #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR)
2402 #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA)
2403 #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index])
2404 #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR)
2405 #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA)
2406 #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index])
2407
2408 /*!
2409 * @}
2410 */ /* end of group CAU_Register_Accessor_Macros */
2411
2412
2413 /* ----------------------------------------------------------------------------
2414 -- CAU Register Masks
2415 ---------------------------------------------------------------------------- */
2416
2417 /*!
2418 * @addtogroup CAU_Register_Masks CAU Register Masks
2419 * @{
2420 */
2421
2422 /* DIRECT Bit Fields */
2423 #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu
2424 #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0
2425 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT0_SHIFT))&CAU_DIRECT_CAU_DIRECT0_MASK)
2426 #define CAU_DIRECT_CAU_DIRECT1_MASK 0xFFFFFFFFu
2427 #define CAU_DIRECT_CAU_DIRECT1_SHIFT 0
2428 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT1_SHIFT))&CAU_DIRECT_CAU_DIRECT1_MASK)
2429 #define CAU_DIRECT_CAU_DIRECT2_MASK 0xFFFFFFFFu
2430 #define CAU_DIRECT_CAU_DIRECT2_SHIFT 0
2431 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT2_SHIFT))&CAU_DIRECT_CAU_DIRECT2_MASK)
2432 #define CAU_DIRECT_CAU_DIRECT3_MASK 0xFFFFFFFFu
2433 #define CAU_DIRECT_CAU_DIRECT3_SHIFT 0
2434 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT3_SHIFT))&CAU_DIRECT_CAU_DIRECT3_MASK)
2435 #define CAU_DIRECT_CAU_DIRECT4_MASK 0xFFFFFFFFu
2436 #define CAU_DIRECT_CAU_DIRECT4_SHIFT 0
2437 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT4_SHIFT))&CAU_DIRECT_CAU_DIRECT4_MASK)
2438 #define CAU_DIRECT_CAU_DIRECT5_MASK 0xFFFFFFFFu
2439 #define CAU_DIRECT_CAU_DIRECT5_SHIFT 0
2440 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT5_SHIFT))&CAU_DIRECT_CAU_DIRECT5_MASK)
2441 #define CAU_DIRECT_CAU_DIRECT6_MASK 0xFFFFFFFFu
2442 #define CAU_DIRECT_CAU_DIRECT6_SHIFT 0
2443 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT6_SHIFT))&CAU_DIRECT_CAU_DIRECT6_MASK)
2444 #define CAU_DIRECT_CAU_DIRECT7_MASK 0xFFFFFFFFu
2445 #define CAU_DIRECT_CAU_DIRECT7_SHIFT 0
2446 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT7_SHIFT))&CAU_DIRECT_CAU_DIRECT7_MASK)
2447 #define CAU_DIRECT_CAU_DIRECT8_MASK 0xFFFFFFFFu
2448 #define CAU_DIRECT_CAU_DIRECT8_SHIFT 0
2449 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT8_SHIFT))&CAU_DIRECT_CAU_DIRECT8_MASK)
2450 #define CAU_DIRECT_CAU_DIRECT9_MASK 0xFFFFFFFFu
2451 #define CAU_DIRECT_CAU_DIRECT9_SHIFT 0
2452 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT9_SHIFT))&CAU_DIRECT_CAU_DIRECT9_MASK)
2453 #define CAU_DIRECT_CAU_DIRECT10_MASK 0xFFFFFFFFu
2454 #define CAU_DIRECT_CAU_DIRECT10_SHIFT 0
2455 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT10_SHIFT))&CAU_DIRECT_CAU_DIRECT10_MASK)
2456 #define CAU_DIRECT_CAU_DIRECT11_MASK 0xFFFFFFFFu
2457 #define CAU_DIRECT_CAU_DIRECT11_SHIFT 0
2458 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT11_SHIFT))&CAU_DIRECT_CAU_DIRECT11_MASK)
2459 #define CAU_DIRECT_CAU_DIRECT12_MASK 0xFFFFFFFFu
2460 #define CAU_DIRECT_CAU_DIRECT12_SHIFT 0
2461 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT12_SHIFT))&CAU_DIRECT_CAU_DIRECT12_MASK)
2462 #define CAU_DIRECT_CAU_DIRECT13_MASK 0xFFFFFFFFu
2463 #define CAU_DIRECT_CAU_DIRECT13_SHIFT 0
2464 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT13_SHIFT))&CAU_DIRECT_CAU_DIRECT13_MASK)
2465 #define CAU_DIRECT_CAU_DIRECT14_MASK 0xFFFFFFFFu
2466 #define CAU_DIRECT_CAU_DIRECT14_SHIFT 0
2467 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT14_SHIFT))&CAU_DIRECT_CAU_DIRECT14_MASK)
2468 #define CAU_DIRECT_CAU_DIRECT15_MASK 0xFFFFFFFFu
2469 #define CAU_DIRECT_CAU_DIRECT15_SHIFT 0
2470 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x))<<CAU_DIRECT_CAU_DIRECT15_SHIFT))&CAU_DIRECT_CAU_DIRECT15_MASK)
2471 /* LDR_CASR Bit Fields */
2472 #define CAU_LDR_CASR_IC_MASK 0x1u
2473 #define CAU_LDR_CASR_IC_SHIFT 0
2474 #define CAU_LDR_CASR_DPE_MASK 0x2u
2475 #define CAU_LDR_CASR_DPE_SHIFT 1
2476 #define CAU_LDR_CASR_VER_MASK 0xF0000000u
2477 #define CAU_LDR_CASR_VER_SHIFT 28
2478 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CASR_VER_SHIFT))&CAU_LDR_CASR_VER_MASK)
2479 /* LDR_CAA Bit Fields */
2480 #define CAU_LDR_CAA_ACC_MASK 0xFFFFFFFFu
2481 #define CAU_LDR_CAA_ACC_SHIFT 0
2482 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CAA_ACC_SHIFT))&CAU_LDR_CAA_ACC_MASK)
2483 /* LDR_CA Bit Fields */
2484 #define CAU_LDR_CA_CA0_MASK 0xFFFFFFFFu
2485 #define CAU_LDR_CA_CA0_SHIFT 0
2486 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA0_SHIFT))&CAU_LDR_CA_CA0_MASK)
2487 #define CAU_LDR_CA_CA1_MASK 0xFFFFFFFFu
2488 #define CAU_LDR_CA_CA1_SHIFT 0
2489 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA1_SHIFT))&CAU_LDR_CA_CA1_MASK)
2490 #define CAU_LDR_CA_CA2_MASK 0xFFFFFFFFu
2491 #define CAU_LDR_CA_CA2_SHIFT 0
2492 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA2_SHIFT))&CAU_LDR_CA_CA2_MASK)
2493 #define CAU_LDR_CA_CA3_MASK 0xFFFFFFFFu
2494 #define CAU_LDR_CA_CA3_SHIFT 0
2495 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA3_SHIFT))&CAU_LDR_CA_CA3_MASK)
2496 #define CAU_LDR_CA_CA4_MASK 0xFFFFFFFFu
2497 #define CAU_LDR_CA_CA4_SHIFT 0
2498 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA4_SHIFT))&CAU_LDR_CA_CA4_MASK)
2499 #define CAU_LDR_CA_CA5_MASK 0xFFFFFFFFu
2500 #define CAU_LDR_CA_CA5_SHIFT 0
2501 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA5_SHIFT))&CAU_LDR_CA_CA5_MASK)
2502 #define CAU_LDR_CA_CA6_MASK 0xFFFFFFFFu
2503 #define CAU_LDR_CA_CA6_SHIFT 0
2504 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA6_SHIFT))&CAU_LDR_CA_CA6_MASK)
2505 #define CAU_LDR_CA_CA7_MASK 0xFFFFFFFFu
2506 #define CAU_LDR_CA_CA7_SHIFT 0
2507 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA7_SHIFT))&CAU_LDR_CA_CA7_MASK)
2508 #define CAU_LDR_CA_CA8_MASK 0xFFFFFFFFu
2509 #define CAU_LDR_CA_CA8_SHIFT 0
2510 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_LDR_CA_CA8_SHIFT))&CAU_LDR_CA_CA8_MASK)
2511 /* STR_CASR Bit Fields */
2512 #define CAU_STR_CASR_IC_MASK 0x1u
2513 #define CAU_STR_CASR_IC_SHIFT 0
2514 #define CAU_STR_CASR_DPE_MASK 0x2u
2515 #define CAU_STR_CASR_DPE_SHIFT 1
2516 #define CAU_STR_CASR_VER_MASK 0xF0000000u
2517 #define CAU_STR_CASR_VER_SHIFT 28
2518 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CASR_VER_SHIFT))&CAU_STR_CASR_VER_MASK)
2519 /* STR_CAA Bit Fields */
2520 #define CAU_STR_CAA_ACC_MASK 0xFFFFFFFFu
2521 #define CAU_STR_CAA_ACC_SHIFT 0
2522 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CAA_ACC_SHIFT))&CAU_STR_CAA_ACC_MASK)
2523 /* STR_CA Bit Fields */
2524 #define CAU_STR_CA_CA0_MASK 0xFFFFFFFFu
2525 #define CAU_STR_CA_CA0_SHIFT 0
2526 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA0_SHIFT))&CAU_STR_CA_CA0_MASK)
2527 #define CAU_STR_CA_CA1_MASK 0xFFFFFFFFu
2528 #define CAU_STR_CA_CA1_SHIFT 0
2529 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA1_SHIFT))&CAU_STR_CA_CA1_MASK)
2530 #define CAU_STR_CA_CA2_MASK 0xFFFFFFFFu
2531 #define CAU_STR_CA_CA2_SHIFT 0
2532 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA2_SHIFT))&CAU_STR_CA_CA2_MASK)
2533 #define CAU_STR_CA_CA3_MASK 0xFFFFFFFFu
2534 #define CAU_STR_CA_CA3_SHIFT 0
2535 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA3_SHIFT))&CAU_STR_CA_CA3_MASK)
2536 #define CAU_STR_CA_CA4_MASK 0xFFFFFFFFu
2537 #define CAU_STR_CA_CA4_SHIFT 0
2538 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA4_SHIFT))&CAU_STR_CA_CA4_MASK)
2539 #define CAU_STR_CA_CA5_MASK 0xFFFFFFFFu
2540 #define CAU_STR_CA_CA5_SHIFT 0
2541 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA5_SHIFT))&CAU_STR_CA_CA5_MASK)
2542 #define CAU_STR_CA_CA6_MASK 0xFFFFFFFFu
2543 #define CAU_STR_CA_CA6_SHIFT 0
2544 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA6_SHIFT))&CAU_STR_CA_CA6_MASK)
2545 #define CAU_STR_CA_CA7_MASK 0xFFFFFFFFu
2546 #define CAU_STR_CA_CA7_SHIFT 0
2547 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA7_SHIFT))&CAU_STR_CA_CA7_MASK)
2548 #define CAU_STR_CA_CA8_MASK 0xFFFFFFFFu
2549 #define CAU_STR_CA_CA8_SHIFT 0
2550 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_STR_CA_CA8_SHIFT))&CAU_STR_CA_CA8_MASK)
2551 /* ADR_CASR Bit Fields */
2552 #define CAU_ADR_CASR_IC_MASK 0x1u
2553 #define CAU_ADR_CASR_IC_SHIFT 0
2554 #define CAU_ADR_CASR_DPE_MASK 0x2u
2555 #define CAU_ADR_CASR_DPE_SHIFT 1
2556 #define CAU_ADR_CASR_VER_MASK 0xF0000000u
2557 #define CAU_ADR_CASR_VER_SHIFT 28
2558 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CASR_VER_SHIFT))&CAU_ADR_CASR_VER_MASK)
2559 /* ADR_CAA Bit Fields */
2560 #define CAU_ADR_CAA_ACC_MASK 0xFFFFFFFFu
2561 #define CAU_ADR_CAA_ACC_SHIFT 0
2562 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CAA_ACC_SHIFT))&CAU_ADR_CAA_ACC_MASK)
2563 /* ADR_CA Bit Fields */
2564 #define CAU_ADR_CA_CA0_MASK 0xFFFFFFFFu
2565 #define CAU_ADR_CA_CA0_SHIFT 0
2566 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA0_SHIFT))&CAU_ADR_CA_CA0_MASK)
2567 #define CAU_ADR_CA_CA1_MASK 0xFFFFFFFFu
2568 #define CAU_ADR_CA_CA1_SHIFT 0
2569 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA1_SHIFT))&CAU_ADR_CA_CA1_MASK)
2570 #define CAU_ADR_CA_CA2_MASK 0xFFFFFFFFu
2571 #define CAU_ADR_CA_CA2_SHIFT 0
2572 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA2_SHIFT))&CAU_ADR_CA_CA2_MASK)
2573 #define CAU_ADR_CA_CA3_MASK 0xFFFFFFFFu
2574 #define CAU_ADR_CA_CA3_SHIFT 0
2575 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA3_SHIFT))&CAU_ADR_CA_CA3_MASK)
2576 #define CAU_ADR_CA_CA4_MASK 0xFFFFFFFFu
2577 #define CAU_ADR_CA_CA4_SHIFT 0
2578 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA4_SHIFT))&CAU_ADR_CA_CA4_MASK)
2579 #define CAU_ADR_CA_CA5_MASK 0xFFFFFFFFu
2580 #define CAU_ADR_CA_CA5_SHIFT 0
2581 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA5_SHIFT))&CAU_ADR_CA_CA5_MASK)
2582 #define CAU_ADR_CA_CA6_MASK 0xFFFFFFFFu
2583 #define CAU_ADR_CA_CA6_SHIFT 0
2584 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA6_SHIFT))&CAU_ADR_CA_CA6_MASK)
2585 #define CAU_ADR_CA_CA7_MASK 0xFFFFFFFFu
2586 #define CAU_ADR_CA_CA7_SHIFT 0
2587 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA7_SHIFT))&CAU_ADR_CA_CA7_MASK)
2588 #define CAU_ADR_CA_CA8_MASK 0xFFFFFFFFu
2589 #define CAU_ADR_CA_CA8_SHIFT 0
2590 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ADR_CA_CA8_SHIFT))&CAU_ADR_CA_CA8_MASK)
2591 /* RADR_CASR Bit Fields */
2592 #define CAU_RADR_CASR_IC_MASK 0x1u
2593 #define CAU_RADR_CASR_IC_SHIFT 0
2594 #define CAU_RADR_CASR_DPE_MASK 0x2u
2595 #define CAU_RADR_CASR_DPE_SHIFT 1
2596 #define CAU_RADR_CASR_VER_MASK 0xF0000000u
2597 #define CAU_RADR_CASR_VER_SHIFT 28
2598 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CASR_VER_SHIFT))&CAU_RADR_CASR_VER_MASK)
2599 /* RADR_CAA Bit Fields */
2600 #define CAU_RADR_CAA_ACC_MASK 0xFFFFFFFFu
2601 #define CAU_RADR_CAA_ACC_SHIFT 0
2602 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CAA_ACC_SHIFT))&CAU_RADR_CAA_ACC_MASK)
2603 /* RADR_CA Bit Fields */
2604 #define CAU_RADR_CA_CA0_MASK 0xFFFFFFFFu
2605 #define CAU_RADR_CA_CA0_SHIFT 0
2606 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA0_SHIFT))&CAU_RADR_CA_CA0_MASK)
2607 #define CAU_RADR_CA_CA1_MASK 0xFFFFFFFFu
2608 #define CAU_RADR_CA_CA1_SHIFT 0
2609 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA1_SHIFT))&CAU_RADR_CA_CA1_MASK)
2610 #define CAU_RADR_CA_CA2_MASK 0xFFFFFFFFu
2611 #define CAU_RADR_CA_CA2_SHIFT 0
2612 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA2_SHIFT))&CAU_RADR_CA_CA2_MASK)
2613 #define CAU_RADR_CA_CA3_MASK 0xFFFFFFFFu
2614 #define CAU_RADR_CA_CA3_SHIFT 0
2615 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA3_SHIFT))&CAU_RADR_CA_CA3_MASK)
2616 #define CAU_RADR_CA_CA4_MASK 0xFFFFFFFFu
2617 #define CAU_RADR_CA_CA4_SHIFT 0
2618 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA4_SHIFT))&CAU_RADR_CA_CA4_MASK)
2619 #define CAU_RADR_CA_CA5_MASK 0xFFFFFFFFu
2620 #define CAU_RADR_CA_CA5_SHIFT 0
2621 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA5_SHIFT))&CAU_RADR_CA_CA5_MASK)
2622 #define CAU_RADR_CA_CA6_MASK 0xFFFFFFFFu
2623 #define CAU_RADR_CA_CA6_SHIFT 0
2624 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA6_SHIFT))&CAU_RADR_CA_CA6_MASK)
2625 #define CAU_RADR_CA_CA7_MASK 0xFFFFFFFFu
2626 #define CAU_RADR_CA_CA7_SHIFT 0
2627 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA7_SHIFT))&CAU_RADR_CA_CA7_MASK)
2628 #define CAU_RADR_CA_CA8_MASK 0xFFFFFFFFu
2629 #define CAU_RADR_CA_CA8_SHIFT 0
2630 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_RADR_CA_CA8_SHIFT))&CAU_RADR_CA_CA8_MASK)
2631 /* XOR_CASR Bit Fields */
2632 #define CAU_XOR_CASR_IC_MASK 0x1u
2633 #define CAU_XOR_CASR_IC_SHIFT 0
2634 #define CAU_XOR_CASR_DPE_MASK 0x2u
2635 #define CAU_XOR_CASR_DPE_SHIFT 1
2636 #define CAU_XOR_CASR_VER_MASK 0xF0000000u
2637 #define CAU_XOR_CASR_VER_SHIFT 28
2638 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CASR_VER_SHIFT))&CAU_XOR_CASR_VER_MASK)
2639 /* XOR_CAA Bit Fields */
2640 #define CAU_XOR_CAA_ACC_MASK 0xFFFFFFFFu
2641 #define CAU_XOR_CAA_ACC_SHIFT 0
2642 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CAA_ACC_SHIFT))&CAU_XOR_CAA_ACC_MASK)
2643 /* XOR_CA Bit Fields */
2644 #define CAU_XOR_CA_CA0_MASK 0xFFFFFFFFu
2645 #define CAU_XOR_CA_CA0_SHIFT 0
2646 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA0_SHIFT))&CAU_XOR_CA_CA0_MASK)
2647 #define CAU_XOR_CA_CA1_MASK 0xFFFFFFFFu
2648 #define CAU_XOR_CA_CA1_SHIFT 0
2649 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA1_SHIFT))&CAU_XOR_CA_CA1_MASK)
2650 #define CAU_XOR_CA_CA2_MASK 0xFFFFFFFFu
2651 #define CAU_XOR_CA_CA2_SHIFT 0
2652 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA2_SHIFT))&CAU_XOR_CA_CA2_MASK)
2653 #define CAU_XOR_CA_CA3_MASK 0xFFFFFFFFu
2654 #define CAU_XOR_CA_CA3_SHIFT 0
2655 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA3_SHIFT))&CAU_XOR_CA_CA3_MASK)
2656 #define CAU_XOR_CA_CA4_MASK 0xFFFFFFFFu
2657 #define CAU_XOR_CA_CA4_SHIFT 0
2658 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA4_SHIFT))&CAU_XOR_CA_CA4_MASK)
2659 #define CAU_XOR_CA_CA5_MASK 0xFFFFFFFFu
2660 #define CAU_XOR_CA_CA5_SHIFT 0
2661 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA5_SHIFT))&CAU_XOR_CA_CA5_MASK)
2662 #define CAU_XOR_CA_CA6_MASK 0xFFFFFFFFu
2663 #define CAU_XOR_CA_CA6_SHIFT 0
2664 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA6_SHIFT))&CAU_XOR_CA_CA6_MASK)
2665 #define CAU_XOR_CA_CA7_MASK 0xFFFFFFFFu
2666 #define CAU_XOR_CA_CA7_SHIFT 0
2667 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA7_SHIFT))&CAU_XOR_CA_CA7_MASK)
2668 #define CAU_XOR_CA_CA8_MASK 0xFFFFFFFFu
2669 #define CAU_XOR_CA_CA8_SHIFT 0
2670 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_XOR_CA_CA8_SHIFT))&CAU_XOR_CA_CA8_MASK)
2671 /* ROTL_CASR Bit Fields */
2672 #define CAU_ROTL_CASR_IC_MASK 0x1u
2673 #define CAU_ROTL_CASR_IC_SHIFT 0
2674 #define CAU_ROTL_CASR_DPE_MASK 0x2u
2675 #define CAU_ROTL_CASR_DPE_SHIFT 1
2676 #define CAU_ROTL_CASR_VER_MASK 0xF0000000u
2677 #define CAU_ROTL_CASR_VER_SHIFT 28
2678 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CASR_VER_SHIFT))&CAU_ROTL_CASR_VER_MASK)
2679 /* ROTL_CAA Bit Fields */
2680 #define CAU_ROTL_CAA_ACC_MASK 0xFFFFFFFFu
2681 #define CAU_ROTL_CAA_ACC_SHIFT 0
2682 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CAA_ACC_SHIFT))&CAU_ROTL_CAA_ACC_MASK)
2683 /* ROTL_CA Bit Fields */
2684 #define CAU_ROTL_CA_CA0_MASK 0xFFFFFFFFu
2685 #define CAU_ROTL_CA_CA0_SHIFT 0
2686 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA0_SHIFT))&CAU_ROTL_CA_CA0_MASK)
2687 #define CAU_ROTL_CA_CA1_MASK 0xFFFFFFFFu
2688 #define CAU_ROTL_CA_CA1_SHIFT 0
2689 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA1_SHIFT))&CAU_ROTL_CA_CA1_MASK)
2690 #define CAU_ROTL_CA_CA2_MASK 0xFFFFFFFFu
2691 #define CAU_ROTL_CA_CA2_SHIFT 0
2692 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA2_SHIFT))&CAU_ROTL_CA_CA2_MASK)
2693 #define CAU_ROTL_CA_CA3_MASK 0xFFFFFFFFu
2694 #define CAU_ROTL_CA_CA3_SHIFT 0
2695 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA3_SHIFT))&CAU_ROTL_CA_CA3_MASK)
2696 #define CAU_ROTL_CA_CA4_MASK 0xFFFFFFFFu
2697 #define CAU_ROTL_CA_CA4_SHIFT 0
2698 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA4_SHIFT))&CAU_ROTL_CA_CA4_MASK)
2699 #define CAU_ROTL_CA_CA5_MASK 0xFFFFFFFFu
2700 #define CAU_ROTL_CA_CA5_SHIFT 0
2701 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA5_SHIFT))&CAU_ROTL_CA_CA5_MASK)
2702 #define CAU_ROTL_CA_CA6_MASK 0xFFFFFFFFu
2703 #define CAU_ROTL_CA_CA6_SHIFT 0
2704 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA6_SHIFT))&CAU_ROTL_CA_CA6_MASK)
2705 #define CAU_ROTL_CA_CA7_MASK 0xFFFFFFFFu
2706 #define CAU_ROTL_CA_CA7_SHIFT 0
2707 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA7_SHIFT))&CAU_ROTL_CA_CA7_MASK)
2708 #define CAU_ROTL_CA_CA8_MASK 0xFFFFFFFFu
2709 #define CAU_ROTL_CA_CA8_SHIFT 0
2710 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_ROTL_CA_CA8_SHIFT))&CAU_ROTL_CA_CA8_MASK)
2711 /* AESC_CASR Bit Fields */
2712 #define CAU_AESC_CASR_IC_MASK 0x1u
2713 #define CAU_AESC_CASR_IC_SHIFT 0
2714 #define CAU_AESC_CASR_DPE_MASK 0x2u
2715 #define CAU_AESC_CASR_DPE_SHIFT 1
2716 #define CAU_AESC_CASR_VER_MASK 0xF0000000u
2717 #define CAU_AESC_CASR_VER_SHIFT 28
2718 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CASR_VER_SHIFT))&CAU_AESC_CASR_VER_MASK)
2719 /* AESC_CAA Bit Fields */
2720 #define CAU_AESC_CAA_ACC_MASK 0xFFFFFFFFu
2721 #define CAU_AESC_CAA_ACC_SHIFT 0
2722 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CAA_ACC_SHIFT))&CAU_AESC_CAA_ACC_MASK)
2723 /* AESC_CA Bit Fields */
2724 #define CAU_AESC_CA_CA0_MASK 0xFFFFFFFFu
2725 #define CAU_AESC_CA_CA0_SHIFT 0
2726 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA0_SHIFT))&CAU_AESC_CA_CA0_MASK)
2727 #define CAU_AESC_CA_CA1_MASK 0xFFFFFFFFu
2728 #define CAU_AESC_CA_CA1_SHIFT 0
2729 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA1_SHIFT))&CAU_AESC_CA_CA1_MASK)
2730 #define CAU_AESC_CA_CA2_MASK 0xFFFFFFFFu
2731 #define CAU_AESC_CA_CA2_SHIFT 0
2732 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA2_SHIFT))&CAU_AESC_CA_CA2_MASK)
2733 #define CAU_AESC_CA_CA3_MASK 0xFFFFFFFFu
2734 #define CAU_AESC_CA_CA3_SHIFT 0
2735 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA3_SHIFT))&CAU_AESC_CA_CA3_MASK)
2736 #define CAU_AESC_CA_CA4_MASK 0xFFFFFFFFu
2737 #define CAU_AESC_CA_CA4_SHIFT 0
2738 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA4_SHIFT))&CAU_AESC_CA_CA4_MASK)
2739 #define CAU_AESC_CA_CA5_MASK 0xFFFFFFFFu
2740 #define CAU_AESC_CA_CA5_SHIFT 0
2741 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA5_SHIFT))&CAU_AESC_CA_CA5_MASK)
2742 #define CAU_AESC_CA_CA6_MASK 0xFFFFFFFFu
2743 #define CAU_AESC_CA_CA6_SHIFT 0
2744 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA6_SHIFT))&CAU_AESC_CA_CA6_MASK)
2745 #define CAU_AESC_CA_CA7_MASK 0xFFFFFFFFu
2746 #define CAU_AESC_CA_CA7_SHIFT 0
2747 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA7_SHIFT))&CAU_AESC_CA_CA7_MASK)
2748 #define CAU_AESC_CA_CA8_MASK 0xFFFFFFFFu
2749 #define CAU_AESC_CA_CA8_SHIFT 0
2750 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESC_CA_CA8_SHIFT))&CAU_AESC_CA_CA8_MASK)
2751 /* AESIC_CASR Bit Fields */
2752 #define CAU_AESIC_CASR_IC_MASK 0x1u
2753 #define CAU_AESIC_CASR_IC_SHIFT 0
2754 #define CAU_AESIC_CASR_DPE_MASK 0x2u
2755 #define CAU_AESIC_CASR_DPE_SHIFT 1
2756 #define CAU_AESIC_CASR_VER_MASK 0xF0000000u
2757 #define CAU_AESIC_CASR_VER_SHIFT 28
2758 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CASR_VER_SHIFT))&CAU_AESIC_CASR_VER_MASK)
2759 /* AESIC_CAA Bit Fields */
2760 #define CAU_AESIC_CAA_ACC_MASK 0xFFFFFFFFu
2761 #define CAU_AESIC_CAA_ACC_SHIFT 0
2762 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CAA_ACC_SHIFT))&CAU_AESIC_CAA_ACC_MASK)
2763 /* AESIC_CA Bit Fields */
2764 #define CAU_AESIC_CA_CA0_MASK 0xFFFFFFFFu
2765 #define CAU_AESIC_CA_CA0_SHIFT 0
2766 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA0_SHIFT))&CAU_AESIC_CA_CA0_MASK)
2767 #define CAU_AESIC_CA_CA1_MASK 0xFFFFFFFFu
2768 #define CAU_AESIC_CA_CA1_SHIFT 0
2769 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA1_SHIFT))&CAU_AESIC_CA_CA1_MASK)
2770 #define CAU_AESIC_CA_CA2_MASK 0xFFFFFFFFu
2771 #define CAU_AESIC_CA_CA2_SHIFT 0
2772 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA2_SHIFT))&CAU_AESIC_CA_CA2_MASK)
2773 #define CAU_AESIC_CA_CA3_MASK 0xFFFFFFFFu
2774 #define CAU_AESIC_CA_CA3_SHIFT 0
2775 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA3_SHIFT))&CAU_AESIC_CA_CA3_MASK)
2776 #define CAU_AESIC_CA_CA4_MASK 0xFFFFFFFFu
2777 #define CAU_AESIC_CA_CA4_SHIFT 0
2778 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA4_SHIFT))&CAU_AESIC_CA_CA4_MASK)
2779 #define CAU_AESIC_CA_CA5_MASK 0xFFFFFFFFu
2780 #define CAU_AESIC_CA_CA5_SHIFT 0
2781 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA5_SHIFT))&CAU_AESIC_CA_CA5_MASK)
2782 #define CAU_AESIC_CA_CA6_MASK 0xFFFFFFFFu
2783 #define CAU_AESIC_CA_CA6_SHIFT 0
2784 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA6_SHIFT))&CAU_AESIC_CA_CA6_MASK)
2785 #define CAU_AESIC_CA_CA7_MASK 0xFFFFFFFFu
2786 #define CAU_AESIC_CA_CA7_SHIFT 0
2787 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA7_SHIFT))&CAU_AESIC_CA_CA7_MASK)
2788 #define CAU_AESIC_CA_CA8_MASK 0xFFFFFFFFu
2789 #define CAU_AESIC_CA_CA8_SHIFT 0
2790 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x))<<CAU_AESIC_CA_CA8_SHIFT))&CAU_AESIC_CA_CA8_MASK)
2791
2792 /*!
2793 * @}
2794 */ /* end of group CAU_Register_Masks */
2795
2796
2797 /* CAU - Peripheral instance base addresses */
2798 /** Peripheral CAU base address */
2799 #define CAU_BASE (0xE0081000u)
2800 /** Peripheral CAU base pointer */
2801 #define CAU ((CAU_Type *)CAU_BASE)
2802 #define CAU_BASE_PTR (CAU)
2803 /** Array initializer of CAU peripheral base addresses */
2804 #define CAU_BASE_ADDRS { CAU_BASE }
2805 /** Array initializer of CAU peripheral base pointers */
2806 #define CAU_BASE_PTRS { CAU }
2807
2808 /* ----------------------------------------------------------------------------
2809 -- CAU - Register accessor macros
2810 ---------------------------------------------------------------------------- */
2811
2812 /*!
2813 * @addtogroup CAU_Register_Accessor_Macros CAU - Register accessor macros
2814 * @{
2815 */
2816
2817
2818 /* CAU - Register instance definitions */
2819 /* CAU */
2820 #define CAU_DIRECT0 CAU_DIRECT_REG(CAU,0)
2821 #define CAU_DIRECT1 CAU_DIRECT_REG(CAU,1)
2822 #define CAU_DIRECT2 CAU_DIRECT_REG(CAU,2)
2823 #define CAU_DIRECT3 CAU_DIRECT_REG(CAU,3)
2824 #define CAU_DIRECT4 CAU_DIRECT_REG(CAU,4)
2825 #define CAU_DIRECT5 CAU_DIRECT_REG(CAU,5)
2826 #define CAU_DIRECT6 CAU_DIRECT_REG(CAU,6)
2827 #define CAU_DIRECT7 CAU_DIRECT_REG(CAU,7)
2828 #define CAU_DIRECT8 CAU_DIRECT_REG(CAU,8)
2829 #define CAU_DIRECT9 CAU_DIRECT_REG(CAU,9)
2830 #define CAU_DIRECT10 CAU_DIRECT_REG(CAU,10)
2831 #define CAU_DIRECT11 CAU_DIRECT_REG(CAU,11)
2832 #define CAU_DIRECT12 CAU_DIRECT_REG(CAU,12)
2833 #define CAU_DIRECT13 CAU_DIRECT_REG(CAU,13)
2834 #define CAU_DIRECT14 CAU_DIRECT_REG(CAU,14)
2835 #define CAU_DIRECT15 CAU_DIRECT_REG(CAU,15)
2836 #define CAU_LDR_CASR CAU_LDR_CASR_REG(CAU)
2837 #define CAU_LDR_CAA CAU_LDR_CAA_REG(CAU)
2838 #define CAU_LDR_CA0 CAU_LDR_CA_REG(CAU,0)
2839 #define CAU_LDR_CA1 CAU_LDR_CA_REG(CAU,1)
2840 #define CAU_LDR_CA2 CAU_LDR_CA_REG(CAU,2)
2841 #define CAU_LDR_CA3 CAU_LDR_CA_REG(CAU,3)
2842 #define CAU_LDR_CA4 CAU_LDR_CA_REG(CAU,4)
2843 #define CAU_LDR_CA5 CAU_LDR_CA_REG(CAU,5)
2844 #define CAU_LDR_CA6 CAU_LDR_CA_REG(CAU,6)
2845 #define CAU_LDR_CA7 CAU_LDR_CA_REG(CAU,7)
2846 #define CAU_LDR_CA8 CAU_LDR_CA_REG(CAU,8)
2847 #define CAU_STR_CASR CAU_STR_CASR_REG(CAU)
2848 #define CAU_STR_CAA CAU_STR_CAA_REG(CAU)
2849 #define CAU_STR_CA0 CAU_STR_CA_REG(CAU,0)
2850 #define CAU_STR_CA1 CAU_STR_CA_REG(CAU,1)
2851 #define CAU_STR_CA2 CAU_STR_CA_REG(CAU,2)
2852 #define CAU_STR_CA3 CAU_STR_CA_REG(CAU,3)
2853 #define CAU_STR_CA4 CAU_STR_CA_REG(CAU,4)
2854 #define CAU_STR_CA5 CAU_STR_CA_REG(CAU,5)
2855 #define CAU_STR_CA6 CAU_STR_CA_REG(CAU,6)
2856 #define CAU_STR_CA7 CAU_STR_CA_REG(CAU,7)
2857 #define CAU_STR_CA8 CAU_STR_CA_REG(CAU,8)
2858 #define CAU_ADR_CASR CAU_ADR_CASR_REG(CAU)
2859 #define CAU_ADR_CAA CAU_ADR_CAA_REG(CAU)
2860 #define CAU_ADR_CA0 CAU_ADR_CA_REG(CAU,0)
2861 #define CAU_ADR_CA1 CAU_ADR_CA_REG(CAU,1)
2862 #define CAU_ADR_CA2 CAU_ADR_CA_REG(CAU,2)
2863 #define CAU_ADR_CA3 CAU_ADR_CA_REG(CAU,3)
2864 #define CAU_ADR_CA4 CAU_ADR_CA_REG(CAU,4)
2865 #define CAU_ADR_CA5 CAU_ADR_CA_REG(CAU,5)
2866 #define CAU_ADR_CA6 CAU_ADR_CA_REG(CAU,6)
2867 #define CAU_ADR_CA7 CAU_ADR_CA_REG(CAU,7)
2868 #define CAU_ADR_CA8 CAU_ADR_CA_REG(CAU,8)
2869 #define CAU_RADR_CASR CAU_RADR_CASR_REG(CAU)
2870 #define CAU_RADR_CAA CAU_RADR_CAA_REG(CAU)
2871 #define CAU_RADR_CA0 CAU_RADR_CA_REG(CAU,0)
2872 #define CAU_RADR_CA1 CAU_RADR_CA_REG(CAU,1)
2873 #define CAU_RADR_CA2 CAU_RADR_CA_REG(CAU,2)
2874 #define CAU_RADR_CA3 CAU_RADR_CA_REG(CAU,3)
2875 #define CAU_RADR_CA4 CAU_RADR_CA_REG(CAU,4)
2876 #define CAU_RADR_CA5 CAU_RADR_CA_REG(CAU,5)
2877 #define CAU_RADR_CA6 CAU_RADR_CA_REG(CAU,6)
2878 #define CAU_RADR_CA7 CAU_RADR_CA_REG(CAU,7)
2879 #define CAU_RADR_CA8 CAU_RADR_CA_REG(CAU,8)
2880 #define CAU_XOR_CASR CAU_XOR_CASR_REG(CAU)
2881 #define CAU_XOR_CAA CAU_XOR_CAA_REG(CAU)
2882 #define CAU_XOR_CA0 CAU_XOR_CA_REG(CAU,0)
2883 #define CAU_XOR_CA1 CAU_XOR_CA_REG(CAU,1)
2884 #define CAU_XOR_CA2 CAU_XOR_CA_REG(CAU,2)
2885 #define CAU_XOR_CA3 CAU_XOR_CA_REG(CAU,3)
2886 #define CAU_XOR_CA4 CAU_XOR_CA_REG(CAU,4)
2887 #define CAU_XOR_CA5 CAU_XOR_CA_REG(CAU,5)
2888 #define CAU_XOR_CA6 CAU_XOR_CA_REG(CAU,6)
2889 #define CAU_XOR_CA7 CAU_XOR_CA_REG(CAU,7)
2890 #define CAU_XOR_CA8 CAU_XOR_CA_REG(CAU,8)
2891 #define CAU_ROTL_CASR CAU_ROTL_CASR_REG(CAU)
2892 #define CAU_ROTL_CAA CAU_ROTL_CAA_REG(CAU)
2893 #define CAU_ROTL_CA0 CAU_ROTL_CA_REG(CAU,0)
2894 #define CAU_ROTL_CA1 CAU_ROTL_CA_REG(CAU,1)
2895 #define CAU_ROTL_CA2 CAU_ROTL_CA_REG(CAU,2)
2896 #define CAU_ROTL_CA3 CAU_ROTL_CA_REG(CAU,3)
2897 #define CAU_ROTL_CA4 CAU_ROTL_CA_REG(CAU,4)
2898 #define CAU_ROTL_CA5 CAU_ROTL_CA_REG(CAU,5)
2899 #define CAU_ROTL_CA6 CAU_ROTL_CA_REG(CAU,6)
2900 #define CAU_ROTL_CA7 CAU_ROTL_CA_REG(CAU,7)
2901 #define CAU_ROTL_CA8 CAU_ROTL_CA_REG(CAU,8)
2902 #define CAU_AESC_CASR CAU_AESC_CASR_REG(CAU)
2903 #define CAU_AESC_CAA CAU_AESC_CAA_REG(CAU)
2904 #define CAU_AESC_CA0 CAU_AESC_CA_REG(CAU,0)
2905 #define CAU_AESC_CA1 CAU_AESC_CA_REG(CAU,1)
2906 #define CAU_AESC_CA2 CAU_AESC_CA_REG(CAU,2)
2907 #define CAU_AESC_CA3 CAU_AESC_CA_REG(CAU,3)
2908 #define CAU_AESC_CA4 CAU_AESC_CA_REG(CAU,4)
2909 #define CAU_AESC_CA5 CAU_AESC_CA_REG(CAU,5)
2910 #define CAU_AESC_CA6 CAU_AESC_CA_REG(CAU,6)
2911 #define CAU_AESC_CA7 CAU_AESC_CA_REG(CAU,7)
2912 #define CAU_AESC_CA8 CAU_AESC_CA_REG(CAU,8)
2913 #define CAU_AESIC_CASR CAU_AESIC_CASR_REG(CAU)
2914 #define CAU_AESIC_CAA CAU_AESIC_CAA_REG(CAU)
2915 #define CAU_AESIC_CA0 CAU_AESIC_CA_REG(CAU,0)
2916 #define CAU_AESIC_CA1 CAU_AESIC_CA_REG(CAU,1)
2917 #define CAU_AESIC_CA2 CAU_AESIC_CA_REG(CAU,2)
2918 #define CAU_AESIC_CA3 CAU_AESIC_CA_REG(CAU,3)
2919 #define CAU_AESIC_CA4 CAU_AESIC_CA_REG(CAU,4)
2920 #define CAU_AESIC_CA5 CAU_AESIC_CA_REG(CAU,5)
2921 #define CAU_AESIC_CA6 CAU_AESIC_CA_REG(CAU,6)
2922 #define CAU_AESIC_CA7 CAU_AESIC_CA_REG(CAU,7)
2923 #define CAU_AESIC_CA8 CAU_AESIC_CA_REG(CAU,8)
2924
2925 /* CAU - Register array accessors */
2926 #define CAU_DIRECT(index) CAU_DIRECT_REG(CAU,index)
2927 #define CAU_LDR_CA(index) CAU_LDR_CA_REG(CAU,index)
2928 #define CAU_STR_CA(index) CAU_STR_CA_REG(CAU,index)
2929 #define CAU_ADR_CA(index) CAU_ADR_CA_REG(CAU,index)
2930 #define CAU_RADR_CA(index) CAU_RADR_CA_REG(CAU,index)
2931 #define CAU_XOR_CA(index) CAU_XOR_CA_REG(CAU,index)
2932 #define CAU_ROTL_CA(index) CAU_ROTL_CA_REG(CAU,index)
2933 #define CAU_AESC_CA(index) CAU_AESC_CA_REG(CAU,index)
2934 #define CAU_AESIC_CA(index) CAU_AESIC_CA_REG(CAU,index)
2935
2936 /*!
2937 * @}
2938 */ /* end of group CAU_Register_Accessor_Macros */
2939
2940
2941 /*!
2942 * @}
2943 */ /* end of group CAU_Peripheral_Access_Layer */
2944
2945
2946 /* ----------------------------------------------------------------------------
2947 -- CMP Peripheral Access Layer
2948 ---------------------------------------------------------------------------- */
2949
2950 /*!
2951 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
2952 * @{
2953 */
2954
2955 /** CMP - Register Layout Typedef */
2956 typedef struct {
2957 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
2958 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
2959 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
2960 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
2961 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
2962 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
2963 } CMP_Type, *CMP_MemMapPtr;
2964
2965 /* ----------------------------------------------------------------------------
2966 -- CMP - Register accessor macros
2967 ---------------------------------------------------------------------------- */
2968
2969 /*!
2970 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
2971 * @{
2972 */
2973
2974
2975 /* CMP - Register accessors */
2976 #define CMP_CR0_REG(base) ((base)->CR0)
2977 #define CMP_CR1_REG(base) ((base)->CR1)
2978 #define CMP_FPR_REG(base) ((base)->FPR)
2979 #define CMP_SCR_REG(base) ((base)->SCR)
2980 #define CMP_DACCR_REG(base) ((base)->DACCR)
2981 #define CMP_MUXCR_REG(base) ((base)->MUXCR)
2982
2983 /*!
2984 * @}
2985 */ /* end of group CMP_Register_Accessor_Macros */
2986
2987
2988 /* ----------------------------------------------------------------------------
2989 -- CMP Register Masks
2990 ---------------------------------------------------------------------------- */
2991
2992 /*!
2993 * @addtogroup CMP_Register_Masks CMP Register Masks
2994 * @{
2995 */
2996
2997 /* CR0 Bit Fields */
2998 #define CMP_CR0_HYSTCTR_MASK 0x3u
2999 #define CMP_CR0_HYSTCTR_SHIFT 0
3000 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
3001 #define CMP_CR0_FILTER_CNT_MASK 0x70u
3002 #define CMP_CR0_FILTER_CNT_SHIFT 4
3003 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
3004 /* CR1 Bit Fields */
3005 #define CMP_CR1_EN_MASK 0x1u
3006 #define CMP_CR1_EN_SHIFT 0
3007 #define CMP_CR1_OPE_MASK 0x2u
3008 #define CMP_CR1_OPE_SHIFT 1
3009 #define CMP_CR1_COS_MASK 0x4u
3010 #define CMP_CR1_COS_SHIFT 2
3011 #define CMP_CR1_INV_MASK 0x8u
3012 #define CMP_CR1_INV_SHIFT 3
3013 #define CMP_CR1_PMODE_MASK 0x10u
3014 #define CMP_CR1_PMODE_SHIFT 4
3015 #define CMP_CR1_WE_MASK 0x40u
3016 #define CMP_CR1_WE_SHIFT 6
3017 #define CMP_CR1_SE_MASK 0x80u
3018 #define CMP_CR1_SE_SHIFT 7
3019 /* FPR Bit Fields */
3020 #define CMP_FPR_FILT_PER_MASK 0xFFu
3021 #define CMP_FPR_FILT_PER_SHIFT 0
3022 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
3023 /* SCR Bit Fields */
3024 #define CMP_SCR_COUT_MASK 0x1u
3025 #define CMP_SCR_COUT_SHIFT 0
3026 #define CMP_SCR_CFF_MASK 0x2u
3027 #define CMP_SCR_CFF_SHIFT 1
3028 #define CMP_SCR_CFR_MASK 0x4u
3029 #define CMP_SCR_CFR_SHIFT 2
3030 #define CMP_SCR_IEF_MASK 0x8u
3031 #define CMP_SCR_IEF_SHIFT 3
3032 #define CMP_SCR_IER_MASK 0x10u
3033 #define CMP_SCR_IER_SHIFT 4
3034 #define CMP_SCR_DMAEN_MASK 0x40u
3035 #define CMP_SCR_DMAEN_SHIFT 6
3036 /* DACCR Bit Fields */
3037 #define CMP_DACCR_VOSEL_MASK 0x3Fu
3038 #define CMP_DACCR_VOSEL_SHIFT 0
3039 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
3040 #define CMP_DACCR_VRSEL_MASK 0x40u
3041 #define CMP_DACCR_VRSEL_SHIFT 6
3042 #define CMP_DACCR_DACEN_MASK 0x80u
3043 #define CMP_DACCR_DACEN_SHIFT 7
3044 /* MUXCR Bit Fields */
3045 #define CMP_MUXCR_MSEL_MASK 0x7u
3046 #define CMP_MUXCR_MSEL_SHIFT 0
3047 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
3048 #define CMP_MUXCR_PSEL_MASK 0x38u
3049 #define CMP_MUXCR_PSEL_SHIFT 3
3050 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
3051 #define CMP_MUXCR_PSTM_MASK 0x80u
3052 #define CMP_MUXCR_PSTM_SHIFT 7
3053
3054 /*!
3055 * @}
3056 */ /* end of group CMP_Register_Masks */
3057
3058
3059 /* CMP - Peripheral instance base addresses */
3060 /** Peripheral CMP0 base address */
3061 #define CMP0_BASE (0x40073000u)
3062 /** Peripheral CMP0 base pointer */
3063 #define CMP0 ((CMP_Type *)CMP0_BASE)
3064 #define CMP0_BASE_PTR (CMP0)
3065 /** Peripheral CMP1 base address */
3066 #define CMP1_BASE (0x40073008u)
3067 /** Peripheral CMP1 base pointer */
3068 #define CMP1 ((CMP_Type *)CMP1_BASE)
3069 #define CMP1_BASE_PTR (CMP1)
3070 /** Peripheral CMP2 base address */
3071 #define CMP2_BASE (0x40073010u)
3072 /** Peripheral CMP2 base pointer */
3073 #define CMP2 ((CMP_Type *)CMP2_BASE)
3074 #define CMP2_BASE_PTR (CMP2)
3075 /** Array initializer of CMP peripheral base addresses */
3076 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
3077 /** Array initializer of CMP peripheral base pointers */
3078 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
3079 /** Interrupt vectors for the CMP peripheral type */
3080 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
3081
3082 /* ----------------------------------------------------------------------------
3083 -- CMP - Register accessor macros
3084 ---------------------------------------------------------------------------- */
3085
3086 /*!
3087 * @addtogroup CMP_Register_Accessor_Macros CMP - Register accessor macros
3088 * @{
3089 */
3090
3091
3092 /* CMP - Register instance definitions */
3093 /* CMP0 */
3094 #define CMP0_CR0 CMP_CR0_REG(CMP0)
3095 #define CMP0_CR1 CMP_CR1_REG(CMP0)
3096 #define CMP0_FPR CMP_FPR_REG(CMP0)
3097 #define CMP0_SCR CMP_SCR_REG(CMP0)
3098 #define CMP0_DACCR CMP_DACCR_REG(CMP0)
3099 #define CMP0_MUXCR CMP_MUXCR_REG(CMP0)
3100 /* CMP1 */
3101 #define CMP1_CR0 CMP_CR0_REG(CMP1)
3102 #define CMP1_CR1 CMP_CR1_REG(CMP1)
3103 #define CMP1_FPR CMP_FPR_REG(CMP1)
3104 #define CMP1_SCR CMP_SCR_REG(CMP1)
3105 #define CMP1_DACCR CMP_DACCR_REG(CMP1)
3106 #define CMP1_MUXCR CMP_MUXCR_REG(CMP1)
3107 /* CMP2 */
3108 #define CMP2_CR0 CMP_CR0_REG(CMP2)
3109 #define CMP2_CR1 CMP_CR1_REG(CMP2)
3110 #define CMP2_FPR CMP_FPR_REG(CMP2)
3111 #define CMP2_SCR CMP_SCR_REG(CMP2)
3112 #define CMP2_DACCR CMP_DACCR_REG(CMP2)
3113 #define CMP2_MUXCR CMP_MUXCR_REG(CMP2)
3114
3115 /*!
3116 * @}
3117 */ /* end of group CMP_Register_Accessor_Macros */
3118
3119
3120 /*!
3121 * @}
3122 */ /* end of group CMP_Peripheral_Access_Layer */
3123
3124
3125 /* ----------------------------------------------------------------------------
3126 -- CMT Peripheral Access Layer
3127 ---------------------------------------------------------------------------- */
3128
3129 /*!
3130 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
3131 * @{
3132 */
3133
3134 /** CMT - Register Layout Typedef */
3135 typedef struct {
3136 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
3137 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
3138 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
3139 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
3140 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
3141 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
3142 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
3143 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
3144 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
3145 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
3146 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
3147 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
3148 } CMT_Type, *CMT_MemMapPtr;
3149
3150 /* ----------------------------------------------------------------------------
3151 -- CMT - Register accessor macros
3152 ---------------------------------------------------------------------------- */
3153
3154 /*!
3155 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
3156 * @{
3157 */
3158
3159
3160 /* CMT - Register accessors */
3161 #define CMT_CGH1_REG(base) ((base)->CGH1)
3162 #define CMT_CGL1_REG(base) ((base)->CGL1)
3163 #define CMT_CGH2_REG(base) ((base)->CGH2)
3164 #define CMT_CGL2_REG(base) ((base)->CGL2)
3165 #define CMT_OC_REG(base) ((base)->OC)
3166 #define CMT_MSC_REG(base) ((base)->MSC)
3167 #define CMT_CMD1_REG(base) ((base)->CMD1)
3168 #define CMT_CMD2_REG(base) ((base)->CMD2)
3169 #define CMT_CMD3_REG(base) ((base)->CMD3)
3170 #define CMT_CMD4_REG(base) ((base)->CMD4)
3171 #define CMT_PPS_REG(base) ((base)->PPS)
3172 #define CMT_DMA_REG(base) ((base)->DMA)
3173
3174 /*!
3175 * @}
3176 */ /* end of group CMT_Register_Accessor_Macros */
3177
3178
3179 /* ----------------------------------------------------------------------------
3180 -- CMT Register Masks
3181 ---------------------------------------------------------------------------- */
3182
3183 /*!
3184 * @addtogroup CMT_Register_Masks CMT Register Masks
3185 * @{
3186 */
3187
3188 /* CGH1 Bit Fields */
3189 #define CMT_CGH1_PH_MASK 0xFFu
3190 #define CMT_CGH1_PH_SHIFT 0
3191 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH1_PH_SHIFT))&CMT_CGH1_PH_MASK)
3192 /* CGL1 Bit Fields */
3193 #define CMT_CGL1_PL_MASK 0xFFu
3194 #define CMT_CGL1_PL_SHIFT 0
3195 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL1_PL_SHIFT))&CMT_CGL1_PL_MASK)
3196 /* CGH2 Bit Fields */
3197 #define CMT_CGH2_SH_MASK 0xFFu
3198 #define CMT_CGH2_SH_SHIFT 0
3199 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGH2_SH_SHIFT))&CMT_CGH2_SH_MASK)
3200 /* CGL2 Bit Fields */
3201 #define CMT_CGL2_SL_MASK 0xFFu
3202 #define CMT_CGL2_SL_SHIFT 0
3203 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x))<<CMT_CGL2_SL_SHIFT))&CMT_CGL2_SL_MASK)
3204 /* OC Bit Fields */
3205 #define CMT_OC_IROPEN_MASK 0x20u
3206 #define CMT_OC_IROPEN_SHIFT 5
3207 #define CMT_OC_CMTPOL_MASK 0x40u
3208 #define CMT_OC_CMTPOL_SHIFT 6
3209 #define CMT_OC_IROL_MASK 0x80u
3210 #define CMT_OC_IROL_SHIFT 7
3211 /* MSC Bit Fields */
3212 #define CMT_MSC_MCGEN_MASK 0x1u
3213 #define CMT_MSC_MCGEN_SHIFT 0
3214 #define CMT_MSC_EOCIE_MASK 0x2u
3215 #define CMT_MSC_EOCIE_SHIFT 1
3216 #define CMT_MSC_FSK_MASK 0x4u
3217 #define CMT_MSC_FSK_SHIFT 2
3218 #define CMT_MSC_BASE_MASK 0x8u
3219 #define CMT_MSC_BASE_SHIFT 3
3220 #define CMT_MSC_EXSPC_MASK 0x10u
3221 #define CMT_MSC_EXSPC_SHIFT 4
3222 #define CMT_MSC_CMTDIV_MASK 0x60u
3223 #define CMT_MSC_CMTDIV_SHIFT 5
3224 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_MSC_CMTDIV_SHIFT))&CMT_MSC_CMTDIV_MASK)
3225 #define CMT_MSC_EOCF_MASK 0x80u
3226 #define CMT_MSC_EOCF_SHIFT 7
3227 /* CMD1 Bit Fields */
3228 #define CMT_CMD1_MB_MASK 0xFFu
3229 #define CMT_CMD1_MB_SHIFT 0
3230 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD1_MB_SHIFT))&CMT_CMD1_MB_MASK)
3231 /* CMD2 Bit Fields */
3232 #define CMT_CMD2_MB_MASK 0xFFu
3233 #define CMT_CMD2_MB_SHIFT 0
3234 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD2_MB_SHIFT))&CMT_CMD2_MB_MASK)
3235 /* CMD3 Bit Fields */
3236 #define CMT_CMD3_SB_MASK 0xFFu
3237 #define CMT_CMD3_SB_SHIFT 0
3238 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD3_SB_SHIFT))&CMT_CMD3_SB_MASK)
3239 /* CMD4 Bit Fields */
3240 #define CMT_CMD4_SB_MASK 0xFFu
3241 #define CMT_CMD4_SB_SHIFT 0
3242 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x))<<CMT_CMD4_SB_SHIFT))&CMT_CMD4_SB_MASK)
3243 /* PPS Bit Fields */
3244 #define CMT_PPS_PPSDIV_MASK 0xFu
3245 #define CMT_PPS_PPSDIV_SHIFT 0
3246 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x))<<CMT_PPS_PPSDIV_SHIFT))&CMT_PPS_PPSDIV_MASK)
3247 /* DMA Bit Fields */
3248 #define CMT_DMA_DMA_MASK 0x1u
3249 #define CMT_DMA_DMA_SHIFT 0
3250
3251 /*!
3252 * @}
3253 */ /* end of group CMT_Register_Masks */
3254
3255
3256 /* CMT - Peripheral instance base addresses */
3257 /** Peripheral CMT base address */
3258 #define CMT_BASE (0x40062000u)
3259 /** Peripheral CMT base pointer */
3260 #define CMT ((CMT_Type *)CMT_BASE)
3261 #define CMT_BASE_PTR (CMT)
3262 /** Array initializer of CMT peripheral base addresses */
3263 #define CMT_BASE_ADDRS { CMT_BASE }
3264 /** Array initializer of CMT peripheral base pointers */
3265 #define CMT_BASE_PTRS { CMT }
3266 /** Interrupt vectors for the CMT peripheral type */
3267 #define CMT_IRQS { CMT_IRQn }
3268
3269 /* ----------------------------------------------------------------------------
3270 -- CMT - Register accessor macros
3271 ---------------------------------------------------------------------------- */
3272
3273 /*!
3274 * @addtogroup CMT_Register_Accessor_Macros CMT - Register accessor macros
3275 * @{
3276 */
3277
3278
3279 /* CMT - Register instance definitions */
3280 /* CMT */
3281 #define CMT_CGH1 CMT_CGH1_REG(CMT)
3282 #define CMT_CGL1 CMT_CGL1_REG(CMT)
3283 #define CMT_CGH2 CMT_CGH2_REG(CMT)
3284 #define CMT_CGL2 CMT_CGL2_REG(CMT)
3285 #define CMT_OC CMT_OC_REG(CMT)
3286 #define CMT_MSC CMT_MSC_REG(CMT)
3287 #define CMT_CMD1 CMT_CMD1_REG(CMT)
3288 #define CMT_CMD2 CMT_CMD2_REG(CMT)
3289 #define CMT_CMD3 CMT_CMD3_REG(CMT)
3290 #define CMT_CMD4 CMT_CMD4_REG(CMT)
3291 #define CMT_PPS CMT_PPS_REG(CMT)
3292 #define CMT_DMA CMT_DMA_REG(CMT)
3293
3294 /*!
3295 * @}
3296 */ /* end of group CMT_Register_Accessor_Macros */
3297
3298
3299 /*!
3300 * @}
3301 */ /* end of group CMT_Peripheral_Access_Layer */
3302
3303
3304 /* ----------------------------------------------------------------------------
3305 -- CRC Peripheral Access Layer
3306 ---------------------------------------------------------------------------- */
3307
3308 /*!
3309 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
3310 * @{
3311 */
3312
3313 /** CRC - Register Layout Typedef */
3314 typedef struct {
3315 union { /* offset: 0x0 */
3316 struct { /* offset: 0x0 */
3317 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
3318 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
3319 } ACCESS16BIT;
3320 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
3321 struct { /* offset: 0x0 */
3322 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
3323 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
3324 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
3325 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
3326 } ACCESS8BIT;
3327 };
3328 union { /* offset: 0x4 */
3329 struct { /* offset: 0x4 */
3330 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
3331 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
3332 } GPOLY_ACCESS16BIT;
3333 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
3334 struct { /* offset: 0x4 */
3335 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
3336 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
3337 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
3338 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
3339 } GPOLY_ACCESS8BIT;
3340 };
3341 union { /* offset: 0x8 */
3342 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
3343 struct { /* offset: 0x8 */
3344 uint8_t RESERVED_0[3];
3345 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
3346 } CTRL_ACCESS8BIT;
3347 };
3348 } CRC_Type, *CRC_MemMapPtr;
3349
3350 /* ----------------------------------------------------------------------------
3351 -- CRC - Register accessor macros
3352 ---------------------------------------------------------------------------- */
3353
3354 /*!
3355 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
3356 * @{
3357 */
3358
3359
3360 /* CRC - Register accessors */
3361 #define CRC_DATAL_REG(base) ((base)->ACCESS16BIT.DATAL)
3362 #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH)
3363 #define CRC_DATA_REG(base) ((base)->DATA)
3364 #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL)
3365 #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU)
3366 #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL)
3367 #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU)
3368 #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL)
3369 #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH)
3370 #define CRC_GPOLY_REG(base) ((base)->GPOLY)
3371 #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL)
3372 #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU)
3373 #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL)
3374 #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU)
3375 #define CRC_CTRL_REG(base) ((base)->CTRL)
3376 #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU)
3377
3378 /*!
3379 * @}
3380 */ /* end of group CRC_Register_Accessor_Macros */
3381
3382
3383 /* ----------------------------------------------------------------------------
3384 -- CRC Register Masks
3385 ---------------------------------------------------------------------------- */
3386
3387 /*!
3388 * @addtogroup CRC_Register_Masks CRC Register Masks
3389 * @{
3390 */
3391
3392 /* DATAL Bit Fields */
3393 #define CRC_DATAL_DATAL_MASK 0xFFFFu
3394 #define CRC_DATAL_DATAL_SHIFT 0
3395 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAL_DATAL_SHIFT))&CRC_DATAL_DATAL_MASK)
3396 /* DATAH Bit Fields */
3397 #define CRC_DATAH_DATAH_MASK 0xFFFFu
3398 #define CRC_DATAH_DATAH_SHIFT 0
3399 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x))<<CRC_DATAH_DATAH_SHIFT))&CRC_DATAH_DATAH_MASK)
3400 /* DATA Bit Fields */
3401 #define CRC_DATA_LL_MASK 0xFFu
3402 #define CRC_DATA_LL_SHIFT 0
3403 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LL_SHIFT))&CRC_DATA_LL_MASK)
3404 #define CRC_DATA_LU_MASK 0xFF00u
3405 #define CRC_DATA_LU_SHIFT 8
3406 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_LU_SHIFT))&CRC_DATA_LU_MASK)
3407 #define CRC_DATA_HL_MASK 0xFF0000u
3408 #define CRC_DATA_HL_SHIFT 16
3409 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HL_SHIFT))&CRC_DATA_HL_MASK)
3410 #define CRC_DATA_HU_MASK 0xFF000000u
3411 #define CRC_DATA_HU_SHIFT 24
3412 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x))<<CRC_DATA_HU_SHIFT))&CRC_DATA_HU_MASK)
3413 /* DATALL Bit Fields */
3414 #define CRC_DATALL_DATALL_MASK 0xFFu
3415 #define CRC_DATALL_DATALL_SHIFT 0
3416 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALL_DATALL_SHIFT))&CRC_DATALL_DATALL_MASK)
3417 /* DATALU Bit Fields */
3418 #define CRC_DATALU_DATALU_MASK 0xFFu
3419 #define CRC_DATALU_DATALU_SHIFT 0
3420 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATALU_DATALU_SHIFT))&CRC_DATALU_DATALU_MASK)
3421 /* DATAHL Bit Fields */
3422 #define CRC_DATAHL_DATAHL_MASK 0xFFu
3423 #define CRC_DATAHL_DATAHL_SHIFT 0
3424 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHL_DATAHL_SHIFT))&CRC_DATAHL_DATAHL_MASK)
3425 /* DATAHU Bit Fields */
3426 #define CRC_DATAHU_DATAHU_MASK 0xFFu
3427 #define CRC_DATAHU_DATAHU_SHIFT 0
3428 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_DATAHU_DATAHU_SHIFT))&CRC_DATAHU_DATAHU_MASK)
3429 /* GPOLYL Bit Fields */
3430 #define CRC_GPOLYL_GPOLYL_MASK 0xFFFFu
3431 #define CRC_GPOLYL_GPOLYL_SHIFT 0
3432 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYL_GPOLYL_SHIFT))&CRC_GPOLYL_GPOLYL_MASK)
3433 /* GPOLYH Bit Fields */
3434 #define CRC_GPOLYH_GPOLYH_MASK 0xFFFFu
3435 #define CRC_GPOLYH_GPOLYH_SHIFT 0
3436 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x))<<CRC_GPOLYH_GPOLYH_SHIFT))&CRC_GPOLYH_GPOLYH_MASK)
3437 /* GPOLY Bit Fields */
3438 #define CRC_GPOLY_LOW_MASK 0xFFFFu
3439 #define CRC_GPOLY_LOW_SHIFT 0
3440 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_LOW_SHIFT))&CRC_GPOLY_LOW_MASK)
3441 #define CRC_GPOLY_HIGH_MASK 0xFFFF0000u
3442 #define CRC_GPOLY_HIGH_SHIFT 16
3443 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x))<<CRC_GPOLY_HIGH_SHIFT))&CRC_GPOLY_HIGH_MASK)
3444 /* GPOLYLL Bit Fields */
3445 #define CRC_GPOLYLL_GPOLYLL_MASK 0xFFu
3446 #define CRC_GPOLYLL_GPOLYLL_SHIFT 0
3447 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLL_GPOLYLL_SHIFT))&CRC_GPOLYLL_GPOLYLL_MASK)
3448 /* GPOLYLU Bit Fields */
3449 #define CRC_GPOLYLU_GPOLYLU_MASK 0xFFu
3450 #define CRC_GPOLYLU_GPOLYLU_SHIFT 0
3451 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYLU_GPOLYLU_SHIFT))&CRC_GPOLYLU_GPOLYLU_MASK)
3452 /* GPOLYHL Bit Fields */
3453 #define CRC_GPOLYHL_GPOLYHL_MASK 0xFFu
3454 #define CRC_GPOLYHL_GPOLYHL_SHIFT 0
3455 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHL_GPOLYHL_SHIFT))&CRC_GPOLYHL_GPOLYHL_MASK)
3456 /* GPOLYHU Bit Fields */
3457 #define CRC_GPOLYHU_GPOLYHU_MASK 0xFFu
3458 #define CRC_GPOLYHU_GPOLYHU_SHIFT 0
3459 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x))<<CRC_GPOLYHU_GPOLYHU_SHIFT))&CRC_GPOLYHU_GPOLYHU_MASK)
3460 /* CTRL Bit Fields */
3461 #define CRC_CTRL_TCRC_MASK 0x1000000u
3462 #define CRC_CTRL_TCRC_SHIFT 24
3463 #define CRC_CTRL_WAS_MASK 0x2000000u
3464 #define CRC_CTRL_WAS_SHIFT 25
3465 #define CRC_CTRL_FXOR_MASK 0x4000000u
3466 #define CRC_CTRL_FXOR_SHIFT 26
3467 #define CRC_CTRL_TOTR_MASK 0x30000000u
3468 #define CRC_CTRL_TOTR_SHIFT 28
3469 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOTR_SHIFT))&CRC_CTRL_TOTR_MASK)
3470 #define CRC_CTRL_TOT_MASK 0xC0000000u
3471 #define CRC_CTRL_TOT_SHIFT 30
3472 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x))<<CRC_CTRL_TOT_SHIFT))&CRC_CTRL_TOT_MASK)
3473 /* CTRLHU Bit Fields */
3474 #define CRC_CTRLHU_TCRC_MASK 0x1u
3475 #define CRC_CTRLHU_TCRC_SHIFT 0
3476 #define CRC_CTRLHU_WAS_MASK 0x2u
3477 #define CRC_CTRLHU_WAS_SHIFT 1
3478 #define CRC_CTRLHU_FXOR_MASK 0x4u
3479 #define CRC_CTRLHU_FXOR_SHIFT 2
3480 #define CRC_CTRLHU_TOTR_MASK 0x30u
3481 #define CRC_CTRLHU_TOTR_SHIFT 4
3482 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOTR_SHIFT))&CRC_CTRLHU_TOTR_MASK)
3483 #define CRC_CTRLHU_TOT_MASK 0xC0u
3484 #define CRC_CTRLHU_TOT_SHIFT 6
3485 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x))<<CRC_CTRLHU_TOT_SHIFT))&CRC_CTRLHU_TOT_MASK)
3486
3487 /*!
3488 * @}
3489 */ /* end of group CRC_Register_Masks */
3490
3491
3492 /* CRC - Peripheral instance base addresses */
3493 /** Peripheral CRC base address */
3494 #define CRC_BASE (0x40032000u)
3495 /** Peripheral CRC base pointer */
3496 #define CRC0 ((CRC_Type *)CRC_BASE)
3497 #define CRC_BASE_PTR (CRC0)
3498 /** Array initializer of CRC peripheral base addresses */
3499 #define CRC_BASE_ADDRS { CRC_BASE }
3500 /** Array initializer of CRC peripheral base pointers */
3501 #define CRC_BASE_PTRS { CRC0 }
3502
3503 /* ----------------------------------------------------------------------------
3504 -- CRC - Register accessor macros
3505 ---------------------------------------------------------------------------- */
3506
3507 /*!
3508 * @addtogroup CRC_Register_Accessor_Macros CRC - Register accessor macros
3509 * @{
3510 */
3511
3512
3513 /* CRC - Register instance definitions */
3514 /* CRC */
3515 #define CRC_DATA CRC_DATA_REG(CRC0)
3516 #define CRC_DATAL CRC_DATAL_REG(CRC0)
3517 #define CRC_DATALL CRC_DATALL_REG(CRC0)
3518 #define CRC_DATALU CRC_DATALU_REG(CRC0)
3519 #define CRC_DATAH CRC_DATAH_REG(CRC0)
3520 #define CRC_DATAHL CRC_DATAHL_REG(CRC0)
3521 #define CRC_DATAHU CRC_DATAHU_REG(CRC0)
3522 #define CRC_GPOLY CRC_GPOLY_REG(CRC0)
3523 #define CRC_GPOLYL CRC_GPOLYL_REG(CRC0)
3524 #define CRC_GPOLYLL CRC_GPOLYLL_REG(CRC0)
3525 #define CRC_GPOLYLU CRC_GPOLYLU_REG(CRC0)
3526 #define CRC_GPOLYH CRC_GPOLYH_REG(CRC0)
3527 #define CRC_GPOLYHL CRC_GPOLYHL_REG(CRC0)
3528 #define CRC_GPOLYHU CRC_GPOLYHU_REG(CRC0)
3529 #define CRC_CTRL CRC_CTRL_REG(CRC0)
3530 #define CRC_CTRLHU CRC_CTRLHU_REG(CRC0)
3531
3532 /*!
3533 * @}
3534 */ /* end of group CRC_Register_Accessor_Macros */
3535
3536
3537 /*!
3538 * @}
3539 */ /* end of group CRC_Peripheral_Access_Layer */
3540
3541
3542 /* ----------------------------------------------------------------------------
3543 -- DAC Peripheral Access Layer
3544 ---------------------------------------------------------------------------- */
3545
3546 /*!
3547 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
3548 * @{
3549 */
3550
3551 /** DAC - Register Layout Typedef */
3552 typedef struct {
3553 struct { /* offset: 0x0, array step: 0x2 */
3554 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
3555 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
3556 } DAT[16];
3557 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
3558 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
3559 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
3560 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
3561 } DAC_Type, *DAC_MemMapPtr;
3562
3563 /* ----------------------------------------------------------------------------
3564 -- DAC - Register accessor macros
3565 ---------------------------------------------------------------------------- */
3566
3567 /*!
3568 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
3569 * @{
3570 */
3571
3572
3573 /* DAC - Register accessors */
3574 #define DAC_DATL_REG(base,index) ((base)->DAT[index].DATL)
3575 #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH)
3576 #define DAC_SR_REG(base) ((base)->SR)
3577 #define DAC_C0_REG(base) ((base)->C0)
3578 #define DAC_C1_REG(base) ((base)->C1)
3579 #define DAC_C2_REG(base) ((base)->C2)
3580
3581 /*!
3582 * @}
3583 */ /* end of group DAC_Register_Accessor_Macros */
3584
3585
3586 /* ----------------------------------------------------------------------------
3587 -- DAC Register Masks
3588 ---------------------------------------------------------------------------- */
3589
3590 /*!
3591 * @addtogroup DAC_Register_Masks DAC Register Masks
3592 * @{
3593 */
3594
3595 /* DATL Bit Fields */
3596 #define DAC_DATL_DATA0_MASK 0xFFu
3597 #define DAC_DATL_DATA0_SHIFT 0
3598 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
3599 /* DATH Bit Fields */
3600 #define DAC_DATH_DATA1_MASK 0xFu
3601 #define DAC_DATH_DATA1_SHIFT 0
3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
3603 /* SR Bit Fields */
3604 #define DAC_SR_DACBFRPBF_MASK 0x1u
3605 #define DAC_SR_DACBFRPBF_SHIFT 0
3606 #define DAC_SR_DACBFRPTF_MASK 0x2u
3607 #define DAC_SR_DACBFRPTF_SHIFT 1
3608 #define DAC_SR_DACBFWMF_MASK 0x4u
3609 #define DAC_SR_DACBFWMF_SHIFT 2
3610 /* C0 Bit Fields */
3611 #define DAC_C0_DACBBIEN_MASK 0x1u
3612 #define DAC_C0_DACBBIEN_SHIFT 0
3613 #define DAC_C0_DACBTIEN_MASK 0x2u
3614 #define DAC_C0_DACBTIEN_SHIFT 1
3615 #define DAC_C0_DACBWIEN_MASK 0x4u
3616 #define DAC_C0_DACBWIEN_SHIFT 2
3617 #define DAC_C0_LPEN_MASK 0x8u
3618 #define DAC_C0_LPEN_SHIFT 3
3619 #define DAC_C0_DACSWTRG_MASK 0x10u
3620 #define DAC_C0_DACSWTRG_SHIFT 4
3621 #define DAC_C0_DACTRGSEL_MASK 0x20u
3622 #define DAC_C0_DACTRGSEL_SHIFT 5
3623 #define DAC_C0_DACRFS_MASK 0x40u
3624 #define DAC_C0_DACRFS_SHIFT 6
3625 #define DAC_C0_DACEN_MASK 0x80u
3626 #define DAC_C0_DACEN_SHIFT 7
3627 /* C1 Bit Fields */
3628 #define DAC_C1_DACBFEN_MASK 0x1u
3629 #define DAC_C1_DACBFEN_SHIFT 0
3630 #define DAC_C1_DACBFMD_MASK 0x6u
3631 #define DAC_C1_DACBFMD_SHIFT 1
3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFMD_SHIFT))&DAC_C1_DACBFMD_MASK)
3633 #define DAC_C1_DACBFWM_MASK 0x18u
3634 #define DAC_C1_DACBFWM_SHIFT 3
3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x))<<DAC_C1_DACBFWM_SHIFT))&DAC_C1_DACBFWM_MASK)
3636 #define DAC_C1_DMAEN_MASK 0x80u
3637 #define DAC_C1_DMAEN_SHIFT 7
3638 /* C2 Bit Fields */
3639 #define DAC_C2_DACBFUP_MASK 0xFu
3640 #define DAC_C2_DACBFUP_SHIFT 0
3641 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFUP_SHIFT))&DAC_C2_DACBFUP_MASK)
3642 #define DAC_C2_DACBFRP_MASK 0xF0u
3643 #define DAC_C2_DACBFRP_SHIFT 4
3644 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x))<<DAC_C2_DACBFRP_SHIFT))&DAC_C2_DACBFRP_MASK)
3645
3646 /*!
3647 * @}
3648 */ /* end of group DAC_Register_Masks */
3649
3650
3651 /* DAC - Peripheral instance base addresses */
3652 /** Peripheral DAC0 base address */
3653 #define DAC0_BASE (0x400CC000u)
3654 /** Peripheral DAC0 base pointer */
3655 #define DAC0 ((DAC_Type *)DAC0_BASE)
3656 #define DAC0_BASE_PTR (DAC0)
3657 /** Peripheral DAC1 base address */
3658 #define DAC1_BASE (0x400CD000u)
3659 /** Peripheral DAC1 base pointer */
3660 #define DAC1 ((DAC_Type *)DAC1_BASE)
3661 #define DAC1_BASE_PTR (DAC1)
3662 /** Array initializer of DAC peripheral base addresses */
3663 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
3664 /** Array initializer of DAC peripheral base pointers */
3665 #define DAC_BASE_PTRS { DAC0, DAC1 }
3666 /** Interrupt vectors for the DAC peripheral type */
3667 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
3668
3669 /* ----------------------------------------------------------------------------
3670 -- DAC - Register accessor macros
3671 ---------------------------------------------------------------------------- */
3672
3673 /*!
3674 * @addtogroup DAC_Register_Accessor_Macros DAC - Register accessor macros
3675 * @{
3676 */
3677
3678
3679 /* DAC - Register instance definitions */
3680 /* DAC0 */
3681 #define DAC0_DAT0L DAC_DATL_REG(DAC0,0)
3682 #define DAC0_DAT0H DAC_DATH_REG(DAC0,0)
3683 #define DAC0_DAT1L DAC_DATL_REG(DAC0,1)
3684 #define DAC0_DAT1H DAC_DATH_REG(DAC0,1)
3685 #define DAC0_DAT2L DAC_DATL_REG(DAC0,2)
3686 #define DAC0_DAT2H DAC_DATH_REG(DAC0,2)
3687 #define DAC0_DAT3L DAC_DATL_REG(DAC0,3)
3688 #define DAC0_DAT3H DAC_DATH_REG(DAC0,3)
3689 #define DAC0_DAT4L DAC_DATL_REG(DAC0,4)
3690 #define DAC0_DAT4H DAC_DATH_REG(DAC0,4)
3691 #define DAC0_DAT5L DAC_DATL_REG(DAC0,5)
3692 #define DAC0_DAT5H DAC_DATH_REG(DAC0,5)
3693 #define DAC0_DAT6L DAC_DATL_REG(DAC0,6)
3694 #define DAC0_DAT6H DAC_DATH_REG(DAC0,6)
3695 #define DAC0_DAT7L DAC_DATL_REG(DAC0,7)
3696 #define DAC0_DAT7H DAC_DATH_REG(DAC0,7)
3697 #define DAC0_DAT8L DAC_DATL_REG(DAC0,8)
3698 #define DAC0_DAT8H DAC_DATH_REG(DAC0,8)
3699 #define DAC0_DAT9L DAC_DATL_REG(DAC0,9)
3700 #define DAC0_DAT9H DAC_DATH_REG(DAC0,9)
3701 #define DAC0_DAT10L DAC_DATL_REG(DAC0,10)
3702 #define DAC0_DAT10H DAC_DATH_REG(DAC0,10)
3703 #define DAC0_DAT11L DAC_DATL_REG(DAC0,11)
3704 #define DAC0_DAT11H DAC_DATH_REG(DAC0,11)
3705 #define DAC0_DAT12L DAC_DATL_REG(DAC0,12)
3706 #define DAC0_DAT12H DAC_DATH_REG(DAC0,12)
3707 #define DAC0_DAT13L DAC_DATL_REG(DAC0,13)
3708 #define DAC0_DAT13H DAC_DATH_REG(DAC0,13)
3709 #define DAC0_DAT14L DAC_DATL_REG(DAC0,14)
3710 #define DAC0_DAT14H DAC_DATH_REG(DAC0,14)
3711 #define DAC0_DAT15L DAC_DATL_REG(DAC0,15)
3712 #define DAC0_DAT15H DAC_DATH_REG(DAC0,15)
3713 #define DAC0_SR DAC_SR_REG(DAC0)
3714 #define DAC0_C0 DAC_C0_REG(DAC0)
3715 #define DAC0_C1 DAC_C1_REG(DAC0)
3716 #define DAC0_C2 DAC_C2_REG(DAC0)
3717 /* DAC1 */
3718 #define DAC1_DAT0L DAC_DATL_REG(DAC1,0)
3719 #define DAC1_DAT0H DAC_DATH_REG(DAC1,0)
3720 #define DAC1_DAT1L DAC_DATL_REG(DAC1,1)
3721 #define DAC1_DAT1H DAC_DATH_REG(DAC1,1)
3722 #define DAC1_DAT2L DAC_DATL_REG(DAC1,2)
3723 #define DAC1_DAT2H DAC_DATH_REG(DAC1,2)
3724 #define DAC1_DAT3L DAC_DATL_REG(DAC1,3)
3725 #define DAC1_DAT3H DAC_DATH_REG(DAC1,3)
3726 #define DAC1_DAT4L DAC_DATL_REG(DAC1,4)
3727 #define DAC1_DAT4H DAC_DATH_REG(DAC1,4)
3728 #define DAC1_DAT5L DAC_DATL_REG(DAC1,5)
3729 #define DAC1_DAT5H DAC_DATH_REG(DAC1,5)
3730 #define DAC1_DAT6L DAC_DATL_REG(DAC1,6)
3731 #define DAC1_DAT6H DAC_DATH_REG(DAC1,6)
3732 #define DAC1_DAT7L DAC_DATL_REG(DAC1,7)
3733 #define DAC1_DAT7H DAC_DATH_REG(DAC1,7)
3734 #define DAC1_DAT8L DAC_DATL_REG(DAC1,8)
3735 #define DAC1_DAT8H DAC_DATH_REG(DAC1,8)
3736 #define DAC1_DAT9L DAC_DATL_REG(DAC1,9)
3737 #define DAC1_DAT9H DAC_DATH_REG(DAC1,9)
3738 #define DAC1_DAT10L DAC_DATL_REG(DAC1,10)
3739 #define DAC1_DAT10H DAC_DATH_REG(DAC1,10)
3740 #define DAC1_DAT11L DAC_DATL_REG(DAC1,11)
3741 #define DAC1_DAT11H DAC_DATH_REG(DAC1,11)
3742 #define DAC1_DAT12L DAC_DATL_REG(DAC1,12)
3743 #define DAC1_DAT12H DAC_DATH_REG(DAC1,12)
3744 #define DAC1_DAT13L DAC_DATL_REG(DAC1,13)
3745 #define DAC1_DAT13H DAC_DATH_REG(DAC1,13)
3746 #define DAC1_DAT14L DAC_DATL_REG(DAC1,14)
3747 #define DAC1_DAT14H DAC_DATH_REG(DAC1,14)
3748 #define DAC1_DAT15L DAC_DATL_REG(DAC1,15)
3749 #define DAC1_DAT15H DAC_DATH_REG(DAC1,15)
3750 #define DAC1_SR DAC_SR_REG(DAC1)
3751 #define DAC1_C0 DAC_C0_REG(DAC1)
3752 #define DAC1_C1 DAC_C1_REG(DAC1)
3753 #define DAC1_C2 DAC_C2_REG(DAC1)
3754
3755 /* DAC - Register array accessors */
3756 #define DAC0_DATL(index) DAC_DATL_REG(DAC0,index)
3757 #define DAC1_DATL(index) DAC_DATL_REG(DAC1,index)
3758 #define DAC0_DATH(index) DAC_DATH_REG(DAC0,index)
3759 #define DAC1_DATH(index) DAC_DATH_REG(DAC1,index)
3760
3761 /*!
3762 * @}
3763 */ /* end of group DAC_Register_Accessor_Macros */
3764
3765
3766 /*!
3767 * @}
3768 */ /* end of group DAC_Peripheral_Access_Layer */
3769
3770
3771 /* ----------------------------------------------------------------------------
3772 -- DMA Peripheral Access Layer
3773 ---------------------------------------------------------------------------- */
3774
3775 /*!
3776 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
3777 * @{
3778 */
3779
3780 /** DMA - Register Layout Typedef */
3781 typedef struct {
3782 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
3783 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
3784 uint8_t RESERVED_0[4];
3785 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
3786 uint8_t RESERVED_1[4];
3787 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
3788 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
3789 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
3790 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
3791 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
3792 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
3793 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
3794 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
3795 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
3796 uint8_t RESERVED_2[4];
3797 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
3798 uint8_t RESERVED_3[4];
3799 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
3800 uint8_t RESERVED_4[4];
3801 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
3802 uint8_t RESERVED_5[200];
3803 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
3804 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
3805 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
3806 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
3807 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
3808 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
3809 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
3810 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
3811 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
3812 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
3813 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
3814 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
3815 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
3816 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
3817 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
3818 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
3819 uint8_t RESERVED_6[3824];
3820 struct { /* offset: 0x1000, array step: 0x20 */
3821 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
3822 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
3823 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
3824 union { /* offset: 0x1008, array step: 0x20 */
3825 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
3826 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
3827 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
3828 };
3829 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
3830 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
3831 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
3832 union { /* offset: 0x1016, array step: 0x20 */
3833 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
3834 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
3835 };
3836 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
3837 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
3838 union { /* offset: 0x101E, array step: 0x20 */
3839 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
3840 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
3841 };
3842 } TCD[16];
3843 } DMA_Type, *DMA_MemMapPtr;
3844
3845 /* ----------------------------------------------------------------------------
3846 -- DMA - Register accessor macros
3847 ---------------------------------------------------------------------------- */
3848
3849 /*!
3850 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
3851 * @{
3852 */
3853
3854
3855 /* DMA - Register accessors */
3856 #define DMA_CR_REG(base) ((base)->CR)
3857 #define DMA_ES_REG(base) ((base)->ES)
3858 #define DMA_ERQ_REG(base) ((base)->ERQ)
3859 #define DMA_EEI_REG(base) ((base)->EEI)
3860 #define DMA_CEEI_REG(base) ((base)->CEEI)
3861 #define DMA_SEEI_REG(base) ((base)->SEEI)
3862 #define DMA_CERQ_REG(base) ((base)->CERQ)
3863 #define DMA_SERQ_REG(base) ((base)->SERQ)
3864 #define DMA_CDNE_REG(base) ((base)->CDNE)
3865 #define DMA_SSRT_REG(base) ((base)->SSRT)
3866 #define DMA_CERR_REG(base) ((base)->CERR)
3867 #define DMA_CINT_REG(base) ((base)->CINT)
3868 #define DMA_INT_REG(base) ((base)->INT)
3869 #define DMA_ERR_REG(base) ((base)->ERR)
3870 #define DMA_HRS_REG(base) ((base)->HRS)
3871 #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3)
3872 #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2)
3873 #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1)
3874 #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0)
3875 #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7)
3876 #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6)
3877 #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5)
3878 #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4)
3879 #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11)
3880 #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10)
3881 #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9)
3882 #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8)
3883 #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15)
3884 #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14)
3885 #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13)
3886 #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12)
3887 #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR)
3888 #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF)
3889 #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR)
3890 #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO)
3891 #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO)
3892 #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES)
3893 #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST)
3894 #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR)
3895 #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF)
3896 #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO)
3897 #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES)
3898 #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA)
3899 #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR)
3900 #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO)
3901 #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES)
3902
3903 /*!
3904 * @}
3905 */ /* end of group DMA_Register_Accessor_Macros */
3906
3907
3908 /* ----------------------------------------------------------------------------
3909 -- DMA Register Masks
3910 ---------------------------------------------------------------------------- */
3911
3912 /*!
3913 * @addtogroup DMA_Register_Masks DMA Register Masks
3914 * @{
3915 */
3916
3917 /* CR Bit Fields */
3918 #define DMA_CR_EDBG_MASK 0x2u
3919 #define DMA_CR_EDBG_SHIFT 1
3920 #define DMA_CR_ERCA_MASK 0x4u
3921 #define DMA_CR_ERCA_SHIFT 2
3922 #define DMA_CR_HOE_MASK 0x10u
3923 #define DMA_CR_HOE_SHIFT 4
3924 #define DMA_CR_HALT_MASK 0x20u
3925 #define DMA_CR_HALT_SHIFT 5
3926 #define DMA_CR_CLM_MASK 0x40u
3927 #define DMA_CR_CLM_SHIFT 6
3928 #define DMA_CR_EMLM_MASK 0x80u
3929 #define DMA_CR_EMLM_SHIFT 7
3930 #define DMA_CR_ECX_MASK 0x10000u
3931 #define DMA_CR_ECX_SHIFT 16
3932 #define DMA_CR_CX_MASK 0x20000u
3933 #define DMA_CR_CX_SHIFT 17
3934 /* ES Bit Fields */
3935 #define DMA_ES_DBE_MASK 0x1u
3936 #define DMA_ES_DBE_SHIFT 0
3937 #define DMA_ES_SBE_MASK 0x2u
3938 #define DMA_ES_SBE_SHIFT 1
3939 #define DMA_ES_SGE_MASK 0x4u
3940 #define DMA_ES_SGE_SHIFT 2
3941 #define DMA_ES_NCE_MASK 0x8u
3942 #define DMA_ES_NCE_SHIFT 3
3943 #define DMA_ES_DOE_MASK 0x10u
3944 #define DMA_ES_DOE_SHIFT 4
3945 #define DMA_ES_DAE_MASK 0x20u
3946 #define DMA_ES_DAE_SHIFT 5
3947 #define DMA_ES_SOE_MASK 0x40u
3948 #define DMA_ES_SOE_SHIFT 6
3949 #define DMA_ES_SAE_MASK 0x80u
3950 #define DMA_ES_SAE_SHIFT 7
3951 #define DMA_ES_ERRCHN_MASK 0xF00u
3952 #define DMA_ES_ERRCHN_SHIFT 8
3953 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<<DMA_ES_ERRCHN_SHIFT))&DMA_ES_ERRCHN_MASK)
3954 #define DMA_ES_CPE_MASK 0x4000u
3955 #define DMA_ES_CPE_SHIFT 14
3956 #define DMA_ES_ECX_MASK 0x10000u
3957 #define DMA_ES_ECX_SHIFT 16
3958 #define DMA_ES_VLD_MASK 0x80000000u
3959 #define DMA_ES_VLD_SHIFT 31
3960 /* ERQ Bit Fields */
3961 #define DMA_ERQ_ERQ0_MASK 0x1u
3962 #define DMA_ERQ_ERQ0_SHIFT 0
3963 #define DMA_ERQ_ERQ1_MASK 0x2u
3964 #define DMA_ERQ_ERQ1_SHIFT 1
3965 #define DMA_ERQ_ERQ2_MASK 0x4u
3966 #define DMA_ERQ_ERQ2_SHIFT 2
3967 #define DMA_ERQ_ERQ3_MASK 0x8u
3968 #define DMA_ERQ_ERQ3_SHIFT 3
3969 #define DMA_ERQ_ERQ4_MASK 0x10u
3970 #define DMA_ERQ_ERQ4_SHIFT 4
3971 #define DMA_ERQ_ERQ5_MASK 0x20u
3972 #define DMA_ERQ_ERQ5_SHIFT 5
3973 #define DMA_ERQ_ERQ6_MASK 0x40u
3974 #define DMA_ERQ_ERQ6_SHIFT 6
3975 #define DMA_ERQ_ERQ7_MASK 0x80u
3976 #define DMA_ERQ_ERQ7_SHIFT 7
3977 #define DMA_ERQ_ERQ8_MASK 0x100u
3978 #define DMA_ERQ_ERQ8_SHIFT 8
3979 #define DMA_ERQ_ERQ9_MASK 0x200u
3980 #define DMA_ERQ_ERQ9_SHIFT 9
3981 #define DMA_ERQ_ERQ10_MASK 0x400u
3982 #define DMA_ERQ_ERQ10_SHIFT 10
3983 #define DMA_ERQ_ERQ11_MASK 0x800u
3984 #define DMA_ERQ_ERQ11_SHIFT 11
3985 #define DMA_ERQ_ERQ12_MASK 0x1000u
3986 #define DMA_ERQ_ERQ12_SHIFT 12
3987 #define DMA_ERQ_ERQ13_MASK 0x2000u
3988 #define DMA_ERQ_ERQ13_SHIFT 13
3989 #define DMA_ERQ_ERQ14_MASK 0x4000u
3990 #define DMA_ERQ_ERQ14_SHIFT 14
3991 #define DMA_ERQ_ERQ15_MASK 0x8000u
3992 #define DMA_ERQ_ERQ15_SHIFT 15
3993 /* EEI Bit Fields */
3994 #define DMA_EEI_EEI0_MASK 0x1u
3995 #define DMA_EEI_EEI0_SHIFT 0
3996 #define DMA_EEI_EEI1_MASK 0x2u
3997 #define DMA_EEI_EEI1_SHIFT 1
3998 #define DMA_EEI_EEI2_MASK 0x4u
3999 #define DMA_EEI_EEI2_SHIFT 2
4000 #define DMA_EEI_EEI3_MASK 0x8u
4001 #define DMA_EEI_EEI3_SHIFT 3
4002 #define DMA_EEI_EEI4_MASK 0x10u
4003 #define DMA_EEI_EEI4_SHIFT 4
4004 #define DMA_EEI_EEI5_MASK 0x20u
4005 #define DMA_EEI_EEI5_SHIFT 5
4006 #define DMA_EEI_EEI6_MASK 0x40u
4007 #define DMA_EEI_EEI6_SHIFT 6
4008 #define DMA_EEI_EEI7_MASK 0x80u
4009 #define DMA_EEI_EEI7_SHIFT 7
4010 #define DMA_EEI_EEI8_MASK 0x100u
4011 #define DMA_EEI_EEI8_SHIFT 8
4012 #define DMA_EEI_EEI9_MASK 0x200u
4013 #define DMA_EEI_EEI9_SHIFT 9
4014 #define DMA_EEI_EEI10_MASK 0x400u
4015 #define DMA_EEI_EEI10_SHIFT 10
4016 #define DMA_EEI_EEI11_MASK 0x800u
4017 #define DMA_EEI_EEI11_SHIFT 11
4018 #define DMA_EEI_EEI12_MASK 0x1000u
4019 #define DMA_EEI_EEI12_SHIFT 12
4020 #define DMA_EEI_EEI13_MASK 0x2000u
4021 #define DMA_EEI_EEI13_SHIFT 13
4022 #define DMA_EEI_EEI14_MASK 0x4000u
4023 #define DMA_EEI_EEI14_SHIFT 14
4024 #define DMA_EEI_EEI15_MASK 0x8000u
4025 #define DMA_EEI_EEI15_SHIFT 15
4026 /* CEEI Bit Fields */
4027 #define DMA_CEEI_CEEI_MASK 0xFu
4028 #define DMA_CEEI_CEEI_SHIFT 0
4029 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_CEEI_CEEI_SHIFT))&DMA_CEEI_CEEI_MASK)
4030 #define DMA_CEEI_CAEE_MASK 0x40u
4031 #define DMA_CEEI_CAEE_SHIFT 6
4032 #define DMA_CEEI_NOP_MASK 0x80u
4033 #define DMA_CEEI_NOP_SHIFT 7
4034 /* SEEI Bit Fields */
4035 #define DMA_SEEI_SEEI_MASK 0xFu
4036 #define DMA_SEEI_SEEI_SHIFT 0
4037 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x))<<DMA_SEEI_SEEI_SHIFT))&DMA_SEEI_SEEI_MASK)
4038 #define DMA_SEEI_SAEE_MASK 0x40u
4039 #define DMA_SEEI_SAEE_SHIFT 6
4040 #define DMA_SEEI_NOP_MASK 0x80u
4041 #define DMA_SEEI_NOP_SHIFT 7
4042 /* CERQ Bit Fields */
4043 #define DMA_CERQ_CERQ_MASK 0xFu
4044 #define DMA_CERQ_CERQ_SHIFT 0
4045 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERQ_CERQ_SHIFT))&DMA_CERQ_CERQ_MASK)
4046 #define DMA_CERQ_CAER_MASK 0x40u
4047 #define DMA_CERQ_CAER_SHIFT 6
4048 #define DMA_CERQ_NOP_MASK 0x80u
4049 #define DMA_CERQ_NOP_SHIFT 7
4050 /* SERQ Bit Fields */
4051 #define DMA_SERQ_SERQ_MASK 0xFu
4052 #define DMA_SERQ_SERQ_SHIFT 0
4053 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x))<<DMA_SERQ_SERQ_SHIFT))&DMA_SERQ_SERQ_MASK)
4054 #define DMA_SERQ_SAER_MASK 0x40u
4055 #define DMA_SERQ_SAER_SHIFT 6
4056 #define DMA_SERQ_NOP_MASK 0x80u
4057 #define DMA_SERQ_NOP_SHIFT 7
4058 /* CDNE Bit Fields */
4059 #define DMA_CDNE_CDNE_MASK 0xFu
4060 #define DMA_CDNE_CDNE_SHIFT 0
4061 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x))<<DMA_CDNE_CDNE_SHIFT))&DMA_CDNE_CDNE_MASK)
4062 #define DMA_CDNE_CADN_MASK 0x40u
4063 #define DMA_CDNE_CADN_SHIFT 6
4064 #define DMA_CDNE_NOP_MASK 0x80u
4065 #define DMA_CDNE_NOP_SHIFT 7
4066 /* SSRT Bit Fields */
4067 #define DMA_SSRT_SSRT_MASK 0xFu
4068 #define DMA_SSRT_SSRT_SHIFT 0
4069 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x))<<DMA_SSRT_SSRT_SHIFT))&DMA_SSRT_SSRT_MASK)
4070 #define DMA_SSRT_SAST_MASK 0x40u
4071 #define DMA_SSRT_SAST_SHIFT 6
4072 #define DMA_SSRT_NOP_MASK 0x80u
4073 #define DMA_SSRT_NOP_SHIFT 7
4074 /* CERR Bit Fields */
4075 #define DMA_CERR_CERR_MASK 0xFu
4076 #define DMA_CERR_CERR_SHIFT 0
4077 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x))<<DMA_CERR_CERR_SHIFT))&DMA_CERR_CERR_MASK)
4078 #define DMA_CERR_CAEI_MASK 0x40u
4079 #define DMA_CERR_CAEI_SHIFT 6
4080 #define DMA_CERR_NOP_MASK 0x80u
4081 #define DMA_CERR_NOP_SHIFT 7
4082 /* CINT Bit Fields */
4083 #define DMA_CINT_CINT_MASK 0xFu
4084 #define DMA_CINT_CINT_SHIFT 0
4085 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x))<<DMA_CINT_CINT_SHIFT))&DMA_CINT_CINT_MASK)
4086 #define DMA_CINT_CAIR_MASK 0x40u
4087 #define DMA_CINT_CAIR_SHIFT 6
4088 #define DMA_CINT_NOP_MASK 0x80u
4089 #define DMA_CINT_NOP_SHIFT 7
4090 /* INT Bit Fields */
4091 #define DMA_INT_INT0_MASK 0x1u
4092 #define DMA_INT_INT0_SHIFT 0
4093 #define DMA_INT_INT1_MASK 0x2u
4094 #define DMA_INT_INT1_SHIFT 1
4095 #define DMA_INT_INT2_MASK 0x4u
4096 #define DMA_INT_INT2_SHIFT 2
4097 #define DMA_INT_INT3_MASK 0x8u
4098 #define DMA_INT_INT3_SHIFT 3
4099 #define DMA_INT_INT4_MASK 0x10u
4100 #define DMA_INT_INT4_SHIFT 4
4101 #define DMA_INT_INT5_MASK 0x20u
4102 #define DMA_INT_INT5_SHIFT 5
4103 #define DMA_INT_INT6_MASK 0x40u
4104 #define DMA_INT_INT6_SHIFT 6
4105 #define DMA_INT_INT7_MASK 0x80u
4106 #define DMA_INT_INT7_SHIFT 7
4107 #define DMA_INT_INT8_MASK 0x100u
4108 #define DMA_INT_INT8_SHIFT 8
4109 #define DMA_INT_INT9_MASK 0x200u
4110 #define DMA_INT_INT9_SHIFT 9
4111 #define DMA_INT_INT10_MASK 0x400u
4112 #define DMA_INT_INT10_SHIFT 10
4113 #define DMA_INT_INT11_MASK 0x800u
4114 #define DMA_INT_INT11_SHIFT 11
4115 #define DMA_INT_INT12_MASK 0x1000u
4116 #define DMA_INT_INT12_SHIFT 12
4117 #define DMA_INT_INT13_MASK 0x2000u
4118 #define DMA_INT_INT13_SHIFT 13
4119 #define DMA_INT_INT14_MASK 0x4000u
4120 #define DMA_INT_INT14_SHIFT 14
4121 #define DMA_INT_INT15_MASK 0x8000u
4122 #define DMA_INT_INT15_SHIFT 15
4123 /* ERR Bit Fields */
4124 #define DMA_ERR_ERR0_MASK 0x1u
4125 #define DMA_ERR_ERR0_SHIFT 0
4126 #define DMA_ERR_ERR1_MASK 0x2u
4127 #define DMA_ERR_ERR1_SHIFT 1
4128 #define DMA_ERR_ERR2_MASK 0x4u
4129 #define DMA_ERR_ERR2_SHIFT 2
4130 #define DMA_ERR_ERR3_MASK 0x8u
4131 #define DMA_ERR_ERR3_SHIFT 3
4132 #define DMA_ERR_ERR4_MASK 0x10u
4133 #define DMA_ERR_ERR4_SHIFT 4
4134 #define DMA_ERR_ERR5_MASK 0x20u
4135 #define DMA_ERR_ERR5_SHIFT 5
4136 #define DMA_ERR_ERR6_MASK 0x40u
4137 #define DMA_ERR_ERR6_SHIFT 6
4138 #define DMA_ERR_ERR7_MASK 0x80u
4139 #define DMA_ERR_ERR7_SHIFT 7
4140 #define DMA_ERR_ERR8_MASK 0x100u
4141 #define DMA_ERR_ERR8_SHIFT 8
4142 #define DMA_ERR_ERR9_MASK 0x200u
4143 #define DMA_ERR_ERR9_SHIFT 9
4144 #define DMA_ERR_ERR10_MASK 0x400u
4145 #define DMA_ERR_ERR10_SHIFT 10
4146 #define DMA_ERR_ERR11_MASK 0x800u
4147 #define DMA_ERR_ERR11_SHIFT 11
4148 #define DMA_ERR_ERR12_MASK 0x1000u
4149 #define DMA_ERR_ERR12_SHIFT 12
4150 #define DMA_ERR_ERR13_MASK 0x2000u
4151 #define DMA_ERR_ERR13_SHIFT 13
4152 #define DMA_ERR_ERR14_MASK 0x4000u
4153 #define DMA_ERR_ERR14_SHIFT 14
4154 #define DMA_ERR_ERR15_MASK 0x8000u
4155 #define DMA_ERR_ERR15_SHIFT 15
4156 /* HRS Bit Fields */
4157 #define DMA_HRS_HRS0_MASK 0x1u
4158 #define DMA_HRS_HRS0_SHIFT 0
4159 #define DMA_HRS_HRS1_MASK 0x2u
4160 #define DMA_HRS_HRS1_SHIFT 1
4161 #define DMA_HRS_HRS2_MASK 0x4u
4162 #define DMA_HRS_HRS2_SHIFT 2
4163 #define DMA_HRS_HRS3_MASK 0x8u
4164 #define DMA_HRS_HRS3_SHIFT 3
4165 #define DMA_HRS_HRS4_MASK 0x10u
4166 #define DMA_HRS_HRS4_SHIFT 4
4167 #define DMA_HRS_HRS5_MASK 0x20u
4168 #define DMA_HRS_HRS5_SHIFT 5
4169 #define DMA_HRS_HRS6_MASK 0x40u
4170 #define DMA_HRS_HRS6_SHIFT 6
4171 #define DMA_HRS_HRS7_MASK 0x80u
4172 #define DMA_HRS_HRS7_SHIFT 7
4173 #define DMA_HRS_HRS8_MASK 0x100u
4174 #define DMA_HRS_HRS8_SHIFT 8
4175 #define DMA_HRS_HRS9_MASK 0x200u
4176 #define DMA_HRS_HRS9_SHIFT 9
4177 #define DMA_HRS_HRS10_MASK 0x400u
4178 #define DMA_HRS_HRS10_SHIFT 10
4179 #define DMA_HRS_HRS11_MASK 0x800u
4180 #define DMA_HRS_HRS11_SHIFT 11
4181 #define DMA_HRS_HRS12_MASK 0x1000u
4182 #define DMA_HRS_HRS12_SHIFT 12
4183 #define DMA_HRS_HRS13_MASK 0x2000u
4184 #define DMA_HRS_HRS13_SHIFT 13
4185 #define DMA_HRS_HRS14_MASK 0x4000u
4186 #define DMA_HRS_HRS14_SHIFT 14
4187 #define DMA_HRS_HRS15_MASK 0x8000u
4188 #define DMA_HRS_HRS15_SHIFT 15
4189 /* DCHPRI3 Bit Fields */
4190 #define DMA_DCHPRI3_CHPRI_MASK 0xFu
4191 #define DMA_DCHPRI3_CHPRI_SHIFT 0
4192 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI3_CHPRI_SHIFT))&DMA_DCHPRI3_CHPRI_MASK)
4193 #define DMA_DCHPRI3_DPA_MASK 0x40u
4194 #define DMA_DCHPRI3_DPA_SHIFT 6
4195 #define DMA_DCHPRI3_ECP_MASK 0x80u
4196 #define DMA_DCHPRI3_ECP_SHIFT 7
4197 /* DCHPRI2 Bit Fields */
4198 #define DMA_DCHPRI2_CHPRI_MASK 0xFu
4199 #define DMA_DCHPRI2_CHPRI_SHIFT 0
4200 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI2_CHPRI_SHIFT))&DMA_DCHPRI2_CHPRI_MASK)
4201 #define DMA_DCHPRI2_DPA_MASK 0x40u
4202 #define DMA_DCHPRI2_DPA_SHIFT 6
4203 #define DMA_DCHPRI2_ECP_MASK 0x80u
4204 #define DMA_DCHPRI2_ECP_SHIFT 7
4205 /* DCHPRI1 Bit Fields */
4206 #define DMA_DCHPRI1_CHPRI_MASK 0xFu
4207 #define DMA_DCHPRI1_CHPRI_SHIFT 0
4208 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI1_CHPRI_SHIFT))&DMA_DCHPRI1_CHPRI_MASK)
4209 #define DMA_DCHPRI1_DPA_MASK 0x40u
4210 #define DMA_DCHPRI1_DPA_SHIFT 6
4211 #define DMA_DCHPRI1_ECP_MASK 0x80u
4212 #define DMA_DCHPRI1_ECP_SHIFT 7
4213 /* DCHPRI0 Bit Fields */
4214 #define DMA_DCHPRI0_CHPRI_MASK 0xFu
4215 #define DMA_DCHPRI0_CHPRI_SHIFT 0
4216 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI0_CHPRI_SHIFT))&DMA_DCHPRI0_CHPRI_MASK)
4217 #define DMA_DCHPRI0_DPA_MASK 0x40u
4218 #define DMA_DCHPRI0_DPA_SHIFT 6
4219 #define DMA_DCHPRI0_ECP_MASK 0x80u
4220 #define DMA_DCHPRI0_ECP_SHIFT 7
4221 /* DCHPRI7 Bit Fields */
4222 #define DMA_DCHPRI7_CHPRI_MASK 0xFu
4223 #define DMA_DCHPRI7_CHPRI_SHIFT 0
4224 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI7_CHPRI_SHIFT))&DMA_DCHPRI7_CHPRI_MASK)
4225 #define DMA_DCHPRI7_DPA_MASK 0x40u
4226 #define DMA_DCHPRI7_DPA_SHIFT 6
4227 #define DMA_DCHPRI7_ECP_MASK 0x80u
4228 #define DMA_DCHPRI7_ECP_SHIFT 7
4229 /* DCHPRI6 Bit Fields */
4230 #define DMA_DCHPRI6_CHPRI_MASK 0xFu
4231 #define DMA_DCHPRI6_CHPRI_SHIFT 0
4232 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI6_CHPRI_SHIFT))&DMA_DCHPRI6_CHPRI_MASK)
4233 #define DMA_DCHPRI6_DPA_MASK 0x40u
4234 #define DMA_DCHPRI6_DPA_SHIFT 6
4235 #define DMA_DCHPRI6_ECP_MASK 0x80u
4236 #define DMA_DCHPRI6_ECP_SHIFT 7
4237 /* DCHPRI5 Bit Fields */
4238 #define DMA_DCHPRI5_CHPRI_MASK 0xFu
4239 #define DMA_DCHPRI5_CHPRI_SHIFT 0
4240 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI5_CHPRI_SHIFT))&DMA_DCHPRI5_CHPRI_MASK)
4241 #define DMA_DCHPRI5_DPA_MASK 0x40u
4242 #define DMA_DCHPRI5_DPA_SHIFT 6
4243 #define DMA_DCHPRI5_ECP_MASK 0x80u
4244 #define DMA_DCHPRI5_ECP_SHIFT 7
4245 /* DCHPRI4 Bit Fields */
4246 #define DMA_DCHPRI4_CHPRI_MASK 0xFu
4247 #define DMA_DCHPRI4_CHPRI_SHIFT 0
4248 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI4_CHPRI_SHIFT))&DMA_DCHPRI4_CHPRI_MASK)
4249 #define DMA_DCHPRI4_DPA_MASK 0x40u
4250 #define DMA_DCHPRI4_DPA_SHIFT 6
4251 #define DMA_DCHPRI4_ECP_MASK 0x80u
4252 #define DMA_DCHPRI4_ECP_SHIFT 7
4253 /* DCHPRI11 Bit Fields */
4254 #define DMA_DCHPRI11_CHPRI_MASK 0xFu
4255 #define DMA_DCHPRI11_CHPRI_SHIFT 0
4256 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI11_CHPRI_SHIFT))&DMA_DCHPRI11_CHPRI_MASK)
4257 #define DMA_DCHPRI11_DPA_MASK 0x40u
4258 #define DMA_DCHPRI11_DPA_SHIFT 6
4259 #define DMA_DCHPRI11_ECP_MASK 0x80u
4260 #define DMA_DCHPRI11_ECP_SHIFT 7
4261 /* DCHPRI10 Bit Fields */
4262 #define DMA_DCHPRI10_CHPRI_MASK 0xFu
4263 #define DMA_DCHPRI10_CHPRI_SHIFT 0
4264 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI10_CHPRI_SHIFT))&DMA_DCHPRI10_CHPRI_MASK)
4265 #define DMA_DCHPRI10_DPA_MASK 0x40u
4266 #define DMA_DCHPRI10_DPA_SHIFT 6
4267 #define DMA_DCHPRI10_ECP_MASK 0x80u
4268 #define DMA_DCHPRI10_ECP_SHIFT 7
4269 /* DCHPRI9 Bit Fields */
4270 #define DMA_DCHPRI9_CHPRI_MASK 0xFu
4271 #define DMA_DCHPRI9_CHPRI_SHIFT 0
4272 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI9_CHPRI_SHIFT))&DMA_DCHPRI9_CHPRI_MASK)
4273 #define DMA_DCHPRI9_DPA_MASK 0x40u
4274 #define DMA_DCHPRI9_DPA_SHIFT 6
4275 #define DMA_DCHPRI9_ECP_MASK 0x80u
4276 #define DMA_DCHPRI9_ECP_SHIFT 7
4277 /* DCHPRI8 Bit Fields */
4278 #define DMA_DCHPRI8_CHPRI_MASK 0xFu
4279 #define DMA_DCHPRI8_CHPRI_SHIFT 0
4280 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI8_CHPRI_SHIFT))&DMA_DCHPRI8_CHPRI_MASK)
4281 #define DMA_DCHPRI8_DPA_MASK 0x40u
4282 #define DMA_DCHPRI8_DPA_SHIFT 6
4283 #define DMA_DCHPRI8_ECP_MASK 0x80u
4284 #define DMA_DCHPRI8_ECP_SHIFT 7
4285 /* DCHPRI15 Bit Fields */
4286 #define DMA_DCHPRI15_CHPRI_MASK 0xFu
4287 #define DMA_DCHPRI15_CHPRI_SHIFT 0
4288 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI15_CHPRI_SHIFT))&DMA_DCHPRI15_CHPRI_MASK)
4289 #define DMA_DCHPRI15_DPA_MASK 0x40u
4290 #define DMA_DCHPRI15_DPA_SHIFT 6
4291 #define DMA_DCHPRI15_ECP_MASK 0x80u
4292 #define DMA_DCHPRI15_ECP_SHIFT 7
4293 /* DCHPRI14 Bit Fields */
4294 #define DMA_DCHPRI14_CHPRI_MASK 0xFu
4295 #define DMA_DCHPRI14_CHPRI_SHIFT 0
4296 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI14_CHPRI_SHIFT))&DMA_DCHPRI14_CHPRI_MASK)
4297 #define DMA_DCHPRI14_DPA_MASK 0x40u
4298 #define DMA_DCHPRI14_DPA_SHIFT 6
4299 #define DMA_DCHPRI14_ECP_MASK 0x80u
4300 #define DMA_DCHPRI14_ECP_SHIFT 7
4301 /* DCHPRI13 Bit Fields */
4302 #define DMA_DCHPRI13_CHPRI_MASK 0xFu
4303 #define DMA_DCHPRI13_CHPRI_SHIFT 0
4304 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI13_CHPRI_SHIFT))&DMA_DCHPRI13_CHPRI_MASK)
4305 #define DMA_DCHPRI13_DPA_MASK 0x40u
4306 #define DMA_DCHPRI13_DPA_SHIFT 6
4307 #define DMA_DCHPRI13_ECP_MASK 0x80u
4308 #define DMA_DCHPRI13_ECP_SHIFT 7
4309 /* DCHPRI12 Bit Fields */
4310 #define DMA_DCHPRI12_CHPRI_MASK 0xFu
4311 #define DMA_DCHPRI12_CHPRI_SHIFT 0
4312 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x))<<DMA_DCHPRI12_CHPRI_SHIFT))&DMA_DCHPRI12_CHPRI_MASK)
4313 #define DMA_DCHPRI12_DPA_MASK 0x40u
4314 #define DMA_DCHPRI12_DPA_SHIFT 6
4315 #define DMA_DCHPRI12_ECP_MASK 0x80u
4316 #define DMA_DCHPRI12_ECP_SHIFT 7
4317 /* SADDR Bit Fields */
4318 #define DMA_SADDR_SADDR_MASK 0xFFFFFFFFu
4319 #define DMA_SADDR_SADDR_SHIFT 0
4320 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SADDR_SADDR_SHIFT))&DMA_SADDR_SADDR_MASK)
4321 /* SOFF Bit Fields */
4322 #define DMA_SOFF_SOFF_MASK 0xFFFFu
4323 #define DMA_SOFF_SOFF_SHIFT 0
4324 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_SOFF_SOFF_SHIFT))&DMA_SOFF_SOFF_MASK)
4325 /* ATTR Bit Fields */
4326 #define DMA_ATTR_DSIZE_MASK 0x7u
4327 #define DMA_ATTR_DSIZE_SHIFT 0
4328 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DSIZE_SHIFT))&DMA_ATTR_DSIZE_MASK)
4329 #define DMA_ATTR_DMOD_MASK 0xF8u
4330 #define DMA_ATTR_DMOD_SHIFT 3
4331 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_DMOD_SHIFT))&DMA_ATTR_DMOD_MASK)
4332 #define DMA_ATTR_SSIZE_MASK 0x700u
4333 #define DMA_ATTR_SSIZE_SHIFT 8
4334 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SSIZE_SHIFT))&DMA_ATTR_SSIZE_MASK)
4335 #define DMA_ATTR_SMOD_MASK 0xF800u
4336 #define DMA_ATTR_SMOD_SHIFT 11
4337 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x))<<DMA_ATTR_SMOD_SHIFT))&DMA_ATTR_SMOD_MASK)
4338 /* NBYTES_MLNO Bit Fields */
4339 #define DMA_NBYTES_MLNO_NBYTES_MASK 0xFFFFFFFFu
4340 #define DMA_NBYTES_MLNO_NBYTES_SHIFT 0
4341 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLNO_NBYTES_SHIFT))&DMA_NBYTES_MLNO_NBYTES_MASK)
4342 /* NBYTES_MLOFFNO Bit Fields */
4343 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK 0x3FFFFFFFu
4344 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT 0
4345 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFNO_NBYTES_SHIFT))&DMA_NBYTES_MLOFFNO_NBYTES_MASK)
4346 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK 0x40000000u
4347 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT 30
4348 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK 0x80000000u
4349 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT 31
4350 /* NBYTES_MLOFFYES Bit Fields */
4351 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK 0x3FFu
4352 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT 0
4353 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_NBYTES_SHIFT))&DMA_NBYTES_MLOFFYES_NBYTES_MASK)
4354 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK 0x3FFFFC00u
4355 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT 10
4356 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x))<<DMA_NBYTES_MLOFFYES_MLOFF_SHIFT))&DMA_NBYTES_MLOFFYES_MLOFF_MASK)
4357 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK 0x40000000u
4358 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT 30
4359 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK 0x80000000u
4360 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT 31
4361 /* SLAST Bit Fields */
4362 #define DMA_SLAST_SLAST_MASK 0xFFFFFFFFu
4363 #define DMA_SLAST_SLAST_SHIFT 0
4364 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x))<<DMA_SLAST_SLAST_SHIFT))&DMA_SLAST_SLAST_MASK)
4365 /* DADDR Bit Fields */
4366 #define DMA_DADDR_DADDR_MASK 0xFFFFFFFFu
4367 #define DMA_DADDR_DADDR_SHIFT 0
4368 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DADDR_DADDR_SHIFT))&DMA_DADDR_DADDR_MASK)
4369 /* DOFF Bit Fields */
4370 #define DMA_DOFF_DOFF_MASK 0xFFFFu
4371 #define DMA_DOFF_DOFF_SHIFT 0
4372 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x))<<DMA_DOFF_DOFF_SHIFT))&DMA_DOFF_DOFF_MASK)
4373 /* CITER_ELINKNO Bit Fields */
4374 #define DMA_CITER_ELINKNO_CITER_MASK 0x7FFFu
4375 #define DMA_CITER_ELINKNO_CITER_SHIFT 0
4376 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKNO_CITER_SHIFT))&DMA_CITER_ELINKNO_CITER_MASK)
4377 #define DMA_CITER_ELINKNO_ELINK_MASK 0x8000u
4378 #define DMA_CITER_ELINKNO_ELINK_SHIFT 15
4379 /* CITER_ELINKYES Bit Fields */
4380 #define DMA_CITER_ELINKYES_CITER_MASK 0x1FFu
4381 #define DMA_CITER_ELINKYES_CITER_SHIFT 0
4382 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_CITER_SHIFT))&DMA_CITER_ELINKYES_CITER_MASK)
4383 #define DMA_CITER_ELINKYES_LINKCH_MASK 0x1E00u
4384 #define DMA_CITER_ELINKYES_LINKCH_SHIFT 9
4385 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CITER_ELINKYES_LINKCH_SHIFT))&DMA_CITER_ELINKYES_LINKCH_MASK)
4386 #define DMA_CITER_ELINKYES_ELINK_MASK 0x8000u
4387 #define DMA_CITER_ELINKYES_ELINK_SHIFT 15
4388 /* DLAST_SGA Bit Fields */
4389 #define DMA_DLAST_SGA_DLASTSGA_MASK 0xFFFFFFFFu
4390 #define DMA_DLAST_SGA_DLASTSGA_SHIFT 0
4391 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x))<<DMA_DLAST_SGA_DLASTSGA_SHIFT))&DMA_DLAST_SGA_DLASTSGA_MASK)
4392 /* CSR Bit Fields */
4393 #define DMA_CSR_START_MASK 0x1u
4394 #define DMA_CSR_START_SHIFT 0
4395 #define DMA_CSR_INTMAJOR_MASK 0x2u
4396 #define DMA_CSR_INTMAJOR_SHIFT 1
4397 #define DMA_CSR_INTHALF_MASK 0x4u
4398 #define DMA_CSR_INTHALF_SHIFT 2
4399 #define DMA_CSR_DREQ_MASK 0x8u
4400 #define DMA_CSR_DREQ_SHIFT 3
4401 #define DMA_CSR_ESG_MASK 0x10u
4402 #define DMA_CSR_ESG_SHIFT 4
4403 #define DMA_CSR_MAJORELINK_MASK 0x20u
4404 #define DMA_CSR_MAJORELINK_SHIFT 5
4405 #define DMA_CSR_ACTIVE_MASK 0x40u
4406 #define DMA_CSR_ACTIVE_SHIFT 6
4407 #define DMA_CSR_DONE_MASK 0x80u
4408 #define DMA_CSR_DONE_SHIFT 7
4409 #define DMA_CSR_MAJORLINKCH_MASK 0xF00u
4410 #define DMA_CSR_MAJORLINKCH_SHIFT 8
4411 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_MAJORLINKCH_SHIFT))&DMA_CSR_MAJORLINKCH_MASK)
4412 #define DMA_CSR_BWC_MASK 0xC000u
4413 #define DMA_CSR_BWC_SHIFT 14
4414 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x))<<DMA_CSR_BWC_SHIFT))&DMA_CSR_BWC_MASK)
4415 /* BITER_ELINKNO Bit Fields */
4416 #define DMA_BITER_ELINKNO_BITER_MASK 0x7FFFu
4417 #define DMA_BITER_ELINKNO_BITER_SHIFT 0
4418 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKNO_BITER_SHIFT))&DMA_BITER_ELINKNO_BITER_MASK)
4419 #define DMA_BITER_ELINKNO_ELINK_MASK 0x8000u
4420 #define DMA_BITER_ELINKNO_ELINK_SHIFT 15
4421 /* BITER_ELINKYES Bit Fields */
4422 #define DMA_BITER_ELINKYES_BITER_MASK 0x1FFu
4423 #define DMA_BITER_ELINKYES_BITER_SHIFT 0
4424 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_BITER_SHIFT))&DMA_BITER_ELINKYES_BITER_MASK)
4425 #define DMA_BITER_ELINKYES_LINKCH_MASK 0x1E00u
4426 #define DMA_BITER_ELINKYES_LINKCH_SHIFT 9
4427 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x))<<DMA_BITER_ELINKYES_LINKCH_SHIFT))&DMA_BITER_ELINKYES_LINKCH_MASK)
4428 #define DMA_BITER_ELINKYES_ELINK_MASK 0x8000u
4429 #define DMA_BITER_ELINKYES_ELINK_SHIFT 15
4430
4431 /*!
4432 * @}
4433 */ /* end of group DMA_Register_Masks */
4434
4435
4436 /* DMA - Peripheral instance base addresses */
4437 /** Peripheral DMA base address */
4438 #define DMA_BASE (0x40008000u)
4439 /** Peripheral DMA base pointer */
4440 #define DMA0 ((DMA_Type *)DMA_BASE)
4441 #define DMA_BASE_PTR (DMA0)
4442 /** Array initializer of DMA peripheral base addresses */
4443 #define DMA_BASE_ADDRS { DMA_BASE }
4444 /** Array initializer of DMA peripheral base pointers */
4445 #define DMA_BASE_PTRS { DMA0 }
4446 /** Interrupt vectors for the DMA peripheral type */
4447 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
4448 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
4449
4450 /* ----------------------------------------------------------------------------
4451 -- DMA - Register accessor macros
4452 ---------------------------------------------------------------------------- */
4453
4454 /*!
4455 * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros
4456 * @{
4457 */
4458
4459
4460 /* DMA - Register instance definitions */
4461 /* DMA */
4462 #define DMA_CR DMA_CR_REG(DMA0)
4463 #define DMA_ES DMA_ES_REG(DMA0)
4464 #define DMA_ERQ DMA_ERQ_REG(DMA0)
4465 #define DMA_EEI DMA_EEI_REG(DMA0)
4466 #define DMA_CEEI DMA_CEEI_REG(DMA0)
4467 #define DMA_SEEI DMA_SEEI_REG(DMA0)
4468 #define DMA_CERQ DMA_CERQ_REG(DMA0)
4469 #define DMA_SERQ DMA_SERQ_REG(DMA0)
4470 #define DMA_CDNE DMA_CDNE_REG(DMA0)
4471 #define DMA_SSRT DMA_SSRT_REG(DMA0)
4472 #define DMA_CERR DMA_CERR_REG(DMA0)
4473 #define DMA_CINT DMA_CINT_REG(DMA0)
4474 #define DMA_INT DMA_INT_REG(DMA0)
4475 #define DMA_ERR DMA_ERR_REG(DMA0)
4476 #define DMA_HRS DMA_HRS_REG(DMA0)
4477 #define DMA_DCHPRI3 DMA_DCHPRI3_REG(DMA0)
4478 #define DMA_DCHPRI2 DMA_DCHPRI2_REG(DMA0)
4479 #define DMA_DCHPRI1 DMA_DCHPRI1_REG(DMA0)
4480 #define DMA_DCHPRI0 DMA_DCHPRI0_REG(DMA0)
4481 #define DMA_DCHPRI7 DMA_DCHPRI7_REG(DMA0)
4482 #define DMA_DCHPRI6 DMA_DCHPRI6_REG(DMA0)
4483 #define DMA_DCHPRI5 DMA_DCHPRI5_REG(DMA0)
4484 #define DMA_DCHPRI4 DMA_DCHPRI4_REG(DMA0)
4485 #define DMA_DCHPRI11 DMA_DCHPRI11_REG(DMA0)
4486 #define DMA_DCHPRI10 DMA_DCHPRI10_REG(DMA0)
4487 #define DMA_DCHPRI9 DMA_DCHPRI9_REG(DMA0)
4488 #define DMA_DCHPRI8 DMA_DCHPRI8_REG(DMA0)
4489 #define DMA_DCHPRI15 DMA_DCHPRI15_REG(DMA0)
4490 #define DMA_DCHPRI14 DMA_DCHPRI14_REG(DMA0)
4491 #define DMA_DCHPRI13 DMA_DCHPRI13_REG(DMA0)
4492 #define DMA_DCHPRI12 DMA_DCHPRI12_REG(DMA0)
4493 #define DMA_TCD0_SADDR DMA_SADDR_REG(DMA0,0)
4494 #define DMA_TCD0_SOFF DMA_SOFF_REG(DMA0,0)
4495 #define DMA_TCD0_ATTR DMA_ATTR_REG(DMA0,0)
4496 #define DMA_TCD0_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,0)
4497 #define DMA_TCD0_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,0)
4498 #define DMA_TCD0_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,0)
4499 #define DMA_TCD0_SLAST DMA_SLAST_REG(DMA0,0)
4500 #define DMA_TCD0_DADDR DMA_DADDR_REG(DMA0,0)
4501 #define DMA_TCD0_DOFF DMA_DOFF_REG(DMA0,0)
4502 #define DMA_TCD0_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,0)
4503 #define DMA_TCD0_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,0)
4504 #define DMA_TCD0_DLASTSGA DMA_DLAST_SGA_REG(DMA0,0)
4505 #define DMA_TCD0_CSR DMA_CSR_REG(DMA0,0)
4506 #define DMA_TCD0_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,0)
4507 #define DMA_TCD0_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,0)
4508 #define DMA_TCD1_SADDR DMA_SADDR_REG(DMA0,1)
4509 #define DMA_TCD1_SOFF DMA_SOFF_REG(DMA0,1)
4510 #define DMA_TCD1_ATTR DMA_ATTR_REG(DMA0,1)
4511 #define DMA_TCD1_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,1)
4512 #define DMA_TCD1_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,1)
4513 #define DMA_TCD1_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,1)
4514 #define DMA_TCD1_SLAST DMA_SLAST_REG(DMA0,1)
4515 #define DMA_TCD1_DADDR DMA_DADDR_REG(DMA0,1)
4516 #define DMA_TCD1_DOFF DMA_DOFF_REG(DMA0,1)
4517 #define DMA_TCD1_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,1)
4518 #define DMA_TCD1_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,1)
4519 #define DMA_TCD1_DLASTSGA DMA_DLAST_SGA_REG(DMA0,1)
4520 #define DMA_TCD1_CSR DMA_CSR_REG(DMA0,1)
4521 #define DMA_TCD1_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,1)
4522 #define DMA_TCD1_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,1)
4523 #define DMA_TCD2_SADDR DMA_SADDR_REG(DMA0,2)
4524 #define DMA_TCD2_SOFF DMA_SOFF_REG(DMA0,2)
4525 #define DMA_TCD2_ATTR DMA_ATTR_REG(DMA0,2)
4526 #define DMA_TCD2_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,2)
4527 #define DMA_TCD2_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,2)
4528 #define DMA_TCD2_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,2)
4529 #define DMA_TCD2_SLAST DMA_SLAST_REG(DMA0,2)
4530 #define DMA_TCD2_DADDR DMA_DADDR_REG(DMA0,2)
4531 #define DMA_TCD2_DOFF DMA_DOFF_REG(DMA0,2)
4532 #define DMA_TCD2_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,2)
4533 #define DMA_TCD2_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,2)
4534 #define DMA_TCD2_DLASTSGA DMA_DLAST_SGA_REG(DMA0,2)
4535 #define DMA_TCD2_CSR DMA_CSR_REG(DMA0,2)
4536 #define DMA_TCD2_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,2)
4537 #define DMA_TCD2_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,2)
4538 #define DMA_TCD3_SADDR DMA_SADDR_REG(DMA0,3)
4539 #define DMA_TCD3_SOFF DMA_SOFF_REG(DMA0,3)
4540 #define DMA_TCD3_ATTR DMA_ATTR_REG(DMA0,3)
4541 #define DMA_TCD3_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,3)
4542 #define DMA_TCD3_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,3)
4543 #define DMA_TCD3_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,3)
4544 #define DMA_TCD3_SLAST DMA_SLAST_REG(DMA0,3)
4545 #define DMA_TCD3_DADDR DMA_DADDR_REG(DMA0,3)
4546 #define DMA_TCD3_DOFF DMA_DOFF_REG(DMA0,3)
4547 #define DMA_TCD3_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,3)
4548 #define DMA_TCD3_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,3)
4549 #define DMA_TCD3_DLASTSGA DMA_DLAST_SGA_REG(DMA0,3)
4550 #define DMA_TCD3_CSR DMA_CSR_REG(DMA0,3)
4551 #define DMA_TCD3_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,3)
4552 #define DMA_TCD3_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,3)
4553 #define DMA_TCD4_SADDR DMA_SADDR_REG(DMA0,4)
4554 #define DMA_TCD4_SOFF DMA_SOFF_REG(DMA0,4)
4555 #define DMA_TCD4_ATTR DMA_ATTR_REG(DMA0,4)
4556 #define DMA_TCD4_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,4)
4557 #define DMA_TCD4_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,4)
4558 #define DMA_TCD4_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,4)
4559 #define DMA_TCD4_SLAST DMA_SLAST_REG(DMA0,4)
4560 #define DMA_TCD4_DADDR DMA_DADDR_REG(DMA0,4)
4561 #define DMA_TCD4_DOFF DMA_DOFF_REG(DMA0,4)
4562 #define DMA_TCD4_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,4)
4563 #define DMA_TCD4_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,4)
4564 #define DMA_TCD4_DLASTSGA DMA_DLAST_SGA_REG(DMA0,4)
4565 #define DMA_TCD4_CSR DMA_CSR_REG(DMA0,4)
4566 #define DMA_TCD4_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,4)
4567 #define DMA_TCD4_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,4)
4568 #define DMA_TCD5_SADDR DMA_SADDR_REG(DMA0,5)
4569 #define DMA_TCD5_SOFF DMA_SOFF_REG(DMA0,5)
4570 #define DMA_TCD5_ATTR DMA_ATTR_REG(DMA0,5)
4571 #define DMA_TCD5_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,5)
4572 #define DMA_TCD5_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,5)
4573 #define DMA_TCD5_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,5)
4574 #define DMA_TCD5_SLAST DMA_SLAST_REG(DMA0,5)
4575 #define DMA_TCD5_DADDR DMA_DADDR_REG(DMA0,5)
4576 #define DMA_TCD5_DOFF DMA_DOFF_REG(DMA0,5)
4577 #define DMA_TCD5_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,5)
4578 #define DMA_TCD5_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,5)
4579 #define DMA_TCD5_DLASTSGA DMA_DLAST_SGA_REG(DMA0,5)
4580 #define DMA_TCD5_CSR DMA_CSR_REG(DMA0,5)
4581 #define DMA_TCD5_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,5)
4582 #define DMA_TCD5_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,5)
4583 #define DMA_TCD6_SADDR DMA_SADDR_REG(DMA0,6)
4584 #define DMA_TCD6_SOFF DMA_SOFF_REG(DMA0,6)
4585 #define DMA_TCD6_ATTR DMA_ATTR_REG(DMA0,6)
4586 #define DMA_TCD6_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,6)
4587 #define DMA_TCD6_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,6)
4588 #define DMA_TCD6_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,6)
4589 #define DMA_TCD6_SLAST DMA_SLAST_REG(DMA0,6)
4590 #define DMA_TCD6_DADDR DMA_DADDR_REG(DMA0,6)
4591 #define DMA_TCD6_DOFF DMA_DOFF_REG(DMA0,6)
4592 #define DMA_TCD6_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,6)
4593 #define DMA_TCD6_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,6)
4594 #define DMA_TCD6_DLASTSGA DMA_DLAST_SGA_REG(DMA0,6)
4595 #define DMA_TCD6_CSR DMA_CSR_REG(DMA0,6)
4596 #define DMA_TCD6_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,6)
4597 #define DMA_TCD6_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,6)
4598 #define DMA_TCD7_SADDR DMA_SADDR_REG(DMA0,7)
4599 #define DMA_TCD7_SOFF DMA_SOFF_REG(DMA0,7)
4600 #define DMA_TCD7_ATTR DMA_ATTR_REG(DMA0,7)
4601 #define DMA_TCD7_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,7)
4602 #define DMA_TCD7_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,7)
4603 #define DMA_TCD7_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,7)
4604 #define DMA_TCD7_SLAST DMA_SLAST_REG(DMA0,7)
4605 #define DMA_TCD7_DADDR DMA_DADDR_REG(DMA0,7)
4606 #define DMA_TCD7_DOFF DMA_DOFF_REG(DMA0,7)
4607 #define DMA_TCD7_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,7)
4608 #define DMA_TCD7_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,7)
4609 #define DMA_TCD7_DLASTSGA DMA_DLAST_SGA_REG(DMA0,7)
4610 #define DMA_TCD7_CSR DMA_CSR_REG(DMA0,7)
4611 #define DMA_TCD7_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,7)
4612 #define DMA_TCD7_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,7)
4613 #define DMA_TCD8_SADDR DMA_SADDR_REG(DMA0,8)
4614 #define DMA_TCD8_SOFF DMA_SOFF_REG(DMA0,8)
4615 #define DMA_TCD8_ATTR DMA_ATTR_REG(DMA0,8)
4616 #define DMA_TCD8_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,8)
4617 #define DMA_TCD8_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,8)
4618 #define DMA_TCD8_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,8)
4619 #define DMA_TCD8_SLAST DMA_SLAST_REG(DMA0,8)
4620 #define DMA_TCD8_DADDR DMA_DADDR_REG(DMA0,8)
4621 #define DMA_TCD8_DOFF DMA_DOFF_REG(DMA0,8)
4622 #define DMA_TCD8_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,8)
4623 #define DMA_TCD8_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,8)
4624 #define DMA_TCD8_DLASTSGA DMA_DLAST_SGA_REG(DMA0,8)
4625 #define DMA_TCD8_CSR DMA_CSR_REG(DMA0,8)
4626 #define DMA_TCD8_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,8)
4627 #define DMA_TCD8_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,8)
4628 #define DMA_TCD9_SADDR DMA_SADDR_REG(DMA0,9)
4629 #define DMA_TCD9_SOFF DMA_SOFF_REG(DMA0,9)
4630 #define DMA_TCD9_ATTR DMA_ATTR_REG(DMA0,9)
4631 #define DMA_TCD9_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,9)
4632 #define DMA_TCD9_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,9)
4633 #define DMA_TCD9_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,9)
4634 #define DMA_TCD9_SLAST DMA_SLAST_REG(DMA0,9)
4635 #define DMA_TCD9_DADDR DMA_DADDR_REG(DMA0,9)
4636 #define DMA_TCD9_DOFF DMA_DOFF_REG(DMA0,9)
4637 #define DMA_TCD9_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,9)
4638 #define DMA_TCD9_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,9)
4639 #define DMA_TCD9_DLASTSGA DMA_DLAST_SGA_REG(DMA0,9)
4640 #define DMA_TCD9_CSR DMA_CSR_REG(DMA0,9)
4641 #define DMA_TCD9_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,9)
4642 #define DMA_TCD9_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,9)
4643 #define DMA_TCD10_SADDR DMA_SADDR_REG(DMA0,10)
4644 #define DMA_TCD10_SOFF DMA_SOFF_REG(DMA0,10)
4645 #define DMA_TCD10_ATTR DMA_ATTR_REG(DMA0,10)
4646 #define DMA_TCD10_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,10)
4647 #define DMA_TCD10_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,10)
4648 #define DMA_TCD10_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,10)
4649 #define DMA_TCD10_SLAST DMA_SLAST_REG(DMA0,10)
4650 #define DMA_TCD10_DADDR DMA_DADDR_REG(DMA0,10)
4651 #define DMA_TCD10_DOFF DMA_DOFF_REG(DMA0,10)
4652 #define DMA_TCD10_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,10)
4653 #define DMA_TCD10_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,10)
4654 #define DMA_TCD10_DLASTSGA DMA_DLAST_SGA_REG(DMA0,10)
4655 #define DMA_TCD10_CSR DMA_CSR_REG(DMA0,10)
4656 #define DMA_TCD10_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,10)
4657 #define DMA_TCD10_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,10)
4658 #define DMA_TCD11_SADDR DMA_SADDR_REG(DMA0,11)
4659 #define DMA_TCD11_SOFF DMA_SOFF_REG(DMA0,11)
4660 #define DMA_TCD11_ATTR DMA_ATTR_REG(DMA0,11)
4661 #define DMA_TCD11_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,11)
4662 #define DMA_TCD11_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,11)
4663 #define DMA_TCD11_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,11)
4664 #define DMA_TCD11_SLAST DMA_SLAST_REG(DMA0,11)
4665 #define DMA_TCD11_DADDR DMA_DADDR_REG(DMA0,11)
4666 #define DMA_TCD11_DOFF DMA_DOFF_REG(DMA0,11)
4667 #define DMA_TCD11_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,11)
4668 #define DMA_TCD11_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,11)
4669 #define DMA_TCD11_DLASTSGA DMA_DLAST_SGA_REG(DMA0,11)
4670 #define DMA_TCD11_CSR DMA_CSR_REG(DMA0,11)
4671 #define DMA_TCD11_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,11)
4672 #define DMA_TCD11_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,11)
4673 #define DMA_TCD12_SADDR DMA_SADDR_REG(DMA0,12)
4674 #define DMA_TCD12_SOFF DMA_SOFF_REG(DMA0,12)
4675 #define DMA_TCD12_ATTR DMA_ATTR_REG(DMA0,12)
4676 #define DMA_TCD12_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,12)
4677 #define DMA_TCD12_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,12)
4678 #define DMA_TCD12_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,12)
4679 #define DMA_TCD12_SLAST DMA_SLAST_REG(DMA0,12)
4680 #define DMA_TCD12_DADDR DMA_DADDR_REG(DMA0,12)
4681 #define DMA_TCD12_DOFF DMA_DOFF_REG(DMA0,12)
4682 #define DMA_TCD12_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,12)
4683 #define DMA_TCD12_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,12)
4684 #define DMA_TCD12_DLASTSGA DMA_DLAST_SGA_REG(DMA0,12)
4685 #define DMA_TCD12_CSR DMA_CSR_REG(DMA0,12)
4686 #define DMA_TCD12_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,12)
4687 #define DMA_TCD12_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,12)
4688 #define DMA_TCD13_SADDR DMA_SADDR_REG(DMA0,13)
4689 #define DMA_TCD13_SOFF DMA_SOFF_REG(DMA0,13)
4690 #define DMA_TCD13_ATTR DMA_ATTR_REG(DMA0,13)
4691 #define DMA_TCD13_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,13)
4692 #define DMA_TCD13_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,13)
4693 #define DMA_TCD13_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,13)
4694 #define DMA_TCD13_SLAST DMA_SLAST_REG(DMA0,13)
4695 #define DMA_TCD13_DADDR DMA_DADDR_REG(DMA0,13)
4696 #define DMA_TCD13_DOFF DMA_DOFF_REG(DMA0,13)
4697 #define DMA_TCD13_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,13)
4698 #define DMA_TCD13_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,13)
4699 #define DMA_TCD13_DLASTSGA DMA_DLAST_SGA_REG(DMA0,13)
4700 #define DMA_TCD13_CSR DMA_CSR_REG(DMA0,13)
4701 #define DMA_TCD13_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,13)
4702 #define DMA_TCD13_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,13)
4703 #define DMA_TCD14_SADDR DMA_SADDR_REG(DMA0,14)
4704 #define DMA_TCD14_SOFF DMA_SOFF_REG(DMA0,14)
4705 #define DMA_TCD14_ATTR DMA_ATTR_REG(DMA0,14)
4706 #define DMA_TCD14_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,14)
4707 #define DMA_TCD14_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,14)
4708 #define DMA_TCD14_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,14)
4709 #define DMA_TCD14_SLAST DMA_SLAST_REG(DMA0,14)
4710 #define DMA_TCD14_DADDR DMA_DADDR_REG(DMA0,14)
4711 #define DMA_TCD14_DOFF DMA_DOFF_REG(DMA0,14)
4712 #define DMA_TCD14_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,14)
4713 #define DMA_TCD14_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,14)
4714 #define DMA_TCD14_DLASTSGA DMA_DLAST_SGA_REG(DMA0,14)
4715 #define DMA_TCD14_CSR DMA_CSR_REG(DMA0,14)
4716 #define DMA_TCD14_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,14)
4717 #define DMA_TCD14_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,14)
4718 #define DMA_TCD15_SADDR DMA_SADDR_REG(DMA0,15)
4719 #define DMA_TCD15_SOFF DMA_SOFF_REG(DMA0,15)
4720 #define DMA_TCD15_ATTR DMA_ATTR_REG(DMA0,15)
4721 #define DMA_TCD15_NBYTES_MLNO DMA_NBYTES_MLNO_REG(DMA0,15)
4722 #define DMA_TCD15_NBYTES_MLOFFNO DMA_NBYTES_MLOFFNO_REG(DMA0,15)
4723 #define DMA_TCD15_NBYTES_MLOFFYES DMA_NBYTES_MLOFFYES_REG(DMA0,15)
4724 #define DMA_TCD15_SLAST DMA_SLAST_REG(DMA0,15)
4725 #define DMA_TCD15_DADDR DMA_DADDR_REG(DMA0,15)
4726 #define DMA_TCD15_DOFF DMA_DOFF_REG(DMA0,15)
4727 #define DMA_TCD15_CITER_ELINKNO DMA_CITER_ELINKNO_REG(DMA0,15)
4728 #define DMA_TCD15_CITER_ELINKYES DMA_CITER_ELINKYES_REG(DMA0,15)
4729 #define DMA_TCD15_DLASTSGA DMA_DLAST_SGA_REG(DMA0,15)
4730 #define DMA_TCD15_CSR DMA_CSR_REG(DMA0,15)
4731 #define DMA_TCD15_BITER_ELINKNO DMA_BITER_ELINKNO_REG(DMA0,15)
4732 #define DMA_TCD15_BITER_ELINKYES DMA_BITER_ELINKYES_REG(DMA0,15)
4733
4734 /* DMA - Register array accessors */
4735 #define DMA_SADDR(index) DMA_SADDR_REG(DMA0,index)
4736 #define DMA_SOFF(index) DMA_SOFF_REG(DMA0,index)
4737 #define DMA_ATTR(index) DMA_ATTR_REG(DMA0,index)
4738 #define DMA_NBYTES_MLNO(index) DMA_NBYTES_MLNO_REG(DMA0,index)
4739 #define DMA_NBYTES_MLOFFNO(index) DMA_NBYTES_MLOFFNO_REG(DMA0,index)
4740 #define DMA_NBYTES_MLOFFYES(index) DMA_NBYTES_MLOFFYES_REG(DMA0,index)
4741 #define DMA_SLAST(index) DMA_SLAST_REG(DMA0,index)
4742 #define DMA_DADDR(index) DMA_DADDR_REG(DMA0,index)
4743 #define DMA_DOFF(index) DMA_DOFF_REG(DMA0,index)
4744 #define DMA_CITER_ELINKNO(index) DMA_CITER_ELINKNO_REG(DMA0,index)
4745 #define DMA_CITER_ELINKYES(index) DMA_CITER_ELINKYES_REG(DMA0,index)
4746 #define DMA_DLAST_SGA(index) DMA_DLAST_SGA_REG(DMA0,index)
4747 #define DMA_CSR(index) DMA_CSR_REG(DMA0,index)
4748 #define DMA_BITER_ELINKNO(index) DMA_BITER_ELINKNO_REG(DMA0,index)
4749 #define DMA_BITER_ELINKYES(index) DMA_BITER_ELINKYES_REG(DMA0,index)
4750
4751 /*!
4752 * @}
4753 */ /* end of group DMA_Register_Accessor_Macros */
4754
4755
4756 /*!
4757 * @}
4758 */ /* end of group DMA_Peripheral_Access_Layer */
4759
4760
4761 /* ----------------------------------------------------------------------------
4762 -- DMAMUX Peripheral Access Layer
4763 ---------------------------------------------------------------------------- */
4764
4765 /*!
4766 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
4767 * @{
4768 */
4769
4770 /** DMAMUX - Register Layout Typedef */
4771 typedef struct {
4772 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
4773 } DMAMUX_Type, *DMAMUX_MemMapPtr;
4774
4775 /* ----------------------------------------------------------------------------
4776 -- DMAMUX - Register accessor macros
4777 ---------------------------------------------------------------------------- */
4778
4779 /*!
4780 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
4781 * @{
4782 */
4783
4784
4785 /* DMAMUX - Register accessors */
4786 #define DMAMUX_CHCFG_REG(base,index) ((base)->CHCFG[index])
4787
4788 /*!
4789 * @}
4790 */ /* end of group DMAMUX_Register_Accessor_Macros */
4791
4792
4793 /* ----------------------------------------------------------------------------
4794 -- DMAMUX Register Masks
4795 ---------------------------------------------------------------------------- */
4796
4797 /*!
4798 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
4799 * @{
4800 */
4801
4802 /* CHCFG Bit Fields */
4803 #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
4804 #define DMAMUX_CHCFG_SOURCE_SHIFT 0
4805 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
4806 #define DMAMUX_CHCFG_TRIG_MASK 0x40u
4807 #define DMAMUX_CHCFG_TRIG_SHIFT 6
4808 #define DMAMUX_CHCFG_ENBL_MASK 0x80u
4809 #define DMAMUX_CHCFG_ENBL_SHIFT 7
4810
4811 /*!
4812 * @}
4813 */ /* end of group DMAMUX_Register_Masks */
4814
4815
4816 /* DMAMUX - Peripheral instance base addresses */
4817 /** Peripheral DMAMUX base address */
4818 #define DMAMUX_BASE (0x40021000u)
4819 /** Peripheral DMAMUX base pointer */
4820 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
4821 #define DMAMUX_BASE_PTR (DMAMUX)
4822 /** Array initializer of DMAMUX peripheral base addresses */
4823 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
4824 /** Array initializer of DMAMUX peripheral base pointers */
4825 #define DMAMUX_BASE_PTRS { DMAMUX }
4826
4827 /* ----------------------------------------------------------------------------
4828 -- DMAMUX - Register accessor macros
4829 ---------------------------------------------------------------------------- */
4830
4831 /*!
4832 * @addtogroup DMAMUX_Register_Accessor_Macros DMAMUX - Register accessor macros
4833 * @{
4834 */
4835
4836
4837 /* DMAMUX - Register instance definitions */
4838 /* DMAMUX */
4839 #define DMAMUX_CHCFG0 DMAMUX_CHCFG_REG(DMAMUX,0)
4840 #define DMAMUX_CHCFG1 DMAMUX_CHCFG_REG(DMAMUX,1)
4841 #define DMAMUX_CHCFG2 DMAMUX_CHCFG_REG(DMAMUX,2)
4842 #define DMAMUX_CHCFG3 DMAMUX_CHCFG_REG(DMAMUX,3)
4843 #define DMAMUX_CHCFG4 DMAMUX_CHCFG_REG(DMAMUX,4)
4844 #define DMAMUX_CHCFG5 DMAMUX_CHCFG_REG(DMAMUX,5)
4845 #define DMAMUX_CHCFG6 DMAMUX_CHCFG_REG(DMAMUX,6)
4846 #define DMAMUX_CHCFG7 DMAMUX_CHCFG_REG(DMAMUX,7)
4847 #define DMAMUX_CHCFG8 DMAMUX_CHCFG_REG(DMAMUX,8)
4848 #define DMAMUX_CHCFG9 DMAMUX_CHCFG_REG(DMAMUX,9)
4849 #define DMAMUX_CHCFG10 DMAMUX_CHCFG_REG(DMAMUX,10)
4850 #define DMAMUX_CHCFG11 DMAMUX_CHCFG_REG(DMAMUX,11)
4851 #define DMAMUX_CHCFG12 DMAMUX_CHCFG_REG(DMAMUX,12)
4852 #define DMAMUX_CHCFG13 DMAMUX_CHCFG_REG(DMAMUX,13)
4853 #define DMAMUX_CHCFG14 DMAMUX_CHCFG_REG(DMAMUX,14)
4854 #define DMAMUX_CHCFG15 DMAMUX_CHCFG_REG(DMAMUX,15)
4855
4856 /* DMAMUX - Register array accessors */
4857 #define DMAMUX_CHCFG(index) DMAMUX_CHCFG_REG(DMAMUX,index)
4858
4859 /*!
4860 * @}
4861 */ /* end of group DMAMUX_Register_Accessor_Macros */
4862
4863
4864 /*!
4865 * @}
4866 */ /* end of group DMAMUX_Peripheral_Access_Layer */
4867
4868
4869 /* ----------------------------------------------------------------------------
4870 -- ENET Peripheral Access Layer
4871 ---------------------------------------------------------------------------- */
4872
4873 /*!
4874 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
4875 * @{
4876 */
4877
4878 /** ENET - Register Layout Typedef */
4879 typedef struct {
4880 uint8_t RESERVED_0[4];
4881 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
4882 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
4883 uint8_t RESERVED_1[4];
4884 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
4885 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
4886 uint8_t RESERVED_2[12];
4887 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
4888 uint8_t RESERVED_3[24];
4889 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
4890 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
4891 uint8_t RESERVED_4[28];
4892 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
4893 uint8_t RESERVED_5[28];
4894 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
4895 uint8_t RESERVED_6[60];
4896 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
4897 uint8_t RESERVED_7[28];
4898 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
4899 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
4900 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
4901 uint8_t RESERVED_8[40];
4902 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
4903 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
4904 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
4905 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
4906 uint8_t RESERVED_9[28];
4907 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
4908 uint8_t RESERVED_10[56];
4909 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
4910 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
4911 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
4912 uint8_t RESERVED_11[4];
4913 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
4914 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
4915 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
4916 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
4917 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
4918 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
4919 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
4920 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
4921 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
4922 uint8_t RESERVED_12[12];
4923 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
4924 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
4925 uint8_t RESERVED_13[60];
4926 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
4927 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
4928 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
4929 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
4930 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
4931 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
4932 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
4933 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
4934 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
4935 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
4936 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
4937 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
4938 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
4939 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
4940 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
4941 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
4942 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
4943 uint8_t RESERVED_14[4];
4944 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
4945 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
4946 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
4947 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
4948 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
4949 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
4950 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
4951 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
4952 uint8_t RESERVED_15[4];
4953 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
4954 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
4955 uint8_t RESERVED_16[12];
4956 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
4957 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
4958 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
4959 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
4960 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
4961 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
4962 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
4963 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
4964 uint8_t RESERVED_17[4];
4965 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
4966 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
4967 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
4968 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
4969 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
4970 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
4971 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
4972 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
4973 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
4974 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
4975 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
4976 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
4977 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
4978 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
4979 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
4980 uint8_t RESERVED_18[284];
4981 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
4982 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
4983 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
4984 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
4985 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
4986 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
4987 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
4988 uint8_t RESERVED_19[488];
4989 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
4990 struct { /* offset: 0x608, array step: 0x8 */
4991 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
4992 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
4993 } CHANNEL[4];
4994 } ENET_Type, *ENET_MemMapPtr;
4995
4996 /* ----------------------------------------------------------------------------
4997 -- ENET - Register accessor macros
4998 ---------------------------------------------------------------------------- */
4999
5000 /*!
5001 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
5002 * @{
5003 */
5004
5005
5006 /* ENET - Register accessors */
5007 #define ENET_EIR_REG(base) ((base)->EIR)
5008 #define ENET_EIMR_REG(base) ((base)->EIMR)
5009 #define ENET_RDAR_REG(base) ((base)->RDAR)
5010 #define ENET_TDAR_REG(base) ((base)->TDAR)
5011 #define ENET_ECR_REG(base) ((base)->ECR)
5012 #define ENET_MMFR_REG(base) ((base)->MMFR)
5013 #define ENET_MSCR_REG(base) ((base)->MSCR)
5014 #define ENET_MIBC_REG(base) ((base)->MIBC)
5015 #define ENET_RCR_REG(base) ((base)->RCR)
5016 #define ENET_TCR_REG(base) ((base)->TCR)
5017 #define ENET_PALR_REG(base) ((base)->PALR)
5018 #define ENET_PAUR_REG(base) ((base)->PAUR)
5019 #define ENET_OPD_REG(base) ((base)->OPD)
5020 #define ENET_IAUR_REG(base) ((base)->IAUR)
5021 #define ENET_IALR_REG(base) ((base)->IALR)
5022 #define ENET_GAUR_REG(base) ((base)->GAUR)
5023 #define ENET_GALR_REG(base) ((base)->GALR)
5024 #define ENET_TFWR_REG(base) ((base)->TFWR)
5025 #define ENET_RDSR_REG(base) ((base)->RDSR)
5026 #define ENET_TDSR_REG(base) ((base)->TDSR)
5027 #define ENET_MRBR_REG(base) ((base)->MRBR)
5028 #define ENET_RSFL_REG(base) ((base)->RSFL)
5029 #define ENET_RSEM_REG(base) ((base)->RSEM)
5030 #define ENET_RAEM_REG(base) ((base)->RAEM)
5031 #define ENET_RAFL_REG(base) ((base)->RAFL)
5032 #define ENET_TSEM_REG(base) ((base)->TSEM)
5033 #define ENET_TAEM_REG(base) ((base)->TAEM)
5034 #define ENET_TAFL_REG(base) ((base)->TAFL)
5035 #define ENET_TIPG_REG(base) ((base)->TIPG)
5036 #define ENET_FTRL_REG(base) ((base)->FTRL)
5037 #define ENET_TACC_REG(base) ((base)->TACC)
5038 #define ENET_RACC_REG(base) ((base)->RACC)
5039 #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS)
5040 #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT)
5041 #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT)
5042 #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN)
5043 #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE)
5044 #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE)
5045 #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG)
5046 #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB)
5047 #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL)
5048 #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64)
5049 #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127)
5050 #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255)
5051 #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511)
5052 #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023)
5053 #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047)
5054 #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048)
5055 #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS)
5056 #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK)
5057 #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL)
5058 #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL)
5059 #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF)
5060 #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL)
5061 #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL)
5062 #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR)
5063 #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR)
5064 #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC)
5065 #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK)
5066 #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS)
5067 #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT)
5068 #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT)
5069 #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN)
5070 #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE)
5071 #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE)
5072 #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG)
5073 #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB)
5074 #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64)
5075 #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127)
5076 #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255)
5077 #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511)
5078 #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023)
5079 #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047)
5080 #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048)
5081 #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS)
5082 #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP)
5083 #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK)
5084 #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC)
5085 #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN)
5086 #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR)
5087 #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC)
5088 #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK)
5089 #define ENET_ATCR_REG(base) ((base)->ATCR)
5090 #define ENET_ATVR_REG(base) ((base)->ATVR)
5091 #define ENET_ATOFF_REG(base) ((base)->ATOFF)
5092 #define ENET_ATPER_REG(base) ((base)->ATPER)
5093 #define ENET_ATCOR_REG(base) ((base)->ATCOR)
5094 #define ENET_ATINC_REG(base) ((base)->ATINC)
5095 #define ENET_ATSTMP_REG(base) ((base)->ATSTMP)
5096 #define ENET_TGSR_REG(base) ((base)->TGSR)
5097 #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR)
5098 #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR)
5099
5100 /*!
5101 * @}
5102 */ /* end of group ENET_Register_Accessor_Macros */
5103
5104
5105 /* ----------------------------------------------------------------------------
5106 -- ENET Register Masks
5107 ---------------------------------------------------------------------------- */
5108
5109 /*!
5110 * @addtogroup ENET_Register_Masks ENET Register Masks
5111 * @{
5112 */
5113
5114 /* EIR Bit Fields */
5115 #define ENET_EIR_TS_TIMER_MASK 0x8000u
5116 #define ENET_EIR_TS_TIMER_SHIFT 15
5117 #define ENET_EIR_TS_AVAIL_MASK 0x10000u
5118 #define ENET_EIR_TS_AVAIL_SHIFT 16
5119 #define ENET_EIR_WAKEUP_MASK 0x20000u
5120 #define ENET_EIR_WAKEUP_SHIFT 17
5121 #define ENET_EIR_PLR_MASK 0x40000u
5122 #define ENET_EIR_PLR_SHIFT 18
5123 #define ENET_EIR_UN_MASK 0x80000u
5124 #define ENET_EIR_UN_SHIFT 19
5125 #define ENET_EIR_RL_MASK 0x100000u
5126 #define ENET_EIR_RL_SHIFT 20
5127 #define ENET_EIR_LC_MASK 0x200000u
5128 #define ENET_EIR_LC_SHIFT 21
5129 #define ENET_EIR_EBERR_MASK 0x400000u
5130 #define ENET_EIR_EBERR_SHIFT 22
5131 #define ENET_EIR_MII_MASK 0x800000u
5132 #define ENET_EIR_MII_SHIFT 23
5133 #define ENET_EIR_RXB_MASK 0x1000000u
5134 #define ENET_EIR_RXB_SHIFT 24
5135 #define ENET_EIR_RXF_MASK 0x2000000u
5136 #define ENET_EIR_RXF_SHIFT 25
5137 #define ENET_EIR_TXB_MASK 0x4000000u
5138 #define ENET_EIR_TXB_SHIFT 26
5139 #define ENET_EIR_TXF_MASK 0x8000000u
5140 #define ENET_EIR_TXF_SHIFT 27
5141 #define ENET_EIR_GRA_MASK 0x10000000u
5142 #define ENET_EIR_GRA_SHIFT 28
5143 #define ENET_EIR_BABT_MASK 0x20000000u
5144 #define ENET_EIR_BABT_SHIFT 29
5145 #define ENET_EIR_BABR_MASK 0x40000000u
5146 #define ENET_EIR_BABR_SHIFT 30
5147 /* EIMR Bit Fields */
5148 #define ENET_EIMR_TS_TIMER_MASK 0x8000u
5149 #define ENET_EIMR_TS_TIMER_SHIFT 15
5150 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u
5151 #define ENET_EIMR_TS_AVAIL_SHIFT 16
5152 #define ENET_EIMR_WAKEUP_MASK 0x20000u
5153 #define ENET_EIMR_WAKEUP_SHIFT 17
5154 #define ENET_EIMR_PLR_MASK 0x40000u
5155 #define ENET_EIMR_PLR_SHIFT 18
5156 #define ENET_EIMR_UN_MASK 0x80000u
5157 #define ENET_EIMR_UN_SHIFT 19
5158 #define ENET_EIMR_RL_MASK 0x100000u
5159 #define ENET_EIMR_RL_SHIFT 20
5160 #define ENET_EIMR_LC_MASK 0x200000u
5161 #define ENET_EIMR_LC_SHIFT 21
5162 #define ENET_EIMR_EBERR_MASK 0x400000u
5163 #define ENET_EIMR_EBERR_SHIFT 22
5164 #define ENET_EIMR_MII_MASK 0x800000u
5165 #define ENET_EIMR_MII_SHIFT 23
5166 #define ENET_EIMR_RXB_MASK 0x1000000u
5167 #define ENET_EIMR_RXB_SHIFT 24
5168 #define ENET_EIMR_RXF_MASK 0x2000000u
5169 #define ENET_EIMR_RXF_SHIFT 25
5170 #define ENET_EIMR_TXB_MASK 0x4000000u
5171 #define ENET_EIMR_TXB_SHIFT 26
5172 #define ENET_EIMR_TXF_MASK 0x8000000u
5173 #define ENET_EIMR_TXF_SHIFT 27
5174 #define ENET_EIMR_GRA_MASK 0x10000000u
5175 #define ENET_EIMR_GRA_SHIFT 28
5176 #define ENET_EIMR_BABT_MASK 0x20000000u
5177 #define ENET_EIMR_BABT_SHIFT 29
5178 #define ENET_EIMR_BABR_MASK 0x40000000u
5179 #define ENET_EIMR_BABR_SHIFT 30
5180 /* RDAR Bit Fields */
5181 #define ENET_RDAR_RDAR_MASK 0x1000000u
5182 #define ENET_RDAR_RDAR_SHIFT 24
5183 /* TDAR Bit Fields */
5184 #define ENET_TDAR_TDAR_MASK 0x1000000u
5185 #define ENET_TDAR_TDAR_SHIFT 24
5186 /* ECR Bit Fields */
5187 #define ENET_ECR_RESET_MASK 0x1u
5188 #define ENET_ECR_RESET_SHIFT 0
5189 #define ENET_ECR_ETHEREN_MASK 0x2u
5190 #define ENET_ECR_ETHEREN_SHIFT 1
5191 #define ENET_ECR_MAGICEN_MASK 0x4u
5192 #define ENET_ECR_MAGICEN_SHIFT 2
5193 #define ENET_ECR_SLEEP_MASK 0x8u
5194 #define ENET_ECR_SLEEP_SHIFT 3
5195 #define ENET_ECR_EN1588_MASK 0x10u
5196 #define ENET_ECR_EN1588_SHIFT 4
5197 #define ENET_ECR_DBGEN_MASK 0x40u
5198 #define ENET_ECR_DBGEN_SHIFT 6
5199 #define ENET_ECR_STOPEN_MASK 0x80u
5200 #define ENET_ECR_STOPEN_SHIFT 7
5201 #define ENET_ECR_DBSWP_MASK 0x100u
5202 #define ENET_ECR_DBSWP_SHIFT 8
5203 /* MMFR Bit Fields */
5204 #define ENET_MMFR_DATA_MASK 0xFFFFu
5205 #define ENET_MMFR_DATA_SHIFT 0
5206 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_DATA_SHIFT))&ENET_MMFR_DATA_MASK)
5207 #define ENET_MMFR_TA_MASK 0x30000u
5208 #define ENET_MMFR_TA_SHIFT 16
5209 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_TA_SHIFT))&ENET_MMFR_TA_MASK)
5210 #define ENET_MMFR_RA_MASK 0x7C0000u
5211 #define ENET_MMFR_RA_SHIFT 18
5212 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_RA_SHIFT))&ENET_MMFR_RA_MASK)
5213 #define ENET_MMFR_PA_MASK 0xF800000u
5214 #define ENET_MMFR_PA_SHIFT 23
5215 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_PA_SHIFT))&ENET_MMFR_PA_MASK)
5216 #define ENET_MMFR_OP_MASK 0x30000000u
5217 #define ENET_MMFR_OP_SHIFT 28
5218 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_OP_SHIFT))&ENET_MMFR_OP_MASK)
5219 #define ENET_MMFR_ST_MASK 0xC0000000u
5220 #define ENET_MMFR_ST_SHIFT 30
5221 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x))<<ENET_MMFR_ST_SHIFT))&ENET_MMFR_ST_MASK)
5222 /* MSCR Bit Fields */
5223 #define ENET_MSCR_MII_SPEED_MASK 0x7Eu
5224 #define ENET_MSCR_MII_SPEED_SHIFT 1
5225 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_MII_SPEED_SHIFT))&ENET_MSCR_MII_SPEED_MASK)
5226 #define ENET_MSCR_DIS_PRE_MASK 0x80u
5227 #define ENET_MSCR_DIS_PRE_SHIFT 7
5228 #define ENET_MSCR_HOLDTIME_MASK 0x700u
5229 #define ENET_MSCR_HOLDTIME_SHIFT 8
5230 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_MSCR_HOLDTIME_SHIFT))&ENET_MSCR_HOLDTIME_MASK)
5231 /* MIBC Bit Fields */
5232 #define ENET_MIBC_MIB_CLEAR_MASK 0x20000000u
5233 #define ENET_MIBC_MIB_CLEAR_SHIFT 29
5234 #define ENET_MIBC_MIB_IDLE_MASK 0x40000000u
5235 #define ENET_MIBC_MIB_IDLE_SHIFT 30
5236 #define ENET_MIBC_MIB_DIS_MASK 0x80000000u
5237 #define ENET_MIBC_MIB_DIS_SHIFT 31
5238 /* RCR Bit Fields */
5239 #define ENET_RCR_LOOP_MASK 0x1u
5240 #define ENET_RCR_LOOP_SHIFT 0
5241 #define ENET_RCR_DRT_MASK 0x2u
5242 #define ENET_RCR_DRT_SHIFT 1
5243 #define ENET_RCR_MII_MODE_MASK 0x4u
5244 #define ENET_RCR_MII_MODE_SHIFT 2
5245 #define ENET_RCR_PROM_MASK 0x8u
5246 #define ENET_RCR_PROM_SHIFT 3
5247 #define ENET_RCR_BC_REJ_MASK 0x10u
5248 #define ENET_RCR_BC_REJ_SHIFT 4
5249 #define ENET_RCR_FCE_MASK 0x20u
5250 #define ENET_RCR_FCE_SHIFT 5
5251 #define ENET_RCR_RMII_MODE_MASK 0x100u
5252 #define ENET_RCR_RMII_MODE_SHIFT 8
5253 #define ENET_RCR_RMII_10T_MASK 0x200u
5254 #define ENET_RCR_RMII_10T_SHIFT 9
5255 #define ENET_RCR_PADEN_MASK 0x1000u
5256 #define ENET_RCR_PADEN_SHIFT 12
5257 #define ENET_RCR_PAUFWD_MASK 0x2000u
5258 #define ENET_RCR_PAUFWD_SHIFT 13
5259 #define ENET_RCR_CRCFWD_MASK 0x4000u
5260 #define ENET_RCR_CRCFWD_SHIFT 14
5261 #define ENET_RCR_CFEN_MASK 0x8000u
5262 #define ENET_RCR_CFEN_SHIFT 15
5263 #define ENET_RCR_MAX_FL_MASK 0x3FFF0000u
5264 #define ENET_RCR_MAX_FL_SHIFT 16
5265 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RCR_MAX_FL_SHIFT))&ENET_RCR_MAX_FL_MASK)
5266 #define ENET_RCR_NLC_MASK 0x40000000u
5267 #define ENET_RCR_NLC_SHIFT 30
5268 #define ENET_RCR_GRS_MASK 0x80000000u
5269 #define ENET_RCR_GRS_SHIFT 31
5270 /* TCR Bit Fields */
5271 #define ENET_TCR_GTS_MASK 0x1u
5272 #define ENET_TCR_GTS_SHIFT 0
5273 #define ENET_TCR_FDEN_MASK 0x4u
5274 #define ENET_TCR_FDEN_SHIFT 2
5275 #define ENET_TCR_TFC_PAUSE_MASK 0x8u
5276 #define ENET_TCR_TFC_PAUSE_SHIFT 3
5277 #define ENET_TCR_RFC_PAUSE_MASK 0x10u
5278 #define ENET_TCR_RFC_PAUSE_SHIFT 4
5279 #define ENET_TCR_ADDSEL_MASK 0xE0u
5280 #define ENET_TCR_ADDSEL_SHIFT 5
5281 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCR_ADDSEL_SHIFT))&ENET_TCR_ADDSEL_MASK)
5282 #define ENET_TCR_ADDINS_MASK 0x100u
5283 #define ENET_TCR_ADDINS_SHIFT 8
5284 #define ENET_TCR_CRCFWD_MASK 0x200u
5285 #define ENET_TCR_CRCFWD_SHIFT 9
5286 /* PALR Bit Fields */
5287 #define ENET_PALR_PADDR1_MASK 0xFFFFFFFFu
5288 #define ENET_PALR_PADDR1_SHIFT 0
5289 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_PALR_PADDR1_SHIFT))&ENET_PALR_PADDR1_MASK)
5290 /* PAUR Bit Fields */
5291 #define ENET_PAUR_TYPE_MASK 0xFFFFu
5292 #define ENET_PAUR_TYPE_SHIFT 0
5293 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_TYPE_SHIFT))&ENET_PAUR_TYPE_MASK)
5294 #define ENET_PAUR_PADDR2_MASK 0xFFFF0000u
5295 #define ENET_PAUR_PADDR2_SHIFT 16
5296 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_PAUR_PADDR2_SHIFT))&ENET_PAUR_PADDR2_MASK)
5297 /* OPD Bit Fields */
5298 #define ENET_OPD_PAUSE_DUR_MASK 0xFFFFu
5299 #define ENET_OPD_PAUSE_DUR_SHIFT 0
5300 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_PAUSE_DUR_SHIFT))&ENET_OPD_PAUSE_DUR_MASK)
5301 #define ENET_OPD_OPCODE_MASK 0xFFFF0000u
5302 #define ENET_OPD_OPCODE_SHIFT 16
5303 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_OPD_OPCODE_SHIFT))&ENET_OPD_OPCODE_MASK)
5304 /* IAUR Bit Fields */
5305 #define ENET_IAUR_IADDR1_MASK 0xFFFFFFFFu
5306 #define ENET_IAUR_IADDR1_SHIFT 0
5307 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_IAUR_IADDR1_SHIFT))&ENET_IAUR_IADDR1_MASK)
5308 /* IALR Bit Fields */
5309 #define ENET_IALR_IADDR2_MASK 0xFFFFFFFFu
5310 #define ENET_IALR_IADDR2_SHIFT 0
5311 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_IALR_IADDR2_SHIFT))&ENET_IALR_IADDR2_MASK)
5312 /* GAUR Bit Fields */
5313 #define ENET_GAUR_GADDR1_MASK 0xFFFFFFFFu
5314 #define ENET_GAUR_GADDR1_SHIFT 0
5315 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x))<<ENET_GAUR_GADDR1_SHIFT))&ENET_GAUR_GADDR1_MASK)
5316 /* GALR Bit Fields */
5317 #define ENET_GALR_GADDR2_MASK 0xFFFFFFFFu
5318 #define ENET_GALR_GADDR2_SHIFT 0
5319 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x))<<ENET_GALR_GADDR2_SHIFT))&ENET_GALR_GADDR2_MASK)
5320 /* TFWR Bit Fields */
5321 #define ENET_TFWR_TFWR_MASK 0x3Fu
5322 #define ENET_TFWR_TFWR_SHIFT 0
5323 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x))<<ENET_TFWR_TFWR_SHIFT))&ENET_TFWR_TFWR_MASK)
5324 #define ENET_TFWR_STRFWD_MASK 0x100u
5325 #define ENET_TFWR_STRFWD_SHIFT 8
5326 /* RDSR Bit Fields */
5327 #define ENET_RDSR_R_DES_START_MASK 0xFFFFFFF8u
5328 #define ENET_RDSR_R_DES_START_SHIFT 3
5329 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_RDSR_R_DES_START_SHIFT))&ENET_RDSR_R_DES_START_MASK)
5330 /* TDSR Bit Fields */
5331 #define ENET_TDSR_X_DES_START_MASK 0xFFFFFFF8u
5332 #define ENET_TDSR_X_DES_START_SHIFT 3
5333 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x))<<ENET_TDSR_X_DES_START_SHIFT))&ENET_TDSR_X_DES_START_MASK)
5334 /* MRBR Bit Fields */
5335 #define ENET_MRBR_R_BUF_SIZE_MASK 0x3FF0u
5336 #define ENET_MRBR_R_BUF_SIZE_SHIFT 4
5337 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x))<<ENET_MRBR_R_BUF_SIZE_SHIFT))&ENET_MRBR_R_BUF_SIZE_MASK)
5338 /* RSFL Bit Fields */
5339 #define ENET_RSFL_RX_SECTION_FULL_MASK 0xFFu
5340 #define ENET_RSFL_RX_SECTION_FULL_SHIFT 0
5341 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSFL_RX_SECTION_FULL_SHIFT))&ENET_RSFL_RX_SECTION_FULL_MASK)
5342 /* RSEM Bit Fields */
5343 #define ENET_RSEM_RX_SECTION_EMPTY_MASK 0xFFu
5344 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT 0
5345 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_RX_SECTION_EMPTY_SHIFT))&ENET_RSEM_RX_SECTION_EMPTY_MASK)
5346 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK 0x1F0000u
5347 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT 16
5348 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RSEM_STAT_SECTION_EMPTY_SHIFT))&ENET_RSEM_STAT_SECTION_EMPTY_MASK)
5349 /* RAEM Bit Fields */
5350 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK 0xFFu
5351 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT 0
5352 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAEM_RX_ALMOST_EMPTY_SHIFT))&ENET_RAEM_RX_ALMOST_EMPTY_MASK)
5353 /* RAFL Bit Fields */
5354 #define ENET_RAFL_RX_ALMOST_FULL_MASK 0xFFu
5355 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT 0
5356 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_RAFL_RX_ALMOST_FULL_SHIFT))&ENET_RAFL_RX_ALMOST_FULL_MASK)
5357 /* TSEM Bit Fields */
5358 #define ENET_TSEM_TX_SECTION_EMPTY_MASK 0xFFu
5359 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT 0
5360 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TSEM_TX_SECTION_EMPTY_SHIFT))&ENET_TSEM_TX_SECTION_EMPTY_MASK)
5361 /* TAEM Bit Fields */
5362 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK 0xFFu
5363 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT 0
5364 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAEM_TX_ALMOST_EMPTY_SHIFT))&ENET_TAEM_TX_ALMOST_EMPTY_MASK)
5365 /* TAFL Bit Fields */
5366 #define ENET_TAFL_TX_ALMOST_FULL_MASK 0xFFu
5367 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT 0
5368 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x))<<ENET_TAFL_TX_ALMOST_FULL_SHIFT))&ENET_TAFL_TX_ALMOST_FULL_MASK)
5369 /* TIPG Bit Fields */
5370 #define ENET_TIPG_IPG_MASK 0x1Fu
5371 #define ENET_TIPG_IPG_SHIFT 0
5372 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x))<<ENET_TIPG_IPG_SHIFT))&ENET_TIPG_IPG_MASK)
5373 /* FTRL Bit Fields */
5374 #define ENET_FTRL_TRUNC_FL_MASK 0x3FFFu
5375 #define ENET_FTRL_TRUNC_FL_SHIFT 0
5376 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x))<<ENET_FTRL_TRUNC_FL_SHIFT))&ENET_FTRL_TRUNC_FL_MASK)
5377 /* TACC Bit Fields */
5378 #define ENET_TACC_SHIFT16_MASK 0x1u
5379 #define ENET_TACC_SHIFT16_SHIFT 0
5380 #define ENET_TACC_IPCHK_MASK 0x8u
5381 #define ENET_TACC_IPCHK_SHIFT 3
5382 #define ENET_TACC_PROCHK_MASK 0x10u
5383 #define ENET_TACC_PROCHK_SHIFT 4
5384 /* RACC Bit Fields */
5385 #define ENET_RACC_PADREM_MASK 0x1u
5386 #define ENET_RACC_PADREM_SHIFT 0
5387 #define ENET_RACC_IPDIS_MASK 0x2u
5388 #define ENET_RACC_IPDIS_SHIFT 1
5389 #define ENET_RACC_PRODIS_MASK 0x4u
5390 #define ENET_RACC_PRODIS_SHIFT 2
5391 #define ENET_RACC_LINEDIS_MASK 0x40u
5392 #define ENET_RACC_LINEDIS_SHIFT 6
5393 #define ENET_RACC_SHIFT16_MASK 0x80u
5394 #define ENET_RACC_SHIFT16_SHIFT 7
5395 /* RMON_T_PACKETS Bit Fields */
5396 #define ENET_RMON_T_PACKETS_TXPKTS_MASK 0xFFFFu
5397 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT 0
5398 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_PACKETS_TXPKTS_SHIFT))&ENET_RMON_T_PACKETS_TXPKTS_MASK)
5399 /* RMON_T_BC_PKT Bit Fields */
5400 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK 0xFFFFu
5401 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT 0
5402 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_BC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_BC_PKT_TXPKTS_MASK)
5403 /* RMON_T_MC_PKT Bit Fields */
5404 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK 0xFFFFu
5405 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT 0
5406 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_MC_PKT_TXPKTS_SHIFT))&ENET_RMON_T_MC_PKT_TXPKTS_MASK)
5407 /* RMON_T_CRC_ALIGN Bit Fields */
5408 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK 0xFFFFu
5409 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT 0
5410 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT))&ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
5411 /* RMON_T_UNDERSIZE Bit Fields */
5412 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK 0xFFFFu
5413 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT 0
5414 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
5415 /* RMON_T_OVERSIZE Bit Fields */
5416 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK 0xFFFFu
5417 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT 0
5418 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT))&ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
5419 /* RMON_T_FRAG Bit Fields */
5420 #define ENET_RMON_T_FRAG_TXPKTS_MASK 0xFFFFu
5421 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT 0
5422 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_FRAG_TXPKTS_SHIFT))&ENET_RMON_T_FRAG_TXPKTS_MASK)
5423 /* RMON_T_JAB Bit Fields */
5424 #define ENET_RMON_T_JAB_TXPKTS_MASK 0xFFFFu
5425 #define ENET_RMON_T_JAB_TXPKTS_SHIFT 0
5426 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_JAB_TXPKTS_SHIFT))&ENET_RMON_T_JAB_TXPKTS_MASK)
5427 /* RMON_T_COL Bit Fields */
5428 #define ENET_RMON_T_COL_TXPKTS_MASK 0xFFFFu
5429 #define ENET_RMON_T_COL_TXPKTS_SHIFT 0
5430 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_COL_TXPKTS_SHIFT))&ENET_RMON_T_COL_TXPKTS_MASK)
5431 /* RMON_T_P64 Bit Fields */
5432 #define ENET_RMON_T_P64_TXPKTS_MASK 0xFFFFu
5433 #define ENET_RMON_T_P64_TXPKTS_SHIFT 0
5434 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P64_TXPKTS_SHIFT))&ENET_RMON_T_P64_TXPKTS_MASK)
5435 /* RMON_T_P65TO127 Bit Fields */
5436 #define ENET_RMON_T_P65TO127_TXPKTS_MASK 0xFFFFu
5437 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT 0
5438 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P65TO127_TXPKTS_SHIFT))&ENET_RMON_T_P65TO127_TXPKTS_MASK)
5439 /* RMON_T_P128TO255 Bit Fields */
5440 #define ENET_RMON_T_P128TO255_TXPKTS_MASK 0xFFFFu
5441 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT 0
5442 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P128TO255_TXPKTS_SHIFT))&ENET_RMON_T_P128TO255_TXPKTS_MASK)
5443 /* RMON_T_P256TO511 Bit Fields */
5444 #define ENET_RMON_T_P256TO511_TXPKTS_MASK 0xFFFFu
5445 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT 0
5446 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P256TO511_TXPKTS_SHIFT))&ENET_RMON_T_P256TO511_TXPKTS_MASK)
5447 /* RMON_T_P512TO1023 Bit Fields */
5448 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK 0xFFFFu
5449 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT 0
5450 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P512TO1023_TXPKTS_SHIFT))&ENET_RMON_T_P512TO1023_TXPKTS_MASK)
5451 /* RMON_T_P1024TO2047 Bit Fields */
5452 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK 0xFFFFu
5453 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT 0
5454 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT))&ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
5455 /* RMON_T_P_GTE2048 Bit Fields */
5456 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK 0xFFFFu
5457 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT 0
5458 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT))&ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
5459 /* RMON_T_OCTETS Bit Fields */
5460 #define ENET_RMON_T_OCTETS_TXOCTS_MASK 0xFFFFFFFFu
5461 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT 0
5462 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_T_OCTETS_TXOCTS_SHIFT))&ENET_RMON_T_OCTETS_TXOCTS_MASK)
5463 /* IEEE_T_FRAME_OK Bit Fields */
5464 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK 0xFFFFu
5465 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT 0
5466 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_T_FRAME_OK_COUNT_MASK)
5467 /* IEEE_T_1COL Bit Fields */
5468 #define ENET_IEEE_T_1COL_COUNT_MASK 0xFFFFu
5469 #define ENET_IEEE_T_1COL_COUNT_SHIFT 0
5470 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_1COL_COUNT_SHIFT))&ENET_IEEE_T_1COL_COUNT_MASK)
5471 /* IEEE_T_MCOL Bit Fields */
5472 #define ENET_IEEE_T_MCOL_COUNT_MASK 0xFFFFu
5473 #define ENET_IEEE_T_MCOL_COUNT_SHIFT 0
5474 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MCOL_COUNT_SHIFT))&ENET_IEEE_T_MCOL_COUNT_MASK)
5475 /* IEEE_T_DEF Bit Fields */
5476 #define ENET_IEEE_T_DEF_COUNT_MASK 0xFFFFu
5477 #define ENET_IEEE_T_DEF_COUNT_SHIFT 0
5478 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_DEF_COUNT_SHIFT))&ENET_IEEE_T_DEF_COUNT_MASK)
5479 /* IEEE_T_LCOL Bit Fields */
5480 #define ENET_IEEE_T_LCOL_COUNT_MASK 0xFFFFu
5481 #define ENET_IEEE_T_LCOL_COUNT_SHIFT 0
5482 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_LCOL_COUNT_SHIFT))&ENET_IEEE_T_LCOL_COUNT_MASK)
5483 /* IEEE_T_EXCOL Bit Fields */
5484 #define ENET_IEEE_T_EXCOL_COUNT_MASK 0xFFFFu
5485 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT 0
5486 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_EXCOL_COUNT_SHIFT))&ENET_IEEE_T_EXCOL_COUNT_MASK)
5487 /* IEEE_T_MACERR Bit Fields */
5488 #define ENET_IEEE_T_MACERR_COUNT_MASK 0xFFFFu
5489 #define ENET_IEEE_T_MACERR_COUNT_SHIFT 0
5490 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_MACERR_COUNT_SHIFT))&ENET_IEEE_T_MACERR_COUNT_MASK)
5491 /* IEEE_T_CSERR Bit Fields */
5492 #define ENET_IEEE_T_CSERR_COUNT_MASK 0xFFFFu
5493 #define ENET_IEEE_T_CSERR_COUNT_SHIFT 0
5494 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_CSERR_COUNT_SHIFT))&ENET_IEEE_T_CSERR_COUNT_MASK)
5495 /* IEEE_T_FDXFC Bit Fields */
5496 #define ENET_IEEE_T_FDXFC_COUNT_MASK 0xFFFFu
5497 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT 0
5498 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_FDXFC_COUNT_SHIFT))&ENET_IEEE_T_FDXFC_COUNT_MASK)
5499 /* IEEE_T_OCTETS_OK Bit Fields */
5500 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
5501 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT 0
5502 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
5503 /* RMON_R_PACKETS Bit Fields */
5504 #define ENET_RMON_R_PACKETS_COUNT_MASK 0xFFFFu
5505 #define ENET_RMON_R_PACKETS_COUNT_SHIFT 0
5506 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_PACKETS_COUNT_SHIFT))&ENET_RMON_R_PACKETS_COUNT_MASK)
5507 /* RMON_R_BC_PKT Bit Fields */
5508 #define ENET_RMON_R_BC_PKT_COUNT_MASK 0xFFFFu
5509 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT 0
5510 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_BC_PKT_COUNT_SHIFT))&ENET_RMON_R_BC_PKT_COUNT_MASK)
5511 /* RMON_R_MC_PKT Bit Fields */
5512 #define ENET_RMON_R_MC_PKT_COUNT_MASK 0xFFFFu
5513 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT 0
5514 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_MC_PKT_COUNT_SHIFT))&ENET_RMON_R_MC_PKT_COUNT_MASK)
5515 /* RMON_R_CRC_ALIGN Bit Fields */
5516 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK 0xFFFFu
5517 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT 0
5518 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT))&ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
5519 /* RMON_R_UNDERSIZE Bit Fields */
5520 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK 0xFFFFu
5521 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT 0
5522 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_UNDERSIZE_COUNT_SHIFT))&ENET_RMON_R_UNDERSIZE_COUNT_MASK)
5523 /* RMON_R_OVERSIZE Bit Fields */
5524 #define ENET_RMON_R_OVERSIZE_COUNT_MASK 0xFFFFu
5525 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT 0
5526 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OVERSIZE_COUNT_SHIFT))&ENET_RMON_R_OVERSIZE_COUNT_MASK)
5527 /* RMON_R_FRAG Bit Fields */
5528 #define ENET_RMON_R_FRAG_COUNT_MASK 0xFFFFu
5529 #define ENET_RMON_R_FRAG_COUNT_SHIFT 0
5530 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_FRAG_COUNT_SHIFT))&ENET_RMON_R_FRAG_COUNT_MASK)
5531 /* RMON_R_JAB Bit Fields */
5532 #define ENET_RMON_R_JAB_COUNT_MASK 0xFFFFu
5533 #define ENET_RMON_R_JAB_COUNT_SHIFT 0
5534 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_JAB_COUNT_SHIFT))&ENET_RMON_R_JAB_COUNT_MASK)
5535 /* RMON_R_P64 Bit Fields */
5536 #define ENET_RMON_R_P64_COUNT_MASK 0xFFFFu
5537 #define ENET_RMON_R_P64_COUNT_SHIFT 0
5538 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P64_COUNT_SHIFT))&ENET_RMON_R_P64_COUNT_MASK)
5539 /* RMON_R_P65TO127 Bit Fields */
5540 #define ENET_RMON_R_P65TO127_COUNT_MASK 0xFFFFu
5541 #define ENET_RMON_R_P65TO127_COUNT_SHIFT 0
5542 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P65TO127_COUNT_SHIFT))&ENET_RMON_R_P65TO127_COUNT_MASK)
5543 /* RMON_R_P128TO255 Bit Fields */
5544 #define ENET_RMON_R_P128TO255_COUNT_MASK 0xFFFFu
5545 #define ENET_RMON_R_P128TO255_COUNT_SHIFT 0
5546 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P128TO255_COUNT_SHIFT))&ENET_RMON_R_P128TO255_COUNT_MASK)
5547 /* RMON_R_P256TO511 Bit Fields */
5548 #define ENET_RMON_R_P256TO511_COUNT_MASK 0xFFFFu
5549 #define ENET_RMON_R_P256TO511_COUNT_SHIFT 0
5550 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P256TO511_COUNT_SHIFT))&ENET_RMON_R_P256TO511_COUNT_MASK)
5551 /* RMON_R_P512TO1023 Bit Fields */
5552 #define ENET_RMON_R_P512TO1023_COUNT_MASK 0xFFFFu
5553 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT 0
5554 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P512TO1023_COUNT_SHIFT))&ENET_RMON_R_P512TO1023_COUNT_MASK)
5555 /* RMON_R_P1024TO2047 Bit Fields */
5556 #define ENET_RMON_R_P1024TO2047_COUNT_MASK 0xFFFFu
5557 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT 0
5558 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P1024TO2047_COUNT_SHIFT))&ENET_RMON_R_P1024TO2047_COUNT_MASK)
5559 /* RMON_R_P_GTE2048 Bit Fields */
5560 #define ENET_RMON_R_P_GTE2048_COUNT_MASK 0xFFFFu
5561 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT 0
5562 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_P_GTE2048_COUNT_SHIFT))&ENET_RMON_R_P_GTE2048_COUNT_MASK)
5563 /* RMON_R_OCTETS Bit Fields */
5564 #define ENET_RMON_R_OCTETS_COUNT_MASK 0xFFFFFFFFu
5565 #define ENET_RMON_R_OCTETS_COUNT_SHIFT 0
5566 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_RMON_R_OCTETS_COUNT_SHIFT))&ENET_RMON_R_OCTETS_COUNT_MASK)
5567 /* IEEE_R_DROP Bit Fields */
5568 #define ENET_IEEE_R_DROP_COUNT_MASK 0xFFFFu
5569 #define ENET_IEEE_R_DROP_COUNT_SHIFT 0
5570 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_DROP_COUNT_SHIFT))&ENET_IEEE_R_DROP_COUNT_MASK)
5571 /* IEEE_R_FRAME_OK Bit Fields */
5572 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK 0xFFFFu
5573 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT 0
5574 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FRAME_OK_COUNT_SHIFT))&ENET_IEEE_R_FRAME_OK_COUNT_MASK)
5575 /* IEEE_R_CRC Bit Fields */
5576 #define ENET_IEEE_R_CRC_COUNT_MASK 0xFFFFu
5577 #define ENET_IEEE_R_CRC_COUNT_SHIFT 0
5578 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_CRC_COUNT_SHIFT))&ENET_IEEE_R_CRC_COUNT_MASK)
5579 /* IEEE_R_ALIGN Bit Fields */
5580 #define ENET_IEEE_R_ALIGN_COUNT_MASK 0xFFFFu
5581 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT 0
5582 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_ALIGN_COUNT_SHIFT))&ENET_IEEE_R_ALIGN_COUNT_MASK)
5583 /* IEEE_R_MACERR Bit Fields */
5584 #define ENET_IEEE_R_MACERR_COUNT_MASK 0xFFFFu
5585 #define ENET_IEEE_R_MACERR_COUNT_SHIFT 0
5586 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_MACERR_COUNT_SHIFT))&ENET_IEEE_R_MACERR_COUNT_MASK)
5587 /* IEEE_R_FDXFC Bit Fields */
5588 #define ENET_IEEE_R_FDXFC_COUNT_MASK 0xFFFFu
5589 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT 0
5590 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_FDXFC_COUNT_SHIFT))&ENET_IEEE_R_FDXFC_COUNT_MASK)
5591 /* IEEE_R_OCTETS_OK Bit Fields */
5592 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK 0xFFFFFFFFu
5593 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT 0
5594 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x))<<ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT))&ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
5595 /* ATCR Bit Fields */
5596 #define ENET_ATCR_EN_MASK 0x1u
5597 #define ENET_ATCR_EN_SHIFT 0
5598 #define ENET_ATCR_OFFEN_MASK 0x4u
5599 #define ENET_ATCR_OFFEN_SHIFT 2
5600 #define ENET_ATCR_OFFRST_MASK 0x8u
5601 #define ENET_ATCR_OFFRST_SHIFT 3
5602 #define ENET_ATCR_PEREN_MASK 0x10u
5603 #define ENET_ATCR_PEREN_SHIFT 4
5604 #define ENET_ATCR_PINPER_MASK 0x80u
5605 #define ENET_ATCR_PINPER_SHIFT 7
5606 #define ENET_ATCR_RESTART_MASK 0x200u
5607 #define ENET_ATCR_RESTART_SHIFT 9
5608 #define ENET_ATCR_CAPTURE_MASK 0x800u
5609 #define ENET_ATCR_CAPTURE_SHIFT 11
5610 #define ENET_ATCR_SLAVE_MASK 0x2000u
5611 #define ENET_ATCR_SLAVE_SHIFT 13
5612 /* ATVR Bit Fields */
5613 #define ENET_ATVR_ATIME_MASK 0xFFFFFFFFu
5614 #define ENET_ATVR_ATIME_SHIFT 0
5615 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATVR_ATIME_SHIFT))&ENET_ATVR_ATIME_MASK)
5616 /* ATOFF Bit Fields */
5617 #define ENET_ATOFF_OFFSET_MASK 0xFFFFFFFFu
5618 #define ENET_ATOFF_OFFSET_SHIFT 0
5619 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATOFF_OFFSET_SHIFT))&ENET_ATOFF_OFFSET_MASK)
5620 /* ATPER Bit Fields */
5621 #define ENET_ATPER_PERIOD_MASK 0xFFFFFFFFu
5622 #define ENET_ATPER_PERIOD_SHIFT 0
5623 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATPER_PERIOD_SHIFT))&ENET_ATPER_PERIOD_MASK)
5624 /* ATCOR Bit Fields */
5625 #define ENET_ATCOR_COR_MASK 0x7FFFFFFFu
5626 #define ENET_ATCOR_COR_SHIFT 0
5627 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATCOR_COR_SHIFT))&ENET_ATCOR_COR_MASK)
5628 /* ATINC Bit Fields */
5629 #define ENET_ATINC_INC_MASK 0x7Fu
5630 #define ENET_ATINC_INC_SHIFT 0
5631 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_SHIFT))&ENET_ATINC_INC_MASK)
5632 #define ENET_ATINC_INC_CORR_MASK 0x7F00u
5633 #define ENET_ATINC_INC_CORR_SHIFT 8
5634 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATINC_INC_CORR_SHIFT))&ENET_ATINC_INC_CORR_MASK)
5635 /* ATSTMP Bit Fields */
5636 #define ENET_ATSTMP_TIMESTAMP_MASK 0xFFFFFFFFu
5637 #define ENET_ATSTMP_TIMESTAMP_SHIFT 0
5638 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x))<<ENET_ATSTMP_TIMESTAMP_SHIFT))&ENET_ATSTMP_TIMESTAMP_MASK)
5639 /* TGSR Bit Fields */
5640 #define ENET_TGSR_TF0_MASK 0x1u
5641 #define ENET_TGSR_TF0_SHIFT 0
5642 #define ENET_TGSR_TF1_MASK 0x2u
5643 #define ENET_TGSR_TF1_SHIFT 1
5644 #define ENET_TGSR_TF2_MASK 0x4u
5645 #define ENET_TGSR_TF2_SHIFT 2
5646 #define ENET_TGSR_TF3_MASK 0x8u
5647 #define ENET_TGSR_TF3_SHIFT 3
5648 /* TCSR Bit Fields */
5649 #define ENET_TCSR_TDRE_MASK 0x1u
5650 #define ENET_TCSR_TDRE_SHIFT 0
5651 #define ENET_TCSR_TMODE_MASK 0x3Cu
5652 #define ENET_TCSR_TMODE_SHIFT 2
5653 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCSR_TMODE_SHIFT))&ENET_TCSR_TMODE_MASK)
5654 #define ENET_TCSR_TIE_MASK 0x40u
5655 #define ENET_TCSR_TIE_SHIFT 6
5656 #define ENET_TCSR_TF_MASK 0x80u
5657 #define ENET_TCSR_TF_SHIFT 7
5658 /* TCCR Bit Fields */
5659 #define ENET_TCCR_TCC_MASK 0xFFFFFFFFu
5660 #define ENET_TCCR_TCC_SHIFT 0
5661 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x))<<ENET_TCCR_TCC_SHIFT))&ENET_TCCR_TCC_MASK)
5662
5663 /*!
5664 * @}
5665 */ /* end of group ENET_Register_Masks */
5666
5667
5668 /* ENET - Peripheral instance base addresses */
5669 /** Peripheral ENET base address */
5670 #define ENET_BASE (0x400C0000u)
5671 /** Peripheral ENET base pointer */
5672 #define ENET ((ENET_Type *)ENET_BASE)
5673 #define ENET_BASE_PTR (ENET)
5674 /** Array initializer of ENET peripheral base addresses */
5675 #define ENET_BASE_ADDRS { ENET_BASE }
5676 /** Array initializer of ENET peripheral base pointers */
5677 #define ENET_BASE_PTRS { ENET }
5678 /** Interrupt vectors for the ENET peripheral type */
5679 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
5680 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
5681 #define ENET_Error_IRQS { ENET_Error_IRQn }
5682 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
5683
5684 /* ----------------------------------------------------------------------------
5685 -- ENET - Register accessor macros
5686 ---------------------------------------------------------------------------- */
5687
5688 /*!
5689 * @addtogroup ENET_Register_Accessor_Macros ENET - Register accessor macros
5690 * @{
5691 */
5692
5693
5694 /* ENET - Register instance definitions */
5695 /* ENET */
5696 #define ENET_EIR ENET_EIR_REG(ENET)
5697 #define ENET_EIMR ENET_EIMR_REG(ENET)
5698 #define ENET_RDAR ENET_RDAR_REG(ENET)
5699 #define ENET_TDAR ENET_TDAR_REG(ENET)
5700 #define ENET_ECR ENET_ECR_REG(ENET)
5701 #define ENET_MMFR ENET_MMFR_REG(ENET)
5702 #define ENET_MSCR ENET_MSCR_REG(ENET)
5703 #define ENET_MIBC ENET_MIBC_REG(ENET)
5704 #define ENET_RCR ENET_RCR_REG(ENET)
5705 #define ENET_TCR ENET_TCR_REG(ENET)
5706 #define ENET_PALR ENET_PALR_REG(ENET)
5707 #define ENET_PAUR ENET_PAUR_REG(ENET)
5708 #define ENET_OPD ENET_OPD_REG(ENET)
5709 #define ENET_IAUR ENET_IAUR_REG(ENET)
5710 #define ENET_IALR ENET_IALR_REG(ENET)
5711 #define ENET_GAUR ENET_GAUR_REG(ENET)
5712 #define ENET_GALR ENET_GALR_REG(ENET)
5713 #define ENET_TFWR ENET_TFWR_REG(ENET)
5714 #define ENET_RDSR ENET_RDSR_REG(ENET)
5715 #define ENET_TDSR ENET_TDSR_REG(ENET)
5716 #define ENET_MRBR ENET_MRBR_REG(ENET)
5717 #define ENET_RSFL ENET_RSFL_REG(ENET)
5718 #define ENET_RSEM ENET_RSEM_REG(ENET)
5719 #define ENET_RAEM ENET_RAEM_REG(ENET)
5720 #define ENET_RAFL ENET_RAFL_REG(ENET)
5721 #define ENET_TSEM ENET_TSEM_REG(ENET)
5722 #define ENET_TAEM ENET_TAEM_REG(ENET)
5723 #define ENET_TAFL ENET_TAFL_REG(ENET)
5724 #define ENET_TIPG ENET_TIPG_REG(ENET)
5725 #define ENET_FTRL ENET_FTRL_REG(ENET)
5726 #define ENET_TACC ENET_TACC_REG(ENET)
5727 #define ENET_RACC ENET_RACC_REG(ENET)
5728 #define ENET_RMON_T_PACKETS ENET_RMON_T_PACKETS_REG(ENET)
5729 #define ENET_RMON_T_BC_PKT ENET_RMON_T_BC_PKT_REG(ENET)
5730 #define ENET_RMON_T_MC_PKT ENET_RMON_T_MC_PKT_REG(ENET)
5731 #define ENET_RMON_T_CRC_ALIGN ENET_RMON_T_CRC_ALIGN_REG(ENET)
5732 #define ENET_RMON_T_UNDERSIZE ENET_RMON_T_UNDERSIZE_REG(ENET)
5733 #define ENET_RMON_T_OVERSIZE ENET_RMON_T_OVERSIZE_REG(ENET)
5734 #define ENET_RMON_T_FRAG ENET_RMON_T_FRAG_REG(ENET)
5735 #define ENET_RMON_T_JAB ENET_RMON_T_JAB_REG(ENET)
5736 #define ENET_RMON_T_COL ENET_RMON_T_COL_REG(ENET)
5737 #define ENET_RMON_T_P64 ENET_RMON_T_P64_REG(ENET)
5738 #define ENET_RMON_T_P65TO127 ENET_RMON_T_P65TO127_REG(ENET)
5739 #define ENET_RMON_T_P128TO255 ENET_RMON_T_P128TO255_REG(ENET)
5740 #define ENET_RMON_T_P256TO511 ENET_RMON_T_P256TO511_REG(ENET)
5741 #define ENET_RMON_T_P512TO1023 ENET_RMON_T_P512TO1023_REG(ENET)
5742 #define ENET_RMON_T_P1024TO2047 ENET_RMON_T_P1024TO2047_REG(ENET)
5743 #define ENET_RMON_T_P_GTE2048 ENET_RMON_T_P_GTE2048_REG(ENET)
5744 #define ENET_RMON_T_OCTETS ENET_RMON_T_OCTETS_REG(ENET)
5745 #define ENET_IEEE_T_FRAME_OK ENET_IEEE_T_FRAME_OK_REG(ENET)
5746 #define ENET_IEEE_T_1COL ENET_IEEE_T_1COL_REG(ENET)
5747 #define ENET_IEEE_T_MCOL ENET_IEEE_T_MCOL_REG(ENET)
5748 #define ENET_IEEE_T_DEF ENET_IEEE_T_DEF_REG(ENET)
5749 #define ENET_IEEE_T_LCOL ENET_IEEE_T_LCOL_REG(ENET)
5750 #define ENET_IEEE_T_EXCOL ENET_IEEE_T_EXCOL_REG(ENET)
5751 #define ENET_IEEE_T_MACERR ENET_IEEE_T_MACERR_REG(ENET)
5752 #define ENET_IEEE_T_CSERR ENET_IEEE_T_CSERR_REG(ENET)
5753 #define ENET_IEEE_T_FDXFC ENET_IEEE_T_FDXFC_REG(ENET)
5754 #define ENET_IEEE_T_OCTETS_OK ENET_IEEE_T_OCTETS_OK_REG(ENET)
5755 #define ENET_RMON_R_PACKETS ENET_RMON_R_PACKETS_REG(ENET)
5756 #define ENET_RMON_R_BC_PKT ENET_RMON_R_BC_PKT_REG(ENET)
5757 #define ENET_RMON_R_MC_PKT ENET_RMON_R_MC_PKT_REG(ENET)
5758 #define ENET_RMON_R_CRC_ALIGN ENET_RMON_R_CRC_ALIGN_REG(ENET)
5759 #define ENET_RMON_R_UNDERSIZE ENET_RMON_R_UNDERSIZE_REG(ENET)
5760 #define ENET_RMON_R_OVERSIZE ENET_RMON_R_OVERSIZE_REG(ENET)
5761 #define ENET_RMON_R_FRAG ENET_RMON_R_FRAG_REG(ENET)
5762 #define ENET_RMON_R_JAB ENET_RMON_R_JAB_REG(ENET)
5763 #define ENET_RMON_R_P64 ENET_RMON_R_P64_REG(ENET)
5764 #define ENET_RMON_R_P65TO127 ENET_RMON_R_P65TO127_REG(ENET)
5765 #define ENET_RMON_R_P128TO255 ENET_RMON_R_P128TO255_REG(ENET)
5766 #define ENET_RMON_R_P256TO511 ENET_RMON_R_P256TO511_REG(ENET)
5767 #define ENET_RMON_R_P512TO1023 ENET_RMON_R_P512TO1023_REG(ENET)
5768 #define ENET_RMON_R_P1024TO2047 ENET_RMON_R_P1024TO2047_REG(ENET)
5769 #define ENET_RMON_R_P_GTE2048 ENET_RMON_R_P_GTE2048_REG(ENET)
5770 #define ENET_RMON_R_OCTETS ENET_RMON_R_OCTETS_REG(ENET)
5771 #define ENET_IEEE_R_DROP ENET_IEEE_R_DROP_REG(ENET)
5772 #define ENET_IEEE_R_FRAME_OK ENET_IEEE_R_FRAME_OK_REG(ENET)
5773 #define ENET_IEEE_R_CRC ENET_IEEE_R_CRC_REG(ENET)
5774 #define ENET_IEEE_R_ALIGN ENET_IEEE_R_ALIGN_REG(ENET)
5775 #define ENET_IEEE_R_MACERR ENET_IEEE_R_MACERR_REG(ENET)
5776 #define ENET_IEEE_R_FDXFC ENET_IEEE_R_FDXFC_REG(ENET)
5777 #define ENET_IEEE_R_OCTETS_OK ENET_IEEE_R_OCTETS_OK_REG(ENET)
5778 #define ENET_ATCR ENET_ATCR_REG(ENET)
5779 #define ENET_ATVR ENET_ATVR_REG(ENET)
5780 #define ENET_ATOFF ENET_ATOFF_REG(ENET)
5781 #define ENET_ATPER ENET_ATPER_REG(ENET)
5782 #define ENET_ATCOR ENET_ATCOR_REG(ENET)
5783 #define ENET_ATINC ENET_ATINC_REG(ENET)
5784 #define ENET_ATSTMP ENET_ATSTMP_REG(ENET)
5785 #define ENET_TGSR ENET_TGSR_REG(ENET)
5786 #define ENET_TCSR0 ENET_TCSR_REG(ENET,0)
5787 #define ENET_TCCR0 ENET_TCCR_REG(ENET,0)
5788 #define ENET_TCSR1 ENET_TCSR_REG(ENET,1)
5789 #define ENET_TCCR1 ENET_TCCR_REG(ENET,1)
5790 #define ENET_TCSR2 ENET_TCSR_REG(ENET,2)
5791 #define ENET_TCCR2 ENET_TCCR_REG(ENET,2)
5792 #define ENET_TCSR3 ENET_TCSR_REG(ENET,3)
5793 #define ENET_TCCR3 ENET_TCCR_REG(ENET,3)
5794
5795 /* ENET - Register array accessors */
5796 #define ENET_TCSR(index) ENET_TCSR_REG(ENET,index)
5797 #define ENET_TCCR(index) ENET_TCCR_REG(ENET,index)
5798
5799 /*!
5800 * @}
5801 */ /* end of group ENET_Register_Accessor_Macros */
5802
5803
5804 /*!
5805 * @}
5806 */ /* end of group ENET_Peripheral_Access_Layer */
5807
5808
5809 /* ----------------------------------------------------------------------------
5810 -- EWM Peripheral Access Layer
5811 ---------------------------------------------------------------------------- */
5812
5813 /*!
5814 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
5815 * @{
5816 */
5817
5818 /** EWM - Register Layout Typedef */
5819 typedef struct {
5820 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
5821 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
5822 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
5823 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
5824 } EWM_Type, *EWM_MemMapPtr;
5825
5826 /* ----------------------------------------------------------------------------
5827 -- EWM - Register accessor macros
5828 ---------------------------------------------------------------------------- */
5829
5830 /*!
5831 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
5832 * @{
5833 */
5834
5835
5836 /* EWM - Register accessors */
5837 #define EWM_CTRL_REG(base) ((base)->CTRL)
5838 #define EWM_SERV_REG(base) ((base)->SERV)
5839 #define EWM_CMPL_REG(base) ((base)->CMPL)
5840 #define EWM_CMPH_REG(base) ((base)->CMPH)
5841
5842 /*!
5843 * @}
5844 */ /* end of group EWM_Register_Accessor_Macros */
5845
5846
5847 /* ----------------------------------------------------------------------------
5848 -- EWM Register Masks
5849 ---------------------------------------------------------------------------- */
5850
5851 /*!
5852 * @addtogroup EWM_Register_Masks EWM Register Masks
5853 * @{
5854 */
5855
5856 /* CTRL Bit Fields */
5857 #define EWM_CTRL_EWMEN_MASK 0x1u
5858 #define EWM_CTRL_EWMEN_SHIFT 0
5859 #define EWM_CTRL_ASSIN_MASK 0x2u
5860 #define EWM_CTRL_ASSIN_SHIFT 1
5861 #define EWM_CTRL_INEN_MASK 0x4u
5862 #define EWM_CTRL_INEN_SHIFT 2
5863 #define EWM_CTRL_INTEN_MASK 0x8u
5864 #define EWM_CTRL_INTEN_SHIFT 3
5865 /* SERV Bit Fields */
5866 #define EWM_SERV_SERVICE_MASK 0xFFu
5867 #define EWM_SERV_SERVICE_SHIFT 0
5868 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<<EWM_SERV_SERVICE_SHIFT))&EWM_SERV_SERVICE_MASK)
5869 /* CMPL Bit Fields */
5870 #define EWM_CMPL_COMPAREL_MASK 0xFFu
5871 #define EWM_CMPL_COMPAREL_SHIFT 0
5872 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPL_COMPAREL_SHIFT))&EWM_CMPL_COMPAREL_MASK)
5873 /* CMPH Bit Fields */
5874 #define EWM_CMPH_COMPAREH_MASK 0xFFu
5875 #define EWM_CMPH_COMPAREH_SHIFT 0
5876 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x))<<EWM_CMPH_COMPAREH_SHIFT))&EWM_CMPH_COMPAREH_MASK)
5877
5878 /*!
5879 * @}
5880 */ /* end of group EWM_Register_Masks */
5881
5882
5883 /* EWM - Peripheral instance base addresses */
5884 /** Peripheral EWM base address */
5885 #define EWM_BASE (0x40061000u)
5886 /** Peripheral EWM base pointer */
5887 #define EWM ((EWM_Type *)EWM_BASE)
5888 #define EWM_BASE_PTR (EWM)
5889 /** Array initializer of EWM peripheral base addresses */
5890 #define EWM_BASE_ADDRS { EWM_BASE }
5891 /** Array initializer of EWM peripheral base pointers */
5892 #define EWM_BASE_PTRS { EWM }
5893 /** Interrupt vectors for the EWM peripheral type */
5894 #define EWM_IRQS { Watchdog_IRQn }
5895
5896 /* ----------------------------------------------------------------------------
5897 -- EWM - Register accessor macros
5898 ---------------------------------------------------------------------------- */
5899
5900 /*!
5901 * @addtogroup EWM_Register_Accessor_Macros EWM - Register accessor macros
5902 * @{
5903 */
5904
5905
5906 /* EWM - Register instance definitions */
5907 /* EWM */
5908 #define EWM_CTRL EWM_CTRL_REG(EWM)
5909 #define EWM_SERV EWM_SERV_REG(EWM)
5910 #define EWM_CMPL EWM_CMPL_REG(EWM)
5911 #define EWM_CMPH EWM_CMPH_REG(EWM)
5912
5913 /*!
5914 * @}
5915 */ /* end of group EWM_Register_Accessor_Macros */
5916
5917
5918 /*!
5919 * @}
5920 */ /* end of group EWM_Peripheral_Access_Layer */
5921
5922
5923 /* ----------------------------------------------------------------------------
5924 -- FB Peripheral Access Layer
5925 ---------------------------------------------------------------------------- */
5926
5927 /*!
5928 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
5929 * @{
5930 */
5931
5932 /** FB - Register Layout Typedef */
5933 typedef struct {
5934 struct { /* offset: 0x0, array step: 0xC */
5935 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
5936 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
5937 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
5938 } CS[6];
5939 uint8_t RESERVED_0[24];
5940 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
5941 } FB_Type, *FB_MemMapPtr;
5942
5943 /* ----------------------------------------------------------------------------
5944 -- FB - Register accessor macros
5945 ---------------------------------------------------------------------------- */
5946
5947 /*!
5948 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
5949 * @{
5950 */
5951
5952
5953 /* FB - Register accessors */
5954 #define FB_CSAR_REG(base,index) ((base)->CS[index].CSAR)
5955 #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR)
5956 #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR)
5957 #define FB_CSPMCR_REG(base) ((base)->CSPMCR)
5958
5959 /*!
5960 * @}
5961 */ /* end of group FB_Register_Accessor_Macros */
5962
5963
5964 /* ----------------------------------------------------------------------------
5965 -- FB Register Masks
5966 ---------------------------------------------------------------------------- */
5967
5968 /*!
5969 * @addtogroup FB_Register_Masks FB Register Masks
5970 * @{
5971 */
5972
5973 /* CSAR Bit Fields */
5974 #define FB_CSAR_BA_MASK 0xFFFF0000u
5975 #define FB_CSAR_BA_SHIFT 16
5976 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<<FB_CSAR_BA_SHIFT))&FB_CSAR_BA_MASK)
5977 /* CSMR Bit Fields */
5978 #define FB_CSMR_V_MASK 0x1u
5979 #define FB_CSMR_V_SHIFT 0
5980 #define FB_CSMR_WP_MASK 0x100u
5981 #define FB_CSMR_WP_SHIFT 8
5982 #define FB_CSMR_BAM_MASK 0xFFFF0000u
5983 #define FB_CSMR_BAM_SHIFT 16
5984 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x))<<FB_CSMR_BAM_SHIFT))&FB_CSMR_BAM_MASK)
5985 /* CSCR Bit Fields */
5986 #define FB_CSCR_BSTW_MASK 0x8u
5987 #define FB_CSCR_BSTW_SHIFT 3
5988 #define FB_CSCR_BSTR_MASK 0x10u
5989 #define FB_CSCR_BSTR_SHIFT 4
5990 #define FB_CSCR_BEM_MASK 0x20u
5991 #define FB_CSCR_BEM_SHIFT 5
5992 #define FB_CSCR_PS_MASK 0xC0u
5993 #define FB_CSCR_PS_SHIFT 6
5994 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_PS_SHIFT))&FB_CSCR_PS_MASK)
5995 #define FB_CSCR_AA_MASK 0x100u
5996 #define FB_CSCR_AA_SHIFT 8
5997 #define FB_CSCR_BLS_MASK 0x200u
5998 #define FB_CSCR_BLS_SHIFT 9
5999 #define FB_CSCR_WS_MASK 0xFC00u
6000 #define FB_CSCR_WS_SHIFT 10
6001 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WS_SHIFT))&FB_CSCR_WS_MASK)
6002 #define FB_CSCR_WRAH_MASK 0x30000u
6003 #define FB_CSCR_WRAH_SHIFT 16
6004 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_WRAH_SHIFT))&FB_CSCR_WRAH_MASK)
6005 #define FB_CSCR_RDAH_MASK 0xC0000u
6006 #define FB_CSCR_RDAH_SHIFT 18
6007 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_RDAH_SHIFT))&FB_CSCR_RDAH_MASK)
6008 #define FB_CSCR_ASET_MASK 0x300000u
6009 #define FB_CSCR_ASET_SHIFT 20
6010 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_ASET_SHIFT))&FB_CSCR_ASET_MASK)
6011 #define FB_CSCR_EXTS_MASK 0x400000u
6012 #define FB_CSCR_EXTS_SHIFT 22
6013 #define FB_CSCR_SWSEN_MASK 0x800000u
6014 #define FB_CSCR_SWSEN_SHIFT 23
6015 #define FB_CSCR_SWS_MASK 0xFC000000u
6016 #define FB_CSCR_SWS_SHIFT 26
6017 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x))<<FB_CSCR_SWS_SHIFT))&FB_CSCR_SWS_MASK)
6018 /* CSPMCR Bit Fields */
6019 #define FB_CSPMCR_GROUP5_MASK 0xF000u
6020 #define FB_CSPMCR_GROUP5_SHIFT 12
6021 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP5_SHIFT))&FB_CSPMCR_GROUP5_MASK)
6022 #define FB_CSPMCR_GROUP4_MASK 0xF0000u
6023 #define FB_CSPMCR_GROUP4_SHIFT 16
6024 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP4_SHIFT))&FB_CSPMCR_GROUP4_MASK)
6025 #define FB_CSPMCR_GROUP3_MASK 0xF00000u
6026 #define FB_CSPMCR_GROUP3_SHIFT 20
6027 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP3_SHIFT))&FB_CSPMCR_GROUP3_MASK)
6028 #define FB_CSPMCR_GROUP2_MASK 0xF000000u
6029 #define FB_CSPMCR_GROUP2_SHIFT 24
6030 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP2_SHIFT))&FB_CSPMCR_GROUP2_MASK)
6031 #define FB_CSPMCR_GROUP1_MASK 0xF0000000u
6032 #define FB_CSPMCR_GROUP1_SHIFT 28
6033 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x))<<FB_CSPMCR_GROUP1_SHIFT))&FB_CSPMCR_GROUP1_MASK)
6034
6035 /*!
6036 * @}
6037 */ /* end of group FB_Register_Masks */
6038
6039
6040 /* FB - Peripheral instance base addresses */
6041 /** Peripheral FB base address */
6042 #define FB_BASE (0x4000C000u)
6043 /** Peripheral FB base pointer */
6044 #define FB ((FB_Type *)FB_BASE)
6045 #define FB_BASE_PTR (FB)
6046 /** Array initializer of FB peripheral base addresses */
6047 #define FB_BASE_ADDRS { FB_BASE }
6048 /** Array initializer of FB peripheral base pointers */
6049 #define FB_BASE_PTRS { FB }
6050
6051 /* ----------------------------------------------------------------------------
6052 -- FB - Register accessor macros
6053 ---------------------------------------------------------------------------- */
6054
6055 /*!
6056 * @addtogroup FB_Register_Accessor_Macros FB - Register accessor macros
6057 * @{
6058 */
6059
6060
6061 /* FB - Register instance definitions */
6062 /* FB */
6063 #define FB_CSAR0 FB_CSAR_REG(FB,0)
6064 #define FB_CSMR0 FB_CSMR_REG(FB,0)
6065 #define FB_CSCR0 FB_CSCR_REG(FB,0)
6066 #define FB_CSAR1 FB_CSAR_REG(FB,1)
6067 #define FB_CSMR1 FB_CSMR_REG(FB,1)
6068 #define FB_CSCR1 FB_CSCR_REG(FB,1)
6069 #define FB_CSAR2 FB_CSAR_REG(FB,2)
6070 #define FB_CSMR2 FB_CSMR_REG(FB,2)
6071 #define FB_CSCR2 FB_CSCR_REG(FB,2)
6072 #define FB_CSAR3 FB_CSAR_REG(FB,3)
6073 #define FB_CSMR3 FB_CSMR_REG(FB,3)
6074 #define FB_CSCR3 FB_CSCR_REG(FB,3)
6075 #define FB_CSAR4 FB_CSAR_REG(FB,4)
6076 #define FB_CSMR4 FB_CSMR_REG(FB,4)
6077 #define FB_CSCR4 FB_CSCR_REG(FB,4)
6078 #define FB_CSAR5 FB_CSAR_REG(FB,5)
6079 #define FB_CSMR5 FB_CSMR_REG(FB,5)
6080 #define FB_CSCR5 FB_CSCR_REG(FB,5)
6081 #define FB_CSPMCR FB_CSPMCR_REG(FB)
6082
6083 /* FB - Register array accessors */
6084 #define FB_CSAR(index) FB_CSAR_REG(FB,index)
6085 #define FB_CSMR(index) FB_CSMR_REG(FB,index)
6086 #define FB_CSCR(index) FB_CSCR_REG(FB,index)
6087
6088 /*!
6089 * @}
6090 */ /* end of group FB_Register_Accessor_Macros */
6091
6092
6093 /*!
6094 * @}
6095 */ /* end of group FB_Peripheral_Access_Layer */
6096
6097
6098 /* ----------------------------------------------------------------------------
6099 -- FMC Peripheral Access Layer
6100 ---------------------------------------------------------------------------- */
6101
6102 /*!
6103 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
6104 * @{
6105 */
6106
6107 /** FMC - Register Layout Typedef */
6108 typedef struct {
6109 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
6110 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
6111 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
6112 uint8_t RESERVED_0[244];
6113 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
6114 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
6115 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
6116 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
6117 uint8_t RESERVED_1[192];
6118 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
6119 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
6120 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
6121 } SET[4][4];
6122 } FMC_Type, *FMC_MemMapPtr;
6123
6124 /* ----------------------------------------------------------------------------
6125 -- FMC - Register accessor macros
6126 ---------------------------------------------------------------------------- */
6127
6128 /*!
6129 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
6130 * @{
6131 */
6132
6133
6134 /* FMC - Register accessors */
6135 #define FMC_PFAPR_REG(base) ((base)->PFAPR)
6136 #define FMC_PFB0CR_REG(base) ((base)->PFB0CR)
6137 #define FMC_PFB1CR_REG(base) ((base)->PFB1CR)
6138 #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index])
6139 #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index])
6140 #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index])
6141 #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index])
6142 #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U)
6143 #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L)
6144
6145 /*!
6146 * @}
6147 */ /* end of group FMC_Register_Accessor_Macros */
6148
6149
6150 /* ----------------------------------------------------------------------------
6151 -- FMC Register Masks
6152 ---------------------------------------------------------------------------- */
6153
6154 /*!
6155 * @addtogroup FMC_Register_Masks FMC Register Masks
6156 * @{
6157 */
6158
6159 /* PFAPR Bit Fields */
6160 #define FMC_PFAPR_M0AP_MASK 0x3u
6161 #define FMC_PFAPR_M0AP_SHIFT 0
6162 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M0AP_SHIFT))&FMC_PFAPR_M0AP_MASK)
6163 #define FMC_PFAPR_M1AP_MASK 0xCu
6164 #define FMC_PFAPR_M1AP_SHIFT 2
6165 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M1AP_SHIFT))&FMC_PFAPR_M1AP_MASK)
6166 #define FMC_PFAPR_M2AP_MASK 0x30u
6167 #define FMC_PFAPR_M2AP_SHIFT 4
6168 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M2AP_SHIFT))&FMC_PFAPR_M2AP_MASK)
6169 #define FMC_PFAPR_M3AP_MASK 0xC0u
6170 #define FMC_PFAPR_M3AP_SHIFT 6
6171 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M3AP_SHIFT))&FMC_PFAPR_M3AP_MASK)
6172 #define FMC_PFAPR_M4AP_MASK 0x300u
6173 #define FMC_PFAPR_M4AP_SHIFT 8
6174 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M4AP_SHIFT))&FMC_PFAPR_M4AP_MASK)
6175 #define FMC_PFAPR_M5AP_MASK 0xC00u
6176 #define FMC_PFAPR_M5AP_SHIFT 10
6177 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M5AP_SHIFT))&FMC_PFAPR_M5AP_MASK)
6178 #define FMC_PFAPR_M6AP_MASK 0x3000u
6179 #define FMC_PFAPR_M6AP_SHIFT 12
6180 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M6AP_SHIFT))&FMC_PFAPR_M6AP_MASK)
6181 #define FMC_PFAPR_M7AP_MASK 0xC000u
6182 #define FMC_PFAPR_M7AP_SHIFT 14
6183 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFAPR_M7AP_SHIFT))&FMC_PFAPR_M7AP_MASK)
6184 #define FMC_PFAPR_M0PFD_MASK 0x10000u
6185 #define FMC_PFAPR_M0PFD_SHIFT 16
6186 #define FMC_PFAPR_M1PFD_MASK 0x20000u
6187 #define FMC_PFAPR_M1PFD_SHIFT 17
6188 #define FMC_PFAPR_M2PFD_MASK 0x40000u
6189 #define FMC_PFAPR_M2PFD_SHIFT 18
6190 #define FMC_PFAPR_M3PFD_MASK 0x80000u
6191 #define FMC_PFAPR_M3PFD_SHIFT 19
6192 #define FMC_PFAPR_M4PFD_MASK 0x100000u
6193 #define FMC_PFAPR_M4PFD_SHIFT 20
6194 #define FMC_PFAPR_M5PFD_MASK 0x200000u
6195 #define FMC_PFAPR_M5PFD_SHIFT 21
6196 #define FMC_PFAPR_M6PFD_MASK 0x400000u
6197 #define FMC_PFAPR_M6PFD_SHIFT 22
6198 #define FMC_PFAPR_M7PFD_MASK 0x800000u
6199 #define FMC_PFAPR_M7PFD_SHIFT 23
6200 /* PFB0CR Bit Fields */
6201 #define FMC_PFB0CR_B0SEBE_MASK 0x1u
6202 #define FMC_PFB0CR_B0SEBE_SHIFT 0
6203 #define FMC_PFB0CR_B0IPE_MASK 0x2u
6204 #define FMC_PFB0CR_B0IPE_SHIFT 1
6205 #define FMC_PFB0CR_B0DPE_MASK 0x4u
6206 #define FMC_PFB0CR_B0DPE_SHIFT 2
6207 #define FMC_PFB0CR_B0ICE_MASK 0x8u
6208 #define FMC_PFB0CR_B0ICE_SHIFT 3
6209 #define FMC_PFB0CR_B0DCE_MASK 0x10u
6210 #define FMC_PFB0CR_B0DCE_SHIFT 4
6211 #define FMC_PFB0CR_CRC_MASK 0xE0u
6212 #define FMC_PFB0CR_CRC_SHIFT 5
6213 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CRC_SHIFT))&FMC_PFB0CR_CRC_MASK)
6214 #define FMC_PFB0CR_B0MW_MASK 0x60000u
6215 #define FMC_PFB0CR_B0MW_SHIFT 17
6216 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0MW_SHIFT))&FMC_PFB0CR_B0MW_MASK)
6217 #define FMC_PFB0CR_S_B_INV_MASK 0x80000u
6218 #define FMC_PFB0CR_S_B_INV_SHIFT 19
6219 #define FMC_PFB0CR_CINV_WAY_MASK 0xF00000u
6220 #define FMC_PFB0CR_CINV_WAY_SHIFT 20
6221 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CINV_WAY_SHIFT))&FMC_PFB0CR_CINV_WAY_MASK)
6222 #define FMC_PFB0CR_CLCK_WAY_MASK 0xF000000u
6223 #define FMC_PFB0CR_CLCK_WAY_SHIFT 24
6224 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_CLCK_WAY_SHIFT))&FMC_PFB0CR_CLCK_WAY_MASK)
6225 #define FMC_PFB0CR_B0RWSC_MASK 0xF0000000u
6226 #define FMC_PFB0CR_B0RWSC_SHIFT 28
6227 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB0CR_B0RWSC_SHIFT))&FMC_PFB0CR_B0RWSC_MASK)
6228 /* PFB1CR Bit Fields */
6229 #define FMC_PFB1CR_B1SEBE_MASK 0x1u
6230 #define FMC_PFB1CR_B1SEBE_SHIFT 0
6231 #define FMC_PFB1CR_B1IPE_MASK 0x2u
6232 #define FMC_PFB1CR_B1IPE_SHIFT 1
6233 #define FMC_PFB1CR_B1DPE_MASK 0x4u
6234 #define FMC_PFB1CR_B1DPE_SHIFT 2
6235 #define FMC_PFB1CR_B1ICE_MASK 0x8u
6236 #define FMC_PFB1CR_B1ICE_SHIFT 3
6237 #define FMC_PFB1CR_B1DCE_MASK 0x10u
6238 #define FMC_PFB1CR_B1DCE_SHIFT 4
6239 #define FMC_PFB1CR_B1MW_MASK 0x60000u
6240 #define FMC_PFB1CR_B1MW_SHIFT 17
6241 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1MW_SHIFT))&FMC_PFB1CR_B1MW_MASK)
6242 #define FMC_PFB1CR_B1RWSC_MASK 0xF0000000u
6243 #define FMC_PFB1CR_B1RWSC_SHIFT 28
6244 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x))<<FMC_PFB1CR_B1RWSC_SHIFT))&FMC_PFB1CR_B1RWSC_MASK)
6245 /* TAGVDW0S Bit Fields */
6246 #define FMC_TAGVDW0S_valid_MASK 0x1u
6247 #define FMC_TAGVDW0S_valid_SHIFT 0
6248 #define FMC_TAGVDW0S_tag_MASK 0x7FFE0u
6249 #define FMC_TAGVDW0S_tag_SHIFT 5
6250 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW0S_tag_SHIFT))&FMC_TAGVDW0S_tag_MASK)
6251 /* TAGVDW1S Bit Fields */
6252 #define FMC_TAGVDW1S_valid_MASK 0x1u
6253 #define FMC_TAGVDW1S_valid_SHIFT 0
6254 #define FMC_TAGVDW1S_tag_MASK 0x7FFE0u
6255 #define FMC_TAGVDW1S_tag_SHIFT 5
6256 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW1S_tag_SHIFT))&FMC_TAGVDW1S_tag_MASK)
6257 /* TAGVDW2S Bit Fields */
6258 #define FMC_TAGVDW2S_valid_MASK 0x1u
6259 #define FMC_TAGVDW2S_valid_SHIFT 0
6260 #define FMC_TAGVDW2S_tag_MASK 0x7FFE0u
6261 #define FMC_TAGVDW2S_tag_SHIFT 5
6262 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW2S_tag_SHIFT))&FMC_TAGVDW2S_tag_MASK)
6263 /* TAGVDW3S Bit Fields */
6264 #define FMC_TAGVDW3S_valid_MASK 0x1u
6265 #define FMC_TAGVDW3S_valid_SHIFT 0
6266 #define FMC_TAGVDW3S_tag_MASK 0x7FFE0u
6267 #define FMC_TAGVDW3S_tag_SHIFT 5
6268 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x))<<FMC_TAGVDW3S_tag_SHIFT))&FMC_TAGVDW3S_tag_MASK)
6269 /* DATA_U Bit Fields */
6270 #define FMC_DATA_U_data_MASK 0xFFFFFFFFu
6271 #define FMC_DATA_U_data_SHIFT 0
6272 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_U_data_SHIFT))&FMC_DATA_U_data_MASK)
6273 /* DATA_L Bit Fields */
6274 #define FMC_DATA_L_data_MASK 0xFFFFFFFFu
6275 #define FMC_DATA_L_data_SHIFT 0
6276 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x))<<FMC_DATA_L_data_SHIFT))&FMC_DATA_L_data_MASK)
6277
6278 /*!
6279 * @}
6280 */ /* end of group FMC_Register_Masks */
6281
6282
6283 /* FMC - Peripheral instance base addresses */
6284 /** Peripheral FMC base address */
6285 #define FMC_BASE (0x4001F000u)
6286 /** Peripheral FMC base pointer */
6287 #define FMC ((FMC_Type *)FMC_BASE)
6288 #define FMC_BASE_PTR (FMC)
6289 /** Array initializer of FMC peripheral base addresses */
6290 #define FMC_BASE_ADDRS { FMC_BASE }
6291 /** Array initializer of FMC peripheral base pointers */
6292 #define FMC_BASE_PTRS { FMC }
6293
6294 /* ----------------------------------------------------------------------------
6295 -- FMC - Register accessor macros
6296 ---------------------------------------------------------------------------- */
6297
6298 /*!
6299 * @addtogroup FMC_Register_Accessor_Macros FMC - Register accessor macros
6300 * @{
6301 */
6302
6303
6304 /* FMC - Register instance definitions */
6305 /* FMC */
6306 #define FMC_PFAPR FMC_PFAPR_REG(FMC)
6307 #define FMC_PFB0CR FMC_PFB0CR_REG(FMC)
6308 #define FMC_PFB1CR FMC_PFB1CR_REG(FMC)
6309 #define FMC_TAGVDW0S0 FMC_TAGVDW0S_REG(FMC,0)
6310 #define FMC_TAGVDW0S1 FMC_TAGVDW0S_REG(FMC,1)
6311 #define FMC_TAGVDW0S2 FMC_TAGVDW0S_REG(FMC,2)
6312 #define FMC_TAGVDW0S3 FMC_TAGVDW0S_REG(FMC,3)
6313 #define FMC_TAGVDW1S0 FMC_TAGVDW1S_REG(FMC,0)
6314 #define FMC_TAGVDW1S1 FMC_TAGVDW1S_REG(FMC,1)
6315 #define FMC_TAGVDW1S2 FMC_TAGVDW1S_REG(FMC,2)
6316 #define FMC_TAGVDW1S3 FMC_TAGVDW1S_REG(FMC,3)
6317 #define FMC_TAGVDW2S0 FMC_TAGVDW2S_REG(FMC,0)
6318 #define FMC_TAGVDW2S1 FMC_TAGVDW2S_REG(FMC,1)
6319 #define FMC_TAGVDW2S2 FMC_TAGVDW2S_REG(FMC,2)
6320 #define FMC_TAGVDW2S3 FMC_TAGVDW2S_REG(FMC,3)
6321 #define FMC_TAGVDW3S0 FMC_TAGVDW3S_REG(FMC,0)
6322 #define FMC_TAGVDW3S1 FMC_TAGVDW3S_REG(FMC,1)
6323 #define FMC_TAGVDW3S2 FMC_TAGVDW3S_REG(FMC,2)
6324 #define FMC_TAGVDW3S3 FMC_TAGVDW3S_REG(FMC,3)
6325 #define FMC_DATAW0S0U FMC_DATA_U_REG(FMC,0,0)
6326 #define FMC_DATAW0S0L FMC_DATA_L_REG(FMC,0,0)
6327 #define FMC_DATAW0S1U FMC_DATA_U_REG(FMC,0,1)
6328 #define FMC_DATAW0S1L FMC_DATA_L_REG(FMC,0,1)
6329 #define FMC_DATAW0S2U FMC_DATA_U_REG(FMC,0,2)
6330 #define FMC_DATAW0S2L FMC_DATA_L_REG(FMC,0,2)
6331 #define FMC_DATAW0S3U FMC_DATA_U_REG(FMC,0,3)
6332 #define FMC_DATAW0S3L FMC_DATA_L_REG(FMC,0,3)
6333 #define FMC_DATAW1S0U FMC_DATA_U_REG(FMC,1,0)
6334 #define FMC_DATAW1S0L FMC_DATA_L_REG(FMC,1,0)
6335 #define FMC_DATAW1S1U FMC_DATA_U_REG(FMC,1,1)
6336 #define FMC_DATAW1S1L FMC_DATA_L_REG(FMC,1,1)
6337 #define FMC_DATAW1S2U FMC_DATA_U_REG(FMC,1,2)
6338 #define FMC_DATAW1S2L FMC_DATA_L_REG(FMC,1,2)
6339 #define FMC_DATAW1S3U FMC_DATA_U_REG(FMC,1,3)
6340 #define FMC_DATAW1S3L FMC_DATA_L_REG(FMC,1,3)
6341 #define FMC_DATAW2S0U FMC_DATA_U_REG(FMC,2,0)
6342 #define FMC_DATAW2S0L FMC_DATA_L_REG(FMC,2,0)
6343 #define FMC_DATAW2S1U FMC_DATA_U_REG(FMC,2,1)
6344 #define FMC_DATAW2S1L FMC_DATA_L_REG(FMC,2,1)
6345 #define FMC_DATAW2S2U FMC_DATA_U_REG(FMC,2,2)
6346 #define FMC_DATAW2S2L FMC_DATA_L_REG(FMC,2,2)
6347 #define FMC_DATAW2S3U FMC_DATA_U_REG(FMC,2,3)
6348 #define FMC_DATAW2S3L FMC_DATA_L_REG(FMC,2,3)
6349 #define FMC_DATAW3S0U FMC_DATA_U_REG(FMC,3,0)
6350 #define FMC_DATAW3S0L FMC_DATA_L_REG(FMC,3,0)
6351 #define FMC_DATAW3S1U FMC_DATA_U_REG(FMC,3,1)
6352 #define FMC_DATAW3S1L FMC_DATA_L_REG(FMC,3,1)
6353 #define FMC_DATAW3S2U FMC_DATA_U_REG(FMC,3,2)
6354 #define FMC_DATAW3S2L FMC_DATA_L_REG(FMC,3,2)
6355 #define FMC_DATAW3S3U FMC_DATA_U_REG(FMC,3,3)
6356 #define FMC_DATAW3S3L FMC_DATA_L_REG(FMC,3,3)
6357
6358 /* FMC - Register array accessors */
6359 #define FMC_TAGVDW0S(index) FMC_TAGVDW0S_REG(FMC,index)
6360 #define FMC_TAGVDW1S(index) FMC_TAGVDW1S_REG(FMC,index)
6361 #define FMC_TAGVDW2S(index) FMC_TAGVDW2S_REG(FMC,index)
6362 #define FMC_TAGVDW3S(index) FMC_TAGVDW3S_REG(FMC,index)
6363 #define FMC_DATA_U(index,index2) FMC_DATA_U_REG(FMC,index,index2)
6364 #define FMC_DATA_L(index,index2) FMC_DATA_L_REG(FMC,index,index2)
6365
6366 /*!
6367 * @}
6368 */ /* end of group FMC_Register_Accessor_Macros */
6369
6370
6371 /*!
6372 * @}
6373 */ /* end of group FMC_Peripheral_Access_Layer */
6374
6375
6376 /* ----------------------------------------------------------------------------
6377 -- FTFE Peripheral Access Layer
6378 ---------------------------------------------------------------------------- */
6379
6380 /*!
6381 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
6382 * @{
6383 */
6384
6385 /** FTFE - Register Layout Typedef */
6386 typedef struct {
6387 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
6388 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
6389 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
6390 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
6391 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
6392 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
6393 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
6394 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
6395 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
6396 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
6397 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
6398 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
6399 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
6400 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
6401 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
6402 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
6403 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
6404 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
6405 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
6406 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
6407 uint8_t RESERVED_0[2];
6408 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
6409 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
6410 } FTFE_Type, *FTFE_MemMapPtr;
6411
6412 /* ----------------------------------------------------------------------------
6413 -- FTFE - Register accessor macros
6414 ---------------------------------------------------------------------------- */
6415
6416 /*!
6417 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
6418 * @{
6419 */
6420
6421
6422 /* FTFE - Register accessors */
6423 #define FTFE_FSTAT_REG(base) ((base)->FSTAT)
6424 #define FTFE_FCNFG_REG(base) ((base)->FCNFG)
6425 #define FTFE_FSEC_REG(base) ((base)->FSEC)
6426 #define FTFE_FOPT_REG(base) ((base)->FOPT)
6427 #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3)
6428 #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2)
6429 #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1)
6430 #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0)
6431 #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7)
6432 #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6)
6433 #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5)
6434 #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4)
6435 #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB)
6436 #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA)
6437 #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9)
6438 #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8)
6439 #define FTFE_FPROT3_REG(base) ((base)->FPROT3)
6440 #define FTFE_FPROT2_REG(base) ((base)->FPROT2)
6441 #define FTFE_FPROT1_REG(base) ((base)->FPROT1)
6442 #define FTFE_FPROT0_REG(base) ((base)->FPROT0)
6443 #define FTFE_FEPROT_REG(base) ((base)->FEPROT)
6444 #define FTFE_FDPROT_REG(base) ((base)->FDPROT)
6445
6446 /*!
6447 * @}
6448 */ /* end of group FTFE_Register_Accessor_Macros */
6449
6450
6451 /* ----------------------------------------------------------------------------
6452 -- FTFE Register Masks
6453 ---------------------------------------------------------------------------- */
6454
6455 /*!
6456 * @addtogroup FTFE_Register_Masks FTFE Register Masks
6457 * @{
6458 */
6459
6460 /* FSTAT Bit Fields */
6461 #define FTFE_FSTAT_MGSTAT0_MASK 0x1u
6462 #define FTFE_FSTAT_MGSTAT0_SHIFT 0
6463 #define FTFE_FSTAT_FPVIOL_MASK 0x10u
6464 #define FTFE_FSTAT_FPVIOL_SHIFT 4
6465 #define FTFE_FSTAT_ACCERR_MASK 0x20u
6466 #define FTFE_FSTAT_ACCERR_SHIFT 5
6467 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u
6468 #define FTFE_FSTAT_RDCOLERR_SHIFT 6
6469 #define FTFE_FSTAT_CCIF_MASK 0x80u
6470 #define FTFE_FSTAT_CCIF_SHIFT 7
6471 /* FCNFG Bit Fields */
6472 #define FTFE_FCNFG_EEERDY_MASK 0x1u
6473 #define FTFE_FCNFG_EEERDY_SHIFT 0
6474 #define FTFE_FCNFG_RAMRDY_MASK 0x2u
6475 #define FTFE_FCNFG_RAMRDY_SHIFT 1
6476 #define FTFE_FCNFG_PFLSH_MASK 0x4u
6477 #define FTFE_FCNFG_PFLSH_SHIFT 2
6478 #define FTFE_FCNFG_SWAP_MASK 0x8u
6479 #define FTFE_FCNFG_SWAP_SHIFT 3
6480 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u
6481 #define FTFE_FCNFG_ERSSUSP_SHIFT 4
6482 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u
6483 #define FTFE_FCNFG_ERSAREQ_SHIFT 5
6484 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u
6485 #define FTFE_FCNFG_RDCOLLIE_SHIFT 6
6486 #define FTFE_FCNFG_CCIE_MASK 0x80u
6487 #define FTFE_FCNFG_CCIE_SHIFT 7
6488 /* FSEC Bit Fields */
6489 #define FTFE_FSEC_SEC_MASK 0x3u
6490 #define FTFE_FSEC_SEC_SHIFT 0
6491 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_SEC_SHIFT))&FTFE_FSEC_SEC_MASK)
6492 #define FTFE_FSEC_FSLACC_MASK 0xCu
6493 #define FTFE_FSEC_FSLACC_SHIFT 2
6494 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_FSLACC_SHIFT))&FTFE_FSEC_FSLACC_MASK)
6495 #define FTFE_FSEC_MEEN_MASK 0x30u
6496 #define FTFE_FSEC_MEEN_SHIFT 4
6497 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_MEEN_SHIFT))&FTFE_FSEC_MEEN_MASK)
6498 #define FTFE_FSEC_KEYEN_MASK 0xC0u
6499 #define FTFE_FSEC_KEYEN_SHIFT 6
6500 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FSEC_KEYEN_SHIFT))&FTFE_FSEC_KEYEN_MASK)
6501 /* FOPT Bit Fields */
6502 #define FTFE_FOPT_OPT_MASK 0xFFu
6503 #define FTFE_FOPT_OPT_SHIFT 0
6504 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FOPT_OPT_SHIFT))&FTFE_FOPT_OPT_MASK)
6505 /* FCCOB3 Bit Fields */
6506 #define FTFE_FCCOB3_CCOBn_MASK 0xFFu
6507 #define FTFE_FCCOB3_CCOBn_SHIFT 0
6508 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB3_CCOBn_SHIFT))&FTFE_FCCOB3_CCOBn_MASK)
6509 /* FCCOB2 Bit Fields */
6510 #define FTFE_FCCOB2_CCOBn_MASK 0xFFu
6511 #define FTFE_FCCOB2_CCOBn_SHIFT 0
6512 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB2_CCOBn_SHIFT))&FTFE_FCCOB2_CCOBn_MASK)
6513 /* FCCOB1 Bit Fields */
6514 #define FTFE_FCCOB1_CCOBn_MASK 0xFFu
6515 #define FTFE_FCCOB1_CCOBn_SHIFT 0
6516 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB1_CCOBn_SHIFT))&FTFE_FCCOB1_CCOBn_MASK)
6517 /* FCCOB0 Bit Fields */
6518 #define FTFE_FCCOB0_CCOBn_MASK 0xFFu
6519 #define FTFE_FCCOB0_CCOBn_SHIFT 0
6520 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB0_CCOBn_SHIFT))&FTFE_FCCOB0_CCOBn_MASK)
6521 /* FCCOB7 Bit Fields */
6522 #define FTFE_FCCOB7_CCOBn_MASK 0xFFu
6523 #define FTFE_FCCOB7_CCOBn_SHIFT 0
6524 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB7_CCOBn_SHIFT))&FTFE_FCCOB7_CCOBn_MASK)
6525 /* FCCOB6 Bit Fields */
6526 #define FTFE_FCCOB6_CCOBn_MASK 0xFFu
6527 #define FTFE_FCCOB6_CCOBn_SHIFT 0
6528 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB6_CCOBn_SHIFT))&FTFE_FCCOB6_CCOBn_MASK)
6529 /* FCCOB5 Bit Fields */
6530 #define FTFE_FCCOB5_CCOBn_MASK 0xFFu
6531 #define FTFE_FCCOB5_CCOBn_SHIFT 0
6532 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB5_CCOBn_SHIFT))&FTFE_FCCOB5_CCOBn_MASK)
6533 /* FCCOB4 Bit Fields */
6534 #define FTFE_FCCOB4_CCOBn_MASK 0xFFu
6535 #define FTFE_FCCOB4_CCOBn_SHIFT 0
6536 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB4_CCOBn_SHIFT))&FTFE_FCCOB4_CCOBn_MASK)
6537 /* FCCOBB Bit Fields */
6538 #define FTFE_FCCOBB_CCOBn_MASK 0xFFu
6539 #define FTFE_FCCOBB_CCOBn_SHIFT 0
6540 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBB_CCOBn_SHIFT))&FTFE_FCCOBB_CCOBn_MASK)
6541 /* FCCOBA Bit Fields */
6542 #define FTFE_FCCOBA_CCOBn_MASK 0xFFu
6543 #define FTFE_FCCOBA_CCOBn_SHIFT 0
6544 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOBA_CCOBn_SHIFT))&FTFE_FCCOBA_CCOBn_MASK)
6545 /* FCCOB9 Bit Fields */
6546 #define FTFE_FCCOB9_CCOBn_MASK 0xFFu
6547 #define FTFE_FCCOB9_CCOBn_SHIFT 0
6548 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB9_CCOBn_SHIFT))&FTFE_FCCOB9_CCOBn_MASK)
6549 /* FCCOB8 Bit Fields */
6550 #define FTFE_FCCOB8_CCOBn_MASK 0xFFu
6551 #define FTFE_FCCOB8_CCOBn_SHIFT 0
6552 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FCCOB8_CCOBn_SHIFT))&FTFE_FCCOB8_CCOBn_MASK)
6553 /* FPROT3 Bit Fields */
6554 #define FTFE_FPROT3_PROT_MASK 0xFFu
6555 #define FTFE_FPROT3_PROT_SHIFT 0
6556 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT3_PROT_SHIFT))&FTFE_FPROT3_PROT_MASK)
6557 /* FPROT2 Bit Fields */
6558 #define FTFE_FPROT2_PROT_MASK 0xFFu
6559 #define FTFE_FPROT2_PROT_SHIFT 0
6560 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT2_PROT_SHIFT))&FTFE_FPROT2_PROT_MASK)
6561 /* FPROT1 Bit Fields */
6562 #define FTFE_FPROT1_PROT_MASK 0xFFu
6563 #define FTFE_FPROT1_PROT_SHIFT 0
6564 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT1_PROT_SHIFT))&FTFE_FPROT1_PROT_MASK)
6565 /* FPROT0 Bit Fields */
6566 #define FTFE_FPROT0_PROT_MASK 0xFFu
6567 #define FTFE_FPROT0_PROT_SHIFT 0
6568 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FPROT0_PROT_SHIFT))&FTFE_FPROT0_PROT_MASK)
6569 /* FEPROT Bit Fields */
6570 #define FTFE_FEPROT_EPROT_MASK 0xFFu
6571 #define FTFE_FEPROT_EPROT_SHIFT 0
6572 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FEPROT_EPROT_SHIFT))&FTFE_FEPROT_EPROT_MASK)
6573 /* FDPROT Bit Fields */
6574 #define FTFE_FDPROT_DPROT_MASK 0xFFu
6575 #define FTFE_FDPROT_DPROT_SHIFT 0
6576 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<FTFE_FDPROT_DPROT_SHIFT))&FTFE_FDPROT_DPROT_MASK)
6577
6578 /*!
6579 * @}
6580 */ /* end of group FTFE_Register_Masks */
6581
6582
6583 /* FTFE - Peripheral instance base addresses */
6584 /** Peripheral FTFE base address */
6585 #define FTFE_BASE (0x40020000u)
6586 /** Peripheral FTFE base pointer */
6587 #define FTFE ((FTFE_Type *)FTFE_BASE)
6588 #define FTFE_BASE_PTR (FTFE)
6589 /** Array initializer of FTFE peripheral base addresses */
6590 #define FTFE_BASE_ADDRS { FTFE_BASE }
6591 /** Array initializer of FTFE peripheral base pointers */
6592 #define FTFE_BASE_PTRS { FTFE }
6593 /** Interrupt vectors for the FTFE peripheral type */
6594 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
6595 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
6596
6597 /* ----------------------------------------------------------------------------
6598 -- FTFE - Register accessor macros
6599 ---------------------------------------------------------------------------- */
6600
6601 /*!
6602 * @addtogroup FTFE_Register_Accessor_Macros FTFE - Register accessor macros
6603 * @{
6604 */
6605
6606
6607 /* FTFE - Register instance definitions */
6608 /* FTFE */
6609 #define FTFE_FSTAT FTFE_FSTAT_REG(FTFE)
6610 #define FTFE_FCNFG FTFE_FCNFG_REG(FTFE)
6611 #define FTFE_FSEC FTFE_FSEC_REG(FTFE)
6612 #define FTFE_FOPT FTFE_FOPT_REG(FTFE)
6613 #define FTFE_FCCOB3 FTFE_FCCOB3_REG(FTFE)
6614 #define FTFE_FCCOB2 FTFE_FCCOB2_REG(FTFE)
6615 #define FTFE_FCCOB1 FTFE_FCCOB1_REG(FTFE)
6616 #define FTFE_FCCOB0 FTFE_FCCOB0_REG(FTFE)
6617 #define FTFE_FCCOB7 FTFE_FCCOB7_REG(FTFE)
6618 #define FTFE_FCCOB6 FTFE_FCCOB6_REG(FTFE)
6619 #define FTFE_FCCOB5 FTFE_FCCOB5_REG(FTFE)
6620 #define FTFE_FCCOB4 FTFE_FCCOB4_REG(FTFE)
6621 #define FTFE_FCCOBB FTFE_FCCOBB_REG(FTFE)
6622 #define FTFE_FCCOBA FTFE_FCCOBA_REG(FTFE)
6623 #define FTFE_FCCOB9 FTFE_FCCOB9_REG(FTFE)
6624 #define FTFE_FCCOB8 FTFE_FCCOB8_REG(FTFE)
6625 #define FTFE_FPROT3 FTFE_FPROT3_REG(FTFE)
6626 #define FTFE_FPROT2 FTFE_FPROT2_REG(FTFE)
6627 #define FTFE_FPROT1 FTFE_FPROT1_REG(FTFE)
6628 #define FTFE_FPROT0 FTFE_FPROT0_REG(FTFE)
6629 #define FTFE_FEPROT FTFE_FEPROT_REG(FTFE)
6630 #define FTFE_FDPROT FTFE_FDPROT_REG(FTFE)
6631
6632 /*!
6633 * @}
6634 */ /* end of group FTFE_Register_Accessor_Macros */
6635
6636
6637 /*!
6638 * @}
6639 */ /* end of group FTFE_Peripheral_Access_Layer */
6640
6641
6642 /* ----------------------------------------------------------------------------
6643 -- FTM Peripheral Access Layer
6644 ---------------------------------------------------------------------------- */
6645
6646 /*!
6647 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
6648 * @{
6649 */
6650
6651 /** FTM - Register Layout Typedef */
6652 typedef struct {
6653 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
6654 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
6655 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
6656 struct { /* offset: 0xC, array step: 0x8 */
6657 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
6658 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
6659 } CONTROLS[8];
6660 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
6661 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
6662 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
6663 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
6664 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
6665 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
6666 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
6667 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
6668 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
6669 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
6670 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
6671 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
6672 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
6673 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
6674 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
6675 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
6676 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
6677 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
6678 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
6679 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
6680 } FTM_Type, *FTM_MemMapPtr;
6681
6682 /* ----------------------------------------------------------------------------
6683 -- FTM - Register accessor macros
6684 ---------------------------------------------------------------------------- */
6685
6686 /*!
6687 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
6688 * @{
6689 */
6690
6691
6692 /* FTM - Register accessors */
6693 #define FTM_SC_REG(base) ((base)->SC)
6694 #define FTM_CNT_REG(base) ((base)->CNT)
6695 #define FTM_MOD_REG(base) ((base)->MOD)
6696 #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC)
6697 #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV)
6698 #define FTM_CNTIN_REG(base) ((base)->CNTIN)
6699 #define FTM_STATUS_REG(base) ((base)->STATUS)
6700 #define FTM_MODE_REG(base) ((base)->MODE)
6701 #define FTM_SYNC_REG(base) ((base)->SYNC)
6702 #define FTM_OUTINIT_REG(base) ((base)->OUTINIT)
6703 #define FTM_OUTMASK_REG(base) ((base)->OUTMASK)
6704 #define FTM_COMBINE_REG(base) ((base)->COMBINE)
6705 #define FTM_DEADTIME_REG(base) ((base)->DEADTIME)
6706 #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG)
6707 #define FTM_POL_REG(base) ((base)->POL)
6708 #define FTM_FMS_REG(base) ((base)->FMS)
6709 #define FTM_FILTER_REG(base) ((base)->FILTER)
6710 #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL)
6711 #define FTM_QDCTRL_REG(base) ((base)->QDCTRL)
6712 #define FTM_CONF_REG(base) ((base)->CONF)
6713 #define FTM_FLTPOL_REG(base) ((base)->FLTPOL)
6714 #define FTM_SYNCONF_REG(base) ((base)->SYNCONF)
6715 #define FTM_INVCTRL_REG(base) ((base)->INVCTRL)
6716 #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL)
6717 #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD)
6718
6719 /*!
6720 * @}
6721 */ /* end of group FTM_Register_Accessor_Macros */
6722
6723
6724 /* ----------------------------------------------------------------------------
6725 -- FTM Register Masks
6726 ---------------------------------------------------------------------------- */
6727
6728 /*!
6729 * @addtogroup FTM_Register_Masks FTM Register Masks
6730 * @{
6731 */
6732
6733 /* SC Bit Fields */
6734 #define FTM_SC_PS_MASK 0x7u
6735 #define FTM_SC_PS_SHIFT 0
6736 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_PS_SHIFT))&FTM_SC_PS_MASK)
6737 #define FTM_SC_CLKS_MASK 0x18u
6738 #define FTM_SC_CLKS_SHIFT 3
6739 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x))<<FTM_SC_CLKS_SHIFT))&FTM_SC_CLKS_MASK)
6740 #define FTM_SC_CPWMS_MASK 0x20u
6741 #define FTM_SC_CPWMS_SHIFT 5
6742 #define FTM_SC_TOIE_MASK 0x40u
6743 #define FTM_SC_TOIE_SHIFT 6
6744 #define FTM_SC_TOF_MASK 0x80u
6745 #define FTM_SC_TOF_SHIFT 7
6746 /* CNT Bit Fields */
6747 #define FTM_CNT_COUNT_MASK 0xFFFFu
6748 #define FTM_CNT_COUNT_SHIFT 0
6749 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNT_COUNT_SHIFT))&FTM_CNT_COUNT_MASK)
6750 /* MOD Bit Fields */
6751 #define FTM_MOD_MOD_MASK 0xFFFFu
6752 #define FTM_MOD_MOD_SHIFT 0
6753 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<FTM_MOD_MOD_SHIFT))&FTM_MOD_MOD_MASK)
6754 /* CnSC Bit Fields */
6755 #define FTM_CnSC_DMA_MASK 0x1u
6756 #define FTM_CnSC_DMA_SHIFT 0
6757 #define FTM_CnSC_ELSA_MASK 0x4u
6758 #define FTM_CnSC_ELSA_SHIFT 2
6759 #define FTM_CnSC_ELSB_MASK 0x8u
6760 #define FTM_CnSC_ELSB_SHIFT 3
6761 #define FTM_CnSC_MSA_MASK 0x10u
6762 #define FTM_CnSC_MSA_SHIFT 4
6763 #define FTM_CnSC_MSB_MASK 0x20u
6764 #define FTM_CnSC_MSB_SHIFT 5
6765 #define FTM_CnSC_CHIE_MASK 0x40u
6766 #define FTM_CnSC_CHIE_SHIFT 6
6767 #define FTM_CnSC_CHF_MASK 0x80u
6768 #define FTM_CnSC_CHF_SHIFT 7
6769 /* CnV Bit Fields */
6770 #define FTM_CnV_VAL_MASK 0xFFFFu
6771 #define FTM_CnV_VAL_SHIFT 0
6772 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_CnV_VAL_SHIFT))&FTM_CnV_VAL_MASK)
6773 /* CNTIN Bit Fields */
6774 #define FTM_CNTIN_INIT_MASK 0xFFFFu
6775 #define FTM_CNTIN_INIT_SHIFT 0
6776 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x))<<FTM_CNTIN_INIT_SHIFT))&FTM_CNTIN_INIT_MASK)
6777 /* STATUS Bit Fields */
6778 #define FTM_STATUS_CH0F_MASK 0x1u
6779 #define FTM_STATUS_CH0F_SHIFT 0
6780 #define FTM_STATUS_CH1F_MASK 0x2u
6781 #define FTM_STATUS_CH1F_SHIFT 1
6782 #define FTM_STATUS_CH2F_MASK 0x4u
6783 #define FTM_STATUS_CH2F_SHIFT 2
6784 #define FTM_STATUS_CH3F_MASK 0x8u
6785 #define FTM_STATUS_CH3F_SHIFT 3
6786 #define FTM_STATUS_CH4F_MASK 0x10u
6787 #define FTM_STATUS_CH4F_SHIFT 4
6788 #define FTM_STATUS_CH5F_MASK 0x20u
6789 #define FTM_STATUS_CH5F_SHIFT 5
6790 #define FTM_STATUS_CH6F_MASK 0x40u
6791 #define FTM_STATUS_CH6F_SHIFT 6
6792 #define FTM_STATUS_CH7F_MASK 0x80u
6793 #define FTM_STATUS_CH7F_SHIFT 7
6794 /* MODE Bit Fields */
6795 #define FTM_MODE_FTMEN_MASK 0x1u
6796 #define FTM_MODE_FTMEN_SHIFT 0
6797 #define FTM_MODE_INIT_MASK 0x2u
6798 #define FTM_MODE_INIT_SHIFT 1
6799 #define FTM_MODE_WPDIS_MASK 0x4u
6800 #define FTM_MODE_WPDIS_SHIFT 2
6801 #define FTM_MODE_PWMSYNC_MASK 0x8u
6802 #define FTM_MODE_PWMSYNC_SHIFT 3
6803 #define FTM_MODE_CAPTEST_MASK 0x10u
6804 #define FTM_MODE_CAPTEST_SHIFT 4
6805 #define FTM_MODE_FAULTM_MASK 0x60u
6806 #define FTM_MODE_FAULTM_SHIFT 5
6807 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x))<<FTM_MODE_FAULTM_SHIFT))&FTM_MODE_FAULTM_MASK)
6808 #define FTM_MODE_FAULTIE_MASK 0x80u
6809 #define FTM_MODE_FAULTIE_SHIFT 7
6810 /* SYNC Bit Fields */
6811 #define FTM_SYNC_CNTMIN_MASK 0x1u
6812 #define FTM_SYNC_CNTMIN_SHIFT 0
6813 #define FTM_SYNC_CNTMAX_MASK 0x2u
6814 #define FTM_SYNC_CNTMAX_SHIFT 1
6815 #define FTM_SYNC_REINIT_MASK 0x4u
6816 #define FTM_SYNC_REINIT_SHIFT 2
6817 #define FTM_SYNC_SYNCHOM_MASK 0x8u
6818 #define FTM_SYNC_SYNCHOM_SHIFT 3
6819 #define FTM_SYNC_TRIG0_MASK 0x10u
6820 #define FTM_SYNC_TRIG0_SHIFT 4
6821 #define FTM_SYNC_TRIG1_MASK 0x20u
6822 #define FTM_SYNC_TRIG1_SHIFT 5
6823 #define FTM_SYNC_TRIG2_MASK 0x40u
6824 #define FTM_SYNC_TRIG2_SHIFT 6
6825 #define FTM_SYNC_SWSYNC_MASK 0x80u
6826 #define FTM_SYNC_SWSYNC_SHIFT 7
6827 /* OUTINIT Bit Fields */
6828 #define FTM_OUTINIT_CH0OI_MASK 0x1u
6829 #define FTM_OUTINIT_CH0OI_SHIFT 0
6830 #define FTM_OUTINIT_CH1OI_MASK 0x2u
6831 #define FTM_OUTINIT_CH1OI_SHIFT 1
6832 #define FTM_OUTINIT_CH2OI_MASK 0x4u
6833 #define FTM_OUTINIT_CH2OI_SHIFT 2
6834 #define FTM_OUTINIT_CH3OI_MASK 0x8u
6835 #define FTM_OUTINIT_CH3OI_SHIFT 3
6836 #define FTM_OUTINIT_CH4OI_MASK 0x10u
6837 #define FTM_OUTINIT_CH4OI_SHIFT 4
6838 #define FTM_OUTINIT_CH5OI_MASK 0x20u
6839 #define FTM_OUTINIT_CH5OI_SHIFT 5
6840 #define FTM_OUTINIT_CH6OI_MASK 0x40u
6841 #define FTM_OUTINIT_CH6OI_SHIFT 6
6842 #define FTM_OUTINIT_CH7OI_MASK 0x80u
6843 #define FTM_OUTINIT_CH7OI_SHIFT 7
6844 /* OUTMASK Bit Fields */
6845 #define FTM_OUTMASK_CH0OM_MASK 0x1u
6846 #define FTM_OUTMASK_CH0OM_SHIFT 0
6847 #define FTM_OUTMASK_CH1OM_MASK 0x2u
6848 #define FTM_OUTMASK_CH1OM_SHIFT 1
6849 #define FTM_OUTMASK_CH2OM_MASK 0x4u
6850 #define FTM_OUTMASK_CH2OM_SHIFT 2
6851 #define FTM_OUTMASK_CH3OM_MASK 0x8u
6852 #define FTM_OUTMASK_CH3OM_SHIFT 3
6853 #define FTM_OUTMASK_CH4OM_MASK 0x10u
6854 #define FTM_OUTMASK_CH4OM_SHIFT 4
6855 #define FTM_OUTMASK_CH5OM_MASK 0x20u
6856 #define FTM_OUTMASK_CH5OM_SHIFT 5
6857 #define FTM_OUTMASK_CH6OM_MASK 0x40u
6858 #define FTM_OUTMASK_CH6OM_SHIFT 6
6859 #define FTM_OUTMASK_CH7OM_MASK 0x80u
6860 #define FTM_OUTMASK_CH7OM_SHIFT 7
6861 /* COMBINE Bit Fields */
6862 #define FTM_COMBINE_COMBINE0_MASK 0x1u
6863 #define FTM_COMBINE_COMBINE0_SHIFT 0
6864 #define FTM_COMBINE_COMP0_MASK 0x2u
6865 #define FTM_COMBINE_COMP0_SHIFT 1
6866 #define FTM_COMBINE_DECAPEN0_MASK 0x4u
6867 #define FTM_COMBINE_DECAPEN0_SHIFT 2
6868 #define FTM_COMBINE_DECAP0_MASK 0x8u
6869 #define FTM_COMBINE_DECAP0_SHIFT 3
6870 #define FTM_COMBINE_DTEN0_MASK 0x10u
6871 #define FTM_COMBINE_DTEN0_SHIFT 4
6872 #define FTM_COMBINE_SYNCEN0_MASK 0x20u
6873 #define FTM_COMBINE_SYNCEN0_SHIFT 5
6874 #define FTM_COMBINE_FAULTEN0_MASK 0x40u
6875 #define FTM_COMBINE_FAULTEN0_SHIFT 6
6876 #define FTM_COMBINE_COMBINE1_MASK 0x100u
6877 #define FTM_COMBINE_COMBINE1_SHIFT 8
6878 #define FTM_COMBINE_COMP1_MASK 0x200u
6879 #define FTM_COMBINE_COMP1_SHIFT 9
6880 #define FTM_COMBINE_DECAPEN1_MASK 0x400u
6881 #define FTM_COMBINE_DECAPEN1_SHIFT 10
6882 #define FTM_COMBINE_DECAP1_MASK 0x800u
6883 #define FTM_COMBINE_DECAP1_SHIFT 11
6884 #define FTM_COMBINE_DTEN1_MASK 0x1000u
6885 #define FTM_COMBINE_DTEN1_SHIFT 12
6886 #define FTM_COMBINE_SYNCEN1_MASK 0x2000u
6887 #define FTM_COMBINE_SYNCEN1_SHIFT 13
6888 #define FTM_COMBINE_FAULTEN1_MASK 0x4000u
6889 #define FTM_COMBINE_FAULTEN1_SHIFT 14
6890 #define FTM_COMBINE_COMBINE2_MASK 0x10000u
6891 #define FTM_COMBINE_COMBINE2_SHIFT 16
6892 #define FTM_COMBINE_COMP2_MASK 0x20000u
6893 #define FTM_COMBINE_COMP2_SHIFT 17
6894 #define FTM_COMBINE_DECAPEN2_MASK 0x40000u
6895 #define FTM_COMBINE_DECAPEN2_SHIFT 18
6896 #define FTM_COMBINE_DECAP2_MASK 0x80000u
6897 #define FTM_COMBINE_DECAP2_SHIFT 19
6898 #define FTM_COMBINE_DTEN2_MASK 0x100000u
6899 #define FTM_COMBINE_DTEN2_SHIFT 20
6900 #define FTM_COMBINE_SYNCEN2_MASK 0x200000u
6901 #define FTM_COMBINE_SYNCEN2_SHIFT 21
6902 #define FTM_COMBINE_FAULTEN2_MASK 0x400000u
6903 #define FTM_COMBINE_FAULTEN2_SHIFT 22
6904 #define FTM_COMBINE_COMBINE3_MASK 0x1000000u
6905 #define FTM_COMBINE_COMBINE3_SHIFT 24
6906 #define FTM_COMBINE_COMP3_MASK 0x2000000u
6907 #define FTM_COMBINE_COMP3_SHIFT 25
6908 #define FTM_COMBINE_DECAPEN3_MASK 0x4000000u
6909 #define FTM_COMBINE_DECAPEN3_SHIFT 26
6910 #define FTM_COMBINE_DECAP3_MASK 0x8000000u
6911 #define FTM_COMBINE_DECAP3_SHIFT 27
6912 #define FTM_COMBINE_DTEN3_MASK 0x10000000u
6913 #define FTM_COMBINE_DTEN3_SHIFT 28
6914 #define FTM_COMBINE_SYNCEN3_MASK 0x20000000u
6915 #define FTM_COMBINE_SYNCEN3_SHIFT 29
6916 #define FTM_COMBINE_FAULTEN3_MASK 0x40000000u
6917 #define FTM_COMBINE_FAULTEN3_SHIFT 30
6918 /* DEADTIME Bit Fields */
6919 #define FTM_DEADTIME_DTVAL_MASK 0x3Fu
6920 #define FTM_DEADTIME_DTVAL_SHIFT 0
6921 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTVAL_SHIFT))&FTM_DEADTIME_DTVAL_MASK)
6922 #define FTM_DEADTIME_DTPS_MASK 0xC0u
6923 #define FTM_DEADTIME_DTPS_SHIFT 6
6924 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x))<<FTM_DEADTIME_DTPS_SHIFT))&FTM_DEADTIME_DTPS_MASK)
6925 /* EXTTRIG Bit Fields */
6926 #define FTM_EXTTRIG_CH2TRIG_MASK 0x1u
6927 #define FTM_EXTTRIG_CH2TRIG_SHIFT 0
6928 #define FTM_EXTTRIG_CH3TRIG_MASK 0x2u
6929 #define FTM_EXTTRIG_CH3TRIG_SHIFT 1
6930 #define FTM_EXTTRIG_CH4TRIG_MASK 0x4u
6931 #define FTM_EXTTRIG_CH4TRIG_SHIFT 2
6932 #define FTM_EXTTRIG_CH5TRIG_MASK 0x8u
6933 #define FTM_EXTTRIG_CH5TRIG_SHIFT 3
6934 #define FTM_EXTTRIG_CH0TRIG_MASK 0x10u
6935 #define FTM_EXTTRIG_CH0TRIG_SHIFT 4
6936 #define FTM_EXTTRIG_CH1TRIG_MASK 0x20u
6937 #define FTM_EXTTRIG_CH1TRIG_SHIFT 5
6938 #define FTM_EXTTRIG_INITTRIGEN_MASK 0x40u
6939 #define FTM_EXTTRIG_INITTRIGEN_SHIFT 6
6940 #define FTM_EXTTRIG_TRIGF_MASK 0x80u
6941 #define FTM_EXTTRIG_TRIGF_SHIFT 7
6942 /* POL Bit Fields */
6943 #define FTM_POL_POL0_MASK 0x1u
6944 #define FTM_POL_POL0_SHIFT 0
6945 #define FTM_POL_POL1_MASK 0x2u
6946 #define FTM_POL_POL1_SHIFT 1
6947 #define FTM_POL_POL2_MASK 0x4u
6948 #define FTM_POL_POL2_SHIFT 2
6949 #define FTM_POL_POL3_MASK 0x8u
6950 #define FTM_POL_POL3_SHIFT 3
6951 #define FTM_POL_POL4_MASK 0x10u
6952 #define FTM_POL_POL4_SHIFT 4
6953 #define FTM_POL_POL5_MASK 0x20u
6954 #define FTM_POL_POL5_SHIFT 5
6955 #define FTM_POL_POL6_MASK 0x40u
6956 #define FTM_POL_POL6_SHIFT 6
6957 #define FTM_POL_POL7_MASK 0x80u
6958 #define FTM_POL_POL7_SHIFT 7
6959 /* FMS Bit Fields */
6960 #define FTM_FMS_FAULTF0_MASK 0x1u
6961 #define FTM_FMS_FAULTF0_SHIFT 0
6962 #define FTM_FMS_FAULTF1_MASK 0x2u
6963 #define FTM_FMS_FAULTF1_SHIFT 1
6964 #define FTM_FMS_FAULTF2_MASK 0x4u
6965 #define FTM_FMS_FAULTF2_SHIFT 2
6966 #define FTM_FMS_FAULTF3_MASK 0x8u
6967 #define FTM_FMS_FAULTF3_SHIFT 3
6968 #define FTM_FMS_FAULTIN_MASK 0x20u
6969 #define FTM_FMS_FAULTIN_SHIFT 5
6970 #define FTM_FMS_WPEN_MASK 0x40u
6971 #define FTM_FMS_WPEN_SHIFT 6
6972 #define FTM_FMS_FAULTF_MASK 0x80u
6973 #define FTM_FMS_FAULTF_SHIFT 7
6974 /* FILTER Bit Fields */
6975 #define FTM_FILTER_CH0FVAL_MASK 0xFu
6976 #define FTM_FILTER_CH0FVAL_SHIFT 0
6977 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH0FVAL_SHIFT))&FTM_FILTER_CH0FVAL_MASK)
6978 #define FTM_FILTER_CH1FVAL_MASK 0xF0u
6979 #define FTM_FILTER_CH1FVAL_SHIFT 4
6980 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH1FVAL_SHIFT))&FTM_FILTER_CH1FVAL_MASK)
6981 #define FTM_FILTER_CH2FVAL_MASK 0xF00u
6982 #define FTM_FILTER_CH2FVAL_SHIFT 8
6983 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH2FVAL_SHIFT))&FTM_FILTER_CH2FVAL_MASK)
6984 #define FTM_FILTER_CH3FVAL_MASK 0xF000u
6985 #define FTM_FILTER_CH3FVAL_SHIFT 12
6986 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FILTER_CH3FVAL_SHIFT))&FTM_FILTER_CH3FVAL_MASK)
6987 /* FLTCTRL Bit Fields */
6988 #define FTM_FLTCTRL_FAULT0EN_MASK 0x1u
6989 #define FTM_FLTCTRL_FAULT0EN_SHIFT 0
6990 #define FTM_FLTCTRL_FAULT1EN_MASK 0x2u
6991 #define FTM_FLTCTRL_FAULT1EN_SHIFT 1
6992 #define FTM_FLTCTRL_FAULT2EN_MASK 0x4u
6993 #define FTM_FLTCTRL_FAULT2EN_SHIFT 2
6994 #define FTM_FLTCTRL_FAULT3EN_MASK 0x8u
6995 #define FTM_FLTCTRL_FAULT3EN_SHIFT 3
6996 #define FTM_FLTCTRL_FFLTR0EN_MASK 0x10u
6997 #define FTM_FLTCTRL_FFLTR0EN_SHIFT 4
6998 #define FTM_FLTCTRL_FFLTR1EN_MASK 0x20u
6999 #define FTM_FLTCTRL_FFLTR1EN_SHIFT 5
7000 #define FTM_FLTCTRL_FFLTR2EN_MASK 0x40u
7001 #define FTM_FLTCTRL_FFLTR2EN_SHIFT 6
7002 #define FTM_FLTCTRL_FFLTR3EN_MASK 0x80u
7003 #define FTM_FLTCTRL_FFLTR3EN_SHIFT 7
7004 #define FTM_FLTCTRL_FFVAL_MASK 0xF00u
7005 #define FTM_FLTCTRL_FFVAL_SHIFT 8
7006 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x))<<FTM_FLTCTRL_FFVAL_SHIFT))&FTM_FLTCTRL_FFVAL_MASK)
7007 /* QDCTRL Bit Fields */
7008 #define FTM_QDCTRL_QUADEN_MASK 0x1u
7009 #define FTM_QDCTRL_QUADEN_SHIFT 0
7010 #define FTM_QDCTRL_TOFDIR_MASK 0x2u
7011 #define FTM_QDCTRL_TOFDIR_SHIFT 1
7012 #define FTM_QDCTRL_QUADIR_MASK 0x4u
7013 #define FTM_QDCTRL_QUADIR_SHIFT 2
7014 #define FTM_QDCTRL_QUADMODE_MASK 0x8u
7015 #define FTM_QDCTRL_QUADMODE_SHIFT 3
7016 #define FTM_QDCTRL_PHBPOL_MASK 0x10u
7017 #define FTM_QDCTRL_PHBPOL_SHIFT 4
7018 #define FTM_QDCTRL_PHAPOL_MASK 0x20u
7019 #define FTM_QDCTRL_PHAPOL_SHIFT 5
7020 #define FTM_QDCTRL_PHBFLTREN_MASK 0x40u
7021 #define FTM_QDCTRL_PHBFLTREN_SHIFT 6
7022 #define FTM_QDCTRL_PHAFLTREN_MASK 0x80u
7023 #define FTM_QDCTRL_PHAFLTREN_SHIFT 7
7024 /* CONF Bit Fields */
7025 #define FTM_CONF_NUMTOF_MASK 0x1Fu
7026 #define FTM_CONF_NUMTOF_SHIFT 0
7027 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_NUMTOF_SHIFT))&FTM_CONF_NUMTOF_MASK)
7028 #define FTM_CONF_BDMMODE_MASK 0xC0u
7029 #define FTM_CONF_BDMMODE_SHIFT 6
7030 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x))<<FTM_CONF_BDMMODE_SHIFT))&FTM_CONF_BDMMODE_MASK)
7031 #define FTM_CONF_GTBEEN_MASK 0x200u
7032 #define FTM_CONF_GTBEEN_SHIFT 9
7033 #define FTM_CONF_GTBEOUT_MASK 0x400u
7034 #define FTM_CONF_GTBEOUT_SHIFT 10
7035 /* FLTPOL Bit Fields */
7036 #define FTM_FLTPOL_FLT0POL_MASK 0x1u
7037 #define FTM_FLTPOL_FLT0POL_SHIFT 0
7038 #define FTM_FLTPOL_FLT1POL_MASK 0x2u
7039 #define FTM_FLTPOL_FLT1POL_SHIFT 1
7040 #define FTM_FLTPOL_FLT2POL_MASK 0x4u
7041 #define FTM_FLTPOL_FLT2POL_SHIFT 2
7042 #define FTM_FLTPOL_FLT3POL_MASK 0x8u
7043 #define FTM_FLTPOL_FLT3POL_SHIFT 3
7044 /* SYNCONF Bit Fields */
7045 #define FTM_SYNCONF_HWTRIGMODE_MASK 0x1u
7046 #define FTM_SYNCONF_HWTRIGMODE_SHIFT 0
7047 #define FTM_SYNCONF_CNTINC_MASK 0x4u
7048 #define FTM_SYNCONF_CNTINC_SHIFT 2
7049 #define FTM_SYNCONF_INVC_MASK 0x10u
7050 #define FTM_SYNCONF_INVC_SHIFT 4
7051 #define FTM_SYNCONF_SWOC_MASK 0x20u
7052 #define FTM_SYNCONF_SWOC_SHIFT 5
7053 #define FTM_SYNCONF_SYNCMODE_MASK 0x80u
7054 #define FTM_SYNCONF_SYNCMODE_SHIFT 7
7055 #define FTM_SYNCONF_SWRSTCNT_MASK 0x100u
7056 #define FTM_SYNCONF_SWRSTCNT_SHIFT 8
7057 #define FTM_SYNCONF_SWWRBUF_MASK 0x200u
7058 #define FTM_SYNCONF_SWWRBUF_SHIFT 9
7059 #define FTM_SYNCONF_SWOM_MASK 0x400u
7060 #define FTM_SYNCONF_SWOM_SHIFT 10
7061 #define FTM_SYNCONF_SWINVC_MASK 0x800u
7062 #define FTM_SYNCONF_SWINVC_SHIFT 11
7063 #define FTM_SYNCONF_SWSOC_MASK 0x1000u
7064 #define FTM_SYNCONF_SWSOC_SHIFT 12
7065 #define FTM_SYNCONF_HWRSTCNT_MASK 0x10000u
7066 #define FTM_SYNCONF_HWRSTCNT_SHIFT 16
7067 #define FTM_SYNCONF_HWWRBUF_MASK 0x20000u
7068 #define FTM_SYNCONF_HWWRBUF_SHIFT 17
7069 #define FTM_SYNCONF_HWOM_MASK 0x40000u
7070 #define FTM_SYNCONF_HWOM_SHIFT 18
7071 #define FTM_SYNCONF_HWINVC_MASK 0x80000u
7072 #define FTM_SYNCONF_HWINVC_SHIFT 19
7073 #define FTM_SYNCONF_HWSOC_MASK 0x100000u
7074 #define FTM_SYNCONF_HWSOC_SHIFT 20
7075 /* INVCTRL Bit Fields */
7076 #define FTM_INVCTRL_INV0EN_MASK 0x1u
7077 #define FTM_INVCTRL_INV0EN_SHIFT 0
7078 #define FTM_INVCTRL_INV1EN_MASK 0x2u
7079 #define FTM_INVCTRL_INV1EN_SHIFT 1
7080 #define FTM_INVCTRL_INV2EN_MASK 0x4u
7081 #define FTM_INVCTRL_INV2EN_SHIFT 2
7082 #define FTM_INVCTRL_INV3EN_MASK 0x8u
7083 #define FTM_INVCTRL_INV3EN_SHIFT 3
7084 /* SWOCTRL Bit Fields */
7085 #define FTM_SWOCTRL_CH0OC_MASK 0x1u
7086 #define FTM_SWOCTRL_CH0OC_SHIFT 0
7087 #define FTM_SWOCTRL_CH1OC_MASK 0x2u
7088 #define FTM_SWOCTRL_CH1OC_SHIFT 1
7089 #define FTM_SWOCTRL_CH2OC_MASK 0x4u
7090 #define FTM_SWOCTRL_CH2OC_SHIFT 2
7091 #define FTM_SWOCTRL_CH3OC_MASK 0x8u
7092 #define FTM_SWOCTRL_CH3OC_SHIFT 3
7093 #define FTM_SWOCTRL_CH4OC_MASK 0x10u
7094 #define FTM_SWOCTRL_CH4OC_SHIFT 4
7095 #define FTM_SWOCTRL_CH5OC_MASK 0x20u
7096 #define FTM_SWOCTRL_CH5OC_SHIFT 5
7097 #define FTM_SWOCTRL_CH6OC_MASK 0x40u
7098 #define FTM_SWOCTRL_CH6OC_SHIFT 6
7099 #define FTM_SWOCTRL_CH7OC_MASK 0x80u
7100 #define FTM_SWOCTRL_CH7OC_SHIFT 7
7101 #define FTM_SWOCTRL_CH0OCV_MASK 0x100u
7102 #define FTM_SWOCTRL_CH0OCV_SHIFT 8
7103 #define FTM_SWOCTRL_CH1OCV_MASK 0x200u
7104 #define FTM_SWOCTRL_CH1OCV_SHIFT 9
7105 #define FTM_SWOCTRL_CH2OCV_MASK 0x400u
7106 #define FTM_SWOCTRL_CH2OCV_SHIFT 10
7107 #define FTM_SWOCTRL_CH3OCV_MASK 0x800u
7108 #define FTM_SWOCTRL_CH3OCV_SHIFT 11
7109 #define FTM_SWOCTRL_CH4OCV_MASK 0x1000u
7110 #define FTM_SWOCTRL_CH4OCV_SHIFT 12
7111 #define FTM_SWOCTRL_CH5OCV_MASK 0x2000u
7112 #define FTM_SWOCTRL_CH5OCV_SHIFT 13
7113 #define FTM_SWOCTRL_CH6OCV_MASK 0x4000u
7114 #define FTM_SWOCTRL_CH6OCV_SHIFT 14
7115 #define FTM_SWOCTRL_CH7OCV_MASK 0x8000u
7116 #define FTM_SWOCTRL_CH7OCV_SHIFT 15
7117 /* PWMLOAD Bit Fields */
7118 #define FTM_PWMLOAD_CH0SEL_MASK 0x1u
7119 #define FTM_PWMLOAD_CH0SEL_SHIFT 0
7120 #define FTM_PWMLOAD_CH1SEL_MASK 0x2u
7121 #define FTM_PWMLOAD_CH1SEL_SHIFT 1
7122 #define FTM_PWMLOAD_CH2SEL_MASK 0x4u
7123 #define FTM_PWMLOAD_CH2SEL_SHIFT 2
7124 #define FTM_PWMLOAD_CH3SEL_MASK 0x8u
7125 #define FTM_PWMLOAD_CH3SEL_SHIFT 3
7126 #define FTM_PWMLOAD_CH4SEL_MASK 0x10u
7127 #define FTM_PWMLOAD_CH4SEL_SHIFT 4
7128 #define FTM_PWMLOAD_CH5SEL_MASK 0x20u
7129 #define FTM_PWMLOAD_CH5SEL_SHIFT 5
7130 #define FTM_PWMLOAD_CH6SEL_MASK 0x40u
7131 #define FTM_PWMLOAD_CH6SEL_SHIFT 6
7132 #define FTM_PWMLOAD_CH7SEL_MASK 0x80u
7133 #define FTM_PWMLOAD_CH7SEL_SHIFT 7
7134 #define FTM_PWMLOAD_LDOK_MASK 0x200u
7135 #define FTM_PWMLOAD_LDOK_SHIFT 9
7136
7137 /*!
7138 * @}
7139 */ /* end of group FTM_Register_Masks */
7140
7141
7142 /* FTM - Peripheral instance base addresses */
7143 /** Peripheral FTM0 base address */
7144 #define FTM0_BASE (0x40038000u)
7145 /** Peripheral FTM0 base pointer */
7146 #define FTM0 ((FTM_Type *)FTM0_BASE)
7147 #define FTM0_BASE_PTR (FTM0)
7148 /** Peripheral FTM1 base address */
7149 #define FTM1_BASE (0x40039000u)
7150 /** Peripheral FTM1 base pointer */
7151 #define FTM1 ((FTM_Type *)FTM1_BASE)
7152 #define FTM1_BASE_PTR (FTM1)
7153 /** Peripheral FTM2 base address */
7154 #define FTM2_BASE (0x4003A000u)
7155 /** Peripheral FTM2 base pointer */
7156 #define FTM2 ((FTM_Type *)FTM2_BASE)
7157 #define FTM2_BASE_PTR (FTM2)
7158 /** Peripheral FTM3 base address */
7159 #define FTM3_BASE (0x400B9000u)
7160 /** Peripheral FTM3 base pointer */
7161 #define FTM3 ((FTM_Type *)FTM3_BASE)
7162 #define FTM3_BASE_PTR (FTM3)
7163 /** Array initializer of FTM peripheral base addresses */
7164 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
7165 /** Array initializer of FTM peripheral base pointers */
7166 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
7167 /** Interrupt vectors for the FTM peripheral type */
7168 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
7169
7170 /* ----------------------------------------------------------------------------
7171 -- FTM - Register accessor macros
7172 ---------------------------------------------------------------------------- */
7173
7174 /*!
7175 * @addtogroup FTM_Register_Accessor_Macros FTM - Register accessor macros
7176 * @{
7177 */
7178
7179
7180 /* FTM - Register instance definitions */
7181 /* FTM0 */
7182 #define FTM0_SC FTM_SC_REG(FTM0)
7183 #define FTM0_CNT FTM_CNT_REG(FTM0)
7184 #define FTM0_MOD FTM_MOD_REG(FTM0)
7185 #define FTM0_C0SC FTM_CnSC_REG(FTM0,0)
7186 #define FTM0_C0V FTM_CnV_REG(FTM0,0)
7187 #define FTM0_C1SC FTM_CnSC_REG(FTM0,1)
7188 #define FTM0_C1V FTM_CnV_REG(FTM0,1)
7189 #define FTM0_C2SC FTM_CnSC_REG(FTM0,2)
7190 #define FTM0_C2V FTM_CnV_REG(FTM0,2)
7191 #define FTM0_C3SC FTM_CnSC_REG(FTM0,3)
7192 #define FTM0_C3V FTM_CnV_REG(FTM0,3)
7193 #define FTM0_C4SC FTM_CnSC_REG(FTM0,4)
7194 #define FTM0_C4V FTM_CnV_REG(FTM0,4)
7195 #define FTM0_C5SC FTM_CnSC_REG(FTM0,5)
7196 #define FTM0_C5V FTM_CnV_REG(FTM0,5)
7197 #define FTM0_C6SC FTM_CnSC_REG(FTM0,6)
7198 #define FTM0_C6V FTM_CnV_REG(FTM0,6)
7199 #define FTM0_C7SC FTM_CnSC_REG(FTM0,7)
7200 #define FTM0_C7V FTM_CnV_REG(FTM0,7)
7201 #define FTM0_CNTIN FTM_CNTIN_REG(FTM0)
7202 #define FTM0_STATUS FTM_STATUS_REG(FTM0)
7203 #define FTM0_MODE FTM_MODE_REG(FTM0)
7204 #define FTM0_SYNC FTM_SYNC_REG(FTM0)
7205 #define FTM0_OUTINIT FTM_OUTINIT_REG(FTM0)
7206 #define FTM0_OUTMASK FTM_OUTMASK_REG(FTM0)
7207 #define FTM0_COMBINE FTM_COMBINE_REG(FTM0)
7208 #define FTM0_DEADTIME FTM_DEADTIME_REG(FTM0)
7209 #define FTM0_EXTTRIG FTM_EXTTRIG_REG(FTM0)
7210 #define FTM0_POL FTM_POL_REG(FTM0)
7211 #define FTM0_FMS FTM_FMS_REG(FTM0)
7212 #define FTM0_FILTER FTM_FILTER_REG(FTM0)
7213 #define FTM0_FLTCTRL FTM_FLTCTRL_REG(FTM0)
7214 #define FTM0_QDCTRL FTM_QDCTRL_REG(FTM0)
7215 #define FTM0_CONF FTM_CONF_REG(FTM0)
7216 #define FTM0_FLTPOL FTM_FLTPOL_REG(FTM0)
7217 #define FTM0_SYNCONF FTM_SYNCONF_REG(FTM0)
7218 #define FTM0_INVCTRL FTM_INVCTRL_REG(FTM0)
7219 #define FTM0_SWOCTRL FTM_SWOCTRL_REG(FTM0)
7220 #define FTM0_PWMLOAD FTM_PWMLOAD_REG(FTM0)
7221 /* FTM1 */
7222 #define FTM1_SC FTM_SC_REG(FTM1)
7223 #define FTM1_CNT FTM_CNT_REG(FTM1)
7224 #define FTM1_MOD FTM_MOD_REG(FTM1)
7225 #define FTM1_C0SC FTM_CnSC_REG(FTM1,0)
7226 #define FTM1_C0V FTM_CnV_REG(FTM1,0)
7227 #define FTM1_C1SC FTM_CnSC_REG(FTM1,1)
7228 #define FTM1_C1V FTM_CnV_REG(FTM1,1)
7229 #define FTM1_CNTIN FTM_CNTIN_REG(FTM1)
7230 #define FTM1_STATUS FTM_STATUS_REG(FTM1)
7231 #define FTM1_MODE FTM_MODE_REG(FTM1)
7232 #define FTM1_SYNC FTM_SYNC_REG(FTM1)
7233 #define FTM1_OUTINIT FTM_OUTINIT_REG(FTM1)
7234 #define FTM1_OUTMASK FTM_OUTMASK_REG(FTM1)
7235 #define FTM1_COMBINE FTM_COMBINE_REG(FTM1)
7236 #define FTM1_DEADTIME FTM_DEADTIME_REG(FTM1)
7237 #define FTM1_EXTTRIG FTM_EXTTRIG_REG(FTM1)
7238 #define FTM1_POL FTM_POL_REG(FTM1)
7239 #define FTM1_FMS FTM_FMS_REG(FTM1)
7240 #define FTM1_FILTER FTM_FILTER_REG(FTM1)
7241 #define FTM1_FLTCTRL FTM_FLTCTRL_REG(FTM1)
7242 #define FTM1_QDCTRL FTM_QDCTRL_REG(FTM1)
7243 #define FTM1_CONF FTM_CONF_REG(FTM1)
7244 #define FTM1_FLTPOL FTM_FLTPOL_REG(FTM1)
7245 #define FTM1_SYNCONF FTM_SYNCONF_REG(FTM1)
7246 #define FTM1_INVCTRL FTM_INVCTRL_REG(FTM1)
7247 #define FTM1_SWOCTRL FTM_SWOCTRL_REG(FTM1)
7248 #define FTM1_PWMLOAD FTM_PWMLOAD_REG(FTM1)
7249 /* FTM2 */
7250 #define FTM2_SC FTM_SC_REG(FTM2)
7251 #define FTM2_CNT FTM_CNT_REG(FTM2)
7252 #define FTM2_MOD FTM_MOD_REG(FTM2)
7253 #define FTM2_C0SC FTM_CnSC_REG(FTM2,0)
7254 #define FTM2_C0V FTM_CnV_REG(FTM2,0)
7255 #define FTM2_C1SC FTM_CnSC_REG(FTM2,1)
7256 #define FTM2_C1V FTM_CnV_REG(FTM2,1)
7257 #define FTM2_CNTIN FTM_CNTIN_REG(FTM2)
7258 #define FTM2_STATUS FTM_STATUS_REG(FTM2)
7259 #define FTM2_MODE FTM_MODE_REG(FTM2)
7260 #define FTM2_SYNC FTM_SYNC_REG(FTM2)
7261 #define FTM2_OUTINIT FTM_OUTINIT_REG(FTM2)
7262 #define FTM2_OUTMASK FTM_OUTMASK_REG(FTM2)
7263 #define FTM2_COMBINE FTM_COMBINE_REG(FTM2)
7264 #define FTM2_DEADTIME FTM_DEADTIME_REG(FTM2)
7265 #define FTM2_EXTTRIG FTM_EXTTRIG_REG(FTM2)
7266 #define FTM2_POL FTM_POL_REG(FTM2)
7267 #define FTM2_FMS FTM_FMS_REG(FTM2)
7268 #define FTM2_FILTER FTM_FILTER_REG(FTM2)
7269 #define FTM2_FLTCTRL FTM_FLTCTRL_REG(FTM2)
7270 #define FTM2_QDCTRL FTM_QDCTRL_REG(FTM2)
7271 #define FTM2_CONF FTM_CONF_REG(FTM2)
7272 #define FTM2_FLTPOL FTM_FLTPOL_REG(FTM2)
7273 #define FTM2_SYNCONF FTM_SYNCONF_REG(FTM2)
7274 #define FTM2_INVCTRL FTM_INVCTRL_REG(FTM2)
7275 #define FTM2_SWOCTRL FTM_SWOCTRL_REG(FTM2)
7276 #define FTM2_PWMLOAD FTM_PWMLOAD_REG(FTM2)
7277 /* FTM3 */
7278 #define FTM3_SC FTM_SC_REG(FTM3)
7279 #define FTM3_CNT FTM_CNT_REG(FTM3)
7280 #define FTM3_MOD FTM_MOD_REG(FTM3)
7281 #define FTM3_C0SC FTM_CnSC_REG(FTM3,0)
7282 #define FTM3_C0V FTM_CnV_REG(FTM3,0)
7283 #define FTM3_C1SC FTM_CnSC_REG(FTM3,1)
7284 #define FTM3_C1V FTM_CnV_REG(FTM3,1)
7285 #define FTM3_C2SC FTM_CnSC_REG(FTM3,2)
7286 #define FTM3_C2V FTM_CnV_REG(FTM3,2)
7287 #define FTM3_C3SC FTM_CnSC_REG(FTM3,3)
7288 #define FTM3_C3V FTM_CnV_REG(FTM3,3)
7289 #define FTM3_C4SC FTM_CnSC_REG(FTM3,4)
7290 #define FTM3_C4V FTM_CnV_REG(FTM3,4)
7291 #define FTM3_C5SC FTM_CnSC_REG(FTM3,5)
7292 #define FTM3_C5V FTM_CnV_REG(FTM3,5)
7293 #define FTM3_C6SC FTM_CnSC_REG(FTM3,6)
7294 #define FTM3_C6V FTM_CnV_REG(FTM3,6)
7295 #define FTM3_C7SC FTM_CnSC_REG(FTM3,7)
7296 #define FTM3_C7V FTM_CnV_REG(FTM3,7)
7297 #define FTM3_CNTIN FTM_CNTIN_REG(FTM3)
7298 #define FTM3_STATUS FTM_STATUS_REG(FTM3)
7299 #define FTM3_MODE FTM_MODE_REG(FTM3)
7300 #define FTM3_SYNC FTM_SYNC_REG(FTM3)
7301 #define FTM3_OUTINIT FTM_OUTINIT_REG(FTM3)
7302 #define FTM3_OUTMASK FTM_OUTMASK_REG(FTM3)
7303 #define FTM3_COMBINE FTM_COMBINE_REG(FTM3)
7304 #define FTM3_DEADTIME FTM_DEADTIME_REG(FTM3)
7305 #define FTM3_EXTTRIG FTM_EXTTRIG_REG(FTM3)
7306 #define FTM3_POL FTM_POL_REG(FTM3)
7307 #define FTM3_FMS FTM_FMS_REG(FTM3)
7308 #define FTM3_FILTER FTM_FILTER_REG(FTM3)
7309 #define FTM3_FLTCTRL FTM_FLTCTRL_REG(FTM3)
7310 #define FTM3_QDCTRL FTM_QDCTRL_REG(FTM3)
7311 #define FTM3_CONF FTM_CONF_REG(FTM3)
7312 #define FTM3_FLTPOL FTM_FLTPOL_REG(FTM3)
7313 #define FTM3_SYNCONF FTM_SYNCONF_REG(FTM3)
7314 #define FTM3_INVCTRL FTM_INVCTRL_REG(FTM3)
7315 #define FTM3_SWOCTRL FTM_SWOCTRL_REG(FTM3)
7316 #define FTM3_PWMLOAD FTM_PWMLOAD_REG(FTM3)
7317
7318 /* FTM - Register array accessors */
7319 #define FTM0_CnSC(index) FTM_CnSC_REG(FTM0,index)
7320 #define FTM1_CnSC(index) FTM_CnSC_REG(FTM1,index)
7321 #define FTM2_CnSC(index) FTM_CnSC_REG(FTM2,index)
7322 #define FTM3_CnSC(index) FTM_CnSC_REG(FTM3,index)
7323 #define FTM0_CnV(index) FTM_CnV_REG(FTM0,index)
7324 #define FTM1_CnV(index) FTM_CnV_REG(FTM1,index)
7325 #define FTM2_CnV(index) FTM_CnV_REG(FTM2,index)
7326 #define FTM3_CnV(index) FTM_CnV_REG(FTM3,index)
7327
7328 /*!
7329 * @}
7330 */ /* end of group FTM_Register_Accessor_Macros */
7331
7332
7333 /*!
7334 * @}
7335 */ /* end of group FTM_Peripheral_Access_Layer */
7336
7337
7338 /* ----------------------------------------------------------------------------
7339 -- GPIO Peripheral Access Layer
7340 ---------------------------------------------------------------------------- */
7341
7342 /*!
7343 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
7344 * @{
7345 */
7346
7347 /** GPIO - Register Layout Typedef */
7348 typedef struct {
7349 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
7350 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
7351 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
7352 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
7353 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
7354 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
7355 } GPIO_Type, *GPIO_MemMapPtr;
7356
7357 /* ----------------------------------------------------------------------------
7358 -- GPIO - Register accessor macros
7359 ---------------------------------------------------------------------------- */
7360
7361 /*!
7362 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
7363 * @{
7364 */
7365
7366
7367 /* GPIO - Register accessors */
7368 #define GPIO_PDOR_REG(base) ((base)->PDOR)
7369 #define GPIO_PSOR_REG(base) ((base)->PSOR)
7370 #define GPIO_PCOR_REG(base) ((base)->PCOR)
7371 #define GPIO_PTOR_REG(base) ((base)->PTOR)
7372 #define GPIO_PDIR_REG(base) ((base)->PDIR)
7373 #define GPIO_PDDR_REG(base) ((base)->PDDR)
7374
7375 /*!
7376 * @}
7377 */ /* end of group GPIO_Register_Accessor_Macros */
7378
7379
7380 /* ----------------------------------------------------------------------------
7381 -- GPIO Register Masks
7382 ---------------------------------------------------------------------------- */
7383
7384 /*!
7385 * @addtogroup GPIO_Register_Masks GPIO Register Masks
7386 * @{
7387 */
7388
7389 /* PDOR Bit Fields */
7390 #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
7391 #define GPIO_PDOR_PDO_SHIFT 0
7392 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
7393 /* PSOR Bit Fields */
7394 #define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
7395 #define GPIO_PSOR_PTSO_SHIFT 0
7396 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
7397 /* PCOR Bit Fields */
7398 #define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
7399 #define GPIO_PCOR_PTCO_SHIFT 0
7400 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
7401 /* PTOR Bit Fields */
7402 #define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
7403 #define GPIO_PTOR_PTTO_SHIFT 0
7404 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
7405 /* PDIR Bit Fields */
7406 #define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
7407 #define GPIO_PDIR_PDI_SHIFT 0
7408 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
7409 /* PDDR Bit Fields */
7410 #define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
7411 #define GPIO_PDDR_PDD_SHIFT 0
7412 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
7413
7414 /*!
7415 * @}
7416 */ /* end of group GPIO_Register_Masks */
7417
7418
7419 /* GPIO - Peripheral instance base addresses */
7420 /** Peripheral PTA base address */
7421 #define PTA_BASE (0x400FF000u)
7422 /** Peripheral PTA base pointer */
7423 #define PTA ((GPIO_Type *)PTA_BASE)
7424 #define PTA_BASE_PTR (PTA)
7425 /** Peripheral PTB base address */
7426 #define PTB_BASE (0x400FF040u)
7427 /** Peripheral PTB base pointer */
7428 #define PTB ((GPIO_Type *)PTB_BASE)
7429 #define PTB_BASE_PTR (PTB)
7430 /** Peripheral PTC base address */
7431 #define PTC_BASE (0x400FF080u)
7432 /** Peripheral PTC base pointer */
7433 #define PTC ((GPIO_Type *)PTC_BASE)
7434 #define PTC_BASE_PTR (PTC)
7435 /** Peripheral PTD base address */
7436 #define PTD_BASE (0x400FF0C0u)
7437 /** Peripheral PTD base pointer */
7438 #define PTD ((GPIO_Type *)PTD_BASE)
7439 #define PTD_BASE_PTR (PTD)
7440 /** Peripheral PTE base address */
7441 #define PTE_BASE (0x400FF100u)
7442 /** Peripheral PTE base pointer */
7443 #define PTE ((GPIO_Type *)PTE_BASE)
7444 #define PTE_BASE_PTR (PTE)
7445 /** Array initializer of GPIO peripheral base addresses */
7446 #define GPIO_BASE_ADDRS { PTA_BASE, PTB_BASE, PTC_BASE, PTD_BASE, PTE_BASE }
7447 /** Array initializer of GPIO peripheral base pointers */
7448 #define GPIO_BASE_PTRS { PTA, PTB, PTC, PTD, PTE }
7449
7450 /* ----------------------------------------------------------------------------
7451 -- GPIO - Register accessor macros
7452 ---------------------------------------------------------------------------- */
7453
7454 /*!
7455 * @addtogroup GPIO_Register_Accessor_Macros GPIO - Register accessor macros
7456 * @{
7457 */
7458
7459
7460 /* GPIO - Register instance definitions */
7461 /* PTA */
7462 #define GPIOA_PDOR GPIO_PDOR_REG(PTA)
7463 #define GPIOA_PSOR GPIO_PSOR_REG(PTA)
7464 #define GPIOA_PCOR GPIO_PCOR_REG(PTA)
7465 #define GPIOA_PTOR GPIO_PTOR_REG(PTA)
7466 #define GPIOA_PDIR GPIO_PDIR_REG(PTA)
7467 #define GPIOA_PDDR GPIO_PDDR_REG(PTA)
7468 /* PTB */
7469 #define GPIOB_PDOR GPIO_PDOR_REG(PTB)
7470 #define GPIOB_PSOR GPIO_PSOR_REG(PTB)
7471 #define GPIOB_PCOR GPIO_PCOR_REG(PTB)
7472 #define GPIOB_PTOR GPIO_PTOR_REG(PTB)
7473 #define GPIOB_PDIR GPIO_PDIR_REG(PTB)
7474 #define GPIOB_PDDR GPIO_PDDR_REG(PTB)
7475 /* PTC */
7476 #define GPIOC_PDOR GPIO_PDOR_REG(PTC)
7477 #define GPIOC_PSOR GPIO_PSOR_REG(PTC)
7478 #define GPIOC_PCOR GPIO_PCOR_REG(PTC)
7479 #define GPIOC_PTOR GPIO_PTOR_REG(PTC)
7480 #define GPIOC_PDIR GPIO_PDIR_REG(PTC)
7481 #define GPIOC_PDDR GPIO_PDDR_REG(PTC)
7482 /* PTD */
7483 #define GPIOD_PDOR GPIO_PDOR_REG(PTD)
7484 #define GPIOD_PSOR GPIO_PSOR_REG(PTD)
7485 #define GPIOD_PCOR GPIO_PCOR_REG(PTD)
7486 #define GPIOD_PTOR GPIO_PTOR_REG(PTD)
7487 #define GPIOD_PDIR GPIO_PDIR_REG(PTD)
7488 #define GPIOD_PDDR GPIO_PDDR_REG(PTD)
7489 /* PTE */
7490 #define GPIOE_PDOR GPIO_PDOR_REG(PTE)
7491 #define GPIOE_PSOR GPIO_PSOR_REG(PTE)
7492 #define GPIOE_PCOR GPIO_PCOR_REG(PTE)
7493 #define GPIOE_PTOR GPIO_PTOR_REG(PTE)
7494 #define GPIOE_PDIR GPIO_PDIR_REG(PTE)
7495 #define GPIOE_PDDR GPIO_PDDR_REG(PTE)
7496
7497 /*!
7498 * @}
7499 */ /* end of group GPIO_Register_Accessor_Macros */
7500
7501
7502 /*!
7503 * @}
7504 */ /* end of group GPIO_Peripheral_Access_Layer */
7505
7506
7507 /* ----------------------------------------------------------------------------
7508 -- I2C Peripheral Access Layer
7509 ---------------------------------------------------------------------------- */
7510
7511 /*!
7512 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
7513 * @{
7514 */
7515
7516 /** I2C - Register Layout Typedef */
7517 typedef struct {
7518 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
7519 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
7520 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
7521 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
7522 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
7523 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
7524 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
7525 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
7526 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
7527 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
7528 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
7529 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
7530 } I2C_Type, *I2C_MemMapPtr;
7531
7532 /* ----------------------------------------------------------------------------
7533 -- I2C - Register accessor macros
7534 ---------------------------------------------------------------------------- */
7535
7536 /*!
7537 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
7538 * @{
7539 */
7540
7541
7542 /* I2C - Register accessors */
7543 #define I2C_A1_REG(base) ((base)->A1)
7544 #define I2C_F_REG(base) ((base)->F)
7545 #define I2C_C1_REG(base) ((base)->C1)
7546 #define I2C_S_REG(base) ((base)->S)
7547 #define I2C_D_REG(base) ((base)->D)
7548 #define I2C_C2_REG(base) ((base)->C2)
7549 #define I2C_FLT_REG(base) ((base)->FLT)
7550 #define I2C_RA_REG(base) ((base)->RA)
7551 #define I2C_SMB_REG(base) ((base)->SMB)
7552 #define I2C_A2_REG(base) ((base)->A2)
7553 #define I2C_SLTH_REG(base) ((base)->SLTH)
7554 #define I2C_SLTL_REG(base) ((base)->SLTL)
7555
7556 /*!
7557 * @}
7558 */ /* end of group I2C_Register_Accessor_Macros */
7559
7560
7561 /* ----------------------------------------------------------------------------
7562 -- I2C Register Masks
7563 ---------------------------------------------------------------------------- */
7564
7565 /*!
7566 * @addtogroup I2C_Register_Masks I2C Register Masks
7567 * @{
7568 */
7569
7570 /* A1 Bit Fields */
7571 #define I2C_A1_AD_MASK 0xFEu
7572 #define I2C_A1_AD_SHIFT 1
7573 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
7574 /* F Bit Fields */
7575 #define I2C_F_ICR_MASK 0x3Fu
7576 #define I2C_F_ICR_SHIFT 0
7577 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
7578 #define I2C_F_MULT_MASK 0xC0u
7579 #define I2C_F_MULT_SHIFT 6
7580 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
7581 /* C1 Bit Fields */
7582 #define I2C_C1_DMAEN_MASK 0x1u
7583 #define I2C_C1_DMAEN_SHIFT 0
7584 #define I2C_C1_WUEN_MASK 0x2u
7585 #define I2C_C1_WUEN_SHIFT 1
7586 #define I2C_C1_RSTA_MASK 0x4u
7587 #define I2C_C1_RSTA_SHIFT 2
7588 #define I2C_C1_TXAK_MASK 0x8u
7589 #define I2C_C1_TXAK_SHIFT 3
7590 #define I2C_C1_TX_MASK 0x10u
7591 #define I2C_C1_TX_SHIFT 4
7592 #define I2C_C1_MST_MASK 0x20u
7593 #define I2C_C1_MST_SHIFT 5
7594 #define I2C_C1_IICIE_MASK 0x40u
7595 #define I2C_C1_IICIE_SHIFT 6
7596 #define I2C_C1_IICEN_MASK 0x80u
7597 #define I2C_C1_IICEN_SHIFT 7
7598 /* S Bit Fields */
7599 #define I2C_S_RXAK_MASK 0x1u
7600 #define I2C_S_RXAK_SHIFT 0
7601 #define I2C_S_IICIF_MASK 0x2u
7602 #define I2C_S_IICIF_SHIFT 1
7603 #define I2C_S_SRW_MASK 0x4u
7604 #define I2C_S_SRW_SHIFT 2
7605 #define I2C_S_RAM_MASK 0x8u
7606 #define I2C_S_RAM_SHIFT 3
7607 #define I2C_S_ARBL_MASK 0x10u
7608 #define I2C_S_ARBL_SHIFT 4
7609 #define I2C_S_BUSY_MASK 0x20u
7610 #define I2C_S_BUSY_SHIFT 5
7611 #define I2C_S_IAAS_MASK 0x40u
7612 #define I2C_S_IAAS_SHIFT 6
7613 #define I2C_S_TCF_MASK 0x80u
7614 #define I2C_S_TCF_SHIFT 7
7615 /* D Bit Fields */
7616 #define I2C_D_DATA_MASK 0xFFu
7617 #define I2C_D_DATA_SHIFT 0
7618 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
7619 /* C2 Bit Fields */
7620 #define I2C_C2_AD_MASK 0x7u
7621 #define I2C_C2_AD_SHIFT 0
7622 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
7623 #define I2C_C2_RMEN_MASK 0x8u
7624 #define I2C_C2_RMEN_SHIFT 3
7625 #define I2C_C2_SBRC_MASK 0x10u
7626 #define I2C_C2_SBRC_SHIFT 4
7627 #define I2C_C2_HDRS_MASK 0x20u
7628 #define I2C_C2_HDRS_SHIFT 5
7629 #define I2C_C2_ADEXT_MASK 0x40u
7630 #define I2C_C2_ADEXT_SHIFT 6
7631 #define I2C_C2_GCAEN_MASK 0x80u
7632 #define I2C_C2_GCAEN_SHIFT 7
7633 /* FLT Bit Fields */
7634 #define I2C_FLT_FLT_MASK 0xFu
7635 #define I2C_FLT_FLT_SHIFT 0
7636 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
7637 #define I2C_FLT_STARTF_MASK 0x10u
7638 #define I2C_FLT_STARTF_SHIFT 4
7639 #define I2C_FLT_SSIE_MASK 0x20u
7640 #define I2C_FLT_SSIE_SHIFT 5
7641 #define I2C_FLT_STOPF_MASK 0x40u
7642 #define I2C_FLT_STOPF_SHIFT 6
7643 #define I2C_FLT_SHEN_MASK 0x80u
7644 #define I2C_FLT_SHEN_SHIFT 7
7645 /* RA Bit Fields */
7646 #define I2C_RA_RAD_MASK 0xFEu
7647 #define I2C_RA_RAD_SHIFT 1
7648 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
7649 /* SMB Bit Fields */
7650 #define I2C_SMB_SHTF2IE_MASK 0x1u
7651 #define I2C_SMB_SHTF2IE_SHIFT 0
7652 #define I2C_SMB_SHTF2_MASK 0x2u
7653 #define I2C_SMB_SHTF2_SHIFT 1
7654 #define I2C_SMB_SHTF1_MASK 0x4u
7655 #define I2C_SMB_SHTF1_SHIFT 2
7656 #define I2C_SMB_SLTF_MASK 0x8u
7657 #define I2C_SMB_SLTF_SHIFT 3
7658 #define I2C_SMB_TCKSEL_MASK 0x10u
7659 #define I2C_SMB_TCKSEL_SHIFT 4
7660 #define I2C_SMB_SIICAEN_MASK 0x20u
7661 #define I2C_SMB_SIICAEN_SHIFT 5
7662 #define I2C_SMB_ALERTEN_MASK 0x40u
7663 #define I2C_SMB_ALERTEN_SHIFT 6
7664 #define I2C_SMB_FACK_MASK 0x80u
7665 #define I2C_SMB_FACK_SHIFT 7
7666 /* A2 Bit Fields */
7667 #define I2C_A2_SAD_MASK 0xFEu
7668 #define I2C_A2_SAD_SHIFT 1
7669 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
7670 /* SLTH Bit Fields */
7671 #define I2C_SLTH_SSLT_MASK 0xFFu
7672 #define I2C_SLTH_SSLT_SHIFT 0
7673 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
7674 /* SLTL Bit Fields */
7675 #define I2C_SLTL_SSLT_MASK 0xFFu
7676 #define I2C_SLTL_SSLT_SHIFT 0
7677 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
7678
7679 /*!
7680 * @}
7681 */ /* end of group I2C_Register_Masks */
7682
7683
7684 /* I2C - Peripheral instance base addresses */
7685 /** Peripheral I2C0 base address */
7686 #define I2C0_BASE (0x40066000u)
7687 /** Peripheral I2C0 base pointer */
7688 #define I2C0 ((I2C_Type *)I2C0_BASE)
7689 #define I2C0_BASE_PTR (I2C0)
7690 /** Peripheral I2C1 base address */
7691 #define I2C1_BASE (0x40067000u)
7692 /** Peripheral I2C1 base pointer */
7693 #define I2C1 ((I2C_Type *)I2C1_BASE)
7694 #define I2C1_BASE_PTR (I2C1)
7695 /** Peripheral I2C2 base address */
7696 #define I2C2_BASE (0x400E6000u)
7697 /** Peripheral I2C2 base pointer */
7698 #define I2C2 ((I2C_Type *)I2C2_BASE)
7699 #define I2C2_BASE_PTR (I2C2)
7700 /** Array initializer of I2C peripheral base addresses */
7701 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
7702 /** Array initializer of I2C peripheral base pointers */
7703 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
7704 /** Interrupt vectors for the I2C peripheral type */
7705 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
7706
7707 /* ----------------------------------------------------------------------------
7708 -- I2C - Register accessor macros
7709 ---------------------------------------------------------------------------- */
7710
7711 /*!
7712 * @addtogroup I2C_Register_Accessor_Macros I2C - Register accessor macros
7713 * @{
7714 */
7715
7716
7717 /* I2C - Register instance definitions */
7718 /* I2C0 */
7719 #define I2C0_A1 I2C_A1_REG(I2C0)
7720 #define I2C0_F I2C_F_REG(I2C0)
7721 #define I2C0_C1 I2C_C1_REG(I2C0)
7722 #define I2C0_S I2C_S_REG(I2C0)
7723 #define I2C0_D I2C_D_REG(I2C0)
7724 #define I2C0_C2 I2C_C2_REG(I2C0)
7725 #define I2C0_FLT I2C_FLT_REG(I2C0)
7726 #define I2C0_RA I2C_RA_REG(I2C0)
7727 #define I2C0_SMB I2C_SMB_REG(I2C0)
7728 #define I2C0_A2 I2C_A2_REG(I2C0)
7729 #define I2C0_SLTH I2C_SLTH_REG(I2C0)
7730 #define I2C0_SLTL I2C_SLTL_REG(I2C0)
7731 /* I2C1 */
7732 #define I2C1_A1 I2C_A1_REG(I2C1)
7733 #define I2C1_F I2C_F_REG(I2C1)
7734 #define I2C1_C1 I2C_C1_REG(I2C1)
7735 #define I2C1_S I2C_S_REG(I2C1)
7736 #define I2C1_D I2C_D_REG(I2C1)
7737 #define I2C1_C2 I2C_C2_REG(I2C1)
7738 #define I2C1_FLT I2C_FLT_REG(I2C1)
7739 #define I2C1_RA I2C_RA_REG(I2C1)
7740 #define I2C1_SMB I2C_SMB_REG(I2C1)
7741 #define I2C1_A2 I2C_A2_REG(I2C1)
7742 #define I2C1_SLTH I2C_SLTH_REG(I2C1)
7743 #define I2C1_SLTL I2C_SLTL_REG(I2C1)
7744 /* I2C2 */
7745 #define I2C2_A1 I2C_A1_REG(I2C2)
7746 #define I2C2_F I2C_F_REG(I2C2)
7747 #define I2C2_C1 I2C_C1_REG(I2C2)
7748 #define I2C2_S I2C_S_REG(I2C2)
7749 #define I2C2_D I2C_D_REG(I2C2)
7750 #define I2C2_C2 I2C_C2_REG(I2C2)
7751 #define I2C2_FLT I2C_FLT_REG(I2C2)
7752 #define I2C2_RA I2C_RA_REG(I2C2)
7753 #define I2C2_SMB I2C_SMB_REG(I2C2)
7754 #define I2C2_A2 I2C_A2_REG(I2C2)
7755 #define I2C2_SLTH I2C_SLTH_REG(I2C2)
7756 #define I2C2_SLTL I2C_SLTL_REG(I2C2)
7757
7758 /*!
7759 * @}
7760 */ /* end of group I2C_Register_Accessor_Macros */
7761
7762
7763 /*!
7764 * @}
7765 */ /* end of group I2C_Peripheral_Access_Layer */
7766
7767
7768 /* ----------------------------------------------------------------------------
7769 -- I2S Peripheral Access Layer
7770 ---------------------------------------------------------------------------- */
7771
7772 /*!
7773 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
7774 * @{
7775 */
7776
7777 /** I2S - Register Layout Typedef */
7778 typedef struct {
7779 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
7780 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
7781 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
7782 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
7783 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
7784 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
7785 uint8_t RESERVED_0[8];
7786 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
7787 uint8_t RESERVED_1[24];
7788 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
7789 uint8_t RESERVED_2[24];
7790 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
7791 uint8_t RESERVED_3[28];
7792 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
7793 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
7794 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
7795 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
7796 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
7797 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
7798 uint8_t RESERVED_4[8];
7799 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
7800 uint8_t RESERVED_5[24];
7801 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
7802 uint8_t RESERVED_6[24];
7803 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
7804 uint8_t RESERVED_7[28];
7805 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
7806 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
7807 } I2S_Type, *I2S_MemMapPtr;
7808
7809 /* ----------------------------------------------------------------------------
7810 -- I2S - Register accessor macros
7811 ---------------------------------------------------------------------------- */
7812
7813 /*!
7814 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
7815 * @{
7816 */
7817
7818
7819 /* I2S - Register accessors */
7820 #define I2S_TCSR_REG(base) ((base)->TCSR)
7821 #define I2S_TCR1_REG(base) ((base)->TCR1)
7822 #define I2S_TCR2_REG(base) ((base)->TCR2)
7823 #define I2S_TCR3_REG(base) ((base)->TCR3)
7824 #define I2S_TCR4_REG(base) ((base)->TCR4)
7825 #define I2S_TCR5_REG(base) ((base)->TCR5)
7826 #define I2S_TDR_REG(base,index) ((base)->TDR[index])
7827 #define I2S_TFR_REG(base,index) ((base)->TFR[index])
7828 #define I2S_TMR_REG(base) ((base)->TMR)
7829 #define I2S_RCSR_REG(base) ((base)->RCSR)
7830 #define I2S_RCR1_REG(base) ((base)->RCR1)
7831 #define I2S_RCR2_REG(base) ((base)->RCR2)
7832 #define I2S_RCR3_REG(base) ((base)->RCR3)
7833 #define I2S_RCR4_REG(base) ((base)->RCR4)
7834 #define I2S_RCR5_REG(base) ((base)->RCR5)
7835 #define I2S_RDR_REG(base,index) ((base)->RDR[index])
7836 #define I2S_RFR_REG(base,index) ((base)->RFR[index])
7837 #define I2S_RMR_REG(base) ((base)->RMR)
7838 #define I2S_MCR_REG(base) ((base)->MCR)
7839 #define I2S_MDR_REG(base) ((base)->MDR)
7840
7841 /*!
7842 * @}
7843 */ /* end of group I2S_Register_Accessor_Macros */
7844
7845
7846 /* ----------------------------------------------------------------------------
7847 -- I2S Register Masks
7848 ---------------------------------------------------------------------------- */
7849
7850 /*!
7851 * @addtogroup I2S_Register_Masks I2S Register Masks
7852 * @{
7853 */
7854
7855 /* TCSR Bit Fields */
7856 #define I2S_TCSR_FRDE_MASK 0x1u
7857 #define I2S_TCSR_FRDE_SHIFT 0
7858 #define I2S_TCSR_FWDE_MASK 0x2u
7859 #define I2S_TCSR_FWDE_SHIFT 1
7860 #define I2S_TCSR_FRIE_MASK 0x100u
7861 #define I2S_TCSR_FRIE_SHIFT 8
7862 #define I2S_TCSR_FWIE_MASK 0x200u
7863 #define I2S_TCSR_FWIE_SHIFT 9
7864 #define I2S_TCSR_FEIE_MASK 0x400u
7865 #define I2S_TCSR_FEIE_SHIFT 10
7866 #define I2S_TCSR_SEIE_MASK 0x800u
7867 #define I2S_TCSR_SEIE_SHIFT 11
7868 #define I2S_TCSR_WSIE_MASK 0x1000u
7869 #define I2S_TCSR_WSIE_SHIFT 12
7870 #define I2S_TCSR_FRF_MASK 0x10000u
7871 #define I2S_TCSR_FRF_SHIFT 16
7872 #define I2S_TCSR_FWF_MASK 0x20000u
7873 #define I2S_TCSR_FWF_SHIFT 17
7874 #define I2S_TCSR_FEF_MASK 0x40000u
7875 #define I2S_TCSR_FEF_SHIFT 18
7876 #define I2S_TCSR_SEF_MASK 0x80000u
7877 #define I2S_TCSR_SEF_SHIFT 19
7878 #define I2S_TCSR_WSF_MASK 0x100000u
7879 #define I2S_TCSR_WSF_SHIFT 20
7880 #define I2S_TCSR_SR_MASK 0x1000000u
7881 #define I2S_TCSR_SR_SHIFT 24
7882 #define I2S_TCSR_FR_MASK 0x2000000u
7883 #define I2S_TCSR_FR_SHIFT 25
7884 #define I2S_TCSR_BCE_MASK 0x10000000u
7885 #define I2S_TCSR_BCE_SHIFT 28
7886 #define I2S_TCSR_DBGE_MASK 0x20000000u
7887 #define I2S_TCSR_DBGE_SHIFT 29
7888 #define I2S_TCSR_STOPE_MASK 0x40000000u
7889 #define I2S_TCSR_STOPE_SHIFT 30
7890 #define I2S_TCSR_TE_MASK 0x80000000u
7891 #define I2S_TCSR_TE_SHIFT 31
7892 /* TCR1 Bit Fields */
7893 #define I2S_TCR1_TFW_MASK 0x7u
7894 #define I2S_TCR1_TFW_SHIFT 0
7895 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR1_TFW_SHIFT))&I2S_TCR1_TFW_MASK)
7896 /* TCR2 Bit Fields */
7897 #define I2S_TCR2_DIV_MASK 0xFFu
7898 #define I2S_TCR2_DIV_SHIFT 0
7899 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_DIV_SHIFT))&I2S_TCR2_DIV_MASK)
7900 #define I2S_TCR2_BCD_MASK 0x1000000u
7901 #define I2S_TCR2_BCD_SHIFT 24
7902 #define I2S_TCR2_BCP_MASK 0x2000000u
7903 #define I2S_TCR2_BCP_SHIFT 25
7904 #define I2S_TCR2_MSEL_MASK 0xC000000u
7905 #define I2S_TCR2_MSEL_SHIFT 26
7906 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_MSEL_SHIFT))&I2S_TCR2_MSEL_MASK)
7907 #define I2S_TCR2_BCI_MASK 0x10000000u
7908 #define I2S_TCR2_BCI_SHIFT 28
7909 #define I2S_TCR2_BCS_MASK 0x20000000u
7910 #define I2S_TCR2_BCS_SHIFT 29
7911 #define I2S_TCR2_SYNC_MASK 0xC0000000u
7912 #define I2S_TCR2_SYNC_SHIFT 30
7913 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR2_SYNC_SHIFT))&I2S_TCR2_SYNC_MASK)
7914 /* TCR3 Bit Fields */
7915 #define I2S_TCR3_WDFL_MASK 0x1Fu
7916 #define I2S_TCR3_WDFL_SHIFT 0
7917 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_WDFL_SHIFT))&I2S_TCR3_WDFL_MASK)
7918 #define I2S_TCR3_TCE_MASK 0x30000u
7919 #define I2S_TCR3_TCE_SHIFT 16
7920 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR3_TCE_SHIFT))&I2S_TCR3_TCE_MASK)
7921 /* TCR4 Bit Fields */
7922 #define I2S_TCR4_FSD_MASK 0x1u
7923 #define I2S_TCR4_FSD_SHIFT 0
7924 #define I2S_TCR4_FSP_MASK 0x2u
7925 #define I2S_TCR4_FSP_SHIFT 1
7926 #define I2S_TCR4_FSE_MASK 0x8u
7927 #define I2S_TCR4_FSE_SHIFT 3
7928 #define I2S_TCR4_MF_MASK 0x10u
7929 #define I2S_TCR4_MF_SHIFT 4
7930 #define I2S_TCR4_SYWD_MASK 0x1F00u
7931 #define I2S_TCR4_SYWD_SHIFT 8
7932 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_SYWD_SHIFT))&I2S_TCR4_SYWD_MASK)
7933 #define I2S_TCR4_FRSZ_MASK 0x1F0000u
7934 #define I2S_TCR4_FRSZ_SHIFT 16
7935 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR4_FRSZ_SHIFT))&I2S_TCR4_FRSZ_MASK)
7936 /* TCR5 Bit Fields */
7937 #define I2S_TCR5_FBT_MASK 0x1F00u
7938 #define I2S_TCR5_FBT_SHIFT 8
7939 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_FBT_SHIFT))&I2S_TCR5_FBT_MASK)
7940 #define I2S_TCR5_W0W_MASK 0x1F0000u
7941 #define I2S_TCR5_W0W_SHIFT 16
7942 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_W0W_SHIFT))&I2S_TCR5_W0W_MASK)
7943 #define I2S_TCR5_WNW_MASK 0x1F000000u
7944 #define I2S_TCR5_WNW_SHIFT 24
7945 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_TCR5_WNW_SHIFT))&I2S_TCR5_WNW_MASK)
7946 /* TDR Bit Fields */
7947 #define I2S_TDR_TDR_MASK 0xFFFFFFFFu
7948 #define I2S_TDR_TDR_SHIFT 0
7949 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_TDR_TDR_SHIFT))&I2S_TDR_TDR_MASK)
7950 /* TFR Bit Fields */
7951 #define I2S_TFR_RFP_MASK 0xFu
7952 #define I2S_TFR_RFP_SHIFT 0
7953 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_RFP_SHIFT))&I2S_TFR_RFP_MASK)
7954 #define I2S_TFR_WFP_MASK 0xF0000u
7955 #define I2S_TFR_WFP_SHIFT 16
7956 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_TFR_WFP_SHIFT))&I2S_TFR_WFP_MASK)
7957 /* TMR Bit Fields */
7958 #define I2S_TMR_TWM_MASK 0xFFFFFFFFu
7959 #define I2S_TMR_TWM_SHIFT 0
7960 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_TMR_TWM_SHIFT))&I2S_TMR_TWM_MASK)
7961 /* RCSR Bit Fields */
7962 #define I2S_RCSR_FRDE_MASK 0x1u
7963 #define I2S_RCSR_FRDE_SHIFT 0
7964 #define I2S_RCSR_FWDE_MASK 0x2u
7965 #define I2S_RCSR_FWDE_SHIFT 1
7966 #define I2S_RCSR_FRIE_MASK 0x100u
7967 #define I2S_RCSR_FRIE_SHIFT 8
7968 #define I2S_RCSR_FWIE_MASK 0x200u
7969 #define I2S_RCSR_FWIE_SHIFT 9
7970 #define I2S_RCSR_FEIE_MASK 0x400u
7971 #define I2S_RCSR_FEIE_SHIFT 10
7972 #define I2S_RCSR_SEIE_MASK 0x800u
7973 #define I2S_RCSR_SEIE_SHIFT 11
7974 #define I2S_RCSR_WSIE_MASK 0x1000u
7975 #define I2S_RCSR_WSIE_SHIFT 12
7976 #define I2S_RCSR_FRF_MASK 0x10000u
7977 #define I2S_RCSR_FRF_SHIFT 16
7978 #define I2S_RCSR_FWF_MASK 0x20000u
7979 #define I2S_RCSR_FWF_SHIFT 17
7980 #define I2S_RCSR_FEF_MASK 0x40000u
7981 #define I2S_RCSR_FEF_SHIFT 18
7982 #define I2S_RCSR_SEF_MASK 0x80000u
7983 #define I2S_RCSR_SEF_SHIFT 19
7984 #define I2S_RCSR_WSF_MASK 0x100000u
7985 #define I2S_RCSR_WSF_SHIFT 20
7986 #define I2S_RCSR_SR_MASK 0x1000000u
7987 #define I2S_RCSR_SR_SHIFT 24
7988 #define I2S_RCSR_FR_MASK 0x2000000u
7989 #define I2S_RCSR_FR_SHIFT 25
7990 #define I2S_RCSR_BCE_MASK 0x10000000u
7991 #define I2S_RCSR_BCE_SHIFT 28
7992 #define I2S_RCSR_DBGE_MASK 0x20000000u
7993 #define I2S_RCSR_DBGE_SHIFT 29
7994 #define I2S_RCSR_STOPE_MASK 0x40000000u
7995 #define I2S_RCSR_STOPE_SHIFT 30
7996 #define I2S_RCSR_RE_MASK 0x80000000u
7997 #define I2S_RCSR_RE_SHIFT 31
7998 /* RCR1 Bit Fields */
7999 #define I2S_RCR1_RFW_MASK 0x7u
8000 #define I2S_RCR1_RFW_SHIFT 0
8001 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR1_RFW_SHIFT))&I2S_RCR1_RFW_MASK)
8002 /* RCR2 Bit Fields */
8003 #define I2S_RCR2_DIV_MASK 0xFFu
8004 #define I2S_RCR2_DIV_SHIFT 0
8005 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_DIV_SHIFT))&I2S_RCR2_DIV_MASK)
8006 #define I2S_RCR2_BCD_MASK 0x1000000u
8007 #define I2S_RCR2_BCD_SHIFT 24
8008 #define I2S_RCR2_BCP_MASK 0x2000000u
8009 #define I2S_RCR2_BCP_SHIFT 25
8010 #define I2S_RCR2_MSEL_MASK 0xC000000u
8011 #define I2S_RCR2_MSEL_SHIFT 26
8012 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_MSEL_SHIFT))&I2S_RCR2_MSEL_MASK)
8013 #define I2S_RCR2_BCI_MASK 0x10000000u
8014 #define I2S_RCR2_BCI_SHIFT 28
8015 #define I2S_RCR2_BCS_MASK 0x20000000u
8016 #define I2S_RCR2_BCS_SHIFT 29
8017 #define I2S_RCR2_SYNC_MASK 0xC0000000u
8018 #define I2S_RCR2_SYNC_SHIFT 30
8019 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR2_SYNC_SHIFT))&I2S_RCR2_SYNC_MASK)
8020 /* RCR3 Bit Fields */
8021 #define I2S_RCR3_WDFL_MASK 0x1Fu
8022 #define I2S_RCR3_WDFL_SHIFT 0
8023 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_WDFL_SHIFT))&I2S_RCR3_WDFL_MASK)
8024 #define I2S_RCR3_RCE_MASK 0x30000u
8025 #define I2S_RCR3_RCE_SHIFT 16
8026 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR3_RCE_SHIFT))&I2S_RCR3_RCE_MASK)
8027 /* RCR4 Bit Fields */
8028 #define I2S_RCR4_FSD_MASK 0x1u
8029 #define I2S_RCR4_FSD_SHIFT 0
8030 #define I2S_RCR4_FSP_MASK 0x2u
8031 #define I2S_RCR4_FSP_SHIFT 1
8032 #define I2S_RCR4_FSE_MASK 0x8u
8033 #define I2S_RCR4_FSE_SHIFT 3
8034 #define I2S_RCR4_MF_MASK 0x10u
8035 #define I2S_RCR4_MF_SHIFT 4
8036 #define I2S_RCR4_SYWD_MASK 0x1F00u
8037 #define I2S_RCR4_SYWD_SHIFT 8
8038 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_SYWD_SHIFT))&I2S_RCR4_SYWD_MASK)
8039 #define I2S_RCR4_FRSZ_MASK 0x1F0000u
8040 #define I2S_RCR4_FRSZ_SHIFT 16
8041 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR4_FRSZ_SHIFT))&I2S_RCR4_FRSZ_MASK)
8042 /* RCR5 Bit Fields */
8043 #define I2S_RCR5_FBT_MASK 0x1F00u
8044 #define I2S_RCR5_FBT_SHIFT 8
8045 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_FBT_SHIFT))&I2S_RCR5_FBT_MASK)
8046 #define I2S_RCR5_W0W_MASK 0x1F0000u
8047 #define I2S_RCR5_W0W_SHIFT 16
8048 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_W0W_SHIFT))&I2S_RCR5_W0W_MASK)
8049 #define I2S_RCR5_WNW_MASK 0x1F000000u
8050 #define I2S_RCR5_WNW_SHIFT 24
8051 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x))<<I2S_RCR5_WNW_SHIFT))&I2S_RCR5_WNW_MASK)
8052 /* RDR Bit Fields */
8053 #define I2S_RDR_RDR_MASK 0xFFFFFFFFu
8054 #define I2S_RDR_RDR_SHIFT 0
8055 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x))<<I2S_RDR_RDR_SHIFT))&I2S_RDR_RDR_MASK)
8056 /* RFR Bit Fields */
8057 #define I2S_RFR_RFP_MASK 0xFu
8058 #define I2S_RFR_RFP_SHIFT 0
8059 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_RFP_SHIFT))&I2S_RFR_RFP_MASK)
8060 #define I2S_RFR_WFP_MASK 0xF0000u
8061 #define I2S_RFR_WFP_SHIFT 16
8062 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x))<<I2S_RFR_WFP_SHIFT))&I2S_RFR_WFP_MASK)
8063 /* RMR Bit Fields */
8064 #define I2S_RMR_RWM_MASK 0xFFFFFFFFu
8065 #define I2S_RMR_RWM_SHIFT 0
8066 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x))<<I2S_RMR_RWM_SHIFT))&I2S_RMR_RWM_MASK)
8067 /* MCR Bit Fields */
8068 #define I2S_MCR_MICS_MASK 0x3000000u
8069 #define I2S_MCR_MICS_SHIFT 24
8070 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x))<<I2S_MCR_MICS_SHIFT))&I2S_MCR_MICS_MASK)
8071 #define I2S_MCR_MOE_MASK 0x40000000u
8072 #define I2S_MCR_MOE_SHIFT 30
8073 #define I2S_MCR_DUF_MASK 0x80000000u
8074 #define I2S_MCR_DUF_SHIFT 31
8075 /* MDR Bit Fields */
8076 #define I2S_MDR_DIVIDE_MASK 0xFFFu
8077 #define I2S_MDR_DIVIDE_SHIFT 0
8078 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_DIVIDE_SHIFT))&I2S_MDR_DIVIDE_MASK)
8079 #define I2S_MDR_FRACT_MASK 0xFF000u
8080 #define I2S_MDR_FRACT_SHIFT 12
8081 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x))<<I2S_MDR_FRACT_SHIFT))&I2S_MDR_FRACT_MASK)
8082
8083 /*!
8084 * @}
8085 */ /* end of group I2S_Register_Masks */
8086
8087
8088 /* I2S - Peripheral instance base addresses */
8089 /** Peripheral I2S0 base address */
8090 #define I2S0_BASE (0x4002F000u)
8091 /** Peripheral I2S0 base pointer */
8092 #define I2S0 ((I2S_Type *)I2S0_BASE)
8093 #define I2S0_BASE_PTR (I2S0)
8094 /** Array initializer of I2S peripheral base addresses */
8095 #define I2S_BASE_ADDRS { I2S0_BASE }
8096 /** Array initializer of I2S peripheral base pointers */
8097 #define I2S_BASE_PTRS { I2S0 }
8098 /** Interrupt vectors for the I2S peripheral type */
8099 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
8100 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
8101
8102 /* ----------------------------------------------------------------------------
8103 -- I2S - Register accessor macros
8104 ---------------------------------------------------------------------------- */
8105
8106 /*!
8107 * @addtogroup I2S_Register_Accessor_Macros I2S - Register accessor macros
8108 * @{
8109 */
8110
8111
8112 /* I2S - Register instance definitions */
8113 /* I2S0 */
8114 #define I2S0_TCSR I2S_TCSR_REG(I2S0)
8115 #define I2S0_TCR1 I2S_TCR1_REG(I2S0)
8116 #define I2S0_TCR2 I2S_TCR2_REG(I2S0)
8117 #define I2S0_TCR3 I2S_TCR3_REG(I2S0)
8118 #define I2S0_TCR4 I2S_TCR4_REG(I2S0)
8119 #define I2S0_TCR5 I2S_TCR5_REG(I2S0)
8120 #define I2S0_TDR0 I2S_TDR_REG(I2S0,0)
8121 #define I2S0_TDR1 I2S_TDR_REG(I2S0,1)
8122 #define I2S0_TFR0 I2S_TFR_REG(I2S0,0)
8123 #define I2S0_TFR1 I2S_TFR_REG(I2S0,1)
8124 #define I2S0_TMR I2S_TMR_REG(I2S0)
8125 #define I2S0_RCSR I2S_RCSR_REG(I2S0)
8126 #define I2S0_RCR1 I2S_RCR1_REG(I2S0)
8127 #define I2S0_RCR2 I2S_RCR2_REG(I2S0)
8128 #define I2S0_RCR3 I2S_RCR3_REG(I2S0)
8129 #define I2S0_RCR4 I2S_RCR4_REG(I2S0)
8130 #define I2S0_RCR5 I2S_RCR5_REG(I2S0)
8131 #define I2S0_RDR0 I2S_RDR_REG(I2S0,0)
8132 #define I2S0_RDR1 I2S_RDR_REG(I2S0,1)
8133 #define I2S0_RFR0 I2S_RFR_REG(I2S0,0)
8134 #define I2S0_RFR1 I2S_RFR_REG(I2S0,1)
8135 #define I2S0_RMR I2S_RMR_REG(I2S0)
8136 #define I2S0_MCR I2S_MCR_REG(I2S0)
8137 #define I2S0_MDR I2S_MDR_REG(I2S0)
8138
8139 /* I2S - Register array accessors */
8140 #define I2S0_TDR(index) I2S_TDR_REG(I2S0,index)
8141 #define I2S0_TFR(index) I2S_TFR_REG(I2S0,index)
8142 #define I2S0_RDR(index) I2S_RDR_REG(I2S0,index)
8143 #define I2S0_RFR(index) I2S_RFR_REG(I2S0,index)
8144
8145 /*!
8146 * @}
8147 */ /* end of group I2S_Register_Accessor_Macros */
8148
8149
8150 /*!
8151 * @}
8152 */ /* end of group I2S_Peripheral_Access_Layer */
8153
8154
8155 /* ----------------------------------------------------------------------------
8156 -- LLWU Peripheral Access Layer
8157 ---------------------------------------------------------------------------- */
8158
8159 /*!
8160 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
8161 * @{
8162 */
8163
8164 /** LLWU - Register Layout Typedef */
8165 typedef struct {
8166 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
8167 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
8168 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
8169 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
8170 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
8171 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
8172 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
8173 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
8174 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
8175 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
8176 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
8177 } LLWU_Type, *LLWU_MemMapPtr;
8178
8179 /* ----------------------------------------------------------------------------
8180 -- LLWU - Register accessor macros
8181 ---------------------------------------------------------------------------- */
8182
8183 /*!
8184 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
8185 * @{
8186 */
8187
8188
8189 /* LLWU - Register accessors */
8190 #define LLWU_PE1_REG(base) ((base)->PE1)
8191 #define LLWU_PE2_REG(base) ((base)->PE2)
8192 #define LLWU_PE3_REG(base) ((base)->PE3)
8193 #define LLWU_PE4_REG(base) ((base)->PE4)
8194 #define LLWU_ME_REG(base) ((base)->ME)
8195 #define LLWU_F1_REG(base) ((base)->F1)
8196 #define LLWU_F2_REG(base) ((base)->F2)
8197 #define LLWU_F3_REG(base) ((base)->F3)
8198 #define LLWU_FILT1_REG(base) ((base)->FILT1)
8199 #define LLWU_FILT2_REG(base) ((base)->FILT2)
8200 #define LLWU_RST_REG(base) ((base)->RST)
8201
8202 /*!
8203 * @}
8204 */ /* end of group LLWU_Register_Accessor_Macros */
8205
8206
8207 /* ----------------------------------------------------------------------------
8208 -- LLWU Register Masks
8209 ---------------------------------------------------------------------------- */
8210
8211 /*!
8212 * @addtogroup LLWU_Register_Masks LLWU Register Masks
8213 * @{
8214 */
8215
8216 /* PE1 Bit Fields */
8217 #define LLWU_PE1_WUPE0_MASK 0x3u
8218 #define LLWU_PE1_WUPE0_SHIFT 0
8219 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
8220 #define LLWU_PE1_WUPE1_MASK 0xCu
8221 #define LLWU_PE1_WUPE1_SHIFT 2
8222 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
8223 #define LLWU_PE1_WUPE2_MASK 0x30u
8224 #define LLWU_PE1_WUPE2_SHIFT 4
8225 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
8226 #define LLWU_PE1_WUPE3_MASK 0xC0u
8227 #define LLWU_PE1_WUPE3_SHIFT 6
8228 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
8229 /* PE2 Bit Fields */
8230 #define LLWU_PE2_WUPE4_MASK 0x3u
8231 #define LLWU_PE2_WUPE4_SHIFT 0
8232 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
8233 #define LLWU_PE2_WUPE5_MASK 0xCu
8234 #define LLWU_PE2_WUPE5_SHIFT 2
8235 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
8236 #define LLWU_PE2_WUPE6_MASK 0x30u
8237 #define LLWU_PE2_WUPE6_SHIFT 4
8238 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
8239 #define LLWU_PE2_WUPE7_MASK 0xC0u
8240 #define LLWU_PE2_WUPE7_SHIFT 6
8241 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
8242 /* PE3 Bit Fields */
8243 #define LLWU_PE3_WUPE8_MASK 0x3u
8244 #define LLWU_PE3_WUPE8_SHIFT 0
8245 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
8246 #define LLWU_PE3_WUPE9_MASK 0xCu
8247 #define LLWU_PE3_WUPE9_SHIFT 2
8248 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
8249 #define LLWU_PE3_WUPE10_MASK 0x30u
8250 #define LLWU_PE3_WUPE10_SHIFT 4
8251 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
8252 #define LLWU_PE3_WUPE11_MASK 0xC0u
8253 #define LLWU_PE3_WUPE11_SHIFT 6
8254 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
8255 /* PE4 Bit Fields */
8256 #define LLWU_PE4_WUPE12_MASK 0x3u
8257 #define LLWU_PE4_WUPE12_SHIFT 0
8258 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
8259 #define LLWU_PE4_WUPE13_MASK 0xCu
8260 #define LLWU_PE4_WUPE13_SHIFT 2
8261 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
8262 #define LLWU_PE4_WUPE14_MASK 0x30u
8263 #define LLWU_PE4_WUPE14_SHIFT 4
8264 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
8265 #define LLWU_PE4_WUPE15_MASK 0xC0u
8266 #define LLWU_PE4_WUPE15_SHIFT 6
8267 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
8268 /* ME Bit Fields */
8269 #define LLWU_ME_WUME0_MASK 0x1u
8270 #define LLWU_ME_WUME0_SHIFT 0
8271 #define LLWU_ME_WUME1_MASK 0x2u
8272 #define LLWU_ME_WUME1_SHIFT 1
8273 #define LLWU_ME_WUME2_MASK 0x4u
8274 #define LLWU_ME_WUME2_SHIFT 2
8275 #define LLWU_ME_WUME3_MASK 0x8u
8276 #define LLWU_ME_WUME3_SHIFT 3
8277 #define LLWU_ME_WUME4_MASK 0x10u
8278 #define LLWU_ME_WUME4_SHIFT 4
8279 #define LLWU_ME_WUME5_MASK 0x20u
8280 #define LLWU_ME_WUME5_SHIFT 5
8281 #define LLWU_ME_WUME6_MASK 0x40u
8282 #define LLWU_ME_WUME6_SHIFT 6
8283 #define LLWU_ME_WUME7_MASK 0x80u
8284 #define LLWU_ME_WUME7_SHIFT 7
8285 /* F1 Bit Fields */
8286 #define LLWU_F1_WUF0_MASK 0x1u
8287 #define LLWU_F1_WUF0_SHIFT 0
8288 #define LLWU_F1_WUF1_MASK 0x2u
8289 #define LLWU_F1_WUF1_SHIFT 1
8290 #define LLWU_F1_WUF2_MASK 0x4u
8291 #define LLWU_F1_WUF2_SHIFT 2
8292 #define LLWU_F1_WUF3_MASK 0x8u
8293 #define LLWU_F1_WUF3_SHIFT 3
8294 #define LLWU_F1_WUF4_MASK 0x10u
8295 #define LLWU_F1_WUF4_SHIFT 4
8296 #define LLWU_F1_WUF5_MASK 0x20u
8297 #define LLWU_F1_WUF5_SHIFT 5
8298 #define LLWU_F1_WUF6_MASK 0x40u
8299 #define LLWU_F1_WUF6_SHIFT 6
8300 #define LLWU_F1_WUF7_MASK 0x80u
8301 #define LLWU_F1_WUF7_SHIFT 7
8302 /* F2 Bit Fields */
8303 #define LLWU_F2_WUF8_MASK 0x1u
8304 #define LLWU_F2_WUF8_SHIFT 0
8305 #define LLWU_F2_WUF9_MASK 0x2u
8306 #define LLWU_F2_WUF9_SHIFT 1
8307 #define LLWU_F2_WUF10_MASK 0x4u
8308 #define LLWU_F2_WUF10_SHIFT 2
8309 #define LLWU_F2_WUF11_MASK 0x8u
8310 #define LLWU_F2_WUF11_SHIFT 3
8311 #define LLWU_F2_WUF12_MASK 0x10u
8312 #define LLWU_F2_WUF12_SHIFT 4
8313 #define LLWU_F2_WUF13_MASK 0x20u
8314 #define LLWU_F2_WUF13_SHIFT 5
8315 #define LLWU_F2_WUF14_MASK 0x40u
8316 #define LLWU_F2_WUF14_SHIFT 6
8317 #define LLWU_F2_WUF15_MASK 0x80u
8318 #define LLWU_F2_WUF15_SHIFT 7
8319 /* F3 Bit Fields */
8320 #define LLWU_F3_MWUF0_MASK 0x1u
8321 #define LLWU_F3_MWUF0_SHIFT 0
8322 #define LLWU_F3_MWUF1_MASK 0x2u
8323 #define LLWU_F3_MWUF1_SHIFT 1
8324 #define LLWU_F3_MWUF2_MASK 0x4u
8325 #define LLWU_F3_MWUF2_SHIFT 2
8326 #define LLWU_F3_MWUF3_MASK 0x8u
8327 #define LLWU_F3_MWUF3_SHIFT 3
8328 #define LLWU_F3_MWUF4_MASK 0x10u
8329 #define LLWU_F3_MWUF4_SHIFT 4
8330 #define LLWU_F3_MWUF5_MASK 0x20u
8331 #define LLWU_F3_MWUF5_SHIFT 5
8332 #define LLWU_F3_MWUF6_MASK 0x40u
8333 #define LLWU_F3_MWUF6_SHIFT 6
8334 #define LLWU_F3_MWUF7_MASK 0x80u
8335 #define LLWU_F3_MWUF7_SHIFT 7
8336 /* FILT1 Bit Fields */
8337 #define LLWU_FILT1_FILTSEL_MASK 0xFu
8338 #define LLWU_FILT1_FILTSEL_SHIFT 0
8339 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
8340 #define LLWU_FILT1_FILTE_MASK 0x60u
8341 #define LLWU_FILT1_FILTE_SHIFT 5
8342 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
8343 #define LLWU_FILT1_FILTF_MASK 0x80u
8344 #define LLWU_FILT1_FILTF_SHIFT 7
8345 /* FILT2 Bit Fields */
8346 #define LLWU_FILT2_FILTSEL_MASK 0xFu
8347 #define LLWU_FILT2_FILTSEL_SHIFT 0
8348 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
8349 #define LLWU_FILT2_FILTE_MASK 0x60u
8350 #define LLWU_FILT2_FILTE_SHIFT 5
8351 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
8352 #define LLWU_FILT2_FILTF_MASK 0x80u
8353 #define LLWU_FILT2_FILTF_SHIFT 7
8354 /* RST Bit Fields */
8355 #define LLWU_RST_RSTFILT_MASK 0x1u
8356 #define LLWU_RST_RSTFILT_SHIFT 0
8357 #define LLWU_RST_LLRSTE_MASK 0x2u
8358 #define LLWU_RST_LLRSTE_SHIFT 1
8359
8360 /*!
8361 * @}
8362 */ /* end of group LLWU_Register_Masks */
8363
8364
8365 /* LLWU - Peripheral instance base addresses */
8366 /** Peripheral LLWU base address */
8367 #define LLWU_BASE (0x4007C000u)
8368 /** Peripheral LLWU base pointer */
8369 #define LLWU ((LLWU_Type *)LLWU_BASE)
8370 #define LLWU_BASE_PTR (LLWU)
8371 /** Array initializer of LLWU peripheral base addresses */
8372 #define LLWU_BASE_ADDRS { LLWU_BASE }
8373 /** Array initializer of LLWU peripheral base pointers */
8374 #define LLWU_BASE_PTRS { LLWU }
8375 /** Interrupt vectors for the LLWU peripheral type */
8376 #define LLWU_IRQS { LLW_IRQn }
8377
8378 /* ----------------------------------------------------------------------------
8379 -- LLWU - Register accessor macros
8380 ---------------------------------------------------------------------------- */
8381
8382 /*!
8383 * @addtogroup LLWU_Register_Accessor_Macros LLWU - Register accessor macros
8384 * @{
8385 */
8386
8387
8388 /* LLWU - Register instance definitions */
8389 /* LLWU */
8390 #define LLWU_PE1 LLWU_PE1_REG(LLWU)
8391 #define LLWU_PE2 LLWU_PE2_REG(LLWU)
8392 #define LLWU_PE3 LLWU_PE3_REG(LLWU)
8393 #define LLWU_PE4 LLWU_PE4_REG(LLWU)
8394 #define LLWU_ME LLWU_ME_REG(LLWU)
8395 #define LLWU_F1 LLWU_F1_REG(LLWU)
8396 #define LLWU_F2 LLWU_F2_REG(LLWU)
8397 #define LLWU_F3 LLWU_F3_REG(LLWU)
8398 #define LLWU_FILT1 LLWU_FILT1_REG(LLWU)
8399 #define LLWU_FILT2 LLWU_FILT2_REG(LLWU)
8400 #define LLWU_RST LLWU_RST_REG(LLWU)
8401
8402 /*!
8403 * @}
8404 */ /* end of group LLWU_Register_Accessor_Macros */
8405
8406
8407 /*!
8408 * @}
8409 */ /* end of group LLWU_Peripheral_Access_Layer */
8410
8411
8412 /* ----------------------------------------------------------------------------
8413 -- LPTMR Peripheral Access Layer
8414 ---------------------------------------------------------------------------- */
8415
8416 /*!
8417 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
8418 * @{
8419 */
8420
8421 /** LPTMR - Register Layout Typedef */
8422 typedef struct {
8423 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
8424 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
8425 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
8426 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
8427 } LPTMR_Type, *LPTMR_MemMapPtr;
8428
8429 /* ----------------------------------------------------------------------------
8430 -- LPTMR - Register accessor macros
8431 ---------------------------------------------------------------------------- */
8432
8433 /*!
8434 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
8435 * @{
8436 */
8437
8438
8439 /* LPTMR - Register accessors */
8440 #define LPTMR_CSR_REG(base) ((base)->CSR)
8441 #define LPTMR_PSR_REG(base) ((base)->PSR)
8442 #define LPTMR_CMR_REG(base) ((base)->CMR)
8443 #define LPTMR_CNR_REG(base) ((base)->CNR)
8444
8445 /*!
8446 * @}
8447 */ /* end of group LPTMR_Register_Accessor_Macros */
8448
8449
8450 /* ----------------------------------------------------------------------------
8451 -- LPTMR Register Masks
8452 ---------------------------------------------------------------------------- */
8453
8454 /*!
8455 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
8456 * @{
8457 */
8458
8459 /* CSR Bit Fields */
8460 #define LPTMR_CSR_TEN_MASK 0x1u
8461 #define LPTMR_CSR_TEN_SHIFT 0
8462 #define LPTMR_CSR_TMS_MASK 0x2u
8463 #define LPTMR_CSR_TMS_SHIFT 1
8464 #define LPTMR_CSR_TFC_MASK 0x4u
8465 #define LPTMR_CSR_TFC_SHIFT 2
8466 #define LPTMR_CSR_TPP_MASK 0x8u
8467 #define LPTMR_CSR_TPP_SHIFT 3
8468 #define LPTMR_CSR_TPS_MASK 0x30u
8469 #define LPTMR_CSR_TPS_SHIFT 4
8470 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
8471 #define LPTMR_CSR_TIE_MASK 0x40u
8472 #define LPTMR_CSR_TIE_SHIFT 6
8473 #define LPTMR_CSR_TCF_MASK 0x80u
8474 #define LPTMR_CSR_TCF_SHIFT 7
8475 /* PSR Bit Fields */
8476 #define LPTMR_PSR_PCS_MASK 0x3u
8477 #define LPTMR_PSR_PCS_SHIFT 0
8478 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
8479 #define LPTMR_PSR_PBYP_MASK 0x4u
8480 #define LPTMR_PSR_PBYP_SHIFT 2
8481 #define LPTMR_PSR_PRESCALE_MASK 0x78u
8482 #define LPTMR_PSR_PRESCALE_SHIFT 3
8483 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
8484 /* CMR Bit Fields */
8485 #define LPTMR_CMR_COMPARE_MASK 0xFFFFu
8486 #define LPTMR_CMR_COMPARE_SHIFT 0
8487 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
8488 /* CNR Bit Fields */
8489 #define LPTMR_CNR_COUNTER_MASK 0xFFFFu
8490 #define LPTMR_CNR_COUNTER_SHIFT 0
8491 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
8492
8493 /*!
8494 * @}
8495 */ /* end of group LPTMR_Register_Masks */
8496
8497
8498 /* LPTMR - Peripheral instance base addresses */
8499 /** Peripheral LPTMR0 base address */
8500 #define LPTMR0_BASE (0x40040000u)
8501 /** Peripheral LPTMR0 base pointer */
8502 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
8503 #define LPTMR0_BASE_PTR (LPTMR0)
8504 /** Array initializer of LPTMR peripheral base addresses */
8505 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
8506 /** Array initializer of LPTMR peripheral base pointers */
8507 #define LPTMR_BASE_PTRS { LPTMR0 }
8508 /** Interrupt vectors for the LPTMR peripheral type */
8509 #define LPTMR_IRQS { LPTimer_IRQn }
8510
8511 /* ----------------------------------------------------------------------------
8512 -- LPTMR - Register accessor macros
8513 ---------------------------------------------------------------------------- */
8514
8515 /*!
8516 * @addtogroup LPTMR_Register_Accessor_Macros LPTMR - Register accessor macros
8517 * @{
8518 */
8519
8520
8521 /* LPTMR - Register instance definitions */
8522 /* LPTMR0 */
8523 #define LPTMR0_CSR LPTMR_CSR_REG(LPTMR0)
8524 #define LPTMR0_PSR LPTMR_PSR_REG(LPTMR0)
8525 #define LPTMR0_CMR LPTMR_CMR_REG(LPTMR0)
8526 #define LPTMR0_CNR LPTMR_CNR_REG(LPTMR0)
8527
8528 /*!
8529 * @}
8530 */ /* end of group LPTMR_Register_Accessor_Macros */
8531
8532
8533 /*!
8534 * @}
8535 */ /* end of group LPTMR_Peripheral_Access_Layer */
8536
8537
8538 /* ----------------------------------------------------------------------------
8539 -- MCG Peripheral Access Layer
8540 ---------------------------------------------------------------------------- */
8541
8542 /*!
8543 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
8544 * @{
8545 */
8546
8547 /** MCG - Register Layout Typedef */
8548 typedef struct {
8549 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
8550 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
8551 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
8552 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
8553 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
8554 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
8555 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
8556 uint8_t RESERVED_0[1];
8557 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
8558 uint8_t RESERVED_1[1];
8559 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
8560 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
8561 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
8562 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
8563 } MCG_Type, *MCG_MemMapPtr;
8564
8565 /* ----------------------------------------------------------------------------
8566 -- MCG - Register accessor macros
8567 ---------------------------------------------------------------------------- */
8568
8569 /*!
8570 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
8571 * @{
8572 */
8573
8574
8575 /* MCG - Register accessors */
8576 #define MCG_C1_REG(base) ((base)->C1)
8577 #define MCG_C2_REG(base) ((base)->C2)
8578 #define MCG_C3_REG(base) ((base)->C3)
8579 #define MCG_C4_REG(base) ((base)->C4)
8580 #define MCG_C5_REG(base) ((base)->C5)
8581 #define MCG_C6_REG(base) ((base)->C6)
8582 #define MCG_S_REG(base) ((base)->S)
8583 #define MCG_SC_REG(base) ((base)->SC)
8584 #define MCG_ATCVH_REG(base) ((base)->ATCVH)
8585 #define MCG_ATCVL_REG(base) ((base)->ATCVL)
8586 #define MCG_C7_REG(base) ((base)->C7)
8587 #define MCG_C8_REG(base) ((base)->C8)
8588
8589 /*!
8590 * @}
8591 */ /* end of group MCG_Register_Accessor_Macros */
8592
8593
8594 /* ----------------------------------------------------------------------------
8595 -- MCG Register Masks
8596 ---------------------------------------------------------------------------- */
8597
8598 /*!
8599 * @addtogroup MCG_Register_Masks MCG Register Masks
8600 * @{
8601 */
8602
8603 /* C1 Bit Fields */
8604 #define MCG_C1_IREFSTEN_MASK 0x1u
8605 #define MCG_C1_IREFSTEN_SHIFT 0
8606 #define MCG_C1_IRCLKEN_MASK 0x2u
8607 #define MCG_C1_IRCLKEN_SHIFT 1
8608 #define MCG_C1_IREFS_MASK 0x4u
8609 #define MCG_C1_IREFS_SHIFT 2
8610 #define MCG_C1_FRDIV_MASK 0x38u
8611 #define MCG_C1_FRDIV_SHIFT 3
8612 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
8613 #define MCG_C1_CLKS_MASK 0xC0u
8614 #define MCG_C1_CLKS_SHIFT 6
8615 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
8616 /* C2 Bit Fields */
8617 #define MCG_C2_IRCS_MASK 0x1u
8618 #define MCG_C2_IRCS_SHIFT 0
8619 #define MCG_C2_LP_MASK 0x2u
8620 #define MCG_C2_LP_SHIFT 1
8621 #define MCG_C2_EREFS_MASK 0x4u
8622 #define MCG_C2_EREFS_SHIFT 2
8623 #define MCG_C2_HGO_MASK 0x8u
8624 #define MCG_C2_HGO_SHIFT 3
8625 #define MCG_C2_RANGE_MASK 0x30u
8626 #define MCG_C2_RANGE_SHIFT 4
8627 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE_SHIFT))&MCG_C2_RANGE_MASK)
8628 #define MCG_C2_FCFTRIM_MASK 0x40u
8629 #define MCG_C2_FCFTRIM_SHIFT 6
8630 #define MCG_C2_LOCRE0_MASK 0x80u
8631 #define MCG_C2_LOCRE0_SHIFT 7
8632 /* C3 Bit Fields */
8633 #define MCG_C3_SCTRIM_MASK 0xFFu
8634 #define MCG_C3_SCTRIM_SHIFT 0
8635 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
8636 /* C4 Bit Fields */
8637 #define MCG_C4_SCFTRIM_MASK 0x1u
8638 #define MCG_C4_SCFTRIM_SHIFT 0
8639 #define MCG_C4_FCTRIM_MASK 0x1Eu
8640 #define MCG_C4_FCTRIM_SHIFT 1
8641 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
8642 #define MCG_C4_DRST_DRS_MASK 0x60u
8643 #define MCG_C4_DRST_DRS_SHIFT 5
8644 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
8645 #define MCG_C4_DMX32_MASK 0x80u
8646 #define MCG_C4_DMX32_SHIFT 7
8647 /* C5 Bit Fields */
8648 #define MCG_C5_PRDIV0_MASK 0x1Fu
8649 #define MCG_C5_PRDIV0_SHIFT 0
8650 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
8651 #define MCG_C5_PLLSTEN0_MASK 0x20u
8652 #define MCG_C5_PLLSTEN0_SHIFT 5
8653 #define MCG_C5_PLLCLKEN0_MASK 0x40u
8654 #define MCG_C5_PLLCLKEN0_SHIFT 6
8655 /* C6 Bit Fields */
8656 #define MCG_C6_VDIV0_MASK 0x1Fu
8657 #define MCG_C6_VDIV0_SHIFT 0
8658 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
8659 #define MCG_C6_CME0_MASK 0x20u
8660 #define MCG_C6_CME0_SHIFT 5
8661 #define MCG_C6_PLLS_MASK 0x40u
8662 #define MCG_C6_PLLS_SHIFT 6
8663 #define MCG_C6_LOLIE0_MASK 0x80u
8664 #define MCG_C6_LOLIE0_SHIFT 7
8665 /* S Bit Fields */
8666 #define MCG_S_IRCST_MASK 0x1u
8667 #define MCG_S_IRCST_SHIFT 0
8668 #define MCG_S_OSCINIT0_MASK 0x2u
8669 #define MCG_S_OSCINIT0_SHIFT 1
8670 #define MCG_S_CLKST_MASK 0xCu
8671 #define MCG_S_CLKST_SHIFT 2
8672 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
8673 #define MCG_S_IREFST_MASK 0x10u
8674 #define MCG_S_IREFST_SHIFT 4
8675 #define MCG_S_PLLST_MASK 0x20u
8676 #define MCG_S_PLLST_SHIFT 5
8677 #define MCG_S_LOCK0_MASK 0x40u
8678 #define MCG_S_LOCK0_SHIFT 6
8679 #define MCG_S_LOLS0_MASK 0x80u
8680 #define MCG_S_LOLS0_SHIFT 7
8681 /* SC Bit Fields */
8682 #define MCG_SC_LOCS0_MASK 0x1u
8683 #define MCG_SC_LOCS0_SHIFT 0
8684 #define MCG_SC_FCRDIV_MASK 0xEu
8685 #define MCG_SC_FCRDIV_SHIFT 1
8686 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
8687 #define MCG_SC_FLTPRSRV_MASK 0x10u
8688 #define MCG_SC_FLTPRSRV_SHIFT 4
8689 #define MCG_SC_ATMF_MASK 0x20u
8690 #define MCG_SC_ATMF_SHIFT 5
8691 #define MCG_SC_ATMS_MASK 0x40u
8692 #define MCG_SC_ATMS_SHIFT 6
8693 #define MCG_SC_ATME_MASK 0x80u
8694 #define MCG_SC_ATME_SHIFT 7
8695 /* ATCVH Bit Fields */
8696 #define MCG_ATCVH_ATCVH_MASK 0xFFu
8697 #define MCG_ATCVH_ATCVH_SHIFT 0
8698 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
8699 /* ATCVL Bit Fields */
8700 #define MCG_ATCVL_ATCVL_MASK 0xFFu
8701 #define MCG_ATCVL_ATCVL_SHIFT 0
8702 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
8703 /* C7 Bit Fields */
8704 #define MCG_C7_OSCSEL_MASK 0x3u
8705 #define MCG_C7_OSCSEL_SHIFT 0
8706 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x))<<MCG_C7_OSCSEL_SHIFT))&MCG_C7_OSCSEL_MASK)
8707 /* C8 Bit Fields */
8708 #define MCG_C8_LOCS1_MASK 0x1u
8709 #define MCG_C8_LOCS1_SHIFT 0
8710 #define MCG_C8_CME1_MASK 0x20u
8711 #define MCG_C8_CME1_SHIFT 5
8712 #define MCG_C8_LOLRE_MASK 0x40u
8713 #define MCG_C8_LOLRE_SHIFT 6
8714 #define MCG_C8_LOCRE1_MASK 0x80u
8715 #define MCG_C8_LOCRE1_SHIFT 7
8716
8717 /*!
8718 * @}
8719 */ /* end of group MCG_Register_Masks */
8720
8721
8722 /* MCG - Peripheral instance base addresses */
8723 /** Peripheral MCG base address */
8724 #define MCG_BASE (0x40064000u)
8725 /** Peripheral MCG base pointer */
8726 #define MCG ((MCG_Type *)MCG_BASE)
8727 #define MCG_BASE_PTR (MCG)
8728 /** Array initializer of MCG peripheral base addresses */
8729 #define MCG_BASE_ADDRS { MCG_BASE }
8730 /** Array initializer of MCG peripheral base pointers */
8731 #define MCG_BASE_PTRS { MCG }
8732
8733 /* ----------------------------------------------------------------------------
8734 -- MCG - Register accessor macros
8735 ---------------------------------------------------------------------------- */
8736
8737 /*!
8738 * @addtogroup MCG_Register_Accessor_Macros MCG - Register accessor macros
8739 * @{
8740 */
8741
8742
8743 /* MCG - Register instance definitions */
8744 /* MCG */
8745 #define MCG_C1 MCG_C1_REG(MCG)
8746 #define MCG_C2 MCG_C2_REG(MCG)
8747 #define MCG_C3 MCG_C3_REG(MCG)
8748 #define MCG_C4 MCG_C4_REG(MCG)
8749 #define MCG_C5 MCG_C5_REG(MCG)
8750 #define MCG_C6 MCG_C6_REG(MCG)
8751 #define MCG_S MCG_S_REG(MCG)
8752 #define MCG_SC MCG_SC_REG(MCG)
8753 #define MCG_ATCVH MCG_ATCVH_REG(MCG)
8754 #define MCG_ATCVL MCG_ATCVL_REG(MCG)
8755 #define MCG_C7 MCG_C7_REG(MCG)
8756 #define MCG_C8 MCG_C8_REG(MCG)
8757
8758 /*!
8759 * @}
8760 */ /* end of group MCG_Register_Accessor_Macros */
8761
8762
8763 /*!
8764 * @}
8765 */ /* end of group MCG_Peripheral_Access_Layer */
8766
8767
8768 /* ----------------------------------------------------------------------------
8769 -- MCM Peripheral Access Layer
8770 ---------------------------------------------------------------------------- */
8771
8772 /*!
8773 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
8774 * @{
8775 */
8776
8777 /** MCM - Register Layout Typedef */
8778 typedef struct {
8779 uint8_t RESERVED_0[8];
8780 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
8781 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
8782 __IO uint32_t CR; /**< Control Register, offset: 0xC */
8783 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
8784 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
8785 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
8786 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
8787 uint8_t RESERVED_1[16];
8788 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
8789 } MCM_Type, *MCM_MemMapPtr;
8790
8791 /* ----------------------------------------------------------------------------
8792 -- MCM - Register accessor macros
8793 ---------------------------------------------------------------------------- */
8794
8795 /*!
8796 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
8797 * @{
8798 */
8799
8800
8801 /* MCM - Register accessors */
8802 #define MCM_PLASC_REG(base) ((base)->PLASC)
8803 #define MCM_PLAMC_REG(base) ((base)->PLAMC)
8804 #define MCM_CR_REG(base) ((base)->CR)
8805 #define MCM_ISCR_REG(base) ((base)->ISCR)
8806 #define MCM_ETBCC_REG(base) ((base)->ETBCC)
8807 #define MCM_ETBRL_REG(base) ((base)->ETBRL)
8808 #define MCM_ETBCNT_REG(base) ((base)->ETBCNT)
8809 #define MCM_PID_REG(base) ((base)->PID)
8810
8811 /*!
8812 * @}
8813 */ /* end of group MCM_Register_Accessor_Macros */
8814
8815
8816 /* ----------------------------------------------------------------------------
8817 -- MCM Register Masks
8818 ---------------------------------------------------------------------------- */
8819
8820 /*!
8821 * @addtogroup MCM_Register_Masks MCM Register Masks
8822 * @{
8823 */
8824
8825 /* PLASC Bit Fields */
8826 #define MCM_PLASC_ASC_MASK 0xFFu
8827 #define MCM_PLASC_ASC_SHIFT 0
8828 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
8829 /* PLAMC Bit Fields */
8830 #define MCM_PLAMC_AMC_MASK 0xFFu
8831 #define MCM_PLAMC_AMC_SHIFT 0
8832 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
8833 /* CR Bit Fields */
8834 #define MCM_CR_SRAMUAP_MASK 0x3000000u
8835 #define MCM_CR_SRAMUAP_SHIFT 24
8836 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMUAP_SHIFT))&MCM_CR_SRAMUAP_MASK)
8837 #define MCM_CR_SRAMUWP_MASK 0x4000000u
8838 #define MCM_CR_SRAMUWP_SHIFT 26
8839 #define MCM_CR_SRAMLAP_MASK 0x30000000u
8840 #define MCM_CR_SRAMLAP_SHIFT 28
8841 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x))<<MCM_CR_SRAMLAP_SHIFT))&MCM_CR_SRAMLAP_MASK)
8842 #define MCM_CR_SRAMLWP_MASK 0x40000000u
8843 #define MCM_CR_SRAMLWP_SHIFT 30
8844 /* ISCR Bit Fields */
8845 #define MCM_ISCR_IRQ_MASK 0x2u
8846 #define MCM_ISCR_IRQ_SHIFT 1
8847 #define MCM_ISCR_NMI_MASK 0x4u
8848 #define MCM_ISCR_NMI_SHIFT 2
8849 #define MCM_ISCR_DHREQ_MASK 0x8u
8850 #define MCM_ISCR_DHREQ_SHIFT 3
8851 #define MCM_ISCR_FIOC_MASK 0x100u
8852 #define MCM_ISCR_FIOC_SHIFT 8
8853 #define MCM_ISCR_FDZC_MASK 0x200u
8854 #define MCM_ISCR_FDZC_SHIFT 9
8855 #define MCM_ISCR_FOFC_MASK 0x400u
8856 #define MCM_ISCR_FOFC_SHIFT 10
8857 #define MCM_ISCR_FUFC_MASK 0x800u
8858 #define MCM_ISCR_FUFC_SHIFT 11
8859 #define MCM_ISCR_FIXC_MASK 0x1000u
8860 #define MCM_ISCR_FIXC_SHIFT 12
8861 #define MCM_ISCR_FIDC_MASK 0x8000u
8862 #define MCM_ISCR_FIDC_SHIFT 15
8863 #define MCM_ISCR_FIOCE_MASK 0x1000000u
8864 #define MCM_ISCR_FIOCE_SHIFT 24
8865 #define MCM_ISCR_FDZCE_MASK 0x2000000u
8866 #define MCM_ISCR_FDZCE_SHIFT 25
8867 #define MCM_ISCR_FOFCE_MASK 0x4000000u
8868 #define MCM_ISCR_FOFCE_SHIFT 26
8869 #define MCM_ISCR_FUFCE_MASK 0x8000000u
8870 #define MCM_ISCR_FUFCE_SHIFT 27
8871 #define MCM_ISCR_FIXCE_MASK 0x10000000u
8872 #define MCM_ISCR_FIXCE_SHIFT 28
8873 #define MCM_ISCR_FIDCE_MASK 0x80000000u
8874 #define MCM_ISCR_FIDCE_SHIFT 31
8875 /* ETBCC Bit Fields */
8876 #define MCM_ETBCC_CNTEN_MASK 0x1u
8877 #define MCM_ETBCC_CNTEN_SHIFT 0
8878 #define MCM_ETBCC_RSPT_MASK 0x6u
8879 #define MCM_ETBCC_RSPT_SHIFT 1
8880 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCC_RSPT_SHIFT))&MCM_ETBCC_RSPT_MASK)
8881 #define MCM_ETBCC_RLRQ_MASK 0x8u
8882 #define MCM_ETBCC_RLRQ_SHIFT 3
8883 #define MCM_ETBCC_ETDIS_MASK 0x10u
8884 #define MCM_ETBCC_ETDIS_SHIFT 4
8885 #define MCM_ETBCC_ITDIS_MASK 0x20u
8886 #define MCM_ETBCC_ITDIS_SHIFT 5
8887 /* ETBRL Bit Fields */
8888 #define MCM_ETBRL_RELOAD_MASK 0x7FFu
8889 #define MCM_ETBRL_RELOAD_SHIFT 0
8890 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBRL_RELOAD_SHIFT))&MCM_ETBRL_RELOAD_MASK)
8891 /* ETBCNT Bit Fields */
8892 #define MCM_ETBCNT_COUNTER_MASK 0x7FFu
8893 #define MCM_ETBCNT_COUNTER_SHIFT 0
8894 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<MCM_ETBCNT_COUNTER_SHIFT))&MCM_ETBCNT_COUNTER_MASK)
8895 /* PID Bit Fields */
8896 #define MCM_PID_PID_MASK 0xFFu
8897 #define MCM_PID_PID_SHIFT 0
8898 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x))<<MCM_PID_PID_SHIFT))&MCM_PID_PID_MASK)
8899
8900 /*!
8901 * @}
8902 */ /* end of group MCM_Register_Masks */
8903
8904
8905 /* MCM - Peripheral instance base addresses */
8906 /** Peripheral MCM base address */
8907 #define MCM_BASE (0xE0080000u)
8908 /** Peripheral MCM base pointer */
8909 #define MCM ((MCM_Type *)MCM_BASE)
8910 #define MCM_BASE_PTR (MCM)
8911 /** Array initializer of MCM peripheral base addresses */
8912 #define MCM_BASE_ADDRS { MCM_BASE }
8913 /** Array initializer of MCM peripheral base pointers */
8914 #define MCM_BASE_PTRS { MCM }
8915
8916 /* ----------------------------------------------------------------------------
8917 -- MCM - Register accessor macros
8918 ---------------------------------------------------------------------------- */
8919
8920 /*!
8921 * @addtogroup MCM_Register_Accessor_Macros MCM - Register accessor macros
8922 * @{
8923 */
8924
8925
8926 /* MCM - Register instance definitions */
8927 /* MCM */
8928 #define MCM_PLASC MCM_PLASC_REG(MCM)
8929 #define MCM_PLAMC MCM_PLAMC_REG(MCM)
8930 #define MCM_CR MCM_CR_REG(MCM)
8931 #define MCM_ISCR MCM_ISCR_REG(MCM)
8932 #define MCM_ETBCC MCM_ETBCC_REG(MCM)
8933 #define MCM_ETBRL MCM_ETBRL_REG(MCM)
8934 #define MCM_ETBCNT MCM_ETBCNT_REG(MCM)
8935 #define MCM_PID MCM_PID_REG(MCM)
8936
8937 /*!
8938 * @}
8939 */ /* end of group MCM_Register_Accessor_Macros */
8940
8941
8942 /*!
8943 * @}
8944 */ /* end of group MCM_Peripheral_Access_Layer */
8945
8946
8947 /* ----------------------------------------------------------------------------
8948 -- MPU Peripheral Access Layer
8949 ---------------------------------------------------------------------------- */
8950
8951 /*!
8952 * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
8953 * @{
8954 */
8955
8956 /** MPU - Register Layout Typedef */
8957 typedef struct {
8958 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
8959 uint8_t RESERVED_0[12];
8960 struct { /* offset: 0x10, array step: 0x8 */
8961 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
8962 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
8963 } SP[5];
8964 uint8_t RESERVED_1[968];
8965 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
8966 uint8_t RESERVED_2[832];
8967 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
8968 } MPU_Type, *MPU_MemMapPtr;
8969
8970 /* ----------------------------------------------------------------------------
8971 -- MPU - Register accessor macros
8972 ---------------------------------------------------------------------------- */
8973
8974 /*!
8975 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
8976 * @{
8977 */
8978
8979
8980 /* MPU - Register accessors */
8981 #define MPU_CESR_REG(base) ((base)->CESR)
8982 #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR)
8983 #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR)
8984 #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2])
8985 #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index])
8986
8987 /*!
8988 * @}
8989 */ /* end of group MPU_Register_Accessor_Macros */
8990
8991
8992 /* ----------------------------------------------------------------------------
8993 -- MPU Register Masks
8994 ---------------------------------------------------------------------------- */
8995
8996 /*!
8997 * @addtogroup MPU_Register_Masks MPU Register Masks
8998 * @{
8999 */
9000
9001 /* CESR Bit Fields */
9002 #define MPU_CESR_VLD_MASK 0x1u
9003 #define MPU_CESR_VLD_SHIFT 0
9004 #define MPU_CESR_NRGD_MASK 0xF00u
9005 #define MPU_CESR_NRGD_SHIFT 8
9006 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NRGD_SHIFT))&MPU_CESR_NRGD_MASK)
9007 #define MPU_CESR_NSP_MASK 0xF000u
9008 #define MPU_CESR_NSP_SHIFT 12
9009 #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_NSP_SHIFT))&MPU_CESR_NSP_MASK)
9010 #define MPU_CESR_HRL_MASK 0xF0000u
9011 #define MPU_CESR_HRL_SHIFT 16
9012 #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_HRL_SHIFT))&MPU_CESR_HRL_MASK)
9013 #define MPU_CESR_SPERR_MASK 0xF8000000u
9014 #define MPU_CESR_SPERR_SHIFT 27
9015 #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x))<<MPU_CESR_SPERR_SHIFT))&MPU_CESR_SPERR_MASK)
9016 /* EAR Bit Fields */
9017 #define MPU_EAR_EADDR_MASK 0xFFFFFFFFu
9018 #define MPU_EAR_EADDR_SHIFT 0
9019 #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EAR_EADDR_SHIFT))&MPU_EAR_EADDR_MASK)
9020 /* EDR Bit Fields */
9021 #define MPU_EDR_ERW_MASK 0x1u
9022 #define MPU_EDR_ERW_SHIFT 0
9023 #define MPU_EDR_EATTR_MASK 0xEu
9024 #define MPU_EDR_EATTR_SHIFT 1
9025 #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EATTR_SHIFT))&MPU_EDR_EATTR_MASK)
9026 #define MPU_EDR_EMN_MASK 0xF0u
9027 #define MPU_EDR_EMN_SHIFT 4
9028 #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EMN_SHIFT))&MPU_EDR_EMN_MASK)
9029 #define MPU_EDR_EPID_MASK 0xFF00u
9030 #define MPU_EDR_EPID_SHIFT 8
9031 #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EPID_SHIFT))&MPU_EDR_EPID_MASK)
9032 #define MPU_EDR_EACD_MASK 0xFFFF0000u
9033 #define MPU_EDR_EACD_SHIFT 16
9034 #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x))<<MPU_EDR_EACD_SHIFT))&MPU_EDR_EACD_MASK)
9035 /* WORD Bit Fields */
9036 #define MPU_WORD_VLD_MASK 0x1u
9037 #define MPU_WORD_VLD_SHIFT 0
9038 #define MPU_WORD_M0UM_MASK 0x7u
9039 #define MPU_WORD_M0UM_SHIFT 0
9040 #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0UM_SHIFT))&MPU_WORD_M0UM_MASK)
9041 #define MPU_WORD_M0SM_MASK 0x18u
9042 #define MPU_WORD_M0SM_SHIFT 3
9043 #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M0SM_SHIFT))&MPU_WORD_M0SM_MASK)
9044 #define MPU_WORD_M0PE_MASK 0x20u
9045 #define MPU_WORD_M0PE_SHIFT 5
9046 #define MPU_WORD_ENDADDR_MASK 0xFFFFFFE0u
9047 #define MPU_WORD_ENDADDR_SHIFT 5
9048 #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_ENDADDR_SHIFT))&MPU_WORD_ENDADDR_MASK)
9049 #define MPU_WORD_SRTADDR_MASK 0xFFFFFFE0u
9050 #define MPU_WORD_SRTADDR_SHIFT 5
9051 #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_SRTADDR_SHIFT))&MPU_WORD_SRTADDR_MASK)
9052 #define MPU_WORD_M1UM_MASK 0x1C0u
9053 #define MPU_WORD_M1UM_SHIFT 6
9054 #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1UM_SHIFT))&MPU_WORD_M1UM_MASK)
9055 #define MPU_WORD_M1SM_MASK 0x600u
9056 #define MPU_WORD_M1SM_SHIFT 9
9057 #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M1SM_SHIFT))&MPU_WORD_M1SM_MASK)
9058 #define MPU_WORD_M1PE_MASK 0x800u
9059 #define MPU_WORD_M1PE_SHIFT 11
9060 #define MPU_WORD_M2UM_MASK 0x7000u
9061 #define MPU_WORD_M2UM_SHIFT 12
9062 #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2UM_SHIFT))&MPU_WORD_M2UM_MASK)
9063 #define MPU_WORD_M2SM_MASK 0x18000u
9064 #define MPU_WORD_M2SM_SHIFT 15
9065 #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M2SM_SHIFT))&MPU_WORD_M2SM_MASK)
9066 #define MPU_WORD_PIDMASK_MASK 0xFF0000u
9067 #define MPU_WORD_PIDMASK_SHIFT 16
9068 #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PIDMASK_SHIFT))&MPU_WORD_PIDMASK_MASK)
9069 #define MPU_WORD_M2PE_MASK 0x20000u
9070 #define MPU_WORD_M2PE_SHIFT 17
9071 #define MPU_WORD_M3UM_MASK 0x1C0000u
9072 #define MPU_WORD_M3UM_SHIFT 18
9073 #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3UM_SHIFT))&MPU_WORD_M3UM_MASK)
9074 #define MPU_WORD_M3SM_MASK 0x600000u
9075 #define MPU_WORD_M3SM_SHIFT 21
9076 #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_M3SM_SHIFT))&MPU_WORD_M3SM_MASK)
9077 #define MPU_WORD_M3PE_MASK 0x800000u
9078 #define MPU_WORD_M3PE_SHIFT 23
9079 #define MPU_WORD_PID_MASK 0xFF000000u
9080 #define MPU_WORD_PID_SHIFT 24
9081 #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x))<<MPU_WORD_PID_SHIFT))&MPU_WORD_PID_MASK)
9082 #define MPU_WORD_M4WE_MASK 0x1000000u
9083 #define MPU_WORD_M4WE_SHIFT 24
9084 #define MPU_WORD_M4RE_MASK 0x2000000u
9085 #define MPU_WORD_M4RE_SHIFT 25
9086 #define MPU_WORD_M5WE_MASK 0x4000000u
9087 #define MPU_WORD_M5WE_SHIFT 26
9088 #define MPU_WORD_M5RE_MASK 0x8000000u
9089 #define MPU_WORD_M5RE_SHIFT 27
9090 #define MPU_WORD_M6WE_MASK 0x10000000u
9091 #define MPU_WORD_M6WE_SHIFT 28
9092 #define MPU_WORD_M6RE_MASK 0x20000000u
9093 #define MPU_WORD_M6RE_SHIFT 29
9094 #define MPU_WORD_M7WE_MASK 0x40000000u
9095 #define MPU_WORD_M7WE_SHIFT 30
9096 #define MPU_WORD_M7RE_MASK 0x80000000u
9097 #define MPU_WORD_M7RE_SHIFT 31
9098 /* RGDAAC Bit Fields */
9099 #define MPU_RGDAAC_M0UM_MASK 0x7u
9100 #define MPU_RGDAAC_M0UM_SHIFT 0
9101 #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0UM_SHIFT))&MPU_RGDAAC_M0UM_MASK)
9102 #define MPU_RGDAAC_M0SM_MASK 0x18u
9103 #define MPU_RGDAAC_M0SM_SHIFT 3
9104 #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M0SM_SHIFT))&MPU_RGDAAC_M0SM_MASK)
9105 #define MPU_RGDAAC_M0PE_MASK 0x20u
9106 #define MPU_RGDAAC_M0PE_SHIFT 5
9107 #define MPU_RGDAAC_M1UM_MASK 0x1C0u
9108 #define MPU_RGDAAC_M1UM_SHIFT 6
9109 #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1UM_SHIFT))&MPU_RGDAAC_M1UM_MASK)
9110 #define MPU_RGDAAC_M1SM_MASK 0x600u
9111 #define MPU_RGDAAC_M1SM_SHIFT 9
9112 #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M1SM_SHIFT))&MPU_RGDAAC_M1SM_MASK)
9113 #define MPU_RGDAAC_M1PE_MASK 0x800u
9114 #define MPU_RGDAAC_M1PE_SHIFT 11
9115 #define MPU_RGDAAC_M2UM_MASK 0x7000u
9116 #define MPU_RGDAAC_M2UM_SHIFT 12
9117 #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2UM_SHIFT))&MPU_RGDAAC_M2UM_MASK)
9118 #define MPU_RGDAAC_M2SM_MASK 0x18000u
9119 #define MPU_RGDAAC_M2SM_SHIFT 15
9120 #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M2SM_SHIFT))&MPU_RGDAAC_M2SM_MASK)
9121 #define MPU_RGDAAC_M2PE_MASK 0x20000u
9122 #define MPU_RGDAAC_M2PE_SHIFT 17
9123 #define MPU_RGDAAC_M3UM_MASK 0x1C0000u
9124 #define MPU_RGDAAC_M3UM_SHIFT 18
9125 #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3UM_SHIFT))&MPU_RGDAAC_M3UM_MASK)
9126 #define MPU_RGDAAC_M3SM_MASK 0x600000u
9127 #define MPU_RGDAAC_M3SM_SHIFT 21
9128 #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x))<<MPU_RGDAAC_M3SM_SHIFT))&MPU_RGDAAC_M3SM_MASK)
9129 #define MPU_RGDAAC_M3PE_MASK 0x800000u
9130 #define MPU_RGDAAC_M3PE_SHIFT 23
9131 #define MPU_RGDAAC_M4WE_MASK 0x1000000u
9132 #define MPU_RGDAAC_M4WE_SHIFT 24
9133 #define MPU_RGDAAC_M4RE_MASK 0x2000000u
9134 #define MPU_RGDAAC_M4RE_SHIFT 25
9135 #define MPU_RGDAAC_M5WE_MASK 0x4000000u
9136 #define MPU_RGDAAC_M5WE_SHIFT 26
9137 #define MPU_RGDAAC_M5RE_MASK 0x8000000u
9138 #define MPU_RGDAAC_M5RE_SHIFT 27
9139 #define MPU_RGDAAC_M6WE_MASK 0x10000000u
9140 #define MPU_RGDAAC_M6WE_SHIFT 28
9141 #define MPU_RGDAAC_M6RE_MASK 0x20000000u
9142 #define MPU_RGDAAC_M6RE_SHIFT 29
9143 #define MPU_RGDAAC_M7WE_MASK 0x40000000u
9144 #define MPU_RGDAAC_M7WE_SHIFT 30
9145 #define MPU_RGDAAC_M7RE_MASK 0x80000000u
9146 #define MPU_RGDAAC_M7RE_SHIFT 31
9147
9148 /*!
9149 * @}
9150 */ /* end of group MPU_Register_Masks */
9151
9152
9153 /* MPU - Peripheral instance base addresses */
9154 /** Peripheral MPU base address */
9155 #define MPU_BASE (0x4000D000u)
9156 /** Peripheral MPU base pointer */
9157 #define MPU ((MPU_Type *)MPU_BASE)
9158 #define MPU_BASE_PTR (MPU)
9159 /** Array initializer of MPU peripheral base addresses */
9160 #define MPU_BASE_ADDRS { MPU_BASE }
9161 /** Array initializer of MPU peripheral base pointers */
9162 #define MPU_BASE_PTRS { MPU }
9163
9164 /* ----------------------------------------------------------------------------
9165 -- MPU - Register accessor macros
9166 ---------------------------------------------------------------------------- */
9167
9168 /*!
9169 * @addtogroup MPU_Register_Accessor_Macros MPU - Register accessor macros
9170 * @{
9171 */
9172
9173
9174 /* MPU - Register instance definitions */
9175 /* MPU */
9176 #define MPU_CESR MPU_CESR_REG(MPU)
9177 #define MPU_EAR0 MPU_EAR_REG(MPU,0)
9178 #define MPU_EDR0 MPU_EDR_REG(MPU,0)
9179 #define MPU_EAR1 MPU_EAR_REG(MPU,1)
9180 #define MPU_EDR1 MPU_EDR_REG(MPU,1)
9181 #define MPU_EAR2 MPU_EAR_REG(MPU,2)
9182 #define MPU_EDR2 MPU_EDR_REG(MPU,2)
9183 #define MPU_EAR3 MPU_EAR_REG(MPU,3)
9184 #define MPU_EDR3 MPU_EDR_REG(MPU,3)
9185 #define MPU_EAR4 MPU_EAR_REG(MPU,4)
9186 #define MPU_EDR4 MPU_EDR_REG(MPU,4)
9187 #define MPU_RGD0_WORD0 MPU_WORD_REG(MPU,0,0)
9188 #define MPU_RGD0_WORD1 MPU_WORD_REG(MPU,0,1)
9189 #define MPU_RGD0_WORD2 MPU_WORD_REG(MPU,0,2)
9190 #define MPU_RGD0_WORD3 MPU_WORD_REG(MPU,0,3)
9191 #define MPU_RGD1_WORD0 MPU_WORD_REG(MPU,1,0)
9192 #define MPU_RGD1_WORD1 MPU_WORD_REG(MPU,1,1)
9193 #define MPU_RGD1_WORD2 MPU_WORD_REG(MPU,1,2)
9194 #define MPU_RGD1_WORD3 MPU_WORD_REG(MPU,1,3)
9195 #define MPU_RGD2_WORD0 MPU_WORD_REG(MPU,2,0)
9196 #define MPU_RGD2_WORD1 MPU_WORD_REG(MPU,2,1)
9197 #define MPU_RGD2_WORD2 MPU_WORD_REG(MPU,2,2)
9198 #define MPU_RGD2_WORD3 MPU_WORD_REG(MPU,2,3)
9199 #define MPU_RGD3_WORD0 MPU_WORD_REG(MPU,3,0)
9200 #define MPU_RGD3_WORD1 MPU_WORD_REG(MPU,3,1)
9201 #define MPU_RGD3_WORD2 MPU_WORD_REG(MPU,3,2)
9202 #define MPU_RGD3_WORD3 MPU_WORD_REG(MPU,3,3)
9203 #define MPU_RGD4_WORD0 MPU_WORD_REG(MPU,4,0)
9204 #define MPU_RGD4_WORD1 MPU_WORD_REG(MPU,4,1)
9205 #define MPU_RGD4_WORD2 MPU_WORD_REG(MPU,4,2)
9206 #define MPU_RGD4_WORD3 MPU_WORD_REG(MPU,4,3)
9207 #define MPU_RGD5_WORD0 MPU_WORD_REG(MPU,5,0)
9208 #define MPU_RGD5_WORD1 MPU_WORD_REG(MPU,5,1)
9209 #define MPU_RGD5_WORD2 MPU_WORD_REG(MPU,5,2)
9210 #define MPU_RGD5_WORD3 MPU_WORD_REG(MPU,5,3)
9211 #define MPU_RGD6_WORD0 MPU_WORD_REG(MPU,6,0)
9212 #define MPU_RGD6_WORD1 MPU_WORD_REG(MPU,6,1)
9213 #define MPU_RGD6_WORD2 MPU_WORD_REG(MPU,6,2)
9214 #define MPU_RGD6_WORD3 MPU_WORD_REG(MPU,6,3)
9215 #define MPU_RGD7_WORD0 MPU_WORD_REG(MPU,7,0)
9216 #define MPU_RGD7_WORD1 MPU_WORD_REG(MPU,7,1)
9217 #define MPU_RGD7_WORD2 MPU_WORD_REG(MPU,7,2)
9218 #define MPU_RGD7_WORD3 MPU_WORD_REG(MPU,7,3)
9219 #define MPU_RGD8_WORD0 MPU_WORD_REG(MPU,8,0)
9220 #define MPU_RGD8_WORD1 MPU_WORD_REG(MPU,8,1)
9221 #define MPU_RGD8_WORD2 MPU_WORD_REG(MPU,8,2)
9222 #define MPU_RGD8_WORD3 MPU_WORD_REG(MPU,8,3)
9223 #define MPU_RGD9_WORD0 MPU_WORD_REG(MPU,9,0)
9224 #define MPU_RGD9_WORD1 MPU_WORD_REG(MPU,9,1)
9225 #define MPU_RGD9_WORD2 MPU_WORD_REG(MPU,9,2)
9226 #define MPU_RGD9_WORD3 MPU_WORD_REG(MPU,9,3)
9227 #define MPU_RGD10_WORD0 MPU_WORD_REG(MPU,10,0)
9228 #define MPU_RGD10_WORD1 MPU_WORD_REG(MPU,10,1)
9229 #define MPU_RGD10_WORD2 MPU_WORD_REG(MPU,10,2)
9230 #define MPU_RGD10_WORD3 MPU_WORD_REG(MPU,10,3)
9231 #define MPU_RGD11_WORD0 MPU_WORD_REG(MPU,11,0)
9232 #define MPU_RGD11_WORD1 MPU_WORD_REG(MPU,11,1)
9233 #define MPU_RGD11_WORD2 MPU_WORD_REG(MPU,11,2)
9234 #define MPU_RGD11_WORD3 MPU_WORD_REG(MPU,11,3)
9235 #define MPU_RGDAAC0 MPU_RGDAAC_REG(MPU,0)
9236 #define MPU_RGDAAC1 MPU_RGDAAC_REG(MPU,1)
9237 #define MPU_RGDAAC2 MPU_RGDAAC_REG(MPU,2)
9238 #define MPU_RGDAAC3 MPU_RGDAAC_REG(MPU,3)
9239 #define MPU_RGDAAC4 MPU_RGDAAC_REG(MPU,4)
9240 #define MPU_RGDAAC5 MPU_RGDAAC_REG(MPU,5)
9241 #define MPU_RGDAAC6 MPU_RGDAAC_REG(MPU,6)
9242 #define MPU_RGDAAC7 MPU_RGDAAC_REG(MPU,7)
9243 #define MPU_RGDAAC8 MPU_RGDAAC_REG(MPU,8)
9244 #define MPU_RGDAAC9 MPU_RGDAAC_REG(MPU,9)
9245 #define MPU_RGDAAC10 MPU_RGDAAC_REG(MPU,10)
9246 #define MPU_RGDAAC11 MPU_RGDAAC_REG(MPU,11)
9247
9248 /* MPU - Register array accessors */
9249 #define MPU_EAR(index) MPU_EAR_REG(MPU,index)
9250 #define MPU_EDR(index) MPU_EDR_REG(MPU,index)
9251 #define MPU_WORD(index,index2) MPU_WORD_REG(MPU,index,index2)
9252 #define MPU_RGDAAC(index) MPU_RGDAAC_REG(MPU,index)
9253
9254 /*!
9255 * @}
9256 */ /* end of group MPU_Register_Accessor_Macros */
9257
9258
9259 /*!
9260 * @}
9261 */ /* end of group MPU_Peripheral_Access_Layer */
9262
9263
9264 /* ----------------------------------------------------------------------------
9265 -- NV Peripheral Access Layer
9266 ---------------------------------------------------------------------------- */
9267
9268 /*!
9269 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
9270 * @{
9271 */
9272
9273 /** NV - Register Layout Typedef */
9274 typedef struct {
9275 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
9276 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
9277 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
9278 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
9279 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
9280 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
9281 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
9282 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
9283 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
9284 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
9285 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
9286 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
9287 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
9288 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
9289 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
9290 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
9291 } NV_Type, *NV_MemMapPtr;
9292
9293 /* ----------------------------------------------------------------------------
9294 -- NV - Register accessor macros
9295 ---------------------------------------------------------------------------- */
9296
9297 /*!
9298 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
9299 * @{
9300 */
9301
9302
9303 /* NV - Register accessors */
9304 #define NV_BACKKEY3_REG(base) ((base)->BACKKEY3)
9305 #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2)
9306 #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1)
9307 #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0)
9308 #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7)
9309 #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6)
9310 #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5)
9311 #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4)
9312 #define NV_FPROT3_REG(base) ((base)->FPROT3)
9313 #define NV_FPROT2_REG(base) ((base)->FPROT2)
9314 #define NV_FPROT1_REG(base) ((base)->FPROT1)
9315 #define NV_FPROT0_REG(base) ((base)->FPROT0)
9316 #define NV_FSEC_REG(base) ((base)->FSEC)
9317 #define NV_FOPT_REG(base) ((base)->FOPT)
9318 #define NV_FEPROT_REG(base) ((base)->FEPROT)
9319 #define NV_FDPROT_REG(base) ((base)->FDPROT)
9320
9321 /*!
9322 * @}
9323 */ /* end of group NV_Register_Accessor_Macros */
9324
9325
9326 /* ----------------------------------------------------------------------------
9327 -- NV Register Masks
9328 ---------------------------------------------------------------------------- */
9329
9330 /*!
9331 * @addtogroup NV_Register_Masks NV Register Masks
9332 * @{
9333 */
9334
9335 /* BACKKEY3 Bit Fields */
9336 #define NV_BACKKEY3_KEY_MASK 0xFFu
9337 #define NV_BACKKEY3_KEY_SHIFT 0
9338 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
9339 /* BACKKEY2 Bit Fields */
9340 #define NV_BACKKEY2_KEY_MASK 0xFFu
9341 #define NV_BACKKEY2_KEY_SHIFT 0
9342 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
9343 /* BACKKEY1 Bit Fields */
9344 #define NV_BACKKEY1_KEY_MASK 0xFFu
9345 #define NV_BACKKEY1_KEY_SHIFT 0
9346 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
9347 /* BACKKEY0 Bit Fields */
9348 #define NV_BACKKEY0_KEY_MASK 0xFFu
9349 #define NV_BACKKEY0_KEY_SHIFT 0
9350 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
9351 /* BACKKEY7 Bit Fields */
9352 #define NV_BACKKEY7_KEY_MASK 0xFFu
9353 #define NV_BACKKEY7_KEY_SHIFT 0
9354 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
9355 /* BACKKEY6 Bit Fields */
9356 #define NV_BACKKEY6_KEY_MASK 0xFFu
9357 #define NV_BACKKEY6_KEY_SHIFT 0
9358 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
9359 /* BACKKEY5 Bit Fields */
9360 #define NV_BACKKEY5_KEY_MASK 0xFFu
9361 #define NV_BACKKEY5_KEY_SHIFT 0
9362 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
9363 /* BACKKEY4 Bit Fields */
9364 #define NV_BACKKEY4_KEY_MASK 0xFFu
9365 #define NV_BACKKEY4_KEY_SHIFT 0
9366 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
9367 /* FPROT3 Bit Fields */
9368 #define NV_FPROT3_PROT_MASK 0xFFu
9369 #define NV_FPROT3_PROT_SHIFT 0
9370 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
9371 /* FPROT2 Bit Fields */
9372 #define NV_FPROT2_PROT_MASK 0xFFu
9373 #define NV_FPROT2_PROT_SHIFT 0
9374 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
9375 /* FPROT1 Bit Fields */
9376 #define NV_FPROT1_PROT_MASK 0xFFu
9377 #define NV_FPROT1_PROT_SHIFT 0
9378 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
9379 /* FPROT0 Bit Fields */
9380 #define NV_FPROT0_PROT_MASK 0xFFu
9381 #define NV_FPROT0_PROT_SHIFT 0
9382 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
9383 /* FSEC Bit Fields */
9384 #define NV_FSEC_SEC_MASK 0x3u
9385 #define NV_FSEC_SEC_SHIFT 0
9386 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
9387 #define NV_FSEC_FSLACC_MASK 0xCu
9388 #define NV_FSEC_FSLACC_SHIFT 2
9389 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
9390 #define NV_FSEC_MEEN_MASK 0x30u
9391 #define NV_FSEC_MEEN_SHIFT 4
9392 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
9393 #define NV_FSEC_KEYEN_MASK 0xC0u
9394 #define NV_FSEC_KEYEN_SHIFT 6
9395 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
9396 /* FOPT Bit Fields */
9397 #define NV_FOPT_LPBOOT_MASK 0x1u
9398 #define NV_FOPT_LPBOOT_SHIFT 0
9399 #define NV_FOPT_EZPORT_DIS_MASK 0x2u
9400 #define NV_FOPT_EZPORT_DIS_SHIFT 1
9401 /* FEPROT Bit Fields */
9402 #define NV_FEPROT_EPROT_MASK 0xFFu
9403 #define NV_FEPROT_EPROT_SHIFT 0
9404 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FEPROT_EPROT_SHIFT))&NV_FEPROT_EPROT_MASK)
9405 /* FDPROT Bit Fields */
9406 #define NV_FDPROT_DPROT_MASK 0xFFu
9407 #define NV_FDPROT_DPROT_SHIFT 0
9408 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FDPROT_DPROT_SHIFT))&NV_FDPROT_DPROT_MASK)
9409
9410 /*!
9411 * @}
9412 */ /* end of group NV_Register_Masks */
9413
9414
9415 /* NV - Peripheral instance base addresses */
9416 /** Peripheral FTFE_FlashConfig base address */
9417 #define FTFE_FlashConfig_BASE (0x400u)
9418 /** Peripheral FTFE_FlashConfig base pointer */
9419 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
9420 #define FTFE_FlashConfig_BASE_PTR (FTFE_FlashConfig)
9421 /** Array initializer of NV peripheral base addresses */
9422 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
9423 /** Array initializer of NV peripheral base pointers */
9424 #define NV_BASE_PTRS { FTFE_FlashConfig }
9425
9426 /* ----------------------------------------------------------------------------
9427 -- NV - Register accessor macros
9428 ---------------------------------------------------------------------------- */
9429
9430 /*!
9431 * @addtogroup NV_Register_Accessor_Macros NV - Register accessor macros
9432 * @{
9433 */
9434
9435
9436 /* NV - Register instance definitions */
9437 /* FTFE_FlashConfig */
9438 #define NV_BACKKEY3 NV_BACKKEY3_REG(FTFE_FlashConfig)
9439 #define NV_BACKKEY2 NV_BACKKEY2_REG(FTFE_FlashConfig)
9440 #define NV_BACKKEY1 NV_BACKKEY1_REG(FTFE_FlashConfig)
9441 #define NV_BACKKEY0 NV_BACKKEY0_REG(FTFE_FlashConfig)
9442 #define NV_BACKKEY7 NV_BACKKEY7_REG(FTFE_FlashConfig)
9443 #define NV_BACKKEY6 NV_BACKKEY6_REG(FTFE_FlashConfig)
9444 #define NV_BACKKEY5 NV_BACKKEY5_REG(FTFE_FlashConfig)
9445 #define NV_BACKKEY4 NV_BACKKEY4_REG(FTFE_FlashConfig)
9446 #define NV_FPROT3 NV_FPROT3_REG(FTFE_FlashConfig)
9447 #define NV_FPROT2 NV_FPROT2_REG(FTFE_FlashConfig)
9448 #define NV_FPROT1 NV_FPROT1_REG(FTFE_FlashConfig)
9449 #define NV_FPROT0 NV_FPROT0_REG(FTFE_FlashConfig)
9450 #define NV_FSEC NV_FSEC_REG(FTFE_FlashConfig)
9451 #define NV_FOPT NV_FOPT_REG(FTFE_FlashConfig)
9452 #define NV_FEPROT NV_FEPROT_REG(FTFE_FlashConfig)
9453 #define NV_FDPROT NV_FDPROT_REG(FTFE_FlashConfig)
9454
9455 /*!
9456 * @}
9457 */ /* end of group NV_Register_Accessor_Macros */
9458
9459
9460 /*!
9461 * @}
9462 */ /* end of group NV_Peripheral_Access_Layer */
9463
9464
9465 /* ----------------------------------------------------------------------------
9466 -- OSC Peripheral Access Layer
9467 ---------------------------------------------------------------------------- */
9468
9469 /*!
9470 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
9471 * @{
9472 */
9473
9474 /** OSC - Register Layout Typedef */
9475 typedef struct {
9476 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
9477 } OSC_Type, *OSC_MemMapPtr;
9478
9479 /* ----------------------------------------------------------------------------
9480 -- OSC - Register accessor macros
9481 ---------------------------------------------------------------------------- */
9482
9483 /*!
9484 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
9485 * @{
9486 */
9487
9488
9489 /* OSC - Register accessors */
9490 #define OSC_CR_REG(base) ((base)->CR)
9491
9492 /*!
9493 * @}
9494 */ /* end of group OSC_Register_Accessor_Macros */
9495
9496
9497 /* ----------------------------------------------------------------------------
9498 -- OSC Register Masks
9499 ---------------------------------------------------------------------------- */
9500
9501 /*!
9502 * @addtogroup OSC_Register_Masks OSC Register Masks
9503 * @{
9504 */
9505
9506 /* CR Bit Fields */
9507 #define OSC_CR_SC16P_MASK 0x1u
9508 #define OSC_CR_SC16P_SHIFT 0
9509 #define OSC_CR_SC8P_MASK 0x2u
9510 #define OSC_CR_SC8P_SHIFT 1
9511 #define OSC_CR_SC4P_MASK 0x4u
9512 #define OSC_CR_SC4P_SHIFT 2
9513 #define OSC_CR_SC2P_MASK 0x8u
9514 #define OSC_CR_SC2P_SHIFT 3
9515 #define OSC_CR_EREFSTEN_MASK 0x20u
9516 #define OSC_CR_EREFSTEN_SHIFT 5
9517 #define OSC_CR_ERCLKEN_MASK 0x80u
9518 #define OSC_CR_ERCLKEN_SHIFT 7
9519
9520 /*!
9521 * @}
9522 */ /* end of group OSC_Register_Masks */
9523
9524
9525 /* OSC - Peripheral instance base addresses */
9526 /** Peripheral OSC base address */
9527 #define OSC_BASE (0x40065000u)
9528 /** Peripheral OSC base pointer */
9529 #define OSC ((OSC_Type *)OSC_BASE)
9530 #define OSC_BASE_PTR (OSC)
9531 /** Array initializer of OSC peripheral base addresses */
9532 #define OSC_BASE_ADDRS { OSC_BASE }
9533 /** Array initializer of OSC peripheral base pointers */
9534 #define OSC_BASE_PTRS { OSC }
9535
9536 /* ----------------------------------------------------------------------------
9537 -- OSC - Register accessor macros
9538 ---------------------------------------------------------------------------- */
9539
9540 /*!
9541 * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros
9542 * @{
9543 */
9544
9545
9546 /* OSC - Register instance definitions */
9547 /* OSC */
9548 #define OSC_CR OSC_CR_REG(OSC)
9549
9550 /*!
9551 * @}
9552 */ /* end of group OSC_Register_Accessor_Macros */
9553
9554
9555 /*!
9556 * @}
9557 */ /* end of group OSC_Peripheral_Access_Layer */
9558
9559
9560 /* ----------------------------------------------------------------------------
9561 -- PDB Peripheral Access Layer
9562 ---------------------------------------------------------------------------- */
9563
9564 /*!
9565 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
9566 * @{
9567 */
9568
9569 /** PDB - Register Layout Typedef */
9570 typedef struct {
9571 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
9572 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
9573 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
9574 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
9575 struct { /* offset: 0x10, array step: 0x28 */
9576 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
9577 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
9578 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
9579 uint8_t RESERVED_0[24];
9580 } CH[2];
9581 uint8_t RESERVED_0[240];
9582 struct { /* offset: 0x150, array step: 0x8 */
9583 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
9584 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
9585 } DAC[2];
9586 uint8_t RESERVED_1[48];
9587 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
9588 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
9589 } PDB_Type, *PDB_MemMapPtr;
9590
9591 /* ----------------------------------------------------------------------------
9592 -- PDB - Register accessor macros
9593 ---------------------------------------------------------------------------- */
9594
9595 /*!
9596 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
9597 * @{
9598 */
9599
9600
9601 /* PDB - Register accessors */
9602 #define PDB_SC_REG(base) ((base)->SC)
9603 #define PDB_MOD_REG(base) ((base)->MOD)
9604 #define PDB_CNT_REG(base) ((base)->CNT)
9605 #define PDB_IDLY_REG(base) ((base)->IDLY)
9606 #define PDB_C1_REG(base,index) ((base)->CH[index].C1)
9607 #define PDB_S_REG(base,index) ((base)->CH[index].S)
9608 #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2])
9609 #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC)
9610 #define PDB_INT_REG(base,index) ((base)->DAC[index].INT)
9611 #define PDB_POEN_REG(base) ((base)->POEN)
9612 #define PDB_PODLY_REG(base,index) ((base)->PODLY[index])
9613
9614 /*!
9615 * @}
9616 */ /* end of group PDB_Register_Accessor_Macros */
9617
9618
9619 /* ----------------------------------------------------------------------------
9620 -- PDB Register Masks
9621 ---------------------------------------------------------------------------- */
9622
9623 /*!
9624 * @addtogroup PDB_Register_Masks PDB Register Masks
9625 * @{
9626 */
9627
9628 /* SC Bit Fields */
9629 #define PDB_SC_LDOK_MASK 0x1u
9630 #define PDB_SC_LDOK_SHIFT 0
9631 #define PDB_SC_CONT_MASK 0x2u
9632 #define PDB_SC_CONT_SHIFT 1
9633 #define PDB_SC_MULT_MASK 0xCu
9634 #define PDB_SC_MULT_SHIFT 2
9635 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_MULT_SHIFT))&PDB_SC_MULT_MASK)
9636 #define PDB_SC_PDBIE_MASK 0x20u
9637 #define PDB_SC_PDBIE_SHIFT 5
9638 #define PDB_SC_PDBIF_MASK 0x40u
9639 #define PDB_SC_PDBIF_SHIFT 6
9640 #define PDB_SC_PDBEN_MASK 0x80u
9641 #define PDB_SC_PDBEN_SHIFT 7
9642 #define PDB_SC_TRGSEL_MASK 0xF00u
9643 #define PDB_SC_TRGSEL_SHIFT 8
9644 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_TRGSEL_SHIFT))&PDB_SC_TRGSEL_MASK)
9645 #define PDB_SC_PRESCALER_MASK 0x7000u
9646 #define PDB_SC_PRESCALER_SHIFT 12
9647 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_PRESCALER_SHIFT))&PDB_SC_PRESCALER_MASK)
9648 #define PDB_SC_DMAEN_MASK 0x8000u
9649 #define PDB_SC_DMAEN_SHIFT 15
9650 #define PDB_SC_SWTRIG_MASK 0x10000u
9651 #define PDB_SC_SWTRIG_SHIFT 16
9652 #define PDB_SC_PDBEIE_MASK 0x20000u
9653 #define PDB_SC_PDBEIE_SHIFT 17
9654 #define PDB_SC_LDMOD_MASK 0xC0000u
9655 #define PDB_SC_LDMOD_SHIFT 18
9656 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_SC_LDMOD_SHIFT))&PDB_SC_LDMOD_MASK)
9657 /* MOD Bit Fields */
9658 #define PDB_MOD_MOD_MASK 0xFFFFu
9659 #define PDB_MOD_MOD_SHIFT 0
9660 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<PDB_MOD_MOD_SHIFT))&PDB_MOD_MOD_MASK)
9661 /* CNT Bit Fields */
9662 #define PDB_CNT_CNT_MASK 0xFFFFu
9663 #define PDB_CNT_CNT_SHIFT 0
9664 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x))<<PDB_CNT_CNT_SHIFT))&PDB_CNT_CNT_MASK)
9665 /* IDLY Bit Fields */
9666 #define PDB_IDLY_IDLY_MASK 0xFFFFu
9667 #define PDB_IDLY_IDLY_SHIFT 0
9668 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_IDLY_IDLY_SHIFT))&PDB_IDLY_IDLY_MASK)
9669 /* C1 Bit Fields */
9670 #define PDB_C1_EN_MASK 0xFFu
9671 #define PDB_C1_EN_SHIFT 0
9672 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_EN_SHIFT))&PDB_C1_EN_MASK)
9673 #define PDB_C1_TOS_MASK 0xFF00u
9674 #define PDB_C1_TOS_SHIFT 8
9675 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_TOS_SHIFT))&PDB_C1_TOS_MASK)
9676 #define PDB_C1_BB_MASK 0xFF0000u
9677 #define PDB_C1_BB_SHIFT 16
9678 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x))<<PDB_C1_BB_SHIFT))&PDB_C1_BB_MASK)
9679 /* S Bit Fields */
9680 #define PDB_S_ERR_MASK 0xFFu
9681 #define PDB_S_ERR_SHIFT 0
9682 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_ERR_SHIFT))&PDB_S_ERR_MASK)
9683 #define PDB_S_CF_MASK 0xFF0000u
9684 #define PDB_S_CF_SHIFT 16
9685 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x))<<PDB_S_CF_SHIFT))&PDB_S_CF_MASK)
9686 /* DLY Bit Fields */
9687 #define PDB_DLY_DLY_MASK 0xFFFFu
9688 #define PDB_DLY_DLY_SHIFT 0
9689 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x))<<PDB_DLY_DLY_SHIFT))&PDB_DLY_DLY_MASK)
9690 /* INTC Bit Fields */
9691 #define PDB_INTC_TOE_MASK 0x1u
9692 #define PDB_INTC_TOE_SHIFT 0
9693 #define PDB_INTC_EXT_MASK 0x2u
9694 #define PDB_INTC_EXT_SHIFT 1
9695 /* INT Bit Fields */
9696 #define PDB_INT_INT_MASK 0xFFFFu
9697 #define PDB_INT_INT_SHIFT 0
9698 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x))<<PDB_INT_INT_SHIFT))&PDB_INT_INT_MASK)
9699 /* POEN Bit Fields */
9700 #define PDB_POEN_POEN_MASK 0xFFu
9701 #define PDB_POEN_POEN_SHIFT 0
9702 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x))<<PDB_POEN_POEN_SHIFT))&PDB_POEN_POEN_MASK)
9703 /* PODLY Bit Fields */
9704 #define PDB_PODLY_DLY2_MASK 0xFFFFu
9705 #define PDB_PODLY_DLY2_SHIFT 0
9706 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY2_SHIFT))&PDB_PODLY_DLY2_MASK)
9707 #define PDB_PODLY_DLY1_MASK 0xFFFF0000u
9708 #define PDB_PODLY_DLY1_SHIFT 16
9709 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x))<<PDB_PODLY_DLY1_SHIFT))&PDB_PODLY_DLY1_MASK)
9710
9711 /*!
9712 * @}
9713 */ /* end of group PDB_Register_Masks */
9714
9715
9716 /* PDB - Peripheral instance base addresses */
9717 /** Peripheral PDB0 base address */
9718 #define PDB0_BASE (0x40036000u)
9719 /** Peripheral PDB0 base pointer */
9720 #define PDB0 ((PDB_Type *)PDB0_BASE)
9721 #define PDB0_BASE_PTR (PDB0)
9722 /** Array initializer of PDB peripheral base addresses */
9723 #define PDB_BASE_ADDRS { PDB0_BASE }
9724 /** Array initializer of PDB peripheral base pointers */
9725 #define PDB_BASE_PTRS { PDB0 }
9726 /** Interrupt vectors for the PDB peripheral type */
9727 #define PDB_IRQS { PDB0_IRQn }
9728
9729 /* ----------------------------------------------------------------------------
9730 -- PDB - Register accessor macros
9731 ---------------------------------------------------------------------------- */
9732
9733 /*!
9734 * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros
9735 * @{
9736 */
9737
9738
9739 /* PDB - Register instance definitions */
9740 /* PDB0 */
9741 #define PDB0_SC PDB_SC_REG(PDB0)
9742 #define PDB0_MOD PDB_MOD_REG(PDB0)
9743 #define PDB0_CNT PDB_CNT_REG(PDB0)
9744 #define PDB0_IDLY PDB_IDLY_REG(PDB0)
9745 #define PDB0_CH0C1 PDB_C1_REG(PDB0,0)
9746 #define PDB0_CH0S PDB_S_REG(PDB0,0)
9747 #define PDB0_CH0DLY0 PDB_DLY_REG(PDB0,0,0)
9748 #define PDB0_CH0DLY1 PDB_DLY_REG(PDB0,0,1)
9749 #define PDB0_CH1C1 PDB_C1_REG(PDB0,1)
9750 #define PDB0_CH1S PDB_S_REG(PDB0,1)
9751 #define PDB0_CH1DLY0 PDB_DLY_REG(PDB0,1,0)
9752 #define PDB0_CH1DLY1 PDB_DLY_REG(PDB0,1,1)
9753 #define PDB0_DACINTC0 PDB_INTC_REG(PDB0,0)
9754 #define PDB0_DACINT0 PDB_INT_REG(PDB0,0)
9755 #define PDB0_DACINTC1 PDB_INTC_REG(PDB0,1)
9756 #define PDB0_DACINT1 PDB_INT_REG(PDB0,1)
9757 #define PDB0_POEN PDB_POEN_REG(PDB0)
9758 #define PDB0_PO0DLY PDB_PODLY_REG(PDB0,0)
9759 #define PDB0_PO1DLY PDB_PODLY_REG(PDB0,1)
9760 #define PDB0_PO2DLY PDB_PODLY_REG(PDB0,2)
9761
9762 /* PDB - Register array accessors */
9763 #define PDB0_C1(index) PDB_C1_REG(PDB0,index)
9764 #define PDB0_S(index) PDB_S_REG(PDB0,index)
9765 #define PDB0_DLY(index,index2) PDB_DLY_REG(PDB0,index,index2)
9766 #define PDB0_INTC(index) PDB_INTC_REG(PDB0,index)
9767 #define PDB0_INT(index) PDB_INT_REG(PDB0,index)
9768 #define PDB0_PODLY(index) PDB_PODLY_REG(PDB0,index)
9769
9770 /*!
9771 * @}
9772 */ /* end of group PDB_Register_Accessor_Macros */
9773
9774
9775 /*!
9776 * @}
9777 */ /* end of group PDB_Peripheral_Access_Layer */
9778
9779
9780 /* ----------------------------------------------------------------------------
9781 -- PIT Peripheral Access Layer
9782 ---------------------------------------------------------------------------- */
9783
9784 /*!
9785 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
9786 * @{
9787 */
9788
9789 /** PIT - Register Layout Typedef */
9790 typedef struct {
9791 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
9792 uint8_t RESERVED_0[252];
9793 struct { /* offset: 0x100, array step: 0x10 */
9794 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
9795 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
9796 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
9797 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
9798 } CHANNEL[4];
9799 } PIT_Type, *PIT_MemMapPtr;
9800
9801 /* ----------------------------------------------------------------------------
9802 -- PIT - Register accessor macros
9803 ---------------------------------------------------------------------------- */
9804
9805 /*!
9806 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
9807 * @{
9808 */
9809
9810
9811 /* PIT - Register accessors */
9812 #define PIT_MCR_REG(base) ((base)->MCR)
9813 #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL)
9814 #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL)
9815 #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL)
9816 #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG)
9817
9818 /*!
9819 * @}
9820 */ /* end of group PIT_Register_Accessor_Macros */
9821
9822
9823 /* ----------------------------------------------------------------------------
9824 -- PIT Register Masks
9825 ---------------------------------------------------------------------------- */
9826
9827 /*!
9828 * @addtogroup PIT_Register_Masks PIT Register Masks
9829 * @{
9830 */
9831
9832 /* MCR Bit Fields */
9833 #define PIT_MCR_FRZ_MASK 0x1u
9834 #define PIT_MCR_FRZ_SHIFT 0
9835 #define PIT_MCR_MDIS_MASK 0x2u
9836 #define PIT_MCR_MDIS_SHIFT 1
9837 /* LDVAL Bit Fields */
9838 #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
9839 #define PIT_LDVAL_TSV_SHIFT 0
9840 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
9841 /* CVAL Bit Fields */
9842 #define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
9843 #define PIT_CVAL_TVL_SHIFT 0
9844 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
9845 /* TCTRL Bit Fields */
9846 #define PIT_TCTRL_TEN_MASK 0x1u
9847 #define PIT_TCTRL_TEN_SHIFT 0
9848 #define PIT_TCTRL_TIE_MASK 0x2u
9849 #define PIT_TCTRL_TIE_SHIFT 1
9850 #define PIT_TCTRL_CHN_MASK 0x4u
9851 #define PIT_TCTRL_CHN_SHIFT 2
9852 /* TFLG Bit Fields */
9853 #define PIT_TFLG_TIF_MASK 0x1u
9854 #define PIT_TFLG_TIF_SHIFT 0
9855
9856 /*!
9857 * @}
9858 */ /* end of group PIT_Register_Masks */
9859
9860
9861 /* PIT - Peripheral instance base addresses */
9862 /** Peripheral PIT base address */
9863 #define PIT_BASE (0x40037000u)
9864 /** Peripheral PIT base pointer */
9865 #define PIT ((PIT_Type *)PIT_BASE)
9866 #define PIT_BASE_PTR (PIT)
9867 /** Array initializer of PIT peripheral base addresses */
9868 #define PIT_BASE_ADDRS { PIT_BASE }
9869 /** Array initializer of PIT peripheral base pointers */
9870 #define PIT_BASE_PTRS { PIT }
9871 /** Interrupt vectors for the PIT peripheral type */
9872 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
9873
9874 /* ----------------------------------------------------------------------------
9875 -- PIT - Register accessor macros
9876 ---------------------------------------------------------------------------- */
9877
9878 /*!
9879 * @addtogroup PIT_Register_Accessor_Macros PIT - Register accessor macros
9880 * @{
9881 */
9882
9883
9884 /* PIT - Register instance definitions */
9885 /* PIT */
9886 #define PIT_MCR PIT_MCR_REG(PIT)
9887 #define PIT_LDVAL0 PIT_LDVAL_REG(PIT,0)
9888 #define PIT_CVAL0 PIT_CVAL_REG(PIT,0)
9889 #define PIT_TCTRL0 PIT_TCTRL_REG(PIT,0)
9890 #define PIT_TFLG0 PIT_TFLG_REG(PIT,0)
9891 #define PIT_LDVAL1 PIT_LDVAL_REG(PIT,1)
9892 #define PIT_CVAL1 PIT_CVAL_REG(PIT,1)
9893 #define PIT_TCTRL1 PIT_TCTRL_REG(PIT,1)
9894 #define PIT_TFLG1 PIT_TFLG_REG(PIT,1)
9895 #define PIT_LDVAL2 PIT_LDVAL_REG(PIT,2)
9896 #define PIT_CVAL2 PIT_CVAL_REG(PIT,2)
9897 #define PIT_TCTRL2 PIT_TCTRL_REG(PIT,2)
9898 #define PIT_TFLG2 PIT_TFLG_REG(PIT,2)
9899 #define PIT_LDVAL3 PIT_LDVAL_REG(PIT,3)
9900 #define PIT_CVAL3 PIT_CVAL_REG(PIT,3)
9901 #define PIT_TCTRL3 PIT_TCTRL_REG(PIT,3)
9902 #define PIT_TFLG3 PIT_TFLG_REG(PIT,3)
9903
9904 /* PIT - Register array accessors */
9905 #define PIT_LDVAL(index) PIT_LDVAL_REG(PIT,index)
9906 #define PIT_CVAL(index) PIT_CVAL_REG(PIT,index)
9907 #define PIT_TCTRL(index) PIT_TCTRL_REG(PIT,index)
9908 #define PIT_TFLG(index) PIT_TFLG_REG(PIT,index)
9909
9910 /*!
9911 * @}
9912 */ /* end of group PIT_Register_Accessor_Macros */
9913
9914
9915 /*!
9916 * @}
9917 */ /* end of group PIT_Peripheral_Access_Layer */
9918
9919
9920 /* ----------------------------------------------------------------------------
9921 -- PMC Peripheral Access Layer
9922 ---------------------------------------------------------------------------- */
9923
9924 /*!
9925 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
9926 * @{
9927 */
9928
9929 /** PMC - Register Layout Typedef */
9930 typedef struct {
9931 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
9932 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
9933 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
9934 } PMC_Type, *PMC_MemMapPtr;
9935
9936 /* ----------------------------------------------------------------------------
9937 -- PMC - Register accessor macros
9938 ---------------------------------------------------------------------------- */
9939
9940 /*!
9941 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
9942 * @{
9943 */
9944
9945
9946 /* PMC - Register accessors */
9947 #define PMC_LVDSC1_REG(base) ((base)->LVDSC1)
9948 #define PMC_LVDSC2_REG(base) ((base)->LVDSC2)
9949 #define PMC_REGSC_REG(base) ((base)->REGSC)
9950
9951 /*!
9952 * @}
9953 */ /* end of group PMC_Register_Accessor_Macros */
9954
9955
9956 /* ----------------------------------------------------------------------------
9957 -- PMC Register Masks
9958 ---------------------------------------------------------------------------- */
9959
9960 /*!
9961 * @addtogroup PMC_Register_Masks PMC Register Masks
9962 * @{
9963 */
9964
9965 /* LVDSC1 Bit Fields */
9966 #define PMC_LVDSC1_LVDV_MASK 0x3u
9967 #define PMC_LVDSC1_LVDV_SHIFT 0
9968 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
9969 #define PMC_LVDSC1_LVDRE_MASK 0x10u
9970 #define PMC_LVDSC1_LVDRE_SHIFT 4
9971 #define PMC_LVDSC1_LVDIE_MASK 0x20u
9972 #define PMC_LVDSC1_LVDIE_SHIFT 5
9973 #define PMC_LVDSC1_LVDACK_MASK 0x40u
9974 #define PMC_LVDSC1_LVDACK_SHIFT 6
9975 #define PMC_LVDSC1_LVDF_MASK 0x80u
9976 #define PMC_LVDSC1_LVDF_SHIFT 7
9977 /* LVDSC2 Bit Fields */
9978 #define PMC_LVDSC2_LVWV_MASK 0x3u
9979 #define PMC_LVDSC2_LVWV_SHIFT 0
9980 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
9981 #define PMC_LVDSC2_LVWIE_MASK 0x20u
9982 #define PMC_LVDSC2_LVWIE_SHIFT 5
9983 #define PMC_LVDSC2_LVWACK_MASK 0x40u
9984 #define PMC_LVDSC2_LVWACK_SHIFT 6
9985 #define PMC_LVDSC2_LVWF_MASK 0x80u
9986 #define PMC_LVDSC2_LVWF_SHIFT 7
9987 /* REGSC Bit Fields */
9988 #define PMC_REGSC_BGBE_MASK 0x1u
9989 #define PMC_REGSC_BGBE_SHIFT 0
9990 #define PMC_REGSC_REGONS_MASK 0x4u
9991 #define PMC_REGSC_REGONS_SHIFT 2
9992 #define PMC_REGSC_ACKISO_MASK 0x8u
9993 #define PMC_REGSC_ACKISO_SHIFT 3
9994 #define PMC_REGSC_BGEN_MASK 0x10u
9995 #define PMC_REGSC_BGEN_SHIFT 4
9996
9997 /*!
9998 * @}
9999 */ /* end of group PMC_Register_Masks */
10000
10001
10002 /* PMC - Peripheral instance base addresses */
10003 /** Peripheral PMC base address */
10004 #define PMC_BASE (0x4007D000u)
10005 /** Peripheral PMC base pointer */
10006 #define PMC ((PMC_Type *)PMC_BASE)
10007 #define PMC_BASE_PTR (PMC)
10008 /** Array initializer of PMC peripheral base addresses */
10009 #define PMC_BASE_ADDRS { PMC_BASE }
10010 /** Array initializer of PMC peripheral base pointers */
10011 #define PMC_BASE_PTRS { PMC }
10012 /** Interrupt vectors for the PMC peripheral type */
10013 #define PMC_IRQS { LVD_LVW_IRQn }
10014
10015 /* ----------------------------------------------------------------------------
10016 -- PMC - Register accessor macros
10017 ---------------------------------------------------------------------------- */
10018
10019 /*!
10020 * @addtogroup PMC_Register_Accessor_Macros PMC - Register accessor macros
10021 * @{
10022 */
10023
10024
10025 /* PMC - Register instance definitions */
10026 /* PMC */
10027 #define PMC_LVDSC1 PMC_LVDSC1_REG(PMC)
10028 #define PMC_LVDSC2 PMC_LVDSC2_REG(PMC)
10029 #define PMC_REGSC PMC_REGSC_REG(PMC)
10030
10031 /*!
10032 * @}
10033 */ /* end of group PMC_Register_Accessor_Macros */
10034
10035
10036 /*!
10037 * @}
10038 */ /* end of group PMC_Peripheral_Access_Layer */
10039
10040
10041 /* ----------------------------------------------------------------------------
10042 -- PORT Peripheral Access Layer
10043 ---------------------------------------------------------------------------- */
10044
10045 /*!
10046 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
10047 * @{
10048 */
10049
10050 /** PORT - Register Layout Typedef */
10051 typedef struct {
10052 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
10053 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
10054 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
10055 uint8_t RESERVED_0[24];
10056 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
10057 uint8_t RESERVED_1[28];
10058 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
10059 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
10060 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
10061 } PORT_Type, *PORT_MemMapPtr;
10062
10063 /* ----------------------------------------------------------------------------
10064 -- PORT - Register accessor macros
10065 ---------------------------------------------------------------------------- */
10066
10067 /*!
10068 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
10069 * @{
10070 */
10071
10072
10073 /* PORT - Register accessors */
10074 #define PORT_PCR_REG(base,index) ((base)->PCR[index])
10075 #define PORT_GPCLR_REG(base) ((base)->GPCLR)
10076 #define PORT_GPCHR_REG(base) ((base)->GPCHR)
10077 #define PORT_ISFR_REG(base) ((base)->ISFR)
10078 #define PORT_DFER_REG(base) ((base)->DFER)
10079 #define PORT_DFCR_REG(base) ((base)->DFCR)
10080 #define PORT_DFWR_REG(base) ((base)->DFWR)
10081
10082 /*!
10083 * @}
10084 */ /* end of group PORT_Register_Accessor_Macros */
10085
10086
10087 /* ----------------------------------------------------------------------------
10088 -- PORT Register Masks
10089 ---------------------------------------------------------------------------- */
10090
10091 /*!
10092 * @addtogroup PORT_Register_Masks PORT Register Masks
10093 * @{
10094 */
10095
10096 /* PCR Bit Fields */
10097 #define PORT_PCR_PS_MASK 0x1u
10098 #define PORT_PCR_PS_SHIFT 0
10099 #define PORT_PCR_PE_MASK 0x2u
10100 #define PORT_PCR_PE_SHIFT 1
10101 #define PORT_PCR_SRE_MASK 0x4u
10102 #define PORT_PCR_SRE_SHIFT 2
10103 #define PORT_PCR_PFE_MASK 0x10u
10104 #define PORT_PCR_PFE_SHIFT 4
10105 #define PORT_PCR_ODE_MASK 0x20u
10106 #define PORT_PCR_ODE_SHIFT 5
10107 #define PORT_PCR_DSE_MASK 0x40u
10108 #define PORT_PCR_DSE_SHIFT 6
10109 #define PORT_PCR_MUX_MASK 0x700u
10110 #define PORT_PCR_MUX_SHIFT 8
10111 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
10112 #define PORT_PCR_LK_MASK 0x8000u
10113 #define PORT_PCR_LK_SHIFT 15
10114 #define PORT_PCR_IRQC_MASK 0xF0000u
10115 #define PORT_PCR_IRQC_SHIFT 16
10116 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
10117 #define PORT_PCR_ISF_MASK 0x1000000u
10118 #define PORT_PCR_ISF_SHIFT 24
10119 /* GPCLR Bit Fields */
10120 #define PORT_GPCLR_GPWD_MASK 0xFFFFu
10121 #define PORT_GPCLR_GPWD_SHIFT 0
10122 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
10123 #define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
10124 #define PORT_GPCLR_GPWE_SHIFT 16
10125 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
10126 /* GPCHR Bit Fields */
10127 #define PORT_GPCHR_GPWD_MASK 0xFFFFu
10128 #define PORT_GPCHR_GPWD_SHIFT 0
10129 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
10130 #define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
10131 #define PORT_GPCHR_GPWE_SHIFT 16
10132 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
10133 /* ISFR Bit Fields */
10134 #define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
10135 #define PORT_ISFR_ISF_SHIFT 0
10136 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
10137 /* DFER Bit Fields */
10138 #define PORT_DFER_DFE_MASK 0xFFFFFFFFu
10139 #define PORT_DFER_DFE_SHIFT 0
10140 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFER_DFE_SHIFT))&PORT_DFER_DFE_MASK)
10141 /* DFCR Bit Fields */
10142 #define PORT_DFCR_CS_MASK 0x1u
10143 #define PORT_DFCR_CS_SHIFT 0
10144 /* DFWR Bit Fields */
10145 #define PORT_DFWR_FILT_MASK 0x1Fu
10146 #define PORT_DFWR_FILT_SHIFT 0
10147 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x))<<PORT_DFWR_FILT_SHIFT))&PORT_DFWR_FILT_MASK)
10148
10149 /*!
10150 * @}
10151 */ /* end of group PORT_Register_Masks */
10152
10153
10154 /* PORT - Peripheral instance base addresses */
10155 /** Peripheral PORTA base address */
10156 #define PORTA_BASE (0x40049000u)
10157 /** Peripheral PORTA base pointer */
10158 #define PORTA ((PORT_Type *)PORTA_BASE)
10159 #define PORTA_BASE_PTR (PORTA)
10160 /** Peripheral PORTB base address */
10161 #define PORTB_BASE (0x4004A000u)
10162 /** Peripheral PORTB base pointer */
10163 #define PORTB ((PORT_Type *)PORTB_BASE)
10164 #define PORTB_BASE_PTR (PORTB)
10165 /** Peripheral PORTC base address */
10166 #define PORTC_BASE (0x4004B000u)
10167 /** Peripheral PORTC base pointer */
10168 #define PORTC ((PORT_Type *)PORTC_BASE)
10169 #define PORTC_BASE_PTR (PORTC)
10170 /** Peripheral PORTD base address */
10171 #define PORTD_BASE (0x4004C000u)
10172 /** Peripheral PORTD base pointer */
10173 #define PORTD ((PORT_Type *)PORTD_BASE)
10174 #define PORTD_BASE_PTR (PORTD)
10175 /** Peripheral PORTE base address */
10176 #define PORTE_BASE (0x4004D000u)
10177 /** Peripheral PORTE base pointer */
10178 #define PORTE ((PORT_Type *)PORTE_BASE)
10179 #define PORTE_BASE_PTR (PORTE)
10180 /** Array initializer of PORT peripheral base addresses */
10181 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
10182 /** Array initializer of PORT peripheral base pointers */
10183 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
10184 /** Interrupt vectors for the PORT peripheral type */
10185 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
10186
10187 /* ----------------------------------------------------------------------------
10188 -- PORT - Register accessor macros
10189 ---------------------------------------------------------------------------- */
10190
10191 /*!
10192 * @addtogroup PORT_Register_Accessor_Macros PORT - Register accessor macros
10193 * @{
10194 */
10195
10196
10197 /* PORT - Register instance definitions */
10198 /* PORTA */
10199 #define PORTA_PCR0 PORT_PCR_REG(PORTA,0)
10200 #define PORTA_PCR1 PORT_PCR_REG(PORTA,1)
10201 #define PORTA_PCR2 PORT_PCR_REG(PORTA,2)
10202 #define PORTA_PCR3 PORT_PCR_REG(PORTA,3)
10203 #define PORTA_PCR4 PORT_PCR_REG(PORTA,4)
10204 #define PORTA_PCR5 PORT_PCR_REG(PORTA,5)
10205 #define PORTA_PCR6 PORT_PCR_REG(PORTA,6)
10206 #define PORTA_PCR7 PORT_PCR_REG(PORTA,7)
10207 #define PORTA_PCR8 PORT_PCR_REG(PORTA,8)
10208 #define PORTA_PCR9 PORT_PCR_REG(PORTA,9)
10209 #define PORTA_PCR10 PORT_PCR_REG(PORTA,10)
10210 #define PORTA_PCR11 PORT_PCR_REG(PORTA,11)
10211 #define PORTA_PCR12 PORT_PCR_REG(PORTA,12)
10212 #define PORTA_PCR13 PORT_PCR_REG(PORTA,13)
10213 #define PORTA_PCR14 PORT_PCR_REG(PORTA,14)
10214 #define PORTA_PCR15 PORT_PCR_REG(PORTA,15)
10215 #define PORTA_PCR16 PORT_PCR_REG(PORTA,16)
10216 #define PORTA_PCR17 PORT_PCR_REG(PORTA,17)
10217 #define PORTA_PCR18 PORT_PCR_REG(PORTA,18)
10218 #define PORTA_PCR19 PORT_PCR_REG(PORTA,19)
10219 #define PORTA_PCR20 PORT_PCR_REG(PORTA,20)
10220 #define PORTA_PCR21 PORT_PCR_REG(PORTA,21)
10221 #define PORTA_PCR22 PORT_PCR_REG(PORTA,22)
10222 #define PORTA_PCR23 PORT_PCR_REG(PORTA,23)
10223 #define PORTA_PCR24 PORT_PCR_REG(PORTA,24)
10224 #define PORTA_PCR25 PORT_PCR_REG(PORTA,25)
10225 #define PORTA_PCR26 PORT_PCR_REG(PORTA,26)
10226 #define PORTA_PCR27 PORT_PCR_REG(PORTA,27)
10227 #define PORTA_PCR28 PORT_PCR_REG(PORTA,28)
10228 #define PORTA_PCR29 PORT_PCR_REG(PORTA,29)
10229 #define PORTA_PCR30 PORT_PCR_REG(PORTA,30)
10230 #define PORTA_PCR31 PORT_PCR_REG(PORTA,31)
10231 #define PORTA_GPCLR PORT_GPCLR_REG(PORTA)
10232 #define PORTA_GPCHR PORT_GPCHR_REG(PORTA)
10233 #define PORTA_ISFR PORT_ISFR_REG(PORTA)
10234 /* PORTB */
10235 #define PORTB_PCR0 PORT_PCR_REG(PORTB,0)
10236 #define PORTB_PCR1 PORT_PCR_REG(PORTB,1)
10237 #define PORTB_PCR2 PORT_PCR_REG(PORTB,2)
10238 #define PORTB_PCR3 PORT_PCR_REG(PORTB,3)
10239 #define PORTB_PCR4 PORT_PCR_REG(PORTB,4)
10240 #define PORTB_PCR5 PORT_PCR_REG(PORTB,5)
10241 #define PORTB_PCR6 PORT_PCR_REG(PORTB,6)
10242 #define PORTB_PCR7 PORT_PCR_REG(PORTB,7)
10243 #define PORTB_PCR8 PORT_PCR_REG(PORTB,8)
10244 #define PORTB_PCR9 PORT_PCR_REG(PORTB,9)
10245 #define PORTB_PCR10 PORT_PCR_REG(PORTB,10)
10246 #define PORTB_PCR11 PORT_PCR_REG(PORTB,11)
10247 #define PORTB_PCR12 PORT_PCR_REG(PORTB,12)
10248 #define PORTB_PCR13 PORT_PCR_REG(PORTB,13)
10249 #define PORTB_PCR14 PORT_PCR_REG(PORTB,14)
10250 #define PORTB_PCR15 PORT_PCR_REG(PORTB,15)
10251 #define PORTB_PCR16 PORT_PCR_REG(PORTB,16)
10252 #define PORTB_PCR17 PORT_PCR_REG(PORTB,17)
10253 #define PORTB_PCR18 PORT_PCR_REG(PORTB,18)
10254 #define PORTB_PCR19 PORT_PCR_REG(PORTB,19)
10255 #define PORTB_PCR20 PORT_PCR_REG(PORTB,20)
10256 #define PORTB_PCR21 PORT_PCR_REG(PORTB,21)
10257 #define PORTB_PCR22 PORT_PCR_REG(PORTB,22)
10258 #define PORTB_PCR23 PORT_PCR_REG(PORTB,23)
10259 #define PORTB_PCR24 PORT_PCR_REG(PORTB,24)
10260 #define PORTB_PCR25 PORT_PCR_REG(PORTB,25)
10261 #define PORTB_PCR26 PORT_PCR_REG(PORTB,26)
10262 #define PORTB_PCR27 PORT_PCR_REG(PORTB,27)
10263 #define PORTB_PCR28 PORT_PCR_REG(PORTB,28)
10264 #define PORTB_PCR29 PORT_PCR_REG(PORTB,29)
10265 #define PORTB_PCR30 PORT_PCR_REG(PORTB,30)
10266 #define PORTB_PCR31 PORT_PCR_REG(PORTB,31)
10267 #define PORTB_GPCLR PORT_GPCLR_REG(PORTB)
10268 #define PORTB_GPCHR PORT_GPCHR_REG(PORTB)
10269 #define PORTB_ISFR PORT_ISFR_REG(PORTB)
10270 /* PORTC */
10271 #define PORTC_PCR0 PORT_PCR_REG(PORTC,0)
10272 #define PORTC_PCR1 PORT_PCR_REG(PORTC,1)
10273 #define PORTC_PCR2 PORT_PCR_REG(PORTC,2)
10274 #define PORTC_PCR3 PORT_PCR_REG(PORTC,3)
10275 #define PORTC_PCR4 PORT_PCR_REG(PORTC,4)
10276 #define PORTC_PCR5 PORT_PCR_REG(PORTC,5)
10277 #define PORTC_PCR6 PORT_PCR_REG(PORTC,6)
10278 #define PORTC_PCR7 PORT_PCR_REG(PORTC,7)
10279 #define PORTC_PCR8 PORT_PCR_REG(PORTC,8)
10280 #define PORTC_PCR9 PORT_PCR_REG(PORTC,9)
10281 #define PORTC_PCR10 PORT_PCR_REG(PORTC,10)
10282 #define PORTC_PCR11 PORT_PCR_REG(PORTC,11)
10283 #define PORTC_PCR12 PORT_PCR_REG(PORTC,12)
10284 #define PORTC_PCR13 PORT_PCR_REG(PORTC,13)
10285 #define PORTC_PCR14 PORT_PCR_REG(PORTC,14)
10286 #define PORTC_PCR15 PORT_PCR_REG(PORTC,15)
10287 #define PORTC_PCR16 PORT_PCR_REG(PORTC,16)
10288 #define PORTC_PCR17 PORT_PCR_REG(PORTC,17)
10289 #define PORTC_PCR18 PORT_PCR_REG(PORTC,18)
10290 #define PORTC_PCR19 PORT_PCR_REG(PORTC,19)
10291 #define PORTC_PCR20 PORT_PCR_REG(PORTC,20)
10292 #define PORTC_PCR21 PORT_PCR_REG(PORTC,21)
10293 #define PORTC_PCR22 PORT_PCR_REG(PORTC,22)
10294 #define PORTC_PCR23 PORT_PCR_REG(PORTC,23)
10295 #define PORTC_PCR24 PORT_PCR_REG(PORTC,24)
10296 #define PORTC_PCR25 PORT_PCR_REG(PORTC,25)
10297 #define PORTC_PCR26 PORT_PCR_REG(PORTC,26)
10298 #define PORTC_PCR27 PORT_PCR_REG(PORTC,27)
10299 #define PORTC_PCR28 PORT_PCR_REG(PORTC,28)
10300 #define PORTC_PCR29 PORT_PCR_REG(PORTC,29)
10301 #define PORTC_PCR30 PORT_PCR_REG(PORTC,30)
10302 #define PORTC_PCR31 PORT_PCR_REG(PORTC,31)
10303 #define PORTC_GPCLR PORT_GPCLR_REG(PORTC)
10304 #define PORTC_GPCHR PORT_GPCHR_REG(PORTC)
10305 #define PORTC_ISFR PORT_ISFR_REG(PORTC)
10306 /* PORTD */
10307 #define PORTD_PCR0 PORT_PCR_REG(PORTD,0)
10308 #define PORTD_PCR1 PORT_PCR_REG(PORTD,1)
10309 #define PORTD_PCR2 PORT_PCR_REG(PORTD,2)
10310 #define PORTD_PCR3 PORT_PCR_REG(PORTD,3)
10311 #define PORTD_PCR4 PORT_PCR_REG(PORTD,4)
10312 #define PORTD_PCR5 PORT_PCR_REG(PORTD,5)
10313 #define PORTD_PCR6 PORT_PCR_REG(PORTD,6)
10314 #define PORTD_PCR7 PORT_PCR_REG(PORTD,7)
10315 #define PORTD_PCR8 PORT_PCR_REG(PORTD,8)
10316 #define PORTD_PCR9 PORT_PCR_REG(PORTD,9)
10317 #define PORTD_PCR10 PORT_PCR_REG(PORTD,10)
10318 #define PORTD_PCR11 PORT_PCR_REG(PORTD,11)
10319 #define PORTD_PCR12 PORT_PCR_REG(PORTD,12)
10320 #define PORTD_PCR13 PORT_PCR_REG(PORTD,13)
10321 #define PORTD_PCR14 PORT_PCR_REG(PORTD,14)
10322 #define PORTD_PCR15 PORT_PCR_REG(PORTD,15)
10323 #define PORTD_PCR16 PORT_PCR_REG(PORTD,16)
10324 #define PORTD_PCR17 PORT_PCR_REG(PORTD,17)
10325 #define PORTD_PCR18 PORT_PCR_REG(PORTD,18)
10326 #define PORTD_PCR19 PORT_PCR_REG(PORTD,19)
10327 #define PORTD_PCR20 PORT_PCR_REG(PORTD,20)
10328 #define PORTD_PCR21 PORT_PCR_REG(PORTD,21)
10329 #define PORTD_PCR22 PORT_PCR_REG(PORTD,22)
10330 #define PORTD_PCR23 PORT_PCR_REG(PORTD,23)
10331 #define PORTD_PCR24 PORT_PCR_REG(PORTD,24)
10332 #define PORTD_PCR25 PORT_PCR_REG(PORTD,25)
10333 #define PORTD_PCR26 PORT_PCR_REG(PORTD,26)
10334 #define PORTD_PCR27 PORT_PCR_REG(PORTD,27)
10335 #define PORTD_PCR28 PORT_PCR_REG(PORTD,28)
10336 #define PORTD_PCR29 PORT_PCR_REG(PORTD,29)
10337 #define PORTD_PCR30 PORT_PCR_REG(PORTD,30)
10338 #define PORTD_PCR31 PORT_PCR_REG(PORTD,31)
10339 #define PORTD_GPCLR PORT_GPCLR_REG(PORTD)
10340 #define PORTD_GPCHR PORT_GPCHR_REG(PORTD)
10341 #define PORTD_ISFR PORT_ISFR_REG(PORTD)
10342 #define PORTD_DFER PORT_DFER_REG(PORTD)
10343 #define PORTD_DFCR PORT_DFCR_REG(PORTD)
10344 #define PORTD_DFWR PORT_DFWR_REG(PORTD)
10345 /* PORTE */
10346 #define PORTE_PCR0 PORT_PCR_REG(PORTE,0)
10347 #define PORTE_PCR1 PORT_PCR_REG(PORTE,1)
10348 #define PORTE_PCR2 PORT_PCR_REG(PORTE,2)
10349 #define PORTE_PCR3 PORT_PCR_REG(PORTE,3)
10350 #define PORTE_PCR4 PORT_PCR_REG(PORTE,4)
10351 #define PORTE_PCR5 PORT_PCR_REG(PORTE,5)
10352 #define PORTE_PCR6 PORT_PCR_REG(PORTE,6)
10353 #define PORTE_PCR7 PORT_PCR_REG(PORTE,7)
10354 #define PORTE_PCR8 PORT_PCR_REG(PORTE,8)
10355 #define PORTE_PCR9 PORT_PCR_REG(PORTE,9)
10356 #define PORTE_PCR10 PORT_PCR_REG(PORTE,10)
10357 #define PORTE_PCR11 PORT_PCR_REG(PORTE,11)
10358 #define PORTE_PCR12 PORT_PCR_REG(PORTE,12)
10359 #define PORTE_PCR13 PORT_PCR_REG(PORTE,13)
10360 #define PORTE_PCR14 PORT_PCR_REG(PORTE,14)
10361 #define PORTE_PCR15 PORT_PCR_REG(PORTE,15)
10362 #define PORTE_PCR16 PORT_PCR_REG(PORTE,16)
10363 #define PORTE_PCR17 PORT_PCR_REG(PORTE,17)
10364 #define PORTE_PCR18 PORT_PCR_REG(PORTE,18)
10365 #define PORTE_PCR19 PORT_PCR_REG(PORTE,19)
10366 #define PORTE_PCR20 PORT_PCR_REG(PORTE,20)
10367 #define PORTE_PCR21 PORT_PCR_REG(PORTE,21)
10368 #define PORTE_PCR22 PORT_PCR_REG(PORTE,22)
10369 #define PORTE_PCR23 PORT_PCR_REG(PORTE,23)
10370 #define PORTE_PCR24 PORT_PCR_REG(PORTE,24)
10371 #define PORTE_PCR25 PORT_PCR_REG(PORTE,25)
10372 #define PORTE_PCR26 PORT_PCR_REG(PORTE,26)
10373 #define PORTE_PCR27 PORT_PCR_REG(PORTE,27)
10374 #define PORTE_PCR28 PORT_PCR_REG(PORTE,28)
10375 #define PORTE_PCR29 PORT_PCR_REG(PORTE,29)
10376 #define PORTE_PCR30 PORT_PCR_REG(PORTE,30)
10377 #define PORTE_PCR31 PORT_PCR_REG(PORTE,31)
10378 #define PORTE_GPCLR PORT_GPCLR_REG(PORTE)
10379 #define PORTE_GPCHR PORT_GPCHR_REG(PORTE)
10380 #define PORTE_ISFR PORT_ISFR_REG(PORTE)
10381
10382 /* PORT - Register array accessors */
10383 #define PORTA_PCR(index) PORT_PCR_REG(PORTA,index)
10384 #define PORTB_PCR(index) PORT_PCR_REG(PORTB,index)
10385 #define PORTC_PCR(index) PORT_PCR_REG(PORTC,index)
10386 #define PORTD_PCR(index) PORT_PCR_REG(PORTD,index)
10387 #define PORTE_PCR(index) PORT_PCR_REG(PORTE,index)
10388
10389 /*!
10390 * @}
10391 */ /* end of group PORT_Register_Accessor_Macros */
10392
10393
10394 /*!
10395 * @}
10396 */ /* end of group PORT_Peripheral_Access_Layer */
10397
10398
10399 /* ----------------------------------------------------------------------------
10400 -- RCM Peripheral Access Layer
10401 ---------------------------------------------------------------------------- */
10402
10403 /*!
10404 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
10405 * @{
10406 */
10407
10408 /** RCM - Register Layout Typedef */
10409 typedef struct {
10410 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
10411 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
10412 uint8_t RESERVED_0[2];
10413 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
10414 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
10415 uint8_t RESERVED_1[1];
10416 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
10417 } RCM_Type, *RCM_MemMapPtr;
10418
10419 /* ----------------------------------------------------------------------------
10420 -- RCM - Register accessor macros
10421 ---------------------------------------------------------------------------- */
10422
10423 /*!
10424 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
10425 * @{
10426 */
10427
10428
10429 /* RCM - Register accessors */
10430 #define RCM_SRS0_REG(base) ((base)->SRS0)
10431 #define RCM_SRS1_REG(base) ((base)->SRS1)
10432 #define RCM_RPFC_REG(base) ((base)->RPFC)
10433 #define RCM_RPFW_REG(base) ((base)->RPFW)
10434 #define RCM_MR_REG(base) ((base)->MR)
10435
10436 /*!
10437 * @}
10438 */ /* end of group RCM_Register_Accessor_Macros */
10439
10440
10441 /* ----------------------------------------------------------------------------
10442 -- RCM Register Masks
10443 ---------------------------------------------------------------------------- */
10444
10445 /*!
10446 * @addtogroup RCM_Register_Masks RCM Register Masks
10447 * @{
10448 */
10449
10450 /* SRS0 Bit Fields */
10451 #define RCM_SRS0_WAKEUP_MASK 0x1u
10452 #define RCM_SRS0_WAKEUP_SHIFT 0
10453 #define RCM_SRS0_LVD_MASK 0x2u
10454 #define RCM_SRS0_LVD_SHIFT 1
10455 #define RCM_SRS0_LOC_MASK 0x4u
10456 #define RCM_SRS0_LOC_SHIFT 2
10457 #define RCM_SRS0_LOL_MASK 0x8u
10458 #define RCM_SRS0_LOL_SHIFT 3
10459 #define RCM_SRS0_WDOG_MASK 0x20u
10460 #define RCM_SRS0_WDOG_SHIFT 5
10461 #define RCM_SRS0_PIN_MASK 0x40u
10462 #define RCM_SRS0_PIN_SHIFT 6
10463 #define RCM_SRS0_POR_MASK 0x80u
10464 #define RCM_SRS0_POR_SHIFT 7
10465 /* SRS1 Bit Fields */
10466 #define RCM_SRS1_JTAG_MASK 0x1u
10467 #define RCM_SRS1_JTAG_SHIFT 0
10468 #define RCM_SRS1_LOCKUP_MASK 0x2u
10469 #define RCM_SRS1_LOCKUP_SHIFT 1
10470 #define RCM_SRS1_SW_MASK 0x4u
10471 #define RCM_SRS1_SW_SHIFT 2
10472 #define RCM_SRS1_MDM_AP_MASK 0x8u
10473 #define RCM_SRS1_MDM_AP_SHIFT 3
10474 #define RCM_SRS1_EZPT_MASK 0x10u
10475 #define RCM_SRS1_EZPT_SHIFT 4
10476 #define RCM_SRS1_SACKERR_MASK 0x20u
10477 #define RCM_SRS1_SACKERR_SHIFT 5
10478 /* RPFC Bit Fields */
10479 #define RCM_RPFC_RSTFLTSRW_MASK 0x3u
10480 #define RCM_RPFC_RSTFLTSRW_SHIFT 0
10481 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
10482 #define RCM_RPFC_RSTFLTSS_MASK 0x4u
10483 #define RCM_RPFC_RSTFLTSS_SHIFT 2
10484 /* RPFW Bit Fields */
10485 #define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
10486 #define RCM_RPFW_RSTFLTSEL_SHIFT 0
10487 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
10488 /* MR Bit Fields */
10489 #define RCM_MR_EZP_MS_MASK 0x2u
10490 #define RCM_MR_EZP_MS_SHIFT 1
10491
10492 /*!
10493 * @}
10494 */ /* end of group RCM_Register_Masks */
10495
10496
10497 /* RCM - Peripheral instance base addresses */
10498 /** Peripheral RCM base address */
10499 #define RCM_BASE (0x4007F000u)
10500 /** Peripheral RCM base pointer */
10501 #define RCM ((RCM_Type *)RCM_BASE)
10502 #define RCM_BASE_PTR (RCM)
10503 /** Array initializer of RCM peripheral base addresses */
10504 #define RCM_BASE_ADDRS { RCM_BASE }
10505 /** Array initializer of RCM peripheral base pointers */
10506 #define RCM_BASE_PTRS { RCM }
10507
10508 /* ----------------------------------------------------------------------------
10509 -- RCM - Register accessor macros
10510 ---------------------------------------------------------------------------- */
10511
10512 /*!
10513 * @addtogroup RCM_Register_Accessor_Macros RCM - Register accessor macros
10514 * @{
10515 */
10516
10517
10518 /* RCM - Register instance definitions */
10519 /* RCM */
10520 #define RCM_SRS0 RCM_SRS0_REG(RCM)
10521 #define RCM_SRS1 RCM_SRS1_REG(RCM)
10522 #define RCM_RPFC RCM_RPFC_REG(RCM)
10523 #define RCM_RPFW RCM_RPFW_REG(RCM)
10524 #define RCM_MR RCM_MR_REG(RCM)
10525
10526 /*!
10527 * @}
10528 */ /* end of group RCM_Register_Accessor_Macros */
10529
10530
10531 /*!
10532 * @}
10533 */ /* end of group RCM_Peripheral_Access_Layer */
10534
10535
10536 /* ----------------------------------------------------------------------------
10537 -- RFSYS Peripheral Access Layer
10538 ---------------------------------------------------------------------------- */
10539
10540 /*!
10541 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
10542 * @{
10543 */
10544
10545 /** RFSYS - Register Layout Typedef */
10546 typedef struct {
10547 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
10548 } RFSYS_Type, *RFSYS_MemMapPtr;
10549
10550 /* ----------------------------------------------------------------------------
10551 -- RFSYS - Register accessor macros
10552 ---------------------------------------------------------------------------- */
10553
10554 /*!
10555 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
10556 * @{
10557 */
10558
10559
10560 /* RFSYS - Register accessors */
10561 #define RFSYS_REG_REG(base,index) ((base)->REG[index])
10562
10563 /*!
10564 * @}
10565 */ /* end of group RFSYS_Register_Accessor_Macros */
10566
10567
10568 /* ----------------------------------------------------------------------------
10569 -- RFSYS Register Masks
10570 ---------------------------------------------------------------------------- */
10571
10572 /*!
10573 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
10574 * @{
10575 */
10576
10577 /* REG Bit Fields */
10578 #define RFSYS_REG_LL_MASK 0xFFu
10579 #define RFSYS_REG_LL_SHIFT 0
10580 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LL_SHIFT))&RFSYS_REG_LL_MASK)
10581 #define RFSYS_REG_LH_MASK 0xFF00u
10582 #define RFSYS_REG_LH_SHIFT 8
10583 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_LH_SHIFT))&RFSYS_REG_LH_MASK)
10584 #define RFSYS_REG_HL_MASK 0xFF0000u
10585 #define RFSYS_REG_HL_SHIFT 16
10586 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HL_SHIFT))&RFSYS_REG_HL_MASK)
10587 #define RFSYS_REG_HH_MASK 0xFF000000u
10588 #define RFSYS_REG_HH_SHIFT 24
10589 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFSYS_REG_HH_SHIFT))&RFSYS_REG_HH_MASK)
10590
10591 /*!
10592 * @}
10593 */ /* end of group RFSYS_Register_Masks */
10594
10595
10596 /* RFSYS - Peripheral instance base addresses */
10597 /** Peripheral RFSYS base address */
10598 #define RFSYS_BASE (0x40041000u)
10599 /** Peripheral RFSYS base pointer */
10600 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
10601 #define RFSYS_BASE_PTR (RFSYS)
10602 /** Array initializer of RFSYS peripheral base addresses */
10603 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
10604 /** Array initializer of RFSYS peripheral base pointers */
10605 #define RFSYS_BASE_PTRS { RFSYS }
10606
10607 /* ----------------------------------------------------------------------------
10608 -- RFSYS - Register accessor macros
10609 ---------------------------------------------------------------------------- */
10610
10611 /*!
10612 * @addtogroup RFSYS_Register_Accessor_Macros RFSYS - Register accessor macros
10613 * @{
10614 */
10615
10616
10617 /* RFSYS - Register instance definitions */
10618 /* RFSYS */
10619 #define RFSYS_REG0 RFSYS_REG_REG(RFSYS,0)
10620 #define RFSYS_REG1 RFSYS_REG_REG(RFSYS,1)
10621 #define RFSYS_REG2 RFSYS_REG_REG(RFSYS,2)
10622 #define RFSYS_REG3 RFSYS_REG_REG(RFSYS,3)
10623 #define RFSYS_REG4 RFSYS_REG_REG(RFSYS,4)
10624 #define RFSYS_REG5 RFSYS_REG_REG(RFSYS,5)
10625 #define RFSYS_REG6 RFSYS_REG_REG(RFSYS,6)
10626 #define RFSYS_REG7 RFSYS_REG_REG(RFSYS,7)
10627
10628 /* RFSYS - Register array accessors */
10629 #define RFSYS_REG(index) RFSYS_REG_REG(RFSYS,index)
10630
10631 /*!
10632 * @}
10633 */ /* end of group RFSYS_Register_Accessor_Macros */
10634
10635
10636 /*!
10637 * @}
10638 */ /* end of group RFSYS_Peripheral_Access_Layer */
10639
10640
10641 /* ----------------------------------------------------------------------------
10642 -- RFVBAT Peripheral Access Layer
10643 ---------------------------------------------------------------------------- */
10644
10645 /*!
10646 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
10647 * @{
10648 */
10649
10650 /** RFVBAT - Register Layout Typedef */
10651 typedef struct {
10652 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
10653 } RFVBAT_Type, *RFVBAT_MemMapPtr;
10654
10655 /* ----------------------------------------------------------------------------
10656 -- RFVBAT - Register accessor macros
10657 ---------------------------------------------------------------------------- */
10658
10659 /*!
10660 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
10661 * @{
10662 */
10663
10664
10665 /* RFVBAT - Register accessors */
10666 #define RFVBAT_REG_REG(base,index) ((base)->REG[index])
10667
10668 /*!
10669 * @}
10670 */ /* end of group RFVBAT_Register_Accessor_Macros */
10671
10672
10673 /* ----------------------------------------------------------------------------
10674 -- RFVBAT Register Masks
10675 ---------------------------------------------------------------------------- */
10676
10677 /*!
10678 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
10679 * @{
10680 */
10681
10682 /* REG Bit Fields */
10683 #define RFVBAT_REG_LL_MASK 0xFFu
10684 #define RFVBAT_REG_LL_SHIFT 0
10685 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LL_SHIFT))&RFVBAT_REG_LL_MASK)
10686 #define RFVBAT_REG_LH_MASK 0xFF00u
10687 #define RFVBAT_REG_LH_SHIFT 8
10688 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_LH_SHIFT))&RFVBAT_REG_LH_MASK)
10689 #define RFVBAT_REG_HL_MASK 0xFF0000u
10690 #define RFVBAT_REG_HL_SHIFT 16
10691 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HL_SHIFT))&RFVBAT_REG_HL_MASK)
10692 #define RFVBAT_REG_HH_MASK 0xFF000000u
10693 #define RFVBAT_REG_HH_SHIFT 24
10694 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x))<<RFVBAT_REG_HH_SHIFT))&RFVBAT_REG_HH_MASK)
10695
10696 /*!
10697 * @}
10698 */ /* end of group RFVBAT_Register_Masks */
10699
10700
10701 /* RFVBAT - Peripheral instance base addresses */
10702 /** Peripheral RFVBAT base address */
10703 #define RFVBAT_BASE (0x4003E000u)
10704 /** Peripheral RFVBAT base pointer */
10705 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
10706 #define RFVBAT_BASE_PTR (RFVBAT)
10707 /** Array initializer of RFVBAT peripheral base addresses */
10708 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
10709 /** Array initializer of RFVBAT peripheral base pointers */
10710 #define RFVBAT_BASE_PTRS { RFVBAT }
10711
10712 /* ----------------------------------------------------------------------------
10713 -- RFVBAT - Register accessor macros
10714 ---------------------------------------------------------------------------- */
10715
10716 /*!
10717 * @addtogroup RFVBAT_Register_Accessor_Macros RFVBAT - Register accessor macros
10718 * @{
10719 */
10720
10721
10722 /* RFVBAT - Register instance definitions */
10723 /* RFVBAT */
10724 #define RFVBAT_REG0 RFVBAT_REG_REG(RFVBAT,0)
10725 #define RFVBAT_REG1 RFVBAT_REG_REG(RFVBAT,1)
10726 #define RFVBAT_REG2 RFVBAT_REG_REG(RFVBAT,2)
10727 #define RFVBAT_REG3 RFVBAT_REG_REG(RFVBAT,3)
10728 #define RFVBAT_REG4 RFVBAT_REG_REG(RFVBAT,4)
10729 #define RFVBAT_REG5 RFVBAT_REG_REG(RFVBAT,5)
10730 #define RFVBAT_REG6 RFVBAT_REG_REG(RFVBAT,6)
10731 #define RFVBAT_REG7 RFVBAT_REG_REG(RFVBAT,7)
10732
10733 /* RFVBAT - Register array accessors */
10734 #define RFVBAT_REG(index) RFVBAT_REG_REG(RFVBAT,index)
10735
10736 /*!
10737 * @}
10738 */ /* end of group RFVBAT_Register_Accessor_Macros */
10739
10740
10741 /*!
10742 * @}
10743 */ /* end of group RFVBAT_Peripheral_Access_Layer */
10744
10745
10746 /* ----------------------------------------------------------------------------
10747 -- RNG Peripheral Access Layer
10748 ---------------------------------------------------------------------------- */
10749
10750 /*!
10751 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
10752 * @{
10753 */
10754
10755 /** RNG - Register Layout Typedef */
10756 typedef struct {
10757 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
10758 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
10759 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
10760 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
10761 } RNG_Type, *RNG_MemMapPtr;
10762
10763 /* ----------------------------------------------------------------------------
10764 -- RNG - Register accessor macros
10765 ---------------------------------------------------------------------------- */
10766
10767 /*!
10768 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
10769 * @{
10770 */
10771
10772
10773 /* RNG - Register accessors */
10774 #define RNG_CR_REG(base) ((base)->CR)
10775 #define RNG_SR_REG(base) ((base)->SR)
10776 #define RNG_ER_REG(base) ((base)->ER)
10777 #define RNG_OR_REG(base) ((base)->OR)
10778
10779 /*!
10780 * @}
10781 */ /* end of group RNG_Register_Accessor_Macros */
10782
10783
10784 /* ----------------------------------------------------------------------------
10785 -- RNG Register Masks
10786 ---------------------------------------------------------------------------- */
10787
10788 /*!
10789 * @addtogroup RNG_Register_Masks RNG Register Masks
10790 * @{
10791 */
10792
10793 /* CR Bit Fields */
10794 #define RNG_CR_GO_MASK 0x1u
10795 #define RNG_CR_GO_SHIFT 0
10796 #define RNG_CR_HA_MASK 0x2u
10797 #define RNG_CR_HA_SHIFT 1
10798 #define RNG_CR_INTM_MASK 0x4u
10799 #define RNG_CR_INTM_SHIFT 2
10800 #define RNG_CR_CLRI_MASK 0x8u
10801 #define RNG_CR_CLRI_SHIFT 3
10802 #define RNG_CR_SLP_MASK 0x10u
10803 #define RNG_CR_SLP_SHIFT 4
10804 /* SR Bit Fields */
10805 #define RNG_SR_SECV_MASK 0x1u
10806 #define RNG_SR_SECV_SHIFT 0
10807 #define RNG_SR_LRS_MASK 0x2u
10808 #define RNG_SR_LRS_SHIFT 1
10809 #define RNG_SR_ORU_MASK 0x4u
10810 #define RNG_SR_ORU_SHIFT 2
10811 #define RNG_SR_ERRI_MASK 0x8u
10812 #define RNG_SR_ERRI_SHIFT 3
10813 #define RNG_SR_SLP_MASK 0x10u
10814 #define RNG_SR_SLP_SHIFT 4
10815 #define RNG_SR_OREG_LVL_MASK 0xFF00u
10816 #define RNG_SR_OREG_LVL_SHIFT 8
10817 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_LVL_SHIFT))&RNG_SR_OREG_LVL_MASK)
10818 #define RNG_SR_OREG_SIZE_MASK 0xFF0000u
10819 #define RNG_SR_OREG_SIZE_SHIFT 16
10820 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x))<<RNG_SR_OREG_SIZE_SHIFT))&RNG_SR_OREG_SIZE_MASK)
10821 /* ER Bit Fields */
10822 #define RNG_ER_EXT_ENT_MASK 0xFFFFFFFFu
10823 #define RNG_ER_EXT_ENT_SHIFT 0
10824 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x))<<RNG_ER_EXT_ENT_SHIFT))&RNG_ER_EXT_ENT_MASK)
10825 /* OR Bit Fields */
10826 #define RNG_OR_RANDOUT_MASK 0xFFFFFFFFu
10827 #define RNG_OR_RANDOUT_SHIFT 0
10828 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x))<<RNG_OR_RANDOUT_SHIFT))&RNG_OR_RANDOUT_MASK)
10829
10830 /*!
10831 * @}
10832 */ /* end of group RNG_Register_Masks */
10833
10834
10835 /* RNG - Peripheral instance base addresses */
10836 /** Peripheral RNG base address */
10837 #define RNG_BASE (0x40029000u)
10838 /** Peripheral RNG base pointer */
10839 #define RNG ((RNG_Type *)RNG_BASE)
10840 #define RNG_BASE_PTR (RNG)
10841 /** Array initializer of RNG peripheral base addresses */
10842 #define RNG_BASE_ADDRS { RNG_BASE }
10843 /** Array initializer of RNG peripheral base pointers */
10844 #define RNG_BASE_PTRS { RNG }
10845 /** Interrupt vectors for the RNG peripheral type */
10846 #define RNG_IRQS { RNG_IRQn }
10847
10848 /* ----------------------------------------------------------------------------
10849 -- RNG - Register accessor macros
10850 ---------------------------------------------------------------------------- */
10851
10852 /*!
10853 * @addtogroup RNG_Register_Accessor_Macros RNG - Register accessor macros
10854 * @{
10855 */
10856
10857
10858 /* RNG - Register instance definitions */
10859 /* RNG */
10860 #define RNG_CR RNG_CR_REG(RNG)
10861 #define RNG_SR RNG_SR_REG(RNG)
10862 #define RNG_ER RNG_ER_REG(RNG)
10863 #define RNG_OR RNG_OR_REG(RNG)
10864
10865 /*!
10866 * @}
10867 */ /* end of group RNG_Register_Accessor_Macros */
10868
10869
10870 /*!
10871 * @}
10872 */ /* end of group RNG_Peripheral_Access_Layer */
10873
10874
10875 /* ----------------------------------------------------------------------------
10876 -- RTC Peripheral Access Layer
10877 ---------------------------------------------------------------------------- */
10878
10879 /*!
10880 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
10881 * @{
10882 */
10883
10884 /** RTC - Register Layout Typedef */
10885 typedef struct {
10886 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
10887 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
10888 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
10889 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
10890 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
10891 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
10892 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
10893 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
10894 uint8_t RESERVED_0[2016];
10895 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
10896 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
10897 } RTC_Type, *RTC_MemMapPtr;
10898
10899 /* ----------------------------------------------------------------------------
10900 -- RTC - Register accessor macros
10901 ---------------------------------------------------------------------------- */
10902
10903 /*!
10904 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
10905 * @{
10906 */
10907
10908
10909 /* RTC - Register accessors */
10910 #define RTC_TSR_REG(base) ((base)->TSR)
10911 #define RTC_TPR_REG(base) ((base)->TPR)
10912 #define RTC_TAR_REG(base) ((base)->TAR)
10913 #define RTC_TCR_REG(base) ((base)->TCR)
10914 #define RTC_CR_REG(base) ((base)->CR)
10915 #define RTC_SR_REG(base) ((base)->SR)
10916 #define RTC_LR_REG(base) ((base)->LR)
10917 #define RTC_IER_REG(base) ((base)->IER)
10918 #define RTC_WAR_REG(base) ((base)->WAR)
10919 #define RTC_RAR_REG(base) ((base)->RAR)
10920
10921 /*!
10922 * @}
10923 */ /* end of group RTC_Register_Accessor_Macros */
10924
10925
10926 /* ----------------------------------------------------------------------------
10927 -- RTC Register Masks
10928 ---------------------------------------------------------------------------- */
10929
10930 /*!
10931 * @addtogroup RTC_Register_Masks RTC Register Masks
10932 * @{
10933 */
10934
10935 /* TSR Bit Fields */
10936 #define RTC_TSR_TSR_MASK 0xFFFFFFFFu
10937 #define RTC_TSR_TSR_SHIFT 0
10938 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
10939 /* TPR Bit Fields */
10940 #define RTC_TPR_TPR_MASK 0xFFFFu
10941 #define RTC_TPR_TPR_SHIFT 0
10942 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
10943 /* TAR Bit Fields */
10944 #define RTC_TAR_TAR_MASK 0xFFFFFFFFu
10945 #define RTC_TAR_TAR_SHIFT 0
10946 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
10947 /* TCR Bit Fields */
10948 #define RTC_TCR_TCR_MASK 0xFFu
10949 #define RTC_TCR_TCR_SHIFT 0
10950 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
10951 #define RTC_TCR_CIR_MASK 0xFF00u
10952 #define RTC_TCR_CIR_SHIFT 8
10953 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
10954 #define RTC_TCR_TCV_MASK 0xFF0000u
10955 #define RTC_TCR_TCV_SHIFT 16
10956 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
10957 #define RTC_TCR_CIC_MASK 0xFF000000u
10958 #define RTC_TCR_CIC_SHIFT 24
10959 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
10960 /* CR Bit Fields */
10961 #define RTC_CR_SWR_MASK 0x1u
10962 #define RTC_CR_SWR_SHIFT 0
10963 #define RTC_CR_WPE_MASK 0x2u
10964 #define RTC_CR_WPE_SHIFT 1
10965 #define RTC_CR_SUP_MASK 0x4u
10966 #define RTC_CR_SUP_SHIFT 2
10967 #define RTC_CR_UM_MASK 0x8u
10968 #define RTC_CR_UM_SHIFT 3
10969 #define RTC_CR_WPS_MASK 0x10u
10970 #define RTC_CR_WPS_SHIFT 4
10971 #define RTC_CR_OSCE_MASK 0x100u
10972 #define RTC_CR_OSCE_SHIFT 8
10973 #define RTC_CR_CLKO_MASK 0x200u
10974 #define RTC_CR_CLKO_SHIFT 9
10975 #define RTC_CR_SC16P_MASK 0x400u
10976 #define RTC_CR_SC16P_SHIFT 10
10977 #define RTC_CR_SC8P_MASK 0x800u
10978 #define RTC_CR_SC8P_SHIFT 11
10979 #define RTC_CR_SC4P_MASK 0x1000u
10980 #define RTC_CR_SC4P_SHIFT 12
10981 #define RTC_CR_SC2P_MASK 0x2000u
10982 #define RTC_CR_SC2P_SHIFT 13
10983 /* SR Bit Fields */
10984 #define RTC_SR_TIF_MASK 0x1u
10985 #define RTC_SR_TIF_SHIFT 0
10986 #define RTC_SR_TOF_MASK 0x2u
10987 #define RTC_SR_TOF_SHIFT 1
10988 #define RTC_SR_TAF_MASK 0x4u
10989 #define RTC_SR_TAF_SHIFT 2
10990 #define RTC_SR_TCE_MASK 0x10u
10991 #define RTC_SR_TCE_SHIFT 4
10992 /* LR Bit Fields */
10993 #define RTC_LR_TCL_MASK 0x8u
10994 #define RTC_LR_TCL_SHIFT 3
10995 #define RTC_LR_CRL_MASK 0x10u
10996 #define RTC_LR_CRL_SHIFT 4
10997 #define RTC_LR_SRL_MASK 0x20u
10998 #define RTC_LR_SRL_SHIFT 5
10999 #define RTC_LR_LRL_MASK 0x40u
11000 #define RTC_LR_LRL_SHIFT 6
11001 /* IER Bit Fields */
11002 #define RTC_IER_TIIE_MASK 0x1u
11003 #define RTC_IER_TIIE_SHIFT 0
11004 #define RTC_IER_TOIE_MASK 0x2u
11005 #define RTC_IER_TOIE_SHIFT 1
11006 #define RTC_IER_TAIE_MASK 0x4u
11007 #define RTC_IER_TAIE_SHIFT 2
11008 #define RTC_IER_TSIE_MASK 0x10u
11009 #define RTC_IER_TSIE_SHIFT 4
11010 #define RTC_IER_WPON_MASK 0x80u
11011 #define RTC_IER_WPON_SHIFT 7
11012 /* WAR Bit Fields */
11013 #define RTC_WAR_TSRW_MASK 0x1u
11014 #define RTC_WAR_TSRW_SHIFT 0
11015 #define RTC_WAR_TPRW_MASK 0x2u
11016 #define RTC_WAR_TPRW_SHIFT 1
11017 #define RTC_WAR_TARW_MASK 0x4u
11018 #define RTC_WAR_TARW_SHIFT 2
11019 #define RTC_WAR_TCRW_MASK 0x8u
11020 #define RTC_WAR_TCRW_SHIFT 3
11021 #define RTC_WAR_CRW_MASK 0x10u
11022 #define RTC_WAR_CRW_SHIFT 4
11023 #define RTC_WAR_SRW_MASK 0x20u
11024 #define RTC_WAR_SRW_SHIFT 5
11025 #define RTC_WAR_LRW_MASK 0x40u
11026 #define RTC_WAR_LRW_SHIFT 6
11027 #define RTC_WAR_IERW_MASK 0x80u
11028 #define RTC_WAR_IERW_SHIFT 7
11029 /* RAR Bit Fields */
11030 #define RTC_RAR_TSRR_MASK 0x1u
11031 #define RTC_RAR_TSRR_SHIFT 0
11032 #define RTC_RAR_TPRR_MASK 0x2u
11033 #define RTC_RAR_TPRR_SHIFT 1
11034 #define RTC_RAR_TARR_MASK 0x4u
11035 #define RTC_RAR_TARR_SHIFT 2
11036 #define RTC_RAR_TCRR_MASK 0x8u
11037 #define RTC_RAR_TCRR_SHIFT 3
11038 #define RTC_RAR_CRR_MASK 0x10u
11039 #define RTC_RAR_CRR_SHIFT 4
11040 #define RTC_RAR_SRR_MASK 0x20u
11041 #define RTC_RAR_SRR_SHIFT 5
11042 #define RTC_RAR_LRR_MASK 0x40u
11043 #define RTC_RAR_LRR_SHIFT 6
11044 #define RTC_RAR_IERR_MASK 0x80u
11045 #define RTC_RAR_IERR_SHIFT 7
11046
11047 /*!
11048 * @}
11049 */ /* end of group RTC_Register_Masks */
11050
11051
11052 /* RTC - Peripheral instance base addresses */
11053 /** Peripheral RTC base address */
11054 #define RTC_BASE (0x4003D000u)
11055 /** Peripheral RTC base pointer */
11056 #define RTC ((RTC_Type *)RTC_BASE)
11057 #define RTC_BASE_PTR (RTC)
11058 /** Array initializer of RTC peripheral base addresses */
11059 #define RTC_BASE_ADDRS { RTC_BASE }
11060 /** Array initializer of RTC peripheral base pointers */
11061 #define RTC_BASE_PTRS { RTC }
11062 /** Interrupt vectors for the RTC peripheral type */
11063 #define RTC_IRQS { RTC_IRQn }
11064 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
11065
11066 /* ----------------------------------------------------------------------------
11067 -- RTC - Register accessor macros
11068 ---------------------------------------------------------------------------- */
11069
11070 /*!
11071 * @addtogroup RTC_Register_Accessor_Macros RTC - Register accessor macros
11072 * @{
11073 */
11074
11075
11076 /* RTC - Register instance definitions */
11077 /* RTC */
11078 #define RTC_TSR RTC_TSR_REG(RTC)
11079 #define RTC_TPR RTC_TPR_REG(RTC)
11080 #define RTC_TAR RTC_TAR_REG(RTC)
11081 #define RTC_TCR RTC_TCR_REG(RTC)
11082 #define RTC_CR RTC_CR_REG(RTC)
11083 #define RTC_SR RTC_SR_REG(RTC)
11084 #define RTC_LR RTC_LR_REG(RTC)
11085 #define RTC_IER RTC_IER_REG(RTC)
11086 #define RTC_WAR RTC_WAR_REG(RTC)
11087 #define RTC_RAR RTC_RAR_REG(RTC)
11088
11089 /*!
11090 * @}
11091 */ /* end of group RTC_Register_Accessor_Macros */
11092
11093
11094 /*!
11095 * @}
11096 */ /* end of group RTC_Peripheral_Access_Layer */
11097
11098
11099 /* ----------------------------------------------------------------------------
11100 -- SDHC Peripheral Access Layer
11101 ---------------------------------------------------------------------------- */
11102
11103 /*!
11104 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
11105 * @{
11106 */
11107
11108 /** SDHC - Register Layout Typedef */
11109 typedef struct {
11110 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
11111 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
11112 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
11113 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
11114 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
11115 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
11116 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
11117 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
11118 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
11119 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
11120 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
11121 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
11122 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
11123 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
11124 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
11125 uint8_t RESERVED_0[8];
11126 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
11127 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
11128 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
11129 uint8_t RESERVED_1[100];
11130 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
11131 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
11132 uint8_t RESERVED_2[52];
11133 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
11134 } SDHC_Type, *SDHC_MemMapPtr;
11135
11136 /* ----------------------------------------------------------------------------
11137 -- SDHC - Register accessor macros
11138 ---------------------------------------------------------------------------- */
11139
11140 /*!
11141 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
11142 * @{
11143 */
11144
11145
11146 /* SDHC - Register accessors */
11147 #define SDHC_DSADDR_REG(base) ((base)->DSADDR)
11148 #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR)
11149 #define SDHC_CMDARG_REG(base) ((base)->CMDARG)
11150 #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP)
11151 #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index])
11152 #define SDHC_DATPORT_REG(base) ((base)->DATPORT)
11153 #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT)
11154 #define SDHC_PROCTL_REG(base) ((base)->PROCTL)
11155 #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL)
11156 #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT)
11157 #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN)
11158 #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN)
11159 #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR)
11160 #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT)
11161 #define SDHC_WML_REG(base) ((base)->WML)
11162 #define SDHC_FEVT_REG(base) ((base)->FEVT)
11163 #define SDHC_ADMAES_REG(base) ((base)->ADMAES)
11164 #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR)
11165 #define SDHC_VENDOR_REG(base) ((base)->VENDOR)
11166 #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT)
11167 #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER)
11168
11169 /*!
11170 * @}
11171 */ /* end of group SDHC_Register_Accessor_Macros */
11172
11173
11174 /* ----------------------------------------------------------------------------
11175 -- SDHC Register Masks
11176 ---------------------------------------------------------------------------- */
11177
11178 /*!
11179 * @addtogroup SDHC_Register_Masks SDHC Register Masks
11180 * @{
11181 */
11182
11183 /* DSADDR Bit Fields */
11184 #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu
11185 #define SDHC_DSADDR_DSADDR_SHIFT 2
11186 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DSADDR_DSADDR_SHIFT))&SDHC_DSADDR_DSADDR_MASK)
11187 /* BLKATTR Bit Fields */
11188 #define SDHC_BLKATTR_BLKSIZE_MASK 0x1FFFu
11189 #define SDHC_BLKATTR_BLKSIZE_SHIFT 0
11190 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKSIZE_SHIFT))&SDHC_BLKATTR_BLKSIZE_MASK)
11191 #define SDHC_BLKATTR_BLKCNT_MASK 0xFFFF0000u
11192 #define SDHC_BLKATTR_BLKCNT_SHIFT 16
11193 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_BLKATTR_BLKCNT_SHIFT))&SDHC_BLKATTR_BLKCNT_MASK)
11194 /* CMDARG Bit Fields */
11195 #define SDHC_CMDARG_CMDARG_MASK 0xFFFFFFFFu
11196 #define SDHC_CMDARG_CMDARG_SHIFT 0
11197 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDARG_CMDARG_SHIFT))&SDHC_CMDARG_CMDARG_MASK)
11198 /* XFERTYP Bit Fields */
11199 #define SDHC_XFERTYP_DMAEN_MASK 0x1u
11200 #define SDHC_XFERTYP_DMAEN_SHIFT 0
11201 #define SDHC_XFERTYP_BCEN_MASK 0x2u
11202 #define SDHC_XFERTYP_BCEN_SHIFT 1
11203 #define SDHC_XFERTYP_AC12EN_MASK 0x4u
11204 #define SDHC_XFERTYP_AC12EN_SHIFT 2
11205 #define SDHC_XFERTYP_DTDSEL_MASK 0x10u
11206 #define SDHC_XFERTYP_DTDSEL_SHIFT 4
11207 #define SDHC_XFERTYP_MSBSEL_MASK 0x20u
11208 #define SDHC_XFERTYP_MSBSEL_SHIFT 5
11209 #define SDHC_XFERTYP_RSPTYP_MASK 0x30000u
11210 #define SDHC_XFERTYP_RSPTYP_SHIFT 16
11211 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_RSPTYP_SHIFT))&SDHC_XFERTYP_RSPTYP_MASK)
11212 #define SDHC_XFERTYP_CCCEN_MASK 0x80000u
11213 #define SDHC_XFERTYP_CCCEN_SHIFT 19
11214 #define SDHC_XFERTYP_CICEN_MASK 0x100000u
11215 #define SDHC_XFERTYP_CICEN_SHIFT 20
11216 #define SDHC_XFERTYP_DPSEL_MASK 0x200000u
11217 #define SDHC_XFERTYP_DPSEL_SHIFT 21
11218 #define SDHC_XFERTYP_CMDTYP_MASK 0xC00000u
11219 #define SDHC_XFERTYP_CMDTYP_SHIFT 22
11220 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDTYP_SHIFT))&SDHC_XFERTYP_CMDTYP_MASK)
11221 #define SDHC_XFERTYP_CMDINX_MASK 0x3F000000u
11222 #define SDHC_XFERTYP_CMDINX_SHIFT 24
11223 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x))<<SDHC_XFERTYP_CMDINX_SHIFT))&SDHC_XFERTYP_CMDINX_MASK)
11224 /* CMDRSP Bit Fields */
11225 #define SDHC_CMDRSP_CMDRSP0_MASK 0xFFFFFFFFu
11226 #define SDHC_CMDRSP_CMDRSP0_SHIFT 0
11227 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP0_SHIFT))&SDHC_CMDRSP_CMDRSP0_MASK)
11228 #define SDHC_CMDRSP_CMDRSP1_MASK 0xFFFFFFFFu
11229 #define SDHC_CMDRSP_CMDRSP1_SHIFT 0
11230 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP1_SHIFT))&SDHC_CMDRSP_CMDRSP1_MASK)
11231 #define SDHC_CMDRSP_CMDRSP2_MASK 0xFFFFFFFFu
11232 #define SDHC_CMDRSP_CMDRSP2_SHIFT 0
11233 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP2_SHIFT))&SDHC_CMDRSP_CMDRSP2_MASK)
11234 #define SDHC_CMDRSP_CMDRSP3_MASK 0xFFFFFFFFu
11235 #define SDHC_CMDRSP_CMDRSP3_SHIFT 0
11236 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x))<<SDHC_CMDRSP_CMDRSP3_SHIFT))&SDHC_CMDRSP_CMDRSP3_MASK)
11237 /* DATPORT Bit Fields */
11238 #define SDHC_DATPORT_DATCONT_MASK 0xFFFFFFFFu
11239 #define SDHC_DATPORT_DATCONT_SHIFT 0
11240 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_DATPORT_DATCONT_SHIFT))&SDHC_DATPORT_DATCONT_MASK)
11241 /* PRSSTAT Bit Fields */
11242 #define SDHC_PRSSTAT_CIHB_MASK 0x1u
11243 #define SDHC_PRSSTAT_CIHB_SHIFT 0
11244 #define SDHC_PRSSTAT_CDIHB_MASK 0x2u
11245 #define SDHC_PRSSTAT_CDIHB_SHIFT 1
11246 #define SDHC_PRSSTAT_DLA_MASK 0x4u
11247 #define SDHC_PRSSTAT_DLA_SHIFT 2
11248 #define SDHC_PRSSTAT_SDSTB_MASK 0x8u
11249 #define SDHC_PRSSTAT_SDSTB_SHIFT 3
11250 #define SDHC_PRSSTAT_IPGOFF_MASK 0x10u
11251 #define SDHC_PRSSTAT_IPGOFF_SHIFT 4
11252 #define SDHC_PRSSTAT_HCKOFF_MASK 0x20u
11253 #define SDHC_PRSSTAT_HCKOFF_SHIFT 5
11254 #define SDHC_PRSSTAT_PEROFF_MASK 0x40u
11255 #define SDHC_PRSSTAT_PEROFF_SHIFT 6
11256 #define SDHC_PRSSTAT_SDOFF_MASK 0x80u
11257 #define SDHC_PRSSTAT_SDOFF_SHIFT 7
11258 #define SDHC_PRSSTAT_WTA_MASK 0x100u
11259 #define SDHC_PRSSTAT_WTA_SHIFT 8
11260 #define SDHC_PRSSTAT_RTA_MASK 0x200u
11261 #define SDHC_PRSSTAT_RTA_SHIFT 9
11262 #define SDHC_PRSSTAT_BWEN_MASK 0x400u
11263 #define SDHC_PRSSTAT_BWEN_SHIFT 10
11264 #define SDHC_PRSSTAT_BREN_MASK 0x800u
11265 #define SDHC_PRSSTAT_BREN_SHIFT 11
11266 #define SDHC_PRSSTAT_CINS_MASK 0x10000u
11267 #define SDHC_PRSSTAT_CINS_SHIFT 16
11268 #define SDHC_PRSSTAT_CLSL_MASK 0x800000u
11269 #define SDHC_PRSSTAT_CLSL_SHIFT 23
11270 #define SDHC_PRSSTAT_DLSL_MASK 0xFF000000u
11271 #define SDHC_PRSSTAT_DLSL_SHIFT 24
11272 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PRSSTAT_DLSL_SHIFT))&SDHC_PRSSTAT_DLSL_MASK)
11273 /* PROCTL Bit Fields */
11274 #define SDHC_PROCTL_LCTL_MASK 0x1u
11275 #define SDHC_PROCTL_LCTL_SHIFT 0
11276 #define SDHC_PROCTL_DTW_MASK 0x6u
11277 #define SDHC_PROCTL_DTW_SHIFT 1
11278 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DTW_SHIFT))&SDHC_PROCTL_DTW_MASK)
11279 #define SDHC_PROCTL_D3CD_MASK 0x8u
11280 #define SDHC_PROCTL_D3CD_SHIFT 3
11281 #define SDHC_PROCTL_EMODE_MASK 0x30u
11282 #define SDHC_PROCTL_EMODE_SHIFT 4
11283 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_EMODE_SHIFT))&SDHC_PROCTL_EMODE_MASK)
11284 #define SDHC_PROCTL_CDTL_MASK 0x40u
11285 #define SDHC_PROCTL_CDTL_SHIFT 6
11286 #define SDHC_PROCTL_CDSS_MASK 0x80u
11287 #define SDHC_PROCTL_CDSS_SHIFT 7
11288 #define SDHC_PROCTL_DMAS_MASK 0x300u
11289 #define SDHC_PROCTL_DMAS_SHIFT 8
11290 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_PROCTL_DMAS_SHIFT))&SDHC_PROCTL_DMAS_MASK)
11291 #define SDHC_PROCTL_SABGREQ_MASK 0x10000u
11292 #define SDHC_PROCTL_SABGREQ_SHIFT 16
11293 #define SDHC_PROCTL_CREQ_MASK 0x20000u
11294 #define SDHC_PROCTL_CREQ_SHIFT 17
11295 #define SDHC_PROCTL_RWCTL_MASK 0x40000u
11296 #define SDHC_PROCTL_RWCTL_SHIFT 18
11297 #define SDHC_PROCTL_IABG_MASK 0x80000u
11298 #define SDHC_PROCTL_IABG_SHIFT 19
11299 #define SDHC_PROCTL_WECINT_MASK 0x1000000u
11300 #define SDHC_PROCTL_WECINT_SHIFT 24
11301 #define SDHC_PROCTL_WECINS_MASK 0x2000000u
11302 #define SDHC_PROCTL_WECINS_SHIFT 25
11303 #define SDHC_PROCTL_WECRM_MASK 0x4000000u
11304 #define SDHC_PROCTL_WECRM_SHIFT 26
11305 /* SYSCTL Bit Fields */
11306 #define SDHC_SYSCTL_IPGEN_MASK 0x1u
11307 #define SDHC_SYSCTL_IPGEN_SHIFT 0
11308 #define SDHC_SYSCTL_HCKEN_MASK 0x2u
11309 #define SDHC_SYSCTL_HCKEN_SHIFT 1
11310 #define SDHC_SYSCTL_PEREN_MASK 0x4u
11311 #define SDHC_SYSCTL_PEREN_SHIFT 2
11312 #define SDHC_SYSCTL_SDCLKEN_MASK 0x8u
11313 #define SDHC_SYSCTL_SDCLKEN_SHIFT 3
11314 #define SDHC_SYSCTL_DVS_MASK 0xF0u
11315 #define SDHC_SYSCTL_DVS_SHIFT 4
11316 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DVS_SHIFT))&SDHC_SYSCTL_DVS_MASK)
11317 #define SDHC_SYSCTL_SDCLKFS_MASK 0xFF00u
11318 #define SDHC_SYSCTL_SDCLKFS_SHIFT 8
11319 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_SDCLKFS_SHIFT))&SDHC_SYSCTL_SDCLKFS_MASK)
11320 #define SDHC_SYSCTL_DTOCV_MASK 0xF0000u
11321 #define SDHC_SYSCTL_DTOCV_SHIFT 16
11322 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x))<<SDHC_SYSCTL_DTOCV_SHIFT))&SDHC_SYSCTL_DTOCV_MASK)
11323 #define SDHC_SYSCTL_RSTA_MASK 0x1000000u
11324 #define SDHC_SYSCTL_RSTA_SHIFT 24
11325 #define SDHC_SYSCTL_RSTC_MASK 0x2000000u
11326 #define SDHC_SYSCTL_RSTC_SHIFT 25
11327 #define SDHC_SYSCTL_RSTD_MASK 0x4000000u
11328 #define SDHC_SYSCTL_RSTD_SHIFT 26
11329 #define SDHC_SYSCTL_INITA_MASK 0x8000000u
11330 #define SDHC_SYSCTL_INITA_SHIFT 27
11331 /* IRQSTAT Bit Fields */
11332 #define SDHC_IRQSTAT_CC_MASK 0x1u
11333 #define SDHC_IRQSTAT_CC_SHIFT 0
11334 #define SDHC_IRQSTAT_TC_MASK 0x2u
11335 #define SDHC_IRQSTAT_TC_SHIFT 1
11336 #define SDHC_IRQSTAT_BGE_MASK 0x4u
11337 #define SDHC_IRQSTAT_BGE_SHIFT 2
11338 #define SDHC_IRQSTAT_DINT_MASK 0x8u
11339 #define SDHC_IRQSTAT_DINT_SHIFT 3
11340 #define SDHC_IRQSTAT_BWR_MASK 0x10u
11341 #define SDHC_IRQSTAT_BWR_SHIFT 4
11342 #define SDHC_IRQSTAT_BRR_MASK 0x20u
11343 #define SDHC_IRQSTAT_BRR_SHIFT 5
11344 #define SDHC_IRQSTAT_CINS_MASK 0x40u
11345 #define SDHC_IRQSTAT_CINS_SHIFT 6
11346 #define SDHC_IRQSTAT_CRM_MASK 0x80u
11347 #define SDHC_IRQSTAT_CRM_SHIFT 7
11348 #define SDHC_IRQSTAT_CINT_MASK 0x100u
11349 #define SDHC_IRQSTAT_CINT_SHIFT 8
11350 #define SDHC_IRQSTAT_CTOE_MASK 0x10000u
11351 #define SDHC_IRQSTAT_CTOE_SHIFT 16
11352 #define SDHC_IRQSTAT_CCE_MASK 0x20000u
11353 #define SDHC_IRQSTAT_CCE_SHIFT 17
11354 #define SDHC_IRQSTAT_CEBE_MASK 0x40000u
11355 #define SDHC_IRQSTAT_CEBE_SHIFT 18
11356 #define SDHC_IRQSTAT_CIE_MASK 0x80000u
11357 #define SDHC_IRQSTAT_CIE_SHIFT 19
11358 #define SDHC_IRQSTAT_DTOE_MASK 0x100000u
11359 #define SDHC_IRQSTAT_DTOE_SHIFT 20
11360 #define SDHC_IRQSTAT_DCE_MASK 0x200000u
11361 #define SDHC_IRQSTAT_DCE_SHIFT 21
11362 #define SDHC_IRQSTAT_DEBE_MASK 0x400000u
11363 #define SDHC_IRQSTAT_DEBE_SHIFT 22
11364 #define SDHC_IRQSTAT_AC12E_MASK 0x1000000u
11365 #define SDHC_IRQSTAT_AC12E_SHIFT 24
11366 #define SDHC_IRQSTAT_DMAE_MASK 0x10000000u
11367 #define SDHC_IRQSTAT_DMAE_SHIFT 28
11368 /* IRQSTATEN Bit Fields */
11369 #define SDHC_IRQSTATEN_CCSEN_MASK 0x1u
11370 #define SDHC_IRQSTATEN_CCSEN_SHIFT 0
11371 #define SDHC_IRQSTATEN_TCSEN_MASK 0x2u
11372 #define SDHC_IRQSTATEN_TCSEN_SHIFT 1
11373 #define SDHC_IRQSTATEN_BGESEN_MASK 0x4u
11374 #define SDHC_IRQSTATEN_BGESEN_SHIFT 2
11375 #define SDHC_IRQSTATEN_DINTSEN_MASK 0x8u
11376 #define SDHC_IRQSTATEN_DINTSEN_SHIFT 3
11377 #define SDHC_IRQSTATEN_BWRSEN_MASK 0x10u
11378 #define SDHC_IRQSTATEN_BWRSEN_SHIFT 4
11379 #define SDHC_IRQSTATEN_BRRSEN_MASK 0x20u
11380 #define SDHC_IRQSTATEN_BRRSEN_SHIFT 5
11381 #define SDHC_IRQSTATEN_CINSEN_MASK 0x40u
11382 #define SDHC_IRQSTATEN_CINSEN_SHIFT 6
11383 #define SDHC_IRQSTATEN_CRMSEN_MASK 0x80u
11384 #define SDHC_IRQSTATEN_CRMSEN_SHIFT 7
11385 #define SDHC_IRQSTATEN_CINTSEN_MASK 0x100u
11386 #define SDHC_IRQSTATEN_CINTSEN_SHIFT 8
11387 #define SDHC_IRQSTATEN_CTOESEN_MASK 0x10000u
11388 #define SDHC_IRQSTATEN_CTOESEN_SHIFT 16
11389 #define SDHC_IRQSTATEN_CCESEN_MASK 0x20000u
11390 #define SDHC_IRQSTATEN_CCESEN_SHIFT 17
11391 #define SDHC_IRQSTATEN_CEBESEN_MASK 0x40000u
11392 #define SDHC_IRQSTATEN_CEBESEN_SHIFT 18
11393 #define SDHC_IRQSTATEN_CIESEN_MASK 0x80000u
11394 #define SDHC_IRQSTATEN_CIESEN_SHIFT 19
11395 #define SDHC_IRQSTATEN_DTOESEN_MASK 0x100000u
11396 #define SDHC_IRQSTATEN_DTOESEN_SHIFT 20
11397 #define SDHC_IRQSTATEN_DCESEN_MASK 0x200000u
11398 #define SDHC_IRQSTATEN_DCESEN_SHIFT 21
11399 #define SDHC_IRQSTATEN_DEBESEN_MASK 0x400000u
11400 #define SDHC_IRQSTATEN_DEBESEN_SHIFT 22
11401 #define SDHC_IRQSTATEN_AC12ESEN_MASK 0x1000000u
11402 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT 24
11403 #define SDHC_IRQSTATEN_DMAESEN_MASK 0x10000000u
11404 #define SDHC_IRQSTATEN_DMAESEN_SHIFT 28
11405 /* IRQSIGEN Bit Fields */
11406 #define SDHC_IRQSIGEN_CCIEN_MASK 0x1u
11407 #define SDHC_IRQSIGEN_CCIEN_SHIFT 0
11408 #define SDHC_IRQSIGEN_TCIEN_MASK 0x2u
11409 #define SDHC_IRQSIGEN_TCIEN_SHIFT 1
11410 #define SDHC_IRQSIGEN_BGEIEN_MASK 0x4u
11411 #define SDHC_IRQSIGEN_BGEIEN_SHIFT 2
11412 #define SDHC_IRQSIGEN_DINTIEN_MASK 0x8u
11413 #define SDHC_IRQSIGEN_DINTIEN_SHIFT 3
11414 #define SDHC_IRQSIGEN_BWRIEN_MASK 0x10u
11415 #define SDHC_IRQSIGEN_BWRIEN_SHIFT 4
11416 #define SDHC_IRQSIGEN_BRRIEN_MASK 0x20u
11417 #define SDHC_IRQSIGEN_BRRIEN_SHIFT 5
11418 #define SDHC_IRQSIGEN_CINSIEN_MASK 0x40u
11419 #define SDHC_IRQSIGEN_CINSIEN_SHIFT 6
11420 #define SDHC_IRQSIGEN_CRMIEN_MASK 0x80u
11421 #define SDHC_IRQSIGEN_CRMIEN_SHIFT 7
11422 #define SDHC_IRQSIGEN_CINTIEN_MASK 0x100u
11423 #define SDHC_IRQSIGEN_CINTIEN_SHIFT 8
11424 #define SDHC_IRQSIGEN_CTOEIEN_MASK 0x10000u
11425 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT 16
11426 #define SDHC_IRQSIGEN_CCEIEN_MASK 0x20000u
11427 #define SDHC_IRQSIGEN_CCEIEN_SHIFT 17
11428 #define SDHC_IRQSIGEN_CEBEIEN_MASK 0x40000u
11429 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT 18
11430 #define SDHC_IRQSIGEN_CIEIEN_MASK 0x80000u
11431 #define SDHC_IRQSIGEN_CIEIEN_SHIFT 19
11432 #define SDHC_IRQSIGEN_DTOEIEN_MASK 0x100000u
11433 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT 20
11434 #define SDHC_IRQSIGEN_DCEIEN_MASK 0x200000u
11435 #define SDHC_IRQSIGEN_DCEIEN_SHIFT 21
11436 #define SDHC_IRQSIGEN_DEBEIEN_MASK 0x400000u
11437 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT 22
11438 #define SDHC_IRQSIGEN_AC12EIEN_MASK 0x1000000u
11439 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT 24
11440 #define SDHC_IRQSIGEN_DMAEIEN_MASK 0x10000000u
11441 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT 28
11442 /* AC12ERR Bit Fields */
11443 #define SDHC_AC12ERR_AC12NE_MASK 0x1u
11444 #define SDHC_AC12ERR_AC12NE_SHIFT 0
11445 #define SDHC_AC12ERR_AC12TOE_MASK 0x2u
11446 #define SDHC_AC12ERR_AC12TOE_SHIFT 1
11447 #define SDHC_AC12ERR_AC12EBE_MASK 0x4u
11448 #define SDHC_AC12ERR_AC12EBE_SHIFT 2
11449 #define SDHC_AC12ERR_AC12CE_MASK 0x8u
11450 #define SDHC_AC12ERR_AC12CE_SHIFT 3
11451 #define SDHC_AC12ERR_AC12IE_MASK 0x10u
11452 #define SDHC_AC12ERR_AC12IE_SHIFT 4
11453 #define SDHC_AC12ERR_CNIBAC12E_MASK 0x80u
11454 #define SDHC_AC12ERR_CNIBAC12E_SHIFT 7
11455 /* HTCAPBLT Bit Fields */
11456 #define SDHC_HTCAPBLT_MBL_MASK 0x70000u
11457 #define SDHC_HTCAPBLT_MBL_SHIFT 16
11458 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HTCAPBLT_MBL_SHIFT))&SDHC_HTCAPBLT_MBL_MASK)
11459 #define SDHC_HTCAPBLT_ADMAS_MASK 0x100000u
11460 #define SDHC_HTCAPBLT_ADMAS_SHIFT 20
11461 #define SDHC_HTCAPBLT_HSS_MASK 0x200000u
11462 #define SDHC_HTCAPBLT_HSS_SHIFT 21
11463 #define SDHC_HTCAPBLT_DMAS_MASK 0x400000u
11464 #define SDHC_HTCAPBLT_DMAS_SHIFT 22
11465 #define SDHC_HTCAPBLT_SRS_MASK 0x800000u
11466 #define SDHC_HTCAPBLT_SRS_SHIFT 23
11467 #define SDHC_HTCAPBLT_VS33_MASK 0x1000000u
11468 #define SDHC_HTCAPBLT_VS33_SHIFT 24
11469 /* WML Bit Fields */
11470 #define SDHC_WML_RDWML_MASK 0xFFu
11471 #define SDHC_WML_RDWML_SHIFT 0
11472 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_RDWML_SHIFT))&SDHC_WML_RDWML_MASK)
11473 #define SDHC_WML_WRWML_MASK 0xFF0000u
11474 #define SDHC_WML_WRWML_SHIFT 16
11475 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x))<<SDHC_WML_WRWML_SHIFT))&SDHC_WML_WRWML_MASK)
11476 /* FEVT Bit Fields */
11477 #define SDHC_FEVT_AC12NE_MASK 0x1u
11478 #define SDHC_FEVT_AC12NE_SHIFT 0
11479 #define SDHC_FEVT_AC12TOE_MASK 0x2u
11480 #define SDHC_FEVT_AC12TOE_SHIFT 1
11481 #define SDHC_FEVT_AC12CE_MASK 0x4u
11482 #define SDHC_FEVT_AC12CE_SHIFT 2
11483 #define SDHC_FEVT_AC12EBE_MASK 0x8u
11484 #define SDHC_FEVT_AC12EBE_SHIFT 3
11485 #define SDHC_FEVT_AC12IE_MASK 0x10u
11486 #define SDHC_FEVT_AC12IE_SHIFT 4
11487 #define SDHC_FEVT_CNIBAC12E_MASK 0x80u
11488 #define SDHC_FEVT_CNIBAC12E_SHIFT 7
11489 #define SDHC_FEVT_CTOE_MASK 0x10000u
11490 #define SDHC_FEVT_CTOE_SHIFT 16
11491 #define SDHC_FEVT_CCE_MASK 0x20000u
11492 #define SDHC_FEVT_CCE_SHIFT 17
11493 #define SDHC_FEVT_CEBE_MASK 0x40000u
11494 #define SDHC_FEVT_CEBE_SHIFT 18
11495 #define SDHC_FEVT_CIE_MASK 0x80000u
11496 #define SDHC_FEVT_CIE_SHIFT 19
11497 #define SDHC_FEVT_DTOE_MASK 0x100000u
11498 #define SDHC_FEVT_DTOE_SHIFT 20
11499 #define SDHC_FEVT_DCE_MASK 0x200000u
11500 #define SDHC_FEVT_DCE_SHIFT 21
11501 #define SDHC_FEVT_DEBE_MASK 0x400000u
11502 #define SDHC_FEVT_DEBE_SHIFT 22
11503 #define SDHC_FEVT_AC12E_MASK 0x1000000u
11504 #define SDHC_FEVT_AC12E_SHIFT 24
11505 #define SDHC_FEVT_DMAE_MASK 0x10000000u
11506 #define SDHC_FEVT_DMAE_SHIFT 28
11507 #define SDHC_FEVT_CINT_MASK 0x80000000u
11508 #define SDHC_FEVT_CINT_SHIFT 31
11509 /* ADMAES Bit Fields */
11510 #define SDHC_ADMAES_ADMAES_MASK 0x3u
11511 #define SDHC_ADMAES_ADMAES_SHIFT 0
11512 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADMAES_ADMAES_SHIFT))&SDHC_ADMAES_ADMAES_MASK)
11513 #define SDHC_ADMAES_ADMALME_MASK 0x4u
11514 #define SDHC_ADMAES_ADMALME_SHIFT 2
11515 #define SDHC_ADMAES_ADMADCE_MASK 0x8u
11516 #define SDHC_ADMAES_ADMADCE_SHIFT 3
11517 /* ADSADDR Bit Fields */
11518 #define SDHC_ADSADDR_ADSADDR_MASK 0xFFFFFFFCu
11519 #define SDHC_ADSADDR_ADSADDR_SHIFT 2
11520 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x))<<SDHC_ADSADDR_ADSADDR_SHIFT))&SDHC_ADSADDR_ADSADDR_MASK)
11521 /* VENDOR Bit Fields */
11522 #define SDHC_VENDOR_EXTDMAEN_MASK 0x1u
11523 #define SDHC_VENDOR_EXTDMAEN_SHIFT 0
11524 #define SDHC_VENDOR_EXBLKNU_MASK 0x2u
11525 #define SDHC_VENDOR_EXBLKNU_SHIFT 1
11526 #define SDHC_VENDOR_INTSTVAL_MASK 0xFF0000u
11527 #define SDHC_VENDOR_INTSTVAL_SHIFT 16
11528 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x))<<SDHC_VENDOR_INTSTVAL_SHIFT))&SDHC_VENDOR_INTSTVAL_MASK)
11529 /* MMCBOOT Bit Fields */
11530 #define SDHC_MMCBOOT_DTOCVACK_MASK 0xFu
11531 #define SDHC_MMCBOOT_DTOCVACK_SHIFT 0
11532 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_DTOCVACK_SHIFT))&SDHC_MMCBOOT_DTOCVACK_MASK)
11533 #define SDHC_MMCBOOT_BOOTACK_MASK 0x10u
11534 #define SDHC_MMCBOOT_BOOTACK_SHIFT 4
11535 #define SDHC_MMCBOOT_BOOTMODE_MASK 0x20u
11536 #define SDHC_MMCBOOT_BOOTMODE_SHIFT 5
11537 #define SDHC_MMCBOOT_BOOTEN_MASK 0x40u
11538 #define SDHC_MMCBOOT_BOOTEN_SHIFT 6
11539 #define SDHC_MMCBOOT_AUTOSABGEN_MASK 0x80u
11540 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT 7
11541 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK 0xFFFF0000u
11542 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT 16
11543 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x))<<SDHC_MMCBOOT_BOOTBLKCNT_SHIFT))&SDHC_MMCBOOT_BOOTBLKCNT_MASK)
11544 /* HOSTVER Bit Fields */
11545 #define SDHC_HOSTVER_SVN_MASK 0xFFu
11546 #define SDHC_HOSTVER_SVN_SHIFT 0
11547 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_SVN_SHIFT))&SDHC_HOSTVER_SVN_MASK)
11548 #define SDHC_HOSTVER_VVN_MASK 0xFF00u
11549 #define SDHC_HOSTVER_VVN_SHIFT 8
11550 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x))<<SDHC_HOSTVER_VVN_SHIFT))&SDHC_HOSTVER_VVN_MASK)
11551
11552 /*!
11553 * @}
11554 */ /* end of group SDHC_Register_Masks */
11555
11556
11557 /* SDHC - Peripheral instance base addresses */
11558 /** Peripheral SDHC base address */
11559 #define SDHC_BASE (0x400B1000u)
11560 /** Peripheral SDHC base pointer */
11561 #define SDHC ((SDHC_Type *)SDHC_BASE)
11562 #define SDHC_BASE_PTR (SDHC)
11563 /** Array initializer of SDHC peripheral base addresses */
11564 #define SDHC_BASE_ADDRS { SDHC_BASE }
11565 /** Array initializer of SDHC peripheral base pointers */
11566 #define SDHC_BASE_PTRS { SDHC }
11567 /** Interrupt vectors for the SDHC peripheral type */
11568 #define SDHC_IRQS { SDHC_IRQn }
11569
11570 /* ----------------------------------------------------------------------------
11571 -- SDHC - Register accessor macros
11572 ---------------------------------------------------------------------------- */
11573
11574 /*!
11575 * @addtogroup SDHC_Register_Accessor_Macros SDHC - Register accessor macros
11576 * @{
11577 */
11578
11579
11580 /* SDHC - Register instance definitions */
11581 /* SDHC */
11582 #define SDHC_DSADDR SDHC_DSADDR_REG(SDHC)
11583 #define SDHC_BLKATTR SDHC_BLKATTR_REG(SDHC)
11584 #define SDHC_CMDARG SDHC_CMDARG_REG(SDHC)
11585 #define SDHC_XFERTYP SDHC_XFERTYP_REG(SDHC)
11586 #define SDHC_CMDRSP0 SDHC_CMDRSP_REG(SDHC,0)
11587 #define SDHC_CMDRSP1 SDHC_CMDRSP_REG(SDHC,1)
11588 #define SDHC_CMDRSP2 SDHC_CMDRSP_REG(SDHC,2)
11589 #define SDHC_CMDRSP3 SDHC_CMDRSP_REG(SDHC,3)
11590 #define SDHC_DATPORT SDHC_DATPORT_REG(SDHC)
11591 #define SDHC_PRSSTAT SDHC_PRSSTAT_REG(SDHC)
11592 #define SDHC_PROCTL SDHC_PROCTL_REG(SDHC)
11593 #define SDHC_SYSCTL SDHC_SYSCTL_REG(SDHC)
11594 #define SDHC_IRQSTAT SDHC_IRQSTAT_REG(SDHC)
11595 #define SDHC_IRQSTATEN SDHC_IRQSTATEN_REG(SDHC)
11596 #define SDHC_IRQSIGEN SDHC_IRQSIGEN_REG(SDHC)
11597 #define SDHC_AC12ERR SDHC_AC12ERR_REG(SDHC)
11598 #define SDHC_HTCAPBLT SDHC_HTCAPBLT_REG(SDHC)
11599 #define SDHC_WML SDHC_WML_REG(SDHC)
11600 #define SDHC_FEVT SDHC_FEVT_REG(SDHC)
11601 #define SDHC_ADMAES SDHC_ADMAES_REG(SDHC)
11602 #define SDHC_ADSADDR SDHC_ADSADDR_REG(SDHC)
11603 #define SDHC_VENDOR SDHC_VENDOR_REG(SDHC)
11604 #define SDHC_MMCBOOT SDHC_MMCBOOT_REG(SDHC)
11605 #define SDHC_HOSTVER SDHC_HOSTVER_REG(SDHC)
11606
11607 /* SDHC - Register array accessors */
11608 #define SDHC_CMDRSP(index) SDHC_CMDRSP_REG(SDHC,index)
11609
11610 /*!
11611 * @}
11612 */ /* end of group SDHC_Register_Accessor_Macros */
11613
11614
11615 /*!
11616 * @}
11617 */ /* end of group SDHC_Peripheral_Access_Layer */
11618
11619
11620 /* ----------------------------------------------------------------------------
11621 -- SIM Peripheral Access Layer
11622 ---------------------------------------------------------------------------- */
11623
11624 /*!
11625 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
11626 * @{
11627 */
11628
11629 /** SIM - Register Layout Typedef */
11630 typedef struct {
11631 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
11632 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
11633 uint8_t RESERVED_0[4092];
11634 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
11635 uint8_t RESERVED_1[4];
11636 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
11637 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
11638 uint8_t RESERVED_2[4];
11639 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
11640 uint8_t RESERVED_3[8];
11641 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
11642 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
11643 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
11644 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
11645 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
11646 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
11647 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
11648 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
11649 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
11650 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
11651 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
11652 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
11653 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
11654 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
11655 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
11656 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
11657 } SIM_Type, *SIM_MemMapPtr;
11658
11659 /* ----------------------------------------------------------------------------
11660 -- SIM - Register accessor macros
11661 ---------------------------------------------------------------------------- */
11662
11663 /*!
11664 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
11665 * @{
11666 */
11667
11668
11669 /* SIM - Register accessors */
11670 #define SIM_SOPT1_REG(base) ((base)->SOPT1)
11671 #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG)
11672 #define SIM_SOPT2_REG(base) ((base)->SOPT2)
11673 #define SIM_SOPT4_REG(base) ((base)->SOPT4)
11674 #define SIM_SOPT5_REG(base) ((base)->SOPT5)
11675 #define SIM_SOPT7_REG(base) ((base)->SOPT7)
11676 #define SIM_SDID_REG(base) ((base)->SDID)
11677 #define SIM_SCGC1_REG(base) ((base)->SCGC1)
11678 #define SIM_SCGC2_REG(base) ((base)->SCGC2)
11679 #define SIM_SCGC3_REG(base) ((base)->SCGC3)
11680 #define SIM_SCGC4_REG(base) ((base)->SCGC4)
11681 #define SIM_SCGC5_REG(base) ((base)->SCGC5)
11682 #define SIM_SCGC6_REG(base) ((base)->SCGC6)
11683 #define SIM_SCGC7_REG(base) ((base)->SCGC7)
11684 #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1)
11685 #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2)
11686 #define SIM_FCFG1_REG(base) ((base)->FCFG1)
11687 #define SIM_FCFG2_REG(base) ((base)->FCFG2)
11688 #define SIM_UIDH_REG(base) ((base)->UIDH)
11689 #define SIM_UIDMH_REG(base) ((base)->UIDMH)
11690 #define SIM_UIDML_REG(base) ((base)->UIDML)
11691 #define SIM_UIDL_REG(base) ((base)->UIDL)
11692
11693 /*!
11694 * @}
11695 */ /* end of group SIM_Register_Accessor_Macros */
11696
11697
11698 /* ----------------------------------------------------------------------------
11699 -- SIM Register Masks
11700 ---------------------------------------------------------------------------- */
11701
11702 /*!
11703 * @addtogroup SIM_Register_Masks SIM Register Masks
11704 * @{
11705 */
11706
11707 /* SOPT1 Bit Fields */
11708 #define SIM_SOPT1_RAMSIZE_MASK 0xF000u
11709 #define SIM_SOPT1_RAMSIZE_SHIFT 12
11710 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_RAMSIZE_SHIFT))&SIM_SOPT1_RAMSIZE_MASK)
11711 #define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
11712 #define SIM_SOPT1_OSC32KSEL_SHIFT 18
11713 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
11714 #define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
11715 #define SIM_SOPT1_USBVSTBY_SHIFT 29
11716 #define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
11717 #define SIM_SOPT1_USBSSTBY_SHIFT 30
11718 #define SIM_SOPT1_USBREGEN_MASK 0x80000000u
11719 #define SIM_SOPT1_USBREGEN_SHIFT 31
11720 /* SOPT1CFG Bit Fields */
11721 #define SIM_SOPT1CFG_URWE_MASK 0x1000000u
11722 #define SIM_SOPT1CFG_URWE_SHIFT 24
11723 #define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
11724 #define SIM_SOPT1CFG_UVSWE_SHIFT 25
11725 #define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
11726 #define SIM_SOPT1CFG_USSWE_SHIFT 26
11727 /* SOPT2 Bit Fields */
11728 #define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
11729 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
11730 #define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
11731 #define SIM_SOPT2_CLKOUTSEL_SHIFT 5
11732 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
11733 #define SIM_SOPT2_FBSL_MASK 0x300u
11734 #define SIM_SOPT2_FBSL_SHIFT 8
11735 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_FBSL_SHIFT))&SIM_SOPT2_FBSL_MASK)
11736 #define SIM_SOPT2_PTD7PAD_MASK 0x800u
11737 #define SIM_SOPT2_PTD7PAD_SHIFT 11
11738 #define SIM_SOPT2_TRACECLKSEL_MASK 0x1000u
11739 #define SIM_SOPT2_TRACECLKSEL_SHIFT 12
11740 #define SIM_SOPT2_PLLFLLSEL_MASK 0x30000u
11741 #define SIM_SOPT2_PLLFLLSEL_SHIFT 16
11742 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_PLLFLLSEL_SHIFT))&SIM_SOPT2_PLLFLLSEL_MASK)
11743 #define SIM_SOPT2_USBSRC_MASK 0x40000u
11744 #define SIM_SOPT2_USBSRC_SHIFT 18
11745 #define SIM_SOPT2_RMIISRC_MASK 0x80000u
11746 #define SIM_SOPT2_RMIISRC_SHIFT 19
11747 #define SIM_SOPT2_TIMESRC_MASK 0x300000u
11748 #define SIM_SOPT2_TIMESRC_SHIFT 20
11749 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TIMESRC_SHIFT))&SIM_SOPT2_TIMESRC_MASK)
11750 #define SIM_SOPT2_SDHCSRC_MASK 0x30000000u
11751 #define SIM_SOPT2_SDHCSRC_SHIFT 28
11752 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_SDHCSRC_SHIFT))&SIM_SOPT2_SDHCSRC_MASK)
11753 /* SOPT4 Bit Fields */
11754 #define SIM_SOPT4_FTM0FLT0_MASK 0x1u
11755 #define SIM_SOPT4_FTM0FLT0_SHIFT 0
11756 #define SIM_SOPT4_FTM0FLT1_MASK 0x2u
11757 #define SIM_SOPT4_FTM0FLT1_SHIFT 1
11758 #define SIM_SOPT4_FTM0FLT2_MASK 0x4u
11759 #define SIM_SOPT4_FTM0FLT2_SHIFT 2
11760 #define SIM_SOPT4_FTM1FLT0_MASK 0x10u
11761 #define SIM_SOPT4_FTM1FLT0_SHIFT 4
11762 #define SIM_SOPT4_FTM2FLT0_MASK 0x100u
11763 #define SIM_SOPT4_FTM2FLT0_SHIFT 8
11764 #define SIM_SOPT4_FTM3FLT0_MASK 0x1000u
11765 #define SIM_SOPT4_FTM3FLT0_SHIFT 12
11766 #define SIM_SOPT4_FTM1CH0SRC_MASK 0xC0000u
11767 #define SIM_SOPT4_FTM1CH0SRC_SHIFT 18
11768 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM1CH0SRC_SHIFT))&SIM_SOPT4_FTM1CH0SRC_MASK)
11769 #define SIM_SOPT4_FTM2CH0SRC_MASK 0x300000u
11770 #define SIM_SOPT4_FTM2CH0SRC_SHIFT 20
11771 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT4_FTM2CH0SRC_SHIFT))&SIM_SOPT4_FTM2CH0SRC_MASK)
11772 #define SIM_SOPT4_FTM0CLKSEL_MASK 0x1000000u
11773 #define SIM_SOPT4_FTM0CLKSEL_SHIFT 24
11774 #define SIM_SOPT4_FTM1CLKSEL_MASK 0x2000000u
11775 #define SIM_SOPT4_FTM1CLKSEL_SHIFT 25
11776 #define SIM_SOPT4_FTM2CLKSEL_MASK 0x4000000u
11777 #define SIM_SOPT4_FTM2CLKSEL_SHIFT 26
11778 #define SIM_SOPT4_FTM3CLKSEL_MASK 0x8000000u
11779 #define SIM_SOPT4_FTM3CLKSEL_SHIFT 27
11780 #define SIM_SOPT4_FTM0TRG0SRC_MASK 0x10000000u
11781 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT 28
11782 #define SIM_SOPT4_FTM0TRG1SRC_MASK 0x20000000u
11783 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT 29
11784 #define SIM_SOPT4_FTM3TRG0SRC_MASK 0x40000000u
11785 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT 30
11786 #define SIM_SOPT4_FTM3TRG1SRC_MASK 0x80000000u
11787 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT 31
11788 /* SOPT5 Bit Fields */
11789 #define SIM_SOPT5_UART0TXSRC_MASK 0x3u
11790 #define SIM_SOPT5_UART0TXSRC_SHIFT 0
11791 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
11792 #define SIM_SOPT5_UART0RXSRC_MASK 0xCu
11793 #define SIM_SOPT5_UART0RXSRC_SHIFT 2
11794 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0RXSRC_SHIFT))&SIM_SOPT5_UART0RXSRC_MASK)
11795 #define SIM_SOPT5_UART1TXSRC_MASK 0x30u
11796 #define SIM_SOPT5_UART1TXSRC_SHIFT 4
11797 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
11798 #define SIM_SOPT5_UART1RXSRC_MASK 0xC0u
11799 #define SIM_SOPT5_UART1RXSRC_SHIFT 6
11800 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1RXSRC_SHIFT))&SIM_SOPT5_UART1RXSRC_MASK)
11801 /* SOPT7 Bit Fields */
11802 #define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
11803 #define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
11804 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
11805 #define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
11806 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
11807 #define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
11808 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
11809 #define SIM_SOPT7_ADC1TRGSEL_MASK 0xF00u
11810 #define SIM_SOPT7_ADC1TRGSEL_SHIFT 8
11811 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC1TRGSEL_SHIFT))&SIM_SOPT7_ADC1TRGSEL_MASK)
11812 #define SIM_SOPT7_ADC1PRETRGSEL_MASK 0x1000u
11813 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT 12
11814 #define SIM_SOPT7_ADC1ALTTRGEN_MASK 0x8000u
11815 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT 15
11816 /* SDID Bit Fields */
11817 #define SIM_SDID_PINID_MASK 0xFu
11818 #define SIM_SDID_PINID_SHIFT 0
11819 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
11820 #define SIM_SDID_FAMID_MASK 0x70u
11821 #define SIM_SDID_FAMID_SHIFT 4
11822 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
11823 #define SIM_SDID_DIEID_MASK 0xF80u
11824 #define SIM_SDID_DIEID_SHIFT 7
11825 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
11826 #define SIM_SDID_REVID_MASK 0xF000u
11827 #define SIM_SDID_REVID_SHIFT 12
11828 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
11829 #define SIM_SDID_SERIESID_MASK 0xF00000u
11830 #define SIM_SDID_SERIESID_SHIFT 20
11831 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
11832 #define SIM_SDID_SUBFAMID_MASK 0xF000000u
11833 #define SIM_SDID_SUBFAMID_SHIFT 24
11834 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
11835 #define SIM_SDID_FAMILYID_MASK 0xF0000000u
11836 #define SIM_SDID_FAMILYID_SHIFT 28
11837 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMILYID_SHIFT))&SIM_SDID_FAMILYID_MASK)
11838 /* SCGC1 Bit Fields */
11839 #define SIM_SCGC1_I2C2_MASK 0x40u
11840 #define SIM_SCGC1_I2C2_SHIFT 6
11841 #define SIM_SCGC1_UART4_MASK 0x400u
11842 #define SIM_SCGC1_UART4_SHIFT 10
11843 #define SIM_SCGC1_UART5_MASK 0x800u
11844 #define SIM_SCGC1_UART5_SHIFT 11
11845 /* SCGC2 Bit Fields */
11846 #define SIM_SCGC2_ENET_MASK 0x1u
11847 #define SIM_SCGC2_ENET_SHIFT 0
11848 #define SIM_SCGC2_DAC0_MASK 0x1000u
11849 #define SIM_SCGC2_DAC0_SHIFT 12
11850 #define SIM_SCGC2_DAC1_MASK 0x2000u
11851 #define SIM_SCGC2_DAC1_SHIFT 13
11852 /* SCGC3 Bit Fields */
11853 #define SIM_SCGC3_RNGA_MASK 0x1u
11854 #define SIM_SCGC3_RNGA_SHIFT 0
11855 #define SIM_SCGC3_SPI2_MASK 0x1000u
11856 #define SIM_SCGC3_SPI2_SHIFT 12
11857 #define SIM_SCGC3_SDHC_MASK 0x20000u
11858 #define SIM_SCGC3_SDHC_SHIFT 17
11859 #define SIM_SCGC3_FTM2_MASK 0x1000000u
11860 #define SIM_SCGC3_FTM2_SHIFT 24
11861 #define SIM_SCGC3_FTM3_MASK 0x2000000u
11862 #define SIM_SCGC3_FTM3_SHIFT 25
11863 #define SIM_SCGC3_ADC1_MASK 0x8000000u
11864 #define SIM_SCGC3_ADC1_SHIFT 27
11865 /* SCGC4 Bit Fields */
11866 #define SIM_SCGC4_EWM_MASK 0x2u
11867 #define SIM_SCGC4_EWM_SHIFT 1
11868 #define SIM_SCGC4_CMT_MASK 0x4u
11869 #define SIM_SCGC4_CMT_SHIFT 2
11870 #define SIM_SCGC4_I2C0_MASK 0x40u
11871 #define SIM_SCGC4_I2C0_SHIFT 6
11872 #define SIM_SCGC4_I2C1_MASK 0x80u
11873 #define SIM_SCGC4_I2C1_SHIFT 7
11874 #define SIM_SCGC4_UART0_MASK 0x400u
11875 #define SIM_SCGC4_UART0_SHIFT 10
11876 #define SIM_SCGC4_UART1_MASK 0x800u
11877 #define SIM_SCGC4_UART1_SHIFT 11
11878 #define SIM_SCGC4_UART2_MASK 0x1000u
11879 #define SIM_SCGC4_UART2_SHIFT 12
11880 #define SIM_SCGC4_UART3_MASK 0x2000u
11881 #define SIM_SCGC4_UART3_SHIFT 13
11882 #define SIM_SCGC4_USBOTG_MASK 0x40000u
11883 #define SIM_SCGC4_USBOTG_SHIFT 18
11884 #define SIM_SCGC4_CMP_MASK 0x80000u
11885 #define SIM_SCGC4_CMP_SHIFT 19
11886 #define SIM_SCGC4_VREF_MASK 0x100000u
11887 #define SIM_SCGC4_VREF_SHIFT 20
11888 /* SCGC5 Bit Fields */
11889 #define SIM_SCGC5_LPTMR_MASK 0x1u
11890 #define SIM_SCGC5_LPTMR_SHIFT 0
11891 #define SIM_SCGC5_PORTA_MASK 0x200u
11892 #define SIM_SCGC5_PORTA_SHIFT 9
11893 #define SIM_SCGC5_PORTB_MASK 0x400u
11894 #define SIM_SCGC5_PORTB_SHIFT 10
11895 #define SIM_SCGC5_PORTC_MASK 0x800u
11896 #define SIM_SCGC5_PORTC_SHIFT 11
11897 #define SIM_SCGC5_PORTD_MASK 0x1000u
11898 #define SIM_SCGC5_PORTD_SHIFT 12
11899 #define SIM_SCGC5_PORTE_MASK 0x2000u
11900 #define SIM_SCGC5_PORTE_SHIFT 13
11901 /* SCGC6 Bit Fields */
11902 #define SIM_SCGC6_FTF_MASK 0x1u
11903 #define SIM_SCGC6_FTF_SHIFT 0
11904 #define SIM_SCGC6_DMAMUX_MASK 0x2u
11905 #define SIM_SCGC6_DMAMUX_SHIFT 1
11906 #define SIM_SCGC6_FLEXCAN0_MASK 0x10u
11907 #define SIM_SCGC6_FLEXCAN0_SHIFT 4
11908 #define SIM_SCGC6_RNGA_MASK 0x200u
11909 #define SIM_SCGC6_RNGA_SHIFT 9
11910 #define SIM_SCGC6_SPI0_MASK 0x1000u
11911 #define SIM_SCGC6_SPI0_SHIFT 12
11912 #define SIM_SCGC6_SPI1_MASK 0x2000u
11913 #define SIM_SCGC6_SPI1_SHIFT 13
11914 #define SIM_SCGC6_I2S_MASK 0x8000u
11915 #define SIM_SCGC6_I2S_SHIFT 15
11916 #define SIM_SCGC6_CRC_MASK 0x40000u
11917 #define SIM_SCGC6_CRC_SHIFT 18
11918 #define SIM_SCGC6_USBDCD_MASK 0x200000u
11919 #define SIM_SCGC6_USBDCD_SHIFT 21
11920 #define SIM_SCGC6_PDB_MASK 0x400000u
11921 #define SIM_SCGC6_PDB_SHIFT 22
11922 #define SIM_SCGC6_PIT_MASK 0x800000u
11923 #define SIM_SCGC6_PIT_SHIFT 23
11924 #define SIM_SCGC6_FTM0_MASK 0x1000000u
11925 #define SIM_SCGC6_FTM0_SHIFT 24
11926 #define SIM_SCGC6_FTM1_MASK 0x2000000u
11927 #define SIM_SCGC6_FTM1_SHIFT 25
11928 #define SIM_SCGC6_FTM2_MASK 0x4000000u
11929 #define SIM_SCGC6_FTM2_SHIFT 26
11930 #define SIM_SCGC6_ADC0_MASK 0x8000000u
11931 #define SIM_SCGC6_ADC0_SHIFT 27
11932 #define SIM_SCGC6_RTC_MASK 0x20000000u
11933 #define SIM_SCGC6_RTC_SHIFT 29
11934 #define SIM_SCGC6_DAC0_MASK 0x80000000u
11935 #define SIM_SCGC6_DAC0_SHIFT 31
11936 /* SCGC7 Bit Fields */
11937 #define SIM_SCGC7_FLEXBUS_MASK 0x1u
11938 #define SIM_SCGC7_FLEXBUS_SHIFT 0
11939 #define SIM_SCGC7_DMA_MASK 0x2u
11940 #define SIM_SCGC7_DMA_SHIFT 1
11941 #define SIM_SCGC7_MPU_MASK 0x4u
11942 #define SIM_SCGC7_MPU_SHIFT 2
11943 /* CLKDIV1 Bit Fields */
11944 #define SIM_CLKDIV1_OUTDIV4_MASK 0xF0000u
11945 #define SIM_CLKDIV1_OUTDIV4_SHIFT 16
11946 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
11947 #define SIM_CLKDIV1_OUTDIV3_MASK 0xF00000u
11948 #define SIM_CLKDIV1_OUTDIV3_SHIFT 20
11949 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV3_SHIFT))&SIM_CLKDIV1_OUTDIV3_MASK)
11950 #define SIM_CLKDIV1_OUTDIV2_MASK 0xF000000u
11951 #define SIM_CLKDIV1_OUTDIV2_SHIFT 24
11952 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV2_SHIFT))&SIM_CLKDIV1_OUTDIV2_MASK)
11953 #define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
11954 #define SIM_CLKDIV1_OUTDIV1_SHIFT 28
11955 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
11956 /* CLKDIV2 Bit Fields */
11957 #define SIM_CLKDIV2_USBFRAC_MASK 0x1u
11958 #define SIM_CLKDIV2_USBFRAC_SHIFT 0
11959 #define SIM_CLKDIV2_USBDIV_MASK 0xEu
11960 #define SIM_CLKDIV2_USBDIV_SHIFT 1
11961 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV2_USBDIV_SHIFT))&SIM_CLKDIV2_USBDIV_MASK)
11962 /* FCFG1 Bit Fields */
11963 #define SIM_FCFG1_FLASHDIS_MASK 0x1u
11964 #define SIM_FCFG1_FLASHDIS_SHIFT 0
11965 #define SIM_FCFG1_FLASHDOZE_MASK 0x2u
11966 #define SIM_FCFG1_FLASHDOZE_SHIFT 1
11967 #define SIM_FCFG1_DEPART_MASK 0xF00u
11968 #define SIM_FCFG1_DEPART_SHIFT 8
11969 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_DEPART_SHIFT))&SIM_FCFG1_DEPART_MASK)
11970 #define SIM_FCFG1_EESIZE_MASK 0xF0000u
11971 #define SIM_FCFG1_EESIZE_SHIFT 16
11972 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_EESIZE_SHIFT))&SIM_FCFG1_EESIZE_MASK)
11973 #define SIM_FCFG1_PFSIZE_MASK 0xF000000u
11974 #define SIM_FCFG1_PFSIZE_SHIFT 24
11975 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
11976 #define SIM_FCFG1_NVMSIZE_MASK 0xF0000000u
11977 #define SIM_FCFG1_NVMSIZE_SHIFT 28
11978 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_NVMSIZE_SHIFT))&SIM_FCFG1_NVMSIZE_MASK)
11979 /* FCFG2 Bit Fields */
11980 #define SIM_FCFG2_MAXADDR1_MASK 0x7F0000u
11981 #define SIM_FCFG2_MAXADDR1_SHIFT 16
11982 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR1_SHIFT))&SIM_FCFG2_MAXADDR1_MASK)
11983 #define SIM_FCFG2_PFLSH_MASK 0x800000u
11984 #define SIM_FCFG2_PFLSH_SHIFT 23
11985 #define SIM_FCFG2_MAXADDR0_MASK 0x7F000000u
11986 #define SIM_FCFG2_MAXADDR0_SHIFT 24
11987 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR0_SHIFT))&SIM_FCFG2_MAXADDR0_MASK)
11988 /* UIDH Bit Fields */
11989 #define SIM_UIDH_UID_MASK 0xFFFFFFFFu
11990 #define SIM_UIDH_UID_SHIFT 0
11991 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDH_UID_SHIFT))&SIM_UIDH_UID_MASK)
11992 /* UIDMH Bit Fields */
11993 #define SIM_UIDMH_UID_MASK 0xFFFFFFFFu
11994 #define SIM_UIDMH_UID_SHIFT 0
11995 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
11996 /* UIDML Bit Fields */
11997 #define SIM_UIDML_UID_MASK 0xFFFFFFFFu
11998 #define SIM_UIDML_UID_SHIFT 0
11999 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
12000 /* UIDL Bit Fields */
12001 #define SIM_UIDL_UID_MASK 0xFFFFFFFFu
12002 #define SIM_UIDL_UID_SHIFT 0
12003 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
12004
12005 /*!
12006 * @}
12007 */ /* end of group SIM_Register_Masks */
12008
12009
12010 /* SIM - Peripheral instance base addresses */
12011 /** Peripheral SIM base address */
12012 #define SIM_BASE (0x40047000u)
12013 /** Peripheral SIM base pointer */
12014 #define SIM ((SIM_Type *)SIM_BASE)
12015 #define SIM_BASE_PTR (SIM)
12016 /** Array initializer of SIM peripheral base addresses */
12017 #define SIM_BASE_ADDRS { SIM_BASE }
12018 /** Array initializer of SIM peripheral base pointers */
12019 #define SIM_BASE_PTRS { SIM }
12020
12021 /* ----------------------------------------------------------------------------
12022 -- SIM - Register accessor macros
12023 ---------------------------------------------------------------------------- */
12024
12025 /*!
12026 * @addtogroup SIM_Register_Accessor_Macros SIM - Register accessor macros
12027 * @{
12028 */
12029
12030
12031 /* SIM - Register instance definitions */
12032 /* SIM */
12033 #define SIM_SOPT1 SIM_SOPT1_REG(SIM)
12034 #define SIM_SOPT1CFG SIM_SOPT1CFG_REG(SIM)
12035 #define SIM_SOPT2 SIM_SOPT2_REG(SIM)
12036 #define SIM_SOPT4 SIM_SOPT4_REG(SIM)
12037 #define SIM_SOPT5 SIM_SOPT5_REG(SIM)
12038 #define SIM_SOPT7 SIM_SOPT7_REG(SIM)
12039 #define SIM_SDID SIM_SDID_REG(SIM)
12040 #define SIM_SCGC1 SIM_SCGC1_REG(SIM)
12041 #define SIM_SCGC2 SIM_SCGC2_REG(SIM)
12042 #define SIM_SCGC3 SIM_SCGC3_REG(SIM)
12043 #define SIM_SCGC4 SIM_SCGC4_REG(SIM)
12044 #define SIM_SCGC5 SIM_SCGC5_REG(SIM)
12045 #define SIM_SCGC6 SIM_SCGC6_REG(SIM)
12046 #define SIM_SCGC7 SIM_SCGC7_REG(SIM)
12047 #define SIM_CLKDIV1 SIM_CLKDIV1_REG(SIM)
12048 #define SIM_CLKDIV2 SIM_CLKDIV2_REG(SIM)
12049 #define SIM_FCFG1 SIM_FCFG1_REG(SIM)
12050 #define SIM_FCFG2 SIM_FCFG2_REG(SIM)
12051 #define SIM_UIDH SIM_UIDH_REG(SIM)
12052 #define SIM_UIDMH SIM_UIDMH_REG(SIM)
12053 #define SIM_UIDML SIM_UIDML_REG(SIM)
12054 #define SIM_UIDL SIM_UIDL_REG(SIM)
12055
12056 /*!
12057 * @}
12058 */ /* end of group SIM_Register_Accessor_Macros */
12059
12060
12061 /*!
12062 * @}
12063 */ /* end of group SIM_Peripheral_Access_Layer */
12064
12065
12066 /* ----------------------------------------------------------------------------
12067 -- SMC Peripheral Access Layer
12068 ---------------------------------------------------------------------------- */
12069
12070 /*!
12071 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
12072 * @{
12073 */
12074
12075 /** SMC - Register Layout Typedef */
12076 typedef struct {
12077 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
12078 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
12079 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
12080 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
12081 } SMC_Type, *SMC_MemMapPtr;
12082
12083 /* ----------------------------------------------------------------------------
12084 -- SMC - Register accessor macros
12085 ---------------------------------------------------------------------------- */
12086
12087 /*!
12088 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
12089 * @{
12090 */
12091
12092
12093 /* SMC - Register accessors */
12094 #define SMC_PMPROT_REG(base) ((base)->PMPROT)
12095 #define SMC_PMCTRL_REG(base) ((base)->PMCTRL)
12096 #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL)
12097 #define SMC_PMSTAT_REG(base) ((base)->PMSTAT)
12098
12099 /*!
12100 * @}
12101 */ /* end of group SMC_Register_Accessor_Macros */
12102
12103
12104 /* ----------------------------------------------------------------------------
12105 -- SMC Register Masks
12106 ---------------------------------------------------------------------------- */
12107
12108 /*!
12109 * @addtogroup SMC_Register_Masks SMC Register Masks
12110 * @{
12111 */
12112
12113 /* PMPROT Bit Fields */
12114 #define SMC_PMPROT_AVLLS_MASK 0x2u
12115 #define SMC_PMPROT_AVLLS_SHIFT 1
12116 #define SMC_PMPROT_ALLS_MASK 0x8u
12117 #define SMC_PMPROT_ALLS_SHIFT 3
12118 #define SMC_PMPROT_AVLP_MASK 0x20u
12119 #define SMC_PMPROT_AVLP_SHIFT 5
12120 /* PMCTRL Bit Fields */
12121 #define SMC_PMCTRL_STOPM_MASK 0x7u
12122 #define SMC_PMCTRL_STOPM_SHIFT 0
12123 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
12124 #define SMC_PMCTRL_STOPA_MASK 0x8u
12125 #define SMC_PMCTRL_STOPA_SHIFT 3
12126 #define SMC_PMCTRL_RUNM_MASK 0x60u
12127 #define SMC_PMCTRL_RUNM_SHIFT 5
12128 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
12129 #define SMC_PMCTRL_LPWUI_MASK 0x80u
12130 #define SMC_PMCTRL_LPWUI_SHIFT 7
12131 /* VLLSCTRL Bit Fields */
12132 #define SMC_VLLSCTRL_VLLSM_MASK 0x7u
12133 #define SMC_VLLSCTRL_VLLSM_SHIFT 0
12134 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_VLLSCTRL_VLLSM_SHIFT))&SMC_VLLSCTRL_VLLSM_MASK)
12135 #define SMC_VLLSCTRL_PORPO_MASK 0x20u
12136 #define SMC_VLLSCTRL_PORPO_SHIFT 5
12137 /* PMSTAT Bit Fields */
12138 #define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
12139 #define SMC_PMSTAT_PMSTAT_SHIFT 0
12140 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
12141
12142 /*!
12143 * @}
12144 */ /* end of group SMC_Register_Masks */
12145
12146
12147 /* SMC - Peripheral instance base addresses */
12148 /** Peripheral SMC base address */
12149 #define SMC_BASE (0x4007E000u)
12150 /** Peripheral SMC base pointer */
12151 #define SMC ((SMC_Type *)SMC_BASE)
12152 #define SMC_BASE_PTR (SMC)
12153 /** Array initializer of SMC peripheral base addresses */
12154 #define SMC_BASE_ADDRS { SMC_BASE }
12155 /** Array initializer of SMC peripheral base pointers */
12156 #define SMC_BASE_PTRS { SMC }
12157
12158 /* ----------------------------------------------------------------------------
12159 -- SMC - Register accessor macros
12160 ---------------------------------------------------------------------------- */
12161
12162 /*!
12163 * @addtogroup SMC_Register_Accessor_Macros SMC - Register accessor macros
12164 * @{
12165 */
12166
12167
12168 /* SMC - Register instance definitions */
12169 /* SMC */
12170 #define SMC_PMPROT SMC_PMPROT_REG(SMC)
12171 #define SMC_PMCTRL SMC_PMCTRL_REG(SMC)
12172 #define SMC_VLLSCTRL SMC_VLLSCTRL_REG(SMC)
12173 #define SMC_PMSTAT SMC_PMSTAT_REG(SMC)
12174
12175 /*!
12176 * @}
12177 */ /* end of group SMC_Register_Accessor_Macros */
12178
12179
12180 /*!
12181 * @}
12182 */ /* end of group SMC_Peripheral_Access_Layer */
12183
12184
12185 /* ----------------------------------------------------------------------------
12186 -- SPI Peripheral Access Layer
12187 ---------------------------------------------------------------------------- */
12188
12189 /*!
12190 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
12191 * @{
12192 */
12193
12194 /** SPI - Register Layout Typedef */
12195 typedef struct {
12196 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
12197 uint8_t RESERVED_0[4];
12198 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
12199 union { /* offset: 0xC */
12200 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
12201 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
12202 };
12203 uint8_t RESERVED_1[24];
12204 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
12205 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
12206 union { /* offset: 0x34 */
12207 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
12208 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
12209 };
12210 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
12211 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
12212 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
12213 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
12214 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
12215 uint8_t RESERVED_2[48];
12216 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
12217 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
12218 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
12219 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
12220 } SPI_Type, *SPI_MemMapPtr;
12221
12222 /* ----------------------------------------------------------------------------
12223 -- SPI - Register accessor macros
12224 ---------------------------------------------------------------------------- */
12225
12226 /*!
12227 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
12228 * @{
12229 */
12230
12231
12232 /* SPI - Register accessors */
12233 #define SPI_MCR_REG(base) ((base)->MCR)
12234 #define SPI_TCR_REG(base) ((base)->TCR)
12235 #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2])
12236 #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2])
12237 #define SPI_SR_REG(base) ((base)->SR)
12238 #define SPI_RSER_REG(base) ((base)->RSER)
12239 #define SPI_PUSHR_REG(base) ((base)->PUSHR)
12240 #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE)
12241 #define SPI_POPR_REG(base) ((base)->POPR)
12242 #define SPI_TXFR0_REG(base) ((base)->TXFR0)
12243 #define SPI_TXFR1_REG(base) ((base)->TXFR1)
12244 #define SPI_TXFR2_REG(base) ((base)->TXFR2)
12245 #define SPI_TXFR3_REG(base) ((base)->TXFR3)
12246 #define SPI_RXFR0_REG(base) ((base)->RXFR0)
12247 #define SPI_RXFR1_REG(base) ((base)->RXFR1)
12248 #define SPI_RXFR2_REG(base) ((base)->RXFR2)
12249 #define SPI_RXFR3_REG(base) ((base)->RXFR3)
12250
12251 /*!
12252 * @}
12253 */ /* end of group SPI_Register_Accessor_Macros */
12254
12255
12256 /* ----------------------------------------------------------------------------
12257 -- SPI Register Masks
12258 ---------------------------------------------------------------------------- */
12259
12260 /*!
12261 * @addtogroup SPI_Register_Masks SPI Register Masks
12262 * @{
12263 */
12264
12265 /* MCR Bit Fields */
12266 #define SPI_MCR_HALT_MASK 0x1u
12267 #define SPI_MCR_HALT_SHIFT 0
12268 #define SPI_MCR_SMPL_PT_MASK 0x300u
12269 #define SPI_MCR_SMPL_PT_SHIFT 8
12270 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_SMPL_PT_SHIFT))&SPI_MCR_SMPL_PT_MASK)
12271 #define SPI_MCR_CLR_RXF_MASK 0x400u
12272 #define SPI_MCR_CLR_RXF_SHIFT 10
12273 #define SPI_MCR_CLR_TXF_MASK 0x800u
12274 #define SPI_MCR_CLR_TXF_SHIFT 11
12275 #define SPI_MCR_DIS_RXF_MASK 0x1000u
12276 #define SPI_MCR_DIS_RXF_SHIFT 12
12277 #define SPI_MCR_DIS_TXF_MASK 0x2000u
12278 #define SPI_MCR_DIS_TXF_SHIFT 13
12279 #define SPI_MCR_MDIS_MASK 0x4000u
12280 #define SPI_MCR_MDIS_SHIFT 14
12281 #define SPI_MCR_DOZE_MASK 0x8000u
12282 #define SPI_MCR_DOZE_SHIFT 15
12283 #define SPI_MCR_PCSIS_MASK 0x3F0000u
12284 #define SPI_MCR_PCSIS_SHIFT 16
12285 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_PCSIS_SHIFT))&SPI_MCR_PCSIS_MASK)
12286 #define SPI_MCR_ROOE_MASK 0x1000000u
12287 #define SPI_MCR_ROOE_SHIFT 24
12288 #define SPI_MCR_PCSSE_MASK 0x2000000u
12289 #define SPI_MCR_PCSSE_SHIFT 25
12290 #define SPI_MCR_MTFE_MASK 0x4000000u
12291 #define SPI_MCR_MTFE_SHIFT 26
12292 #define SPI_MCR_FRZ_MASK 0x8000000u
12293 #define SPI_MCR_FRZ_SHIFT 27
12294 #define SPI_MCR_DCONF_MASK 0x30000000u
12295 #define SPI_MCR_DCONF_SHIFT 28
12296 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x))<<SPI_MCR_DCONF_SHIFT))&SPI_MCR_DCONF_MASK)
12297 #define SPI_MCR_CONT_SCKE_MASK 0x40000000u
12298 #define SPI_MCR_CONT_SCKE_SHIFT 30
12299 #define SPI_MCR_MSTR_MASK 0x80000000u
12300 #define SPI_MCR_MSTR_SHIFT 31
12301 /* TCR Bit Fields */
12302 #define SPI_TCR_SPI_TCNT_MASK 0xFFFF0000u
12303 #define SPI_TCR_SPI_TCNT_SHIFT 16
12304 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x))<<SPI_TCR_SPI_TCNT_SHIFT))&SPI_TCR_SPI_TCNT_MASK)
12305 /* CTAR Bit Fields */
12306 #define SPI_CTAR_BR_MASK 0xFu
12307 #define SPI_CTAR_BR_SHIFT 0
12308 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_BR_SHIFT))&SPI_CTAR_BR_MASK)
12309 #define SPI_CTAR_DT_MASK 0xF0u
12310 #define SPI_CTAR_DT_SHIFT 4
12311 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_DT_SHIFT))&SPI_CTAR_DT_MASK)
12312 #define SPI_CTAR_ASC_MASK 0xF00u
12313 #define SPI_CTAR_ASC_SHIFT 8
12314 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_ASC_SHIFT))&SPI_CTAR_ASC_MASK)
12315 #define SPI_CTAR_CSSCK_MASK 0xF000u
12316 #define SPI_CTAR_CSSCK_SHIFT 12
12317 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_CSSCK_SHIFT))&SPI_CTAR_CSSCK_MASK)
12318 #define SPI_CTAR_PBR_MASK 0x30000u
12319 #define SPI_CTAR_PBR_SHIFT 16
12320 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PBR_SHIFT))&SPI_CTAR_PBR_MASK)
12321 #define SPI_CTAR_PDT_MASK 0xC0000u
12322 #define SPI_CTAR_PDT_SHIFT 18
12323 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PDT_SHIFT))&SPI_CTAR_PDT_MASK)
12324 #define SPI_CTAR_PASC_MASK 0x300000u
12325 #define SPI_CTAR_PASC_SHIFT 20
12326 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PASC_SHIFT))&SPI_CTAR_PASC_MASK)
12327 #define SPI_CTAR_PCSSCK_MASK 0xC00000u
12328 #define SPI_CTAR_PCSSCK_SHIFT 22
12329 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_PCSSCK_SHIFT))&SPI_CTAR_PCSSCK_MASK)
12330 #define SPI_CTAR_LSBFE_MASK 0x1000000u
12331 #define SPI_CTAR_LSBFE_SHIFT 24
12332 #define SPI_CTAR_CPHA_MASK 0x2000000u
12333 #define SPI_CTAR_CPHA_SHIFT 25
12334 #define SPI_CTAR_CPOL_MASK 0x4000000u
12335 #define SPI_CTAR_CPOL_SHIFT 26
12336 #define SPI_CTAR_FMSZ_MASK 0x78000000u
12337 #define SPI_CTAR_FMSZ_SHIFT 27
12338 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_FMSZ_SHIFT))&SPI_CTAR_FMSZ_MASK)
12339 #define SPI_CTAR_DBR_MASK 0x80000000u
12340 #define SPI_CTAR_DBR_SHIFT 31
12341 /* CTAR_SLAVE Bit Fields */
12342 #define SPI_CTAR_SLAVE_CPHA_MASK 0x2000000u
12343 #define SPI_CTAR_SLAVE_CPHA_SHIFT 25
12344 #define SPI_CTAR_SLAVE_CPOL_MASK 0x4000000u
12345 #define SPI_CTAR_SLAVE_CPOL_SHIFT 26
12346 #define SPI_CTAR_SLAVE_FMSZ_MASK 0xF8000000u
12347 #define SPI_CTAR_SLAVE_FMSZ_SHIFT 27
12348 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x))<<SPI_CTAR_SLAVE_FMSZ_SHIFT))&SPI_CTAR_SLAVE_FMSZ_MASK)
12349 /* SR Bit Fields */
12350 #define SPI_SR_POPNXTPTR_MASK 0xFu
12351 #define SPI_SR_POPNXTPTR_SHIFT 0
12352 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_POPNXTPTR_SHIFT))&SPI_SR_POPNXTPTR_MASK)
12353 #define SPI_SR_RXCTR_MASK 0xF0u
12354 #define SPI_SR_RXCTR_SHIFT 4
12355 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_RXCTR_SHIFT))&SPI_SR_RXCTR_MASK)
12356 #define SPI_SR_TXNXTPTR_MASK 0xF00u
12357 #define SPI_SR_TXNXTPTR_SHIFT 8
12358 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXNXTPTR_SHIFT))&SPI_SR_TXNXTPTR_MASK)
12359 #define SPI_SR_TXCTR_MASK 0xF000u
12360 #define SPI_SR_TXCTR_SHIFT 12
12361 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x))<<SPI_SR_TXCTR_SHIFT))&SPI_SR_TXCTR_MASK)
12362 #define SPI_SR_RFDF_MASK 0x20000u
12363 #define SPI_SR_RFDF_SHIFT 17
12364 #define SPI_SR_RFOF_MASK 0x80000u
12365 #define SPI_SR_RFOF_SHIFT 19
12366 #define SPI_SR_TFFF_MASK 0x2000000u
12367 #define SPI_SR_TFFF_SHIFT 25
12368 #define SPI_SR_TFUF_MASK 0x8000000u
12369 #define SPI_SR_TFUF_SHIFT 27
12370 #define SPI_SR_EOQF_MASK 0x10000000u
12371 #define SPI_SR_EOQF_SHIFT 28
12372 #define SPI_SR_TXRXS_MASK 0x40000000u
12373 #define SPI_SR_TXRXS_SHIFT 30
12374 #define SPI_SR_TCF_MASK 0x80000000u
12375 #define SPI_SR_TCF_SHIFT 31
12376 /* RSER Bit Fields */
12377 #define SPI_RSER_RFDF_DIRS_MASK 0x10000u
12378 #define SPI_RSER_RFDF_DIRS_SHIFT 16
12379 #define SPI_RSER_RFDF_RE_MASK 0x20000u
12380 #define SPI_RSER_RFDF_RE_SHIFT 17
12381 #define SPI_RSER_RFOF_RE_MASK 0x80000u
12382 #define SPI_RSER_RFOF_RE_SHIFT 19
12383 #define SPI_RSER_TFFF_DIRS_MASK 0x1000000u
12384 #define SPI_RSER_TFFF_DIRS_SHIFT 24
12385 #define SPI_RSER_TFFF_RE_MASK 0x2000000u
12386 #define SPI_RSER_TFFF_RE_SHIFT 25
12387 #define SPI_RSER_TFUF_RE_MASK 0x8000000u
12388 #define SPI_RSER_TFUF_RE_SHIFT 27
12389 #define SPI_RSER_EOQF_RE_MASK 0x10000000u
12390 #define SPI_RSER_EOQF_RE_SHIFT 28
12391 #define SPI_RSER_TCF_RE_MASK 0x80000000u
12392 #define SPI_RSER_TCF_RE_SHIFT 31
12393 /* PUSHR Bit Fields */
12394 #define SPI_PUSHR_TXDATA_MASK 0xFFFFu
12395 #define SPI_PUSHR_TXDATA_SHIFT 0
12396 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_TXDATA_SHIFT))&SPI_PUSHR_TXDATA_MASK)
12397 #define SPI_PUSHR_PCS_MASK 0x3F0000u
12398 #define SPI_PUSHR_PCS_SHIFT 16
12399 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_PCS_SHIFT))&SPI_PUSHR_PCS_MASK)
12400 #define SPI_PUSHR_CTCNT_MASK 0x4000000u
12401 #define SPI_PUSHR_CTCNT_SHIFT 26
12402 #define SPI_PUSHR_EOQ_MASK 0x8000000u
12403 #define SPI_PUSHR_EOQ_SHIFT 27
12404 #define SPI_PUSHR_CTAS_MASK 0x70000000u
12405 #define SPI_PUSHR_CTAS_SHIFT 28
12406 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_CTAS_SHIFT))&SPI_PUSHR_CTAS_MASK)
12407 #define SPI_PUSHR_CONT_MASK 0x80000000u
12408 #define SPI_PUSHR_CONT_SHIFT 31
12409 /* PUSHR_SLAVE Bit Fields */
12410 #define SPI_PUSHR_SLAVE_TXDATA_MASK 0xFFFFFFFFu
12411 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT 0
12412 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_PUSHR_SLAVE_TXDATA_SHIFT))&SPI_PUSHR_SLAVE_TXDATA_MASK)
12413 /* POPR Bit Fields */
12414 #define SPI_POPR_RXDATA_MASK 0xFFFFFFFFu
12415 #define SPI_POPR_RXDATA_SHIFT 0
12416 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_POPR_RXDATA_SHIFT))&SPI_POPR_RXDATA_MASK)
12417 /* TXFR0 Bit Fields */
12418 #define SPI_TXFR0_TXDATA_MASK 0xFFFFu
12419 #define SPI_TXFR0_TXDATA_SHIFT 0
12420 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXDATA_SHIFT))&SPI_TXFR0_TXDATA_MASK)
12421 #define SPI_TXFR0_TXCMD_TXDATA_MASK 0xFFFF0000u
12422 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT 16
12423 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR0_TXCMD_TXDATA_SHIFT))&SPI_TXFR0_TXCMD_TXDATA_MASK)
12424 /* TXFR1 Bit Fields */
12425 #define SPI_TXFR1_TXDATA_MASK 0xFFFFu
12426 #define SPI_TXFR1_TXDATA_SHIFT 0
12427 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXDATA_SHIFT))&SPI_TXFR1_TXDATA_MASK)
12428 #define SPI_TXFR1_TXCMD_TXDATA_MASK 0xFFFF0000u
12429 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT 16
12430 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR1_TXCMD_TXDATA_SHIFT))&SPI_TXFR1_TXCMD_TXDATA_MASK)
12431 /* TXFR2 Bit Fields */
12432 #define SPI_TXFR2_TXDATA_MASK 0xFFFFu
12433 #define SPI_TXFR2_TXDATA_SHIFT 0
12434 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXDATA_SHIFT))&SPI_TXFR2_TXDATA_MASK)
12435 #define SPI_TXFR2_TXCMD_TXDATA_MASK 0xFFFF0000u
12436 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT 16
12437 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR2_TXCMD_TXDATA_SHIFT))&SPI_TXFR2_TXCMD_TXDATA_MASK)
12438 /* TXFR3 Bit Fields */
12439 #define SPI_TXFR3_TXDATA_MASK 0xFFFFu
12440 #define SPI_TXFR3_TXDATA_SHIFT 0
12441 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXDATA_SHIFT))&SPI_TXFR3_TXDATA_MASK)
12442 #define SPI_TXFR3_TXCMD_TXDATA_MASK 0xFFFF0000u
12443 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT 16
12444 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_TXFR3_TXCMD_TXDATA_SHIFT))&SPI_TXFR3_TXCMD_TXDATA_MASK)
12445 /* RXFR0 Bit Fields */
12446 #define SPI_RXFR0_RXDATA_MASK 0xFFFFFFFFu
12447 #define SPI_RXFR0_RXDATA_SHIFT 0
12448 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR0_RXDATA_SHIFT))&SPI_RXFR0_RXDATA_MASK)
12449 /* RXFR1 Bit Fields */
12450 #define SPI_RXFR1_RXDATA_MASK 0xFFFFFFFFu
12451 #define SPI_RXFR1_RXDATA_SHIFT 0
12452 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR1_RXDATA_SHIFT))&SPI_RXFR1_RXDATA_MASK)
12453 /* RXFR2 Bit Fields */
12454 #define SPI_RXFR2_RXDATA_MASK 0xFFFFFFFFu
12455 #define SPI_RXFR2_RXDATA_SHIFT 0
12456 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR2_RXDATA_SHIFT))&SPI_RXFR2_RXDATA_MASK)
12457 /* RXFR3 Bit Fields */
12458 #define SPI_RXFR3_RXDATA_MASK 0xFFFFFFFFu
12459 #define SPI_RXFR3_RXDATA_SHIFT 0
12460 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x))<<SPI_RXFR3_RXDATA_SHIFT))&SPI_RXFR3_RXDATA_MASK)
12461
12462 /*!
12463 * @}
12464 */ /* end of group SPI_Register_Masks */
12465
12466
12467 /* SPI - Peripheral instance base addresses */
12468 /** Peripheral SPI0 base address */
12469 #define SPI0_BASE (0x4002C000u)
12470 /** Peripheral SPI0 base pointer */
12471 #define SPI0 ((SPI_Type *)SPI0_BASE)
12472 #define SPI0_BASE_PTR (SPI0)
12473 /** Peripheral SPI1 base address */
12474 #define SPI1_BASE (0x4002D000u)
12475 /** Peripheral SPI1 base pointer */
12476 #define SPI1 ((SPI_Type *)SPI1_BASE)
12477 #define SPI1_BASE_PTR (SPI1)
12478 /** Peripheral SPI2 base address */
12479 #define SPI2_BASE (0x400AC000u)
12480 /** Peripheral SPI2 base pointer */
12481 #define SPI2 ((SPI_Type *)SPI2_BASE)
12482 #define SPI2_BASE_PTR (SPI2)
12483 /** Array initializer of SPI peripheral base addresses */
12484 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
12485 /** Array initializer of SPI peripheral base pointers */
12486 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
12487 /** Interrupt vectors for the SPI peripheral type */
12488 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
12489
12490 /* ----------------------------------------------------------------------------
12491 -- SPI - Register accessor macros
12492 ---------------------------------------------------------------------------- */
12493
12494 /*!
12495 * @addtogroup SPI_Register_Accessor_Macros SPI - Register accessor macros
12496 * @{
12497 */
12498
12499
12500 /* SPI - Register instance definitions */
12501 /* SPI0 */
12502 #define SPI0_MCR SPI_MCR_REG(SPI0)
12503 #define SPI0_TCR SPI_TCR_REG(SPI0)
12504 #define SPI0_CTAR0 SPI_CTAR_REG(SPI0,0)
12505 #define SPI0_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI0,0)
12506 #define SPI0_CTAR1 SPI_CTAR_REG(SPI0,1)
12507 #define SPI0_SR SPI_SR_REG(SPI0)
12508 #define SPI0_RSER SPI_RSER_REG(SPI0)
12509 #define SPI0_PUSHR SPI_PUSHR_REG(SPI0)
12510 #define SPI0_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI0)
12511 #define SPI0_POPR SPI_POPR_REG(SPI0)
12512 #define SPI0_TXFR0 SPI_TXFR0_REG(SPI0)
12513 #define SPI0_TXFR1 SPI_TXFR1_REG(SPI0)
12514 #define SPI0_TXFR2 SPI_TXFR2_REG(SPI0)
12515 #define SPI0_TXFR3 SPI_TXFR3_REG(SPI0)
12516 #define SPI0_RXFR0 SPI_RXFR0_REG(SPI0)
12517 #define SPI0_RXFR1 SPI_RXFR1_REG(SPI0)
12518 #define SPI0_RXFR2 SPI_RXFR2_REG(SPI0)
12519 #define SPI0_RXFR3 SPI_RXFR3_REG(SPI0)
12520 /* SPI1 */
12521 #define SPI1_MCR SPI_MCR_REG(SPI1)
12522 #define SPI1_TCR SPI_TCR_REG(SPI1)
12523 #define SPI1_CTAR0 SPI_CTAR_REG(SPI1,0)
12524 #define SPI1_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI1,0)
12525 #define SPI1_CTAR1 SPI_CTAR_REG(SPI1,1)
12526 #define SPI1_SR SPI_SR_REG(SPI1)
12527 #define SPI1_RSER SPI_RSER_REG(SPI1)
12528 #define SPI1_PUSHR SPI_PUSHR_REG(SPI1)
12529 #define SPI1_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI1)
12530 #define SPI1_POPR SPI_POPR_REG(SPI1)
12531 #define SPI1_TXFR0 SPI_TXFR0_REG(SPI1)
12532 #define SPI1_TXFR1 SPI_TXFR1_REG(SPI1)
12533 #define SPI1_TXFR2 SPI_TXFR2_REG(SPI1)
12534 #define SPI1_TXFR3 SPI_TXFR3_REG(SPI1)
12535 #define SPI1_RXFR0 SPI_RXFR0_REG(SPI1)
12536 #define SPI1_RXFR1 SPI_RXFR1_REG(SPI1)
12537 #define SPI1_RXFR2 SPI_RXFR2_REG(SPI1)
12538 #define SPI1_RXFR3 SPI_RXFR3_REG(SPI1)
12539 /* SPI2 */
12540 #define SPI2_MCR SPI_MCR_REG(SPI2)
12541 #define SPI2_TCR SPI_TCR_REG(SPI2)
12542 #define SPI2_CTAR0 SPI_CTAR_REG(SPI2,0)
12543 #define SPI2_CTAR0_SLAVE SPI_CTAR_SLAVE_REG(SPI2,0)
12544 #define SPI2_CTAR1 SPI_CTAR_REG(SPI2,1)
12545 #define SPI2_SR SPI_SR_REG(SPI2)
12546 #define SPI2_RSER SPI_RSER_REG(SPI2)
12547 #define SPI2_PUSHR SPI_PUSHR_REG(SPI2)
12548 #define SPI2_PUSHR_SLAVE SPI_PUSHR_SLAVE_REG(SPI2)
12549 #define SPI2_POPR SPI_POPR_REG(SPI2)
12550 #define SPI2_TXFR0 SPI_TXFR0_REG(SPI2)
12551 #define SPI2_TXFR1 SPI_TXFR1_REG(SPI2)
12552 #define SPI2_TXFR2 SPI_TXFR2_REG(SPI2)
12553 #define SPI2_TXFR3 SPI_TXFR3_REG(SPI2)
12554 #define SPI2_RXFR0 SPI_RXFR0_REG(SPI2)
12555 #define SPI2_RXFR1 SPI_RXFR1_REG(SPI2)
12556 #define SPI2_RXFR2 SPI_RXFR2_REG(SPI2)
12557 #define SPI2_RXFR3 SPI_RXFR3_REG(SPI2)
12558
12559 /* SPI - Register array accessors */
12560 #define SPI0_CTAR(index2) SPI_CTAR_REG(SPI0,index2)
12561 #define SPI1_CTAR(index2) SPI_CTAR_REG(SPI1,index2)
12562 #define SPI2_CTAR(index2) SPI_CTAR_REG(SPI2,index2)
12563 #define SPI0_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI0,index2)
12564 #define SPI1_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI1,index2)
12565 #define SPI2_CTAR_SLAVE(index2) SPI_CTAR_SLAVE_REG(SPI2,index2)
12566
12567 /*!
12568 * @}
12569 */ /* end of group SPI_Register_Accessor_Macros */
12570
12571
12572 /*!
12573 * @}
12574 */ /* end of group SPI_Peripheral_Access_Layer */
12575
12576
12577 /* ----------------------------------------------------------------------------
12578 -- UART Peripheral Access Layer
12579 ---------------------------------------------------------------------------- */
12580
12581 /*!
12582 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
12583 * @{
12584 */
12585
12586 /** UART - Register Layout Typedef */
12587 typedef struct {
12588 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
12589 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
12590 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
12591 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
12592 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
12593 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
12594 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
12595 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
12596 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
12597 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
12598 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
12599 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
12600 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
12601 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
12602 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
12603 uint8_t RESERVED_0[1];
12604 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
12605 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
12606 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
12607 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
12608 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
12609 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
12610 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
12611 uint8_t RESERVED_1[1];
12612 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
12613 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
12614 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
12615 union { /* offset: 0x1B */
12616 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
12617 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
12618 };
12619 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
12620 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
12621 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
12622 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
12623 } UART_Type, *UART_MemMapPtr;
12624
12625 /* ----------------------------------------------------------------------------
12626 -- UART - Register accessor macros
12627 ---------------------------------------------------------------------------- */
12628
12629 /*!
12630 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
12631 * @{
12632 */
12633
12634
12635 /* UART - Register accessors */
12636 #define UART_BDH_REG(base) ((base)->BDH)
12637 #define UART_BDL_REG(base) ((base)->BDL)
12638 #define UART_C1_REG(base) ((base)->C1)
12639 #define UART_C2_REG(base) ((base)->C2)
12640 #define UART_S1_REG(base) ((base)->S1)
12641 #define UART_S2_REG(base) ((base)->S2)
12642 #define UART_C3_REG(base) ((base)->C3)
12643 #define UART_D_REG(base) ((base)->D)
12644 #define UART_MA1_REG(base) ((base)->MA1)
12645 #define UART_MA2_REG(base) ((base)->MA2)
12646 #define UART_C4_REG(base) ((base)->C4)
12647 #define UART_C5_REG(base) ((base)->C5)
12648 #define UART_ED_REG(base) ((base)->ED)
12649 #define UART_MODEM_REG(base) ((base)->MODEM)
12650 #define UART_IR_REG(base) ((base)->IR)
12651 #define UART_PFIFO_REG(base) ((base)->PFIFO)
12652 #define UART_CFIFO_REG(base) ((base)->CFIFO)
12653 #define UART_SFIFO_REG(base) ((base)->SFIFO)
12654 #define UART_TWFIFO_REG(base) ((base)->TWFIFO)
12655 #define UART_TCFIFO_REG(base) ((base)->TCFIFO)
12656 #define UART_RWFIFO_REG(base) ((base)->RWFIFO)
12657 #define UART_RCFIFO_REG(base) ((base)->RCFIFO)
12658 #define UART_C7816_REG(base) ((base)->C7816)
12659 #define UART_IE7816_REG(base) ((base)->IE7816)
12660 #define UART_IS7816_REG(base) ((base)->IS7816)
12661 #define UART_WP7816T0_REG(base) ((base)->WP7816T0)
12662 #define UART_WP7816T1_REG(base) ((base)->WP7816T1)
12663 #define UART_WN7816_REG(base) ((base)->WN7816)
12664 #define UART_WF7816_REG(base) ((base)->WF7816)
12665 #define UART_ET7816_REG(base) ((base)->ET7816)
12666 #define UART_TL7816_REG(base) ((base)->TL7816)
12667
12668 /*!
12669 * @}
12670 */ /* end of group UART_Register_Accessor_Macros */
12671
12672
12673 /* ----------------------------------------------------------------------------
12674 -- UART Register Masks
12675 ---------------------------------------------------------------------------- */
12676
12677 /*!
12678 * @addtogroup UART_Register_Masks UART Register Masks
12679 * @{
12680 */
12681
12682 /* BDH Bit Fields */
12683 #define UART_BDH_SBR_MASK 0x1Fu
12684 #define UART_BDH_SBR_SHIFT 0
12685 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
12686 #define UART_BDH_SBNS_MASK 0x20u
12687 #define UART_BDH_SBNS_SHIFT 5
12688 #define UART_BDH_RXEDGIE_MASK 0x40u
12689 #define UART_BDH_RXEDGIE_SHIFT 6
12690 #define UART_BDH_LBKDIE_MASK 0x80u
12691 #define UART_BDH_LBKDIE_SHIFT 7
12692 /* BDL Bit Fields */
12693 #define UART_BDL_SBR_MASK 0xFFu
12694 #define UART_BDL_SBR_SHIFT 0
12695 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
12696 /* C1 Bit Fields */
12697 #define UART_C1_PT_MASK 0x1u
12698 #define UART_C1_PT_SHIFT 0
12699 #define UART_C1_PE_MASK 0x2u
12700 #define UART_C1_PE_SHIFT 1
12701 #define UART_C1_ILT_MASK 0x4u
12702 #define UART_C1_ILT_SHIFT 2
12703 #define UART_C1_WAKE_MASK 0x8u
12704 #define UART_C1_WAKE_SHIFT 3
12705 #define UART_C1_M_MASK 0x10u
12706 #define UART_C1_M_SHIFT 4
12707 #define UART_C1_RSRC_MASK 0x20u
12708 #define UART_C1_RSRC_SHIFT 5
12709 #define UART_C1_UARTSWAI_MASK 0x40u
12710 #define UART_C1_UARTSWAI_SHIFT 6
12711 #define UART_C1_LOOPS_MASK 0x80u
12712 #define UART_C1_LOOPS_SHIFT 7
12713 /* C2 Bit Fields */
12714 #define UART_C2_SBK_MASK 0x1u
12715 #define UART_C2_SBK_SHIFT 0
12716 #define UART_C2_RWU_MASK 0x2u
12717 #define UART_C2_RWU_SHIFT 1
12718 #define UART_C2_RE_MASK 0x4u
12719 #define UART_C2_RE_SHIFT 2
12720 #define UART_C2_TE_MASK 0x8u
12721 #define UART_C2_TE_SHIFT 3
12722 #define UART_C2_ILIE_MASK 0x10u
12723 #define UART_C2_ILIE_SHIFT 4
12724 #define UART_C2_RIE_MASK 0x20u
12725 #define UART_C2_RIE_SHIFT 5
12726 #define UART_C2_TCIE_MASK 0x40u
12727 #define UART_C2_TCIE_SHIFT 6
12728 #define UART_C2_TIE_MASK 0x80u
12729 #define UART_C2_TIE_SHIFT 7
12730 /* S1 Bit Fields */
12731 #define UART_S1_PF_MASK 0x1u
12732 #define UART_S1_PF_SHIFT 0
12733 #define UART_S1_FE_MASK 0x2u
12734 #define UART_S1_FE_SHIFT 1
12735 #define UART_S1_NF_MASK 0x4u
12736 #define UART_S1_NF_SHIFT 2
12737 #define UART_S1_OR_MASK 0x8u
12738 #define UART_S1_OR_SHIFT 3
12739 #define UART_S1_IDLE_MASK 0x10u
12740 #define UART_S1_IDLE_SHIFT 4
12741 #define UART_S1_RDRF_MASK 0x20u
12742 #define UART_S1_RDRF_SHIFT 5
12743 #define UART_S1_TC_MASK 0x40u
12744 #define UART_S1_TC_SHIFT 6
12745 #define UART_S1_TDRE_MASK 0x80u
12746 #define UART_S1_TDRE_SHIFT 7
12747 /* S2 Bit Fields */
12748 #define UART_S2_RAF_MASK 0x1u
12749 #define UART_S2_RAF_SHIFT 0
12750 #define UART_S2_LBKDE_MASK 0x2u
12751 #define UART_S2_LBKDE_SHIFT 1
12752 #define UART_S2_BRK13_MASK 0x4u
12753 #define UART_S2_BRK13_SHIFT 2
12754 #define UART_S2_RWUID_MASK 0x8u
12755 #define UART_S2_RWUID_SHIFT 3
12756 #define UART_S2_RXINV_MASK 0x10u
12757 #define UART_S2_RXINV_SHIFT 4
12758 #define UART_S2_MSBF_MASK 0x20u
12759 #define UART_S2_MSBF_SHIFT 5
12760 #define UART_S2_RXEDGIF_MASK 0x40u
12761 #define UART_S2_RXEDGIF_SHIFT 6
12762 #define UART_S2_LBKDIF_MASK 0x80u
12763 #define UART_S2_LBKDIF_SHIFT 7
12764 /* C3 Bit Fields */
12765 #define UART_C3_PEIE_MASK 0x1u
12766 #define UART_C3_PEIE_SHIFT 0
12767 #define UART_C3_FEIE_MASK 0x2u
12768 #define UART_C3_FEIE_SHIFT 1
12769 #define UART_C3_NEIE_MASK 0x4u
12770 #define UART_C3_NEIE_SHIFT 2
12771 #define UART_C3_ORIE_MASK 0x8u
12772 #define UART_C3_ORIE_SHIFT 3
12773 #define UART_C3_TXINV_MASK 0x10u
12774 #define UART_C3_TXINV_SHIFT 4
12775 #define UART_C3_TXDIR_MASK 0x20u
12776 #define UART_C3_TXDIR_SHIFT 5
12777 #define UART_C3_T8_MASK 0x40u
12778 #define UART_C3_T8_SHIFT 6
12779 #define UART_C3_R8_MASK 0x80u
12780 #define UART_C3_R8_SHIFT 7
12781 /* D Bit Fields */
12782 #define UART_D_RT_MASK 0xFFu
12783 #define UART_D_RT_SHIFT 0
12784 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x))<<UART_D_RT_SHIFT))&UART_D_RT_MASK)
12785 /* MA1 Bit Fields */
12786 #define UART_MA1_MA_MASK 0xFFu
12787 #define UART_MA1_MA_SHIFT 0
12788 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA1_MA_SHIFT))&UART_MA1_MA_MASK)
12789 /* MA2 Bit Fields */
12790 #define UART_MA2_MA_MASK 0xFFu
12791 #define UART_MA2_MA_SHIFT 0
12792 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UART_MA2_MA_SHIFT))&UART_MA2_MA_MASK)
12793 /* C4 Bit Fields */
12794 #define UART_C4_BRFA_MASK 0x1Fu
12795 #define UART_C4_BRFA_SHIFT 0
12796 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x))<<UART_C4_BRFA_SHIFT))&UART_C4_BRFA_MASK)
12797 #define UART_C4_M10_MASK 0x20u
12798 #define UART_C4_M10_SHIFT 5
12799 #define UART_C4_MAEN2_MASK 0x40u
12800 #define UART_C4_MAEN2_SHIFT 6
12801 #define UART_C4_MAEN1_MASK 0x80u
12802 #define UART_C4_MAEN1_SHIFT 7
12803 /* C5 Bit Fields */
12804 #define UART_C5_LBKDDMAS_MASK 0x8u
12805 #define UART_C5_LBKDDMAS_SHIFT 3
12806 #define UART_C5_ILDMAS_MASK 0x10u
12807 #define UART_C5_ILDMAS_SHIFT 4
12808 #define UART_C5_RDMAS_MASK 0x20u
12809 #define UART_C5_RDMAS_SHIFT 5
12810 #define UART_C5_TCDMAS_MASK 0x40u
12811 #define UART_C5_TCDMAS_SHIFT 6
12812 #define UART_C5_TDMAS_MASK 0x80u
12813 #define UART_C5_TDMAS_SHIFT 7
12814 /* ED Bit Fields */
12815 #define UART_ED_PARITYE_MASK 0x40u
12816 #define UART_ED_PARITYE_SHIFT 6
12817 #define UART_ED_NOISY_MASK 0x80u
12818 #define UART_ED_NOISY_SHIFT 7
12819 /* MODEM Bit Fields */
12820 #define UART_MODEM_TXCTSE_MASK 0x1u
12821 #define UART_MODEM_TXCTSE_SHIFT 0
12822 #define UART_MODEM_TXRTSE_MASK 0x2u
12823 #define UART_MODEM_TXRTSE_SHIFT 1
12824 #define UART_MODEM_TXRTSPOL_MASK 0x4u
12825 #define UART_MODEM_TXRTSPOL_SHIFT 2
12826 #define UART_MODEM_RXRTSE_MASK 0x8u
12827 #define UART_MODEM_RXRTSE_SHIFT 3
12828 /* IR Bit Fields */
12829 #define UART_IR_TNP_MASK 0x3u
12830 #define UART_IR_TNP_SHIFT 0
12831 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x))<<UART_IR_TNP_SHIFT))&UART_IR_TNP_MASK)
12832 #define UART_IR_IREN_MASK 0x4u
12833 #define UART_IR_IREN_SHIFT 2
12834 /* PFIFO Bit Fields */
12835 #define UART_PFIFO_RXFIFOSIZE_MASK 0x7u
12836 #define UART_PFIFO_RXFIFOSIZE_SHIFT 0
12837 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_RXFIFOSIZE_SHIFT))&UART_PFIFO_RXFIFOSIZE_MASK)
12838 #define UART_PFIFO_RXFE_MASK 0x8u
12839 #define UART_PFIFO_RXFE_SHIFT 3
12840 #define UART_PFIFO_TXFIFOSIZE_MASK 0x70u
12841 #define UART_PFIFO_TXFIFOSIZE_SHIFT 4
12842 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x))<<UART_PFIFO_TXFIFOSIZE_SHIFT))&UART_PFIFO_TXFIFOSIZE_MASK)
12843 #define UART_PFIFO_TXFE_MASK 0x80u
12844 #define UART_PFIFO_TXFE_SHIFT 7
12845 /* CFIFO Bit Fields */
12846 #define UART_CFIFO_RXUFE_MASK 0x1u
12847 #define UART_CFIFO_RXUFE_SHIFT 0
12848 #define UART_CFIFO_TXOFE_MASK 0x2u
12849 #define UART_CFIFO_TXOFE_SHIFT 1
12850 #define UART_CFIFO_RXOFE_MASK 0x4u
12851 #define UART_CFIFO_RXOFE_SHIFT 2
12852 #define UART_CFIFO_RXFLUSH_MASK 0x40u
12853 #define UART_CFIFO_RXFLUSH_SHIFT 6
12854 #define UART_CFIFO_TXFLUSH_MASK 0x80u
12855 #define UART_CFIFO_TXFLUSH_SHIFT 7
12856 /* SFIFO Bit Fields */
12857 #define UART_SFIFO_RXUF_MASK 0x1u
12858 #define UART_SFIFO_RXUF_SHIFT 0
12859 #define UART_SFIFO_TXOF_MASK 0x2u
12860 #define UART_SFIFO_TXOF_SHIFT 1
12861 #define UART_SFIFO_RXOF_MASK 0x4u
12862 #define UART_SFIFO_RXOF_SHIFT 2
12863 #define UART_SFIFO_RXEMPT_MASK 0x40u
12864 #define UART_SFIFO_RXEMPT_SHIFT 6
12865 #define UART_SFIFO_TXEMPT_MASK 0x80u
12866 #define UART_SFIFO_TXEMPT_SHIFT 7
12867 /* TWFIFO Bit Fields */
12868 #define UART_TWFIFO_TXWATER_MASK 0xFFu
12869 #define UART_TWFIFO_TXWATER_SHIFT 0
12870 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_TWFIFO_TXWATER_SHIFT))&UART_TWFIFO_TXWATER_MASK)
12871 /* TCFIFO Bit Fields */
12872 #define UART_TCFIFO_TXCOUNT_MASK 0xFFu
12873 #define UART_TCFIFO_TXCOUNT_SHIFT 0
12874 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_TCFIFO_TXCOUNT_SHIFT))&UART_TCFIFO_TXCOUNT_MASK)
12875 /* RWFIFO Bit Fields */
12876 #define UART_RWFIFO_RXWATER_MASK 0xFFu
12877 #define UART_RWFIFO_RXWATER_SHIFT 0
12878 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x))<<UART_RWFIFO_RXWATER_SHIFT))&UART_RWFIFO_RXWATER_MASK)
12879 /* RCFIFO Bit Fields */
12880 #define UART_RCFIFO_RXCOUNT_MASK 0xFFu
12881 #define UART_RCFIFO_RXCOUNT_SHIFT 0
12882 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x))<<UART_RCFIFO_RXCOUNT_SHIFT))&UART_RCFIFO_RXCOUNT_MASK)
12883 /* C7816 Bit Fields */
12884 #define UART_C7816_ISO_7816E_MASK 0x1u
12885 #define UART_C7816_ISO_7816E_SHIFT 0
12886 #define UART_C7816_TTYPE_MASK 0x2u
12887 #define UART_C7816_TTYPE_SHIFT 1
12888 #define UART_C7816_INIT_MASK 0x4u
12889 #define UART_C7816_INIT_SHIFT 2
12890 #define UART_C7816_ANACK_MASK 0x8u
12891 #define UART_C7816_ANACK_SHIFT 3
12892 #define UART_C7816_ONACK_MASK 0x10u
12893 #define UART_C7816_ONACK_SHIFT 4
12894 /* IE7816 Bit Fields */
12895 #define UART_IE7816_RXTE_MASK 0x1u
12896 #define UART_IE7816_RXTE_SHIFT 0
12897 #define UART_IE7816_TXTE_MASK 0x2u
12898 #define UART_IE7816_TXTE_SHIFT 1
12899 #define UART_IE7816_GTVE_MASK 0x4u
12900 #define UART_IE7816_GTVE_SHIFT 2
12901 #define UART_IE7816_INITDE_MASK 0x10u
12902 #define UART_IE7816_INITDE_SHIFT 4
12903 #define UART_IE7816_BWTE_MASK 0x20u
12904 #define UART_IE7816_BWTE_SHIFT 5
12905 #define UART_IE7816_CWTE_MASK 0x40u
12906 #define UART_IE7816_CWTE_SHIFT 6
12907 #define UART_IE7816_WTE_MASK 0x80u
12908 #define UART_IE7816_WTE_SHIFT 7
12909 /* IS7816 Bit Fields */
12910 #define UART_IS7816_RXT_MASK 0x1u
12911 #define UART_IS7816_RXT_SHIFT 0
12912 #define UART_IS7816_TXT_MASK 0x2u
12913 #define UART_IS7816_TXT_SHIFT 1
12914 #define UART_IS7816_GTV_MASK 0x4u
12915 #define UART_IS7816_GTV_SHIFT 2
12916 #define UART_IS7816_INITD_MASK 0x10u
12917 #define UART_IS7816_INITD_SHIFT 4
12918 #define UART_IS7816_BWT_MASK 0x20u
12919 #define UART_IS7816_BWT_SHIFT 5
12920 #define UART_IS7816_CWT_MASK 0x40u
12921 #define UART_IS7816_CWT_SHIFT 6
12922 #define UART_IS7816_WT_MASK 0x80u
12923 #define UART_IS7816_WT_SHIFT 7
12924 /* WP7816T0 Bit Fields */
12925 #define UART_WP7816T0_WI_MASK 0xFFu
12926 #define UART_WP7816T0_WI_SHIFT 0
12927 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T0_WI_SHIFT))&UART_WP7816T0_WI_MASK)
12928 /* WP7816T1 Bit Fields */
12929 #define UART_WP7816T1_BWI_MASK 0xFu
12930 #define UART_WP7816T1_BWI_SHIFT 0
12931 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_BWI_SHIFT))&UART_WP7816T1_BWI_MASK)
12932 #define UART_WP7816T1_CWI_MASK 0xF0u
12933 #define UART_WP7816T1_CWI_SHIFT 4
12934 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x))<<UART_WP7816T1_CWI_SHIFT))&UART_WP7816T1_CWI_MASK)
12935 /* WN7816 Bit Fields */
12936 #define UART_WN7816_GTN_MASK 0xFFu
12937 #define UART_WN7816_GTN_SHIFT 0
12938 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x))<<UART_WN7816_GTN_SHIFT))&UART_WN7816_GTN_MASK)
12939 /* WF7816 Bit Fields */
12940 #define UART_WF7816_GTFD_MASK 0xFFu
12941 #define UART_WF7816_GTFD_SHIFT 0
12942 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x))<<UART_WF7816_GTFD_SHIFT))&UART_WF7816_GTFD_MASK)
12943 /* ET7816 Bit Fields */
12944 #define UART_ET7816_RXTHRESHOLD_MASK 0xFu
12945 #define UART_ET7816_RXTHRESHOLD_SHIFT 0
12946 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_RXTHRESHOLD_SHIFT))&UART_ET7816_RXTHRESHOLD_MASK)
12947 #define UART_ET7816_TXTHRESHOLD_MASK 0xF0u
12948 #define UART_ET7816_TXTHRESHOLD_SHIFT 4
12949 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x))<<UART_ET7816_TXTHRESHOLD_SHIFT))&UART_ET7816_TXTHRESHOLD_MASK)
12950 /* TL7816 Bit Fields */
12951 #define UART_TL7816_TLEN_MASK 0xFFu
12952 #define UART_TL7816_TLEN_SHIFT 0
12953 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x))<<UART_TL7816_TLEN_SHIFT))&UART_TL7816_TLEN_MASK)
12954
12955 /*!
12956 * @}
12957 */ /* end of group UART_Register_Masks */
12958
12959
12960 /* UART - Peripheral instance base addresses */
12961 /** Peripheral UART0 base address */
12962 #define UART0_BASE (0x4006A000u)
12963 /** Peripheral UART0 base pointer */
12964 #define UART0 ((UART_Type *)UART0_BASE)
12965 #define UART0_BASE_PTR (UART0)
12966 /** Peripheral UART1 base address */
12967 #define UART1_BASE (0x4006B000u)
12968 /** Peripheral UART1 base pointer */
12969 #define UART1 ((UART_Type *)UART1_BASE)
12970 #define UART1_BASE_PTR (UART1)
12971 /** Peripheral UART2 base address */
12972 #define UART2_BASE (0x4006C000u)
12973 /** Peripheral UART2 base pointer */
12974 #define UART2 ((UART_Type *)UART2_BASE)
12975 #define UART2_BASE_PTR (UART2)
12976 /** Peripheral UART3 base address */
12977 #define UART3_BASE (0x4006D000u)
12978 /** Peripheral UART3 base pointer */
12979 #define UART3 ((UART_Type *)UART3_BASE)
12980 #define UART3_BASE_PTR (UART3)
12981 /** Peripheral UART4 base address */
12982 #define UART4_BASE (0x400EA000u)
12983 /** Peripheral UART4 base pointer */
12984 #define UART4 ((UART_Type *)UART4_BASE)
12985 #define UART4_BASE_PTR (UART4)
12986 /** Peripheral UART5 base address */
12987 #define UART5_BASE (0x400EB000u)
12988 /** Peripheral UART5 base pointer */
12989 #define UART5 ((UART_Type *)UART5_BASE)
12990 #define UART5_BASE_PTR (UART5)
12991 /** Array initializer of UART peripheral base addresses */
12992 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
12993 /** Array initializer of UART peripheral base pointers */
12994 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
12995 /** Interrupt vectors for the UART peripheral type */
12996 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
12997 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
12998 #define UART_LON_IRQS { UART0_LON_IRQn, 0, 0, 0, 0, 0 }
12999
13000 /* ----------------------------------------------------------------------------
13001 -- UART - Register accessor macros
13002 ---------------------------------------------------------------------------- */
13003
13004 /*!
13005 * @addtogroup UART_Register_Accessor_Macros UART - Register accessor macros
13006 * @{
13007 */
13008
13009
13010 /* UART - Register instance definitions */
13011 /* UART0 */
13012 #define UART0_BDH UART_BDH_REG(UART0)
13013 #define UART0_BDL UART_BDL_REG(UART0)
13014 #define UART0_C1 UART_C1_REG(UART0)
13015 #define UART0_C2 UART_C2_REG(UART0)
13016 #define UART0_S1 UART_S1_REG(UART0)
13017 #define UART0_S2 UART_S2_REG(UART0)
13018 #define UART0_C3 UART_C3_REG(UART0)
13019 #define UART0_D UART_D_REG(UART0)
13020 #define UART0_MA1 UART_MA1_REG(UART0)
13021 #define UART0_MA2 UART_MA2_REG(UART0)
13022 #define UART0_C4 UART_C4_REG(UART0)
13023 #define UART0_C5 UART_C5_REG(UART0)
13024 #define UART0_ED UART_ED_REG(UART0)
13025 #define UART0_MODEM UART_MODEM_REG(UART0)
13026 #define UART0_IR UART_IR_REG(UART0)
13027 #define UART0_PFIFO UART_PFIFO_REG(UART0)
13028 #define UART0_CFIFO UART_CFIFO_REG(UART0)
13029 #define UART0_SFIFO UART_SFIFO_REG(UART0)
13030 #define UART0_TWFIFO UART_TWFIFO_REG(UART0)
13031 #define UART0_TCFIFO UART_TCFIFO_REG(UART0)
13032 #define UART0_RWFIFO UART_RWFIFO_REG(UART0)
13033 #define UART0_RCFIFO UART_RCFIFO_REG(UART0)
13034 #define UART0_C7816 UART_C7816_REG(UART0)
13035 #define UART0_IE7816 UART_IE7816_REG(UART0)
13036 #define UART0_IS7816 UART_IS7816_REG(UART0)
13037 #define UART0_WP7816T0 UART_WP7816T0_REG(UART0)
13038 #define UART0_WP7816T1 UART_WP7816T1_REG(UART0)
13039 #define UART0_WN7816 UART_WN7816_REG(UART0)
13040 #define UART0_WF7816 UART_WF7816_REG(UART0)
13041 #define UART0_ET7816 UART_ET7816_REG(UART0)
13042 #define UART0_TL7816 UART_TL7816_REG(UART0)
13043 /* UART1 */
13044 #define UART1_BDH UART_BDH_REG(UART1)
13045 #define UART1_BDL UART_BDL_REG(UART1)
13046 #define UART1_C1 UART_C1_REG(UART1)
13047 #define UART1_C2 UART_C2_REG(UART1)
13048 #define UART1_S1 UART_S1_REG(UART1)
13049 #define UART1_S2 UART_S2_REG(UART1)
13050 #define UART1_C3 UART_C3_REG(UART1)
13051 #define UART1_D UART_D_REG(UART1)
13052 #define UART1_MA1 UART_MA1_REG(UART1)
13053 #define UART1_MA2 UART_MA2_REG(UART1)
13054 #define UART1_C4 UART_C4_REG(UART1)
13055 #define UART1_C5 UART_C5_REG(UART1)
13056 #define UART1_ED UART_ED_REG(UART1)
13057 #define UART1_MODEM UART_MODEM_REG(UART1)
13058 #define UART1_IR UART_IR_REG(UART1)
13059 #define UART1_PFIFO UART_PFIFO_REG(UART1)
13060 #define UART1_CFIFO UART_CFIFO_REG(UART1)
13061 #define UART1_SFIFO UART_SFIFO_REG(UART1)
13062 #define UART1_TWFIFO UART_TWFIFO_REG(UART1)
13063 #define UART1_TCFIFO UART_TCFIFO_REG(UART1)
13064 #define UART1_RWFIFO UART_RWFIFO_REG(UART1)
13065 #define UART1_RCFIFO UART_RCFIFO_REG(UART1)
13066 /* UART2 */
13067 #define UART2_BDH UART_BDH_REG(UART2)
13068 #define UART2_BDL UART_BDL_REG(UART2)
13069 #define UART2_C1 UART_C1_REG(UART2)
13070 #define UART2_C2 UART_C2_REG(UART2)
13071 #define UART2_S1 UART_S1_REG(UART2)
13072 #define UART2_S2 UART_S2_REG(UART2)
13073 #define UART2_C3 UART_C3_REG(UART2)
13074 #define UART2_D UART_D_REG(UART2)
13075 #define UART2_MA1 UART_MA1_REG(UART2)
13076 #define UART2_MA2 UART_MA2_REG(UART2)
13077 #define UART2_C4 UART_C4_REG(UART2)
13078 #define UART2_C5 UART_C5_REG(UART2)
13079 #define UART2_ED UART_ED_REG(UART2)
13080 #define UART2_MODEM UART_MODEM_REG(UART2)
13081 #define UART2_IR UART_IR_REG(UART2)
13082 #define UART2_PFIFO UART_PFIFO_REG(UART2)
13083 #define UART2_CFIFO UART_CFIFO_REG(UART2)
13084 #define UART2_SFIFO UART_SFIFO_REG(UART2)
13085 #define UART2_TWFIFO UART_TWFIFO_REG(UART2)
13086 #define UART2_TCFIFO UART_TCFIFO_REG(UART2)
13087 #define UART2_RWFIFO UART_RWFIFO_REG(UART2)
13088 #define UART2_RCFIFO UART_RCFIFO_REG(UART2)
13089 /* UART3 */
13090 #define UART3_BDH UART_BDH_REG(UART3)
13091 #define UART3_BDL UART_BDL_REG(UART3)
13092 #define UART3_C1 UART_C1_REG(UART3)
13093 #define UART3_C2 UART_C2_REG(UART3)
13094 #define UART3_S1 UART_S1_REG(UART3)
13095 #define UART3_S2 UART_S2_REG(UART3)
13096 #define UART3_C3 UART_C3_REG(UART3)
13097 #define UART3_D UART_D_REG(UART3)
13098 #define UART3_MA1 UART_MA1_REG(UART3)
13099 #define UART3_MA2 UART_MA2_REG(UART3)
13100 #define UART3_C4 UART_C4_REG(UART3)
13101 #define UART3_C5 UART_C5_REG(UART3)
13102 #define UART3_ED UART_ED_REG(UART3)
13103 #define UART3_MODEM UART_MODEM_REG(UART3)
13104 #define UART3_IR UART_IR_REG(UART3)
13105 #define UART3_PFIFO UART_PFIFO_REG(UART3)
13106 #define UART3_CFIFO UART_CFIFO_REG(UART3)
13107 #define UART3_SFIFO UART_SFIFO_REG(UART3)
13108 #define UART3_TWFIFO UART_TWFIFO_REG(UART3)
13109 #define UART3_TCFIFO UART_TCFIFO_REG(UART3)
13110 #define UART3_RWFIFO UART_RWFIFO_REG(UART3)
13111 #define UART3_RCFIFO UART_RCFIFO_REG(UART3)
13112 /* UART4 */
13113 #define UART4_BDH UART_BDH_REG(UART4)
13114 #define UART4_BDL UART_BDL_REG(UART4)
13115 #define UART4_C1 UART_C1_REG(UART4)
13116 #define UART4_C2 UART_C2_REG(UART4)
13117 #define UART4_S1 UART_S1_REG(UART4)
13118 #define UART4_S2 UART_S2_REG(UART4)
13119 #define UART4_C3 UART_C3_REG(UART4)
13120 #define UART4_D UART_D_REG(UART4)
13121 #define UART4_MA1 UART_MA1_REG(UART4)
13122 #define UART4_MA2 UART_MA2_REG(UART4)
13123 #define UART4_C4 UART_C4_REG(UART4)
13124 #define UART4_C5 UART_C5_REG(UART4)
13125 #define UART4_ED UART_ED_REG(UART4)
13126 #define UART4_MODEM UART_MODEM_REG(UART4)
13127 #define UART4_IR UART_IR_REG(UART4)
13128 #define UART4_PFIFO UART_PFIFO_REG(UART4)
13129 #define UART4_CFIFO UART_CFIFO_REG(UART4)
13130 #define UART4_SFIFO UART_SFIFO_REG(UART4)
13131 #define UART4_TWFIFO UART_TWFIFO_REG(UART4)
13132 #define UART4_TCFIFO UART_TCFIFO_REG(UART4)
13133 #define UART4_RWFIFO UART_RWFIFO_REG(UART4)
13134 #define UART4_RCFIFO UART_RCFIFO_REG(UART4)
13135 /* UART5 */
13136 #define UART5_BDH UART_BDH_REG(UART5)
13137 #define UART5_BDL UART_BDL_REG(UART5)
13138 #define UART5_C1 UART_C1_REG(UART5)
13139 #define UART5_C2 UART_C2_REG(UART5)
13140 #define UART5_S1 UART_S1_REG(UART5)
13141 #define UART5_S2 UART_S2_REG(UART5)
13142 #define UART5_C3 UART_C3_REG(UART5)
13143 #define UART5_D UART_D_REG(UART5)
13144 #define UART5_MA1 UART_MA1_REG(UART5)
13145 #define UART5_MA2 UART_MA2_REG(UART5)
13146 #define UART5_C4 UART_C4_REG(UART5)
13147 #define UART5_C5 UART_C5_REG(UART5)
13148 #define UART5_ED UART_ED_REG(UART5)
13149 #define UART5_MODEM UART_MODEM_REG(UART5)
13150 #define UART5_IR UART_IR_REG(UART5)
13151 #define UART5_PFIFO UART_PFIFO_REG(UART5)
13152 #define UART5_CFIFO UART_CFIFO_REG(UART5)
13153 #define UART5_SFIFO UART_SFIFO_REG(UART5)
13154 #define UART5_TWFIFO UART_TWFIFO_REG(UART5)
13155 #define UART5_TCFIFO UART_TCFIFO_REG(UART5)
13156 #define UART5_RWFIFO UART_RWFIFO_REG(UART5)
13157 #define UART5_RCFIFO UART_RCFIFO_REG(UART5)
13158
13159 /*!
13160 * @}
13161 */ /* end of group UART_Register_Accessor_Macros */
13162
13163
13164 /*!
13165 * @}
13166 */ /* end of group UART_Peripheral_Access_Layer */
13167
13168
13169 /* ----------------------------------------------------------------------------
13170 -- USB Peripheral Access Layer
13171 ---------------------------------------------------------------------------- */
13172
13173 /*!
13174 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
13175 * @{
13176 */
13177
13178 /** USB - Register Layout Typedef */
13179 typedef struct {
13180 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
13181 uint8_t RESERVED_0[3];
13182 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
13183 uint8_t RESERVED_1[3];
13184 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
13185 uint8_t RESERVED_2[3];
13186 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
13187 uint8_t RESERVED_3[3];
13188 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
13189 uint8_t RESERVED_4[3];
13190 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
13191 uint8_t RESERVED_5[3];
13192 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
13193 uint8_t RESERVED_6[3];
13194 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
13195 uint8_t RESERVED_7[99];
13196 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
13197 uint8_t RESERVED_8[3];
13198 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
13199 uint8_t RESERVED_9[3];
13200 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
13201 uint8_t RESERVED_10[3];
13202 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
13203 uint8_t RESERVED_11[3];
13204 __I uint8_t STAT; /**< Status register, offset: 0x90 */
13205 uint8_t RESERVED_12[3];
13206 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
13207 uint8_t RESERVED_13[3];
13208 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
13209 uint8_t RESERVED_14[3];
13210 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
13211 uint8_t RESERVED_15[3];
13212 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
13213 uint8_t RESERVED_16[3];
13214 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
13215 uint8_t RESERVED_17[3];
13216 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
13217 uint8_t RESERVED_18[3];
13218 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
13219 uint8_t RESERVED_19[3];
13220 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
13221 uint8_t RESERVED_20[3];
13222 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
13223 uint8_t RESERVED_21[11];
13224 struct { /* offset: 0xC0, array step: 0x4 */
13225 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
13226 uint8_t RESERVED_0[3];
13227 } ENDPOINT[16];
13228 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
13229 uint8_t RESERVED_22[3];
13230 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
13231 uint8_t RESERVED_23[3];
13232 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
13233 uint8_t RESERVED_24[3];
13234 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
13235 uint8_t RESERVED_25[7];
13236 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
13237 uint8_t RESERVED_26[43];
13238 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
13239 uint8_t RESERVED_27[3];
13240 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
13241 uint8_t RESERVED_28[23];
13242 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
13243 } USB_Type, *USB_MemMapPtr;
13244
13245 /* ----------------------------------------------------------------------------
13246 -- USB - Register accessor macros
13247 ---------------------------------------------------------------------------- */
13248
13249 /*!
13250 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
13251 * @{
13252 */
13253
13254
13255 /* USB - Register accessors */
13256 #define USB_PERID_REG(base) ((base)->PERID)
13257 #define USB_IDCOMP_REG(base) ((base)->IDCOMP)
13258 #define USB_REV_REG(base) ((base)->REV)
13259 #define USB_ADDINFO_REG(base) ((base)->ADDINFO)
13260 #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT)
13261 #define USB_OTGICR_REG(base) ((base)->OTGICR)
13262 #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT)
13263 #define USB_OTGCTL_REG(base) ((base)->OTGCTL)
13264 #define USB_ISTAT_REG(base) ((base)->ISTAT)
13265 #define USB_INTEN_REG(base) ((base)->INTEN)
13266 #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT)
13267 #define USB_ERREN_REG(base) ((base)->ERREN)
13268 #define USB_STAT_REG(base) ((base)->STAT)
13269 #define USB_CTL_REG(base) ((base)->CTL)
13270 #define USB_ADDR_REG(base) ((base)->ADDR)
13271 #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1)
13272 #define USB_FRMNUML_REG(base) ((base)->FRMNUML)
13273 #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH)
13274 #define USB_TOKEN_REG(base) ((base)->TOKEN)
13275 #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD)
13276 #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2)
13277 #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3)
13278 #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT)
13279 #define USB_USBCTRL_REG(base) ((base)->USBCTRL)
13280 #define USB_OBSERVE_REG(base) ((base)->OBSERVE)
13281 #define USB_CONTROL_REG(base) ((base)->CONTROL)
13282 #define USB_USBTRC0_REG(base) ((base)->USBTRC0)
13283 #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST)
13284 #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL)
13285 #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN)
13286 #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS)
13287
13288 /*!
13289 * @}
13290 */ /* end of group USB_Register_Accessor_Macros */
13291
13292
13293 /* ----------------------------------------------------------------------------
13294 -- USB Register Masks
13295 ---------------------------------------------------------------------------- */
13296
13297 /*!
13298 * @addtogroup USB_Register_Masks USB Register Masks
13299 * @{
13300 */
13301
13302 /* PERID Bit Fields */
13303 #define USB_PERID_ID_MASK 0x3Fu
13304 #define USB_PERID_ID_SHIFT 0
13305 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
13306 /* IDCOMP Bit Fields */
13307 #define USB_IDCOMP_NID_MASK 0x3Fu
13308 #define USB_IDCOMP_NID_SHIFT 0
13309 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
13310 /* REV Bit Fields */
13311 #define USB_REV_REV_MASK 0xFFu
13312 #define USB_REV_REV_SHIFT 0
13313 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
13314 /* ADDINFO Bit Fields */
13315 #define USB_ADDINFO_IEHOST_MASK 0x1u
13316 #define USB_ADDINFO_IEHOST_SHIFT 0
13317 #define USB_ADDINFO_IRQNUM_MASK 0xF8u
13318 #define USB_ADDINFO_IRQNUM_SHIFT 3
13319 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
13320 /* OTGISTAT Bit Fields */
13321 #define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
13322 #define USB_OTGISTAT_AVBUSCHG_SHIFT 0
13323 #define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
13324 #define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
13325 #define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
13326 #define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
13327 #define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
13328 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
13329 #define USB_OTGISTAT_ONEMSEC_MASK 0x40u
13330 #define USB_OTGISTAT_ONEMSEC_SHIFT 6
13331 #define USB_OTGISTAT_IDCHG_MASK 0x80u
13332 #define USB_OTGISTAT_IDCHG_SHIFT 7
13333 /* OTGICR Bit Fields */
13334 #define USB_OTGICR_AVBUSEN_MASK 0x1u
13335 #define USB_OTGICR_AVBUSEN_SHIFT 0
13336 #define USB_OTGICR_BSESSEN_MASK 0x4u
13337 #define USB_OTGICR_BSESSEN_SHIFT 2
13338 #define USB_OTGICR_SESSVLDEN_MASK 0x8u
13339 #define USB_OTGICR_SESSVLDEN_SHIFT 3
13340 #define USB_OTGICR_LINESTATEEN_MASK 0x20u
13341 #define USB_OTGICR_LINESTATEEN_SHIFT 5
13342 #define USB_OTGICR_ONEMSECEN_MASK 0x40u
13343 #define USB_OTGICR_ONEMSECEN_SHIFT 6
13344 #define USB_OTGICR_IDEN_MASK 0x80u
13345 #define USB_OTGICR_IDEN_SHIFT 7
13346 /* OTGSTAT Bit Fields */
13347 #define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
13348 #define USB_OTGSTAT_AVBUSVLD_SHIFT 0
13349 #define USB_OTGSTAT_BSESSEND_MASK 0x4u
13350 #define USB_OTGSTAT_BSESSEND_SHIFT 2
13351 #define USB_OTGSTAT_SESS_VLD_MASK 0x8u
13352 #define USB_OTGSTAT_SESS_VLD_SHIFT 3
13353 #define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
13354 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
13355 #define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
13356 #define USB_OTGSTAT_ONEMSECEN_SHIFT 6
13357 #define USB_OTGSTAT_ID_MASK 0x80u
13358 #define USB_OTGSTAT_ID_SHIFT 7
13359 /* OTGCTL Bit Fields */
13360 #define USB_OTGCTL_OTGEN_MASK 0x4u
13361 #define USB_OTGCTL_OTGEN_SHIFT 2
13362 #define USB_OTGCTL_DMLOW_MASK 0x10u
13363 #define USB_OTGCTL_DMLOW_SHIFT 4
13364 #define USB_OTGCTL_DPLOW_MASK 0x20u
13365 #define USB_OTGCTL_DPLOW_SHIFT 5
13366 #define USB_OTGCTL_DPHIGH_MASK 0x80u
13367 #define USB_OTGCTL_DPHIGH_SHIFT 7
13368 /* ISTAT Bit Fields */
13369 #define USB_ISTAT_USBRST_MASK 0x1u
13370 #define USB_ISTAT_USBRST_SHIFT 0
13371 #define USB_ISTAT_ERROR_MASK 0x2u
13372 #define USB_ISTAT_ERROR_SHIFT 1
13373 #define USB_ISTAT_SOFTOK_MASK 0x4u
13374 #define USB_ISTAT_SOFTOK_SHIFT 2
13375 #define USB_ISTAT_TOKDNE_MASK 0x8u
13376 #define USB_ISTAT_TOKDNE_SHIFT 3
13377 #define USB_ISTAT_SLEEP_MASK 0x10u
13378 #define USB_ISTAT_SLEEP_SHIFT 4
13379 #define USB_ISTAT_RESUME_MASK 0x20u
13380 #define USB_ISTAT_RESUME_SHIFT 5
13381 #define USB_ISTAT_ATTACH_MASK 0x40u
13382 #define USB_ISTAT_ATTACH_SHIFT 6
13383 #define USB_ISTAT_STALL_MASK 0x80u
13384 #define USB_ISTAT_STALL_SHIFT 7
13385 /* INTEN Bit Fields */
13386 #define USB_INTEN_USBRSTEN_MASK 0x1u
13387 #define USB_INTEN_USBRSTEN_SHIFT 0
13388 #define USB_INTEN_ERROREN_MASK 0x2u
13389 #define USB_INTEN_ERROREN_SHIFT 1
13390 #define USB_INTEN_SOFTOKEN_MASK 0x4u
13391 #define USB_INTEN_SOFTOKEN_SHIFT 2
13392 #define USB_INTEN_TOKDNEEN_MASK 0x8u
13393 #define USB_INTEN_TOKDNEEN_SHIFT 3
13394 #define USB_INTEN_SLEEPEN_MASK 0x10u
13395 #define USB_INTEN_SLEEPEN_SHIFT 4
13396 #define USB_INTEN_RESUMEEN_MASK 0x20u
13397 #define USB_INTEN_RESUMEEN_SHIFT 5
13398 #define USB_INTEN_ATTACHEN_MASK 0x40u
13399 #define USB_INTEN_ATTACHEN_SHIFT 6
13400 #define USB_INTEN_STALLEN_MASK 0x80u
13401 #define USB_INTEN_STALLEN_SHIFT 7
13402 /* ERRSTAT Bit Fields */
13403 #define USB_ERRSTAT_PIDERR_MASK 0x1u
13404 #define USB_ERRSTAT_PIDERR_SHIFT 0
13405 #define USB_ERRSTAT_CRC5EOF_MASK 0x2u
13406 #define USB_ERRSTAT_CRC5EOF_SHIFT 1
13407 #define USB_ERRSTAT_CRC16_MASK 0x4u
13408 #define USB_ERRSTAT_CRC16_SHIFT 2
13409 #define USB_ERRSTAT_DFN8_MASK 0x8u
13410 #define USB_ERRSTAT_DFN8_SHIFT 3
13411 #define USB_ERRSTAT_BTOERR_MASK 0x10u
13412 #define USB_ERRSTAT_BTOERR_SHIFT 4
13413 #define USB_ERRSTAT_DMAERR_MASK 0x20u
13414 #define USB_ERRSTAT_DMAERR_SHIFT 5
13415 #define USB_ERRSTAT_BTSERR_MASK 0x80u
13416 #define USB_ERRSTAT_BTSERR_SHIFT 7
13417 /* ERREN Bit Fields */
13418 #define USB_ERREN_PIDERREN_MASK 0x1u
13419 #define USB_ERREN_PIDERREN_SHIFT 0
13420 #define USB_ERREN_CRC5EOFEN_MASK 0x2u
13421 #define USB_ERREN_CRC5EOFEN_SHIFT 1
13422 #define USB_ERREN_CRC16EN_MASK 0x4u
13423 #define USB_ERREN_CRC16EN_SHIFT 2
13424 #define USB_ERREN_DFN8EN_MASK 0x8u
13425 #define USB_ERREN_DFN8EN_SHIFT 3
13426 #define USB_ERREN_BTOERREN_MASK 0x10u
13427 #define USB_ERREN_BTOERREN_SHIFT 4
13428 #define USB_ERREN_DMAERREN_MASK 0x20u
13429 #define USB_ERREN_DMAERREN_SHIFT 5
13430 #define USB_ERREN_BTSERREN_MASK 0x80u
13431 #define USB_ERREN_BTSERREN_SHIFT 7
13432 /* STAT Bit Fields */
13433 #define USB_STAT_ODD_MASK 0x4u
13434 #define USB_STAT_ODD_SHIFT 2
13435 #define USB_STAT_TX_MASK 0x8u
13436 #define USB_STAT_TX_SHIFT 3
13437 #define USB_STAT_ENDP_MASK 0xF0u
13438 #define USB_STAT_ENDP_SHIFT 4
13439 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
13440 /* CTL Bit Fields */
13441 #define USB_CTL_USBENSOFEN_MASK 0x1u
13442 #define USB_CTL_USBENSOFEN_SHIFT 0
13443 #define USB_CTL_ODDRST_MASK 0x2u
13444 #define USB_CTL_ODDRST_SHIFT 1
13445 #define USB_CTL_RESUME_MASK 0x4u
13446 #define USB_CTL_RESUME_SHIFT 2
13447 #define USB_CTL_HOSTMODEEN_MASK 0x8u
13448 #define USB_CTL_HOSTMODEEN_SHIFT 3
13449 #define USB_CTL_RESET_MASK 0x10u
13450 #define USB_CTL_RESET_SHIFT 4
13451 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
13452 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
13453 #define USB_CTL_SE0_MASK 0x40u
13454 #define USB_CTL_SE0_SHIFT 6
13455 #define USB_CTL_JSTATE_MASK 0x80u
13456 #define USB_CTL_JSTATE_SHIFT 7
13457 /* ADDR Bit Fields */
13458 #define USB_ADDR_ADDR_MASK 0x7Fu
13459 #define USB_ADDR_ADDR_SHIFT 0
13460 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
13461 #define USB_ADDR_LSEN_MASK 0x80u
13462 #define USB_ADDR_LSEN_SHIFT 7
13463 /* BDTPAGE1 Bit Fields */
13464 #define USB_BDTPAGE1_BDTBA_MASK 0xFEu
13465 #define USB_BDTPAGE1_BDTBA_SHIFT 1
13466 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
13467 /* FRMNUML Bit Fields */
13468 #define USB_FRMNUML_FRM_MASK 0xFFu
13469 #define USB_FRMNUML_FRM_SHIFT 0
13470 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
13471 /* FRMNUMH Bit Fields */
13472 #define USB_FRMNUMH_FRM_MASK 0x7u
13473 #define USB_FRMNUMH_FRM_SHIFT 0
13474 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
13475 /* TOKEN Bit Fields */
13476 #define USB_TOKEN_TOKENENDPT_MASK 0xFu
13477 #define USB_TOKEN_TOKENENDPT_SHIFT 0
13478 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
13479 #define USB_TOKEN_TOKENPID_MASK 0xF0u
13480 #define USB_TOKEN_TOKENPID_SHIFT 4
13481 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
13482 /* SOFTHLD Bit Fields */
13483 #define USB_SOFTHLD_CNT_MASK 0xFFu
13484 #define USB_SOFTHLD_CNT_SHIFT 0
13485 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
13486 /* BDTPAGE2 Bit Fields */
13487 #define USB_BDTPAGE2_BDTBA_MASK 0xFFu
13488 #define USB_BDTPAGE2_BDTBA_SHIFT 0
13489 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
13490 /* BDTPAGE3 Bit Fields */
13491 #define USB_BDTPAGE3_BDTBA_MASK 0xFFu
13492 #define USB_BDTPAGE3_BDTBA_SHIFT 0
13493 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
13494 /* ENDPT Bit Fields */
13495 #define USB_ENDPT_EPHSHK_MASK 0x1u
13496 #define USB_ENDPT_EPHSHK_SHIFT 0
13497 #define USB_ENDPT_EPSTALL_MASK 0x2u
13498 #define USB_ENDPT_EPSTALL_SHIFT 1
13499 #define USB_ENDPT_EPTXEN_MASK 0x4u
13500 #define USB_ENDPT_EPTXEN_SHIFT 2
13501 #define USB_ENDPT_EPRXEN_MASK 0x8u
13502 #define USB_ENDPT_EPRXEN_SHIFT 3
13503 #define USB_ENDPT_EPCTLDIS_MASK 0x10u
13504 #define USB_ENDPT_EPCTLDIS_SHIFT 4
13505 #define USB_ENDPT_RETRYDIS_MASK 0x40u
13506 #define USB_ENDPT_RETRYDIS_SHIFT 6
13507 #define USB_ENDPT_HOSTWOHUB_MASK 0x80u
13508 #define USB_ENDPT_HOSTWOHUB_SHIFT 7
13509 /* USBCTRL Bit Fields */
13510 #define USB_USBCTRL_PDE_MASK 0x40u
13511 #define USB_USBCTRL_PDE_SHIFT 6
13512 #define USB_USBCTRL_SUSP_MASK 0x80u
13513 #define USB_USBCTRL_SUSP_SHIFT 7
13514 /* OBSERVE Bit Fields */
13515 #define USB_OBSERVE_DMPD_MASK 0x10u
13516 #define USB_OBSERVE_DMPD_SHIFT 4
13517 #define USB_OBSERVE_DPPD_MASK 0x40u
13518 #define USB_OBSERVE_DPPD_SHIFT 6
13519 #define USB_OBSERVE_DPPU_MASK 0x80u
13520 #define USB_OBSERVE_DPPU_SHIFT 7
13521 /* CONTROL Bit Fields */
13522 #define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
13523 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
13524 /* USBTRC0 Bit Fields */
13525 #define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
13526 #define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
13527 #define USB_USBTRC0_SYNC_DET_MASK 0x2u
13528 #define USB_USBTRC0_SYNC_DET_SHIFT 1
13529 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK 0x4u
13530 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT 2
13531 #define USB_USBTRC0_USBRESMEN_MASK 0x20u
13532 #define USB_USBTRC0_USBRESMEN_SHIFT 5
13533 #define USB_USBTRC0_USBRESET_MASK 0x80u
13534 #define USB_USBTRC0_USBRESET_SHIFT 7
13535 /* USBFRMADJUST Bit Fields */
13536 #define USB_USBFRMADJUST_ADJ_MASK 0xFFu
13537 #define USB_USBFRMADJUST_ADJ_SHIFT 0
13538 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x))<<USB_USBFRMADJUST_ADJ_SHIFT))&USB_USBFRMADJUST_ADJ_MASK)
13539 /* CLK_RECOVER_CTRL Bit Fields */
13540 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK 0x20u
13541 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT 5
13542 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK 0x40u
13543 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT 6
13544 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK 0x80u
13545 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT 7
13546 /* CLK_RECOVER_IRC_EN Bit Fields */
13547 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK 0x1u
13548 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT 0
13549 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK 0x2u
13550 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT 1
13551 /* CLK_RECOVER_INT_STATUS Bit Fields */
13552 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK 0x10u
13553 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT 4
13554
13555 /*!
13556 * @}
13557 */ /* end of group USB_Register_Masks */
13558
13559
13560 /* USB - Peripheral instance base addresses */
13561 /** Peripheral USB0 base address */
13562 #define USB0_BASE (0x40072000u)
13563 /** Peripheral USB0 base pointer */
13564 #define USB0 ((USB_Type *)USB0_BASE)
13565 #define USB0_BASE_PTR (USB0)
13566 /** Array initializer of USB peripheral base addresses */
13567 #define USB_BASE_ADDRS { USB0_BASE }
13568 /** Array initializer of USB peripheral base pointers */
13569 #define USB_BASE_PTRS { USB0 }
13570 /** Interrupt vectors for the USB peripheral type */
13571 #define USB_IRQS { USB0_IRQn }
13572
13573 /* ----------------------------------------------------------------------------
13574 -- USB - Register accessor macros
13575 ---------------------------------------------------------------------------- */
13576
13577 /*!
13578 * @addtogroup USB_Register_Accessor_Macros USB - Register accessor macros
13579 * @{
13580 */
13581
13582
13583 /* USB - Register instance definitions */
13584 /* USB0 */
13585 #define USB0_PERID USB_PERID_REG(USB0)
13586 #define USB0_IDCOMP USB_IDCOMP_REG(USB0)
13587 #define USB0_REV USB_REV_REG(USB0)
13588 #define USB0_ADDINFO USB_ADDINFO_REG(USB0)
13589 #define USB0_OTGISTAT USB_OTGISTAT_REG(USB0)
13590 #define USB0_OTGICR USB_OTGICR_REG(USB0)
13591 #define USB0_OTGSTAT USB_OTGSTAT_REG(USB0)
13592 #define USB0_OTGCTL USB_OTGCTL_REG(USB0)
13593 #define USB0_ISTAT USB_ISTAT_REG(USB0)
13594 #define USB0_INTEN USB_INTEN_REG(USB0)
13595 #define USB0_ERRSTAT USB_ERRSTAT_REG(USB0)
13596 #define USB0_ERREN USB_ERREN_REG(USB0)
13597 #define USB0_STAT USB_STAT_REG(USB0)
13598 #define USB0_CTL USB_CTL_REG(USB0)
13599 #define USB0_ADDR USB_ADDR_REG(USB0)
13600 #define USB0_BDTPAGE1 USB_BDTPAGE1_REG(USB0)
13601 #define USB0_FRMNUML USB_FRMNUML_REG(USB0)
13602 #define USB0_FRMNUMH USB_FRMNUMH_REG(USB0)
13603 #define USB0_TOKEN USB_TOKEN_REG(USB0)
13604 #define USB0_SOFTHLD USB_SOFTHLD_REG(USB0)
13605 #define USB0_BDTPAGE2 USB_BDTPAGE2_REG(USB0)
13606 #define USB0_BDTPAGE3 USB_BDTPAGE3_REG(USB0)
13607 #define USB0_ENDPT0 USB_ENDPT_REG(USB0,0)
13608 #define USB0_ENDPT1 USB_ENDPT_REG(USB0,1)
13609 #define USB0_ENDPT2 USB_ENDPT_REG(USB0,2)
13610 #define USB0_ENDPT3 USB_ENDPT_REG(USB0,3)
13611 #define USB0_ENDPT4 USB_ENDPT_REG(USB0,4)
13612 #define USB0_ENDPT5 USB_ENDPT_REG(USB0,5)
13613 #define USB0_ENDPT6 USB_ENDPT_REG(USB0,6)
13614 #define USB0_ENDPT7 USB_ENDPT_REG(USB0,7)
13615 #define USB0_ENDPT8 USB_ENDPT_REG(USB0,8)
13616 #define USB0_ENDPT9 USB_ENDPT_REG(USB0,9)
13617 #define USB0_ENDPT10 USB_ENDPT_REG(USB0,10)
13618 #define USB0_ENDPT11 USB_ENDPT_REG(USB0,11)
13619 #define USB0_ENDPT12 USB_ENDPT_REG(USB0,12)
13620 #define USB0_ENDPT13 USB_ENDPT_REG(USB0,13)
13621 #define USB0_ENDPT14 USB_ENDPT_REG(USB0,14)
13622 #define USB0_ENDPT15 USB_ENDPT_REG(USB0,15)
13623 #define USB0_USBCTRL USB_USBCTRL_REG(USB0)
13624 #define USB0_OBSERVE USB_OBSERVE_REG(USB0)
13625 #define USB0_CONTROL USB_CONTROL_REG(USB0)
13626 #define USB0_USBTRC0 USB_USBTRC0_REG(USB0)
13627 #define USB0_USBFRMADJUST USB_USBFRMADJUST_REG(USB0)
13628 #define USB0_CLK_RECOVER_CTRL USB_CLK_RECOVER_CTRL_REG(USB0)
13629 #define USB0_CLK_RECOVER_IRC_EN USB_CLK_RECOVER_IRC_EN_REG(USB0)
13630 #define USB0_CLK_RECOVER_INT_STATUS USB_CLK_RECOVER_INT_STATUS_REG(USB0)
13631
13632 /* USB - Register array accessors */
13633 #define USB0_ENDPT(index) USB_ENDPT_REG(USB0,index)
13634
13635 /*!
13636 * @}
13637 */ /* end of group USB_Register_Accessor_Macros */
13638
13639
13640 /*!
13641 * @}
13642 */ /* end of group USB_Peripheral_Access_Layer */
13643
13644
13645 /* ----------------------------------------------------------------------------
13646 -- USBDCD Peripheral Access Layer
13647 ---------------------------------------------------------------------------- */
13648
13649 /*!
13650 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
13651 * @{
13652 */
13653
13654 /** USBDCD - Register Layout Typedef */
13655 typedef struct {
13656 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
13657 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
13658 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
13659 uint8_t RESERVED_0[4];
13660 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
13661 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
13662 union { /* offset: 0x18 */
13663 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
13664 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
13665 };
13666 } USBDCD_Type, *USBDCD_MemMapPtr;
13667
13668 /* ----------------------------------------------------------------------------
13669 -- USBDCD - Register accessor macros
13670 ---------------------------------------------------------------------------- */
13671
13672 /*!
13673 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
13674 * @{
13675 */
13676
13677
13678 /* USBDCD - Register accessors */
13679 #define USBDCD_CONTROL_REG(base) ((base)->CONTROL)
13680 #define USBDCD_CLOCK_REG(base) ((base)->CLOCK)
13681 #define USBDCD_STATUS_REG(base) ((base)->STATUS)
13682 #define USBDCD_TIMER0_REG(base) ((base)->TIMER0)
13683 #define USBDCD_TIMER1_REG(base) ((base)->TIMER1)
13684 #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11)
13685 #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12)
13686
13687 /*!
13688 * @}
13689 */ /* end of group USBDCD_Register_Accessor_Macros */
13690
13691
13692 /* ----------------------------------------------------------------------------
13693 -- USBDCD Register Masks
13694 ---------------------------------------------------------------------------- */
13695
13696 /*!
13697 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
13698 * @{
13699 */
13700
13701 /* CONTROL Bit Fields */
13702 #define USBDCD_CONTROL_IACK_MASK 0x1u
13703 #define USBDCD_CONTROL_IACK_SHIFT 0
13704 #define USBDCD_CONTROL_IF_MASK 0x100u
13705 #define USBDCD_CONTROL_IF_SHIFT 8
13706 #define USBDCD_CONTROL_IE_MASK 0x10000u
13707 #define USBDCD_CONTROL_IE_SHIFT 16
13708 #define USBDCD_CONTROL_BC12_MASK 0x20000u
13709 #define USBDCD_CONTROL_BC12_SHIFT 17
13710 #define USBDCD_CONTROL_START_MASK 0x1000000u
13711 #define USBDCD_CONTROL_START_SHIFT 24
13712 #define USBDCD_CONTROL_SR_MASK 0x2000000u
13713 #define USBDCD_CONTROL_SR_SHIFT 25
13714 /* CLOCK Bit Fields */
13715 #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u
13716 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0
13717 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu
13718 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2
13719 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_CLOCK_CLOCK_SPEED_SHIFT))&USBDCD_CLOCK_CLOCK_SPEED_MASK)
13720 /* STATUS Bit Fields */
13721 #define USBDCD_STATUS_SEQ_RES_MASK 0x30000u
13722 #define USBDCD_STATUS_SEQ_RES_SHIFT 16
13723 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_RES_SHIFT))&USBDCD_STATUS_SEQ_RES_MASK)
13724 #define USBDCD_STATUS_SEQ_STAT_MASK 0xC0000u
13725 #define USBDCD_STATUS_SEQ_STAT_SHIFT 18
13726 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_STATUS_SEQ_STAT_SHIFT))&USBDCD_STATUS_SEQ_STAT_MASK)
13727 #define USBDCD_STATUS_ERR_MASK 0x100000u
13728 #define USBDCD_STATUS_ERR_SHIFT 20
13729 #define USBDCD_STATUS_TO_MASK 0x200000u
13730 #define USBDCD_STATUS_TO_SHIFT 21
13731 #define USBDCD_STATUS_ACTIVE_MASK 0x400000u
13732 #define USBDCD_STATUS_ACTIVE_SHIFT 22
13733 /* TIMER0 Bit Fields */
13734 #define USBDCD_TIMER0_TUNITCON_MASK 0xFFFu
13735 #define USBDCD_TIMER0_TUNITCON_SHIFT 0
13736 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TUNITCON_SHIFT))&USBDCD_TIMER0_TUNITCON_MASK)
13737 #define USBDCD_TIMER0_TSEQ_INIT_MASK 0x3FF0000u
13738 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT 16
13739 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER0_TSEQ_INIT_SHIFT))&USBDCD_TIMER0_TSEQ_INIT_MASK)
13740 /* TIMER1 Bit Fields */
13741 #define USBDCD_TIMER1_TVDPSRC_ON_MASK 0x3FFu
13742 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT 0
13743 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TVDPSRC_ON_SHIFT))&USBDCD_TIMER1_TVDPSRC_ON_MASK)
13744 #define USBDCD_TIMER1_TDCD_DBNC_MASK 0x3FF0000u
13745 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT 16
13746 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER1_TDCD_DBNC_SHIFT))&USBDCD_TIMER1_TDCD_DBNC_MASK)
13747 /* TIMER2_BC11 Bit Fields */
13748 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK 0xFu
13749 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT 0
13750 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_CHECK_DM_SHIFT))&USBDCD_TIMER2_BC11_CHECK_DM_MASK)
13751 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK 0x3FF0000u
13752 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT 16
13753 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT))&USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
13754 /* TIMER2_BC12 Bit Fields */
13755 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK 0x3FFu
13756 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT 0
13757 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT))&USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
13758 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK 0x3FF0000u
13759 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT 16
13760 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x))<<USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT))&USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
13761
13762 /*!
13763 * @}
13764 */ /* end of group USBDCD_Register_Masks */
13765
13766
13767 /* USBDCD - Peripheral instance base addresses */
13768 /** Peripheral USBDCD base address */
13769 #define USBDCD_BASE (0x40035000u)
13770 /** Peripheral USBDCD base pointer */
13771 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
13772 #define USBDCD_BASE_PTR (USBDCD)
13773 /** Array initializer of USBDCD peripheral base addresses */
13774 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
13775 /** Array initializer of USBDCD peripheral base pointers */
13776 #define USBDCD_BASE_PTRS { USBDCD }
13777 /** Interrupt vectors for the USBDCD peripheral type */
13778 #define USBDCD_IRQS { USBDCD_IRQn }
13779
13780 /* ----------------------------------------------------------------------------
13781 -- USBDCD - Register accessor macros
13782 ---------------------------------------------------------------------------- */
13783
13784 /*!
13785 * @addtogroup USBDCD_Register_Accessor_Macros USBDCD - Register accessor macros
13786 * @{
13787 */
13788
13789
13790 /* USBDCD - Register instance definitions */
13791 /* USBDCD */
13792 #define USBDCD_CONTROL USBDCD_CONTROL_REG(USBDCD)
13793 #define USBDCD_CLOCK USBDCD_CLOCK_REG(USBDCD)
13794 #define USBDCD_STATUS USBDCD_STATUS_REG(USBDCD)
13795 #define USBDCD_TIMER0 USBDCD_TIMER0_REG(USBDCD)
13796 #define USBDCD_TIMER1 USBDCD_TIMER1_REG(USBDCD)
13797 #define USBDCD_TIMER2_BC11 USBDCD_TIMER2_BC11_REG(USBDCD)
13798 #define USBDCD_TIMER2_BC12 USBDCD_TIMER2_BC12_REG(USBDCD)
13799
13800 /*!
13801 * @}
13802 */ /* end of group USBDCD_Register_Accessor_Macros */
13803
13804
13805 /*!
13806 * @}
13807 */ /* end of group USBDCD_Peripheral_Access_Layer */
13808
13809
13810 /* ----------------------------------------------------------------------------
13811 -- VREF Peripheral Access Layer
13812 ---------------------------------------------------------------------------- */
13813
13814 /*!
13815 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
13816 * @{
13817 */
13818
13819 /** VREF - Register Layout Typedef */
13820 typedef struct {
13821 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
13822 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
13823 } VREF_Type, *VREF_MemMapPtr;
13824
13825 /* ----------------------------------------------------------------------------
13826 -- VREF - Register accessor macros
13827 ---------------------------------------------------------------------------- */
13828
13829 /*!
13830 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
13831 * @{
13832 */
13833
13834
13835 /* VREF - Register accessors */
13836 #define VREF_TRM_REG(base) ((base)->TRM)
13837 #define VREF_SC_REG(base) ((base)->SC)
13838
13839 /*!
13840 * @}
13841 */ /* end of group VREF_Register_Accessor_Macros */
13842
13843
13844 /* ----------------------------------------------------------------------------
13845 -- VREF Register Masks
13846 ---------------------------------------------------------------------------- */
13847
13848 /*!
13849 * @addtogroup VREF_Register_Masks VREF Register Masks
13850 * @{
13851 */
13852
13853 /* TRM Bit Fields */
13854 #define VREF_TRM_TRIM_MASK 0x3Fu
13855 #define VREF_TRM_TRIM_SHIFT 0
13856 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<<VREF_TRM_TRIM_SHIFT))&VREF_TRM_TRIM_MASK)
13857 #define VREF_TRM_CHOPEN_MASK 0x40u
13858 #define VREF_TRM_CHOPEN_SHIFT 6
13859 /* SC Bit Fields */
13860 #define VREF_SC_MODE_LV_MASK 0x3u
13861 #define VREF_SC_MODE_LV_SHIFT 0
13862 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x))<<VREF_SC_MODE_LV_SHIFT))&VREF_SC_MODE_LV_MASK)
13863 #define VREF_SC_VREFST_MASK 0x4u
13864 #define VREF_SC_VREFST_SHIFT 2
13865 #define VREF_SC_ICOMPEN_MASK 0x20u
13866 #define VREF_SC_ICOMPEN_SHIFT 5
13867 #define VREF_SC_REGEN_MASK 0x40u
13868 #define VREF_SC_REGEN_SHIFT 6
13869 #define VREF_SC_VREFEN_MASK 0x80u
13870 #define VREF_SC_VREFEN_SHIFT 7
13871
13872 /*!
13873 * @}
13874 */ /* end of group VREF_Register_Masks */
13875
13876
13877 /* VREF - Peripheral instance base addresses */
13878 /** Peripheral VREF base address */
13879 #define VREF_BASE (0x40074000u)
13880 /** Peripheral VREF base pointer */
13881 #define VREF ((VREF_Type *)VREF_BASE)
13882 #define VREF_BASE_PTR (VREF)
13883 /** Array initializer of VREF peripheral base addresses */
13884 #define VREF_BASE_ADDRS { VREF_BASE }
13885 /** Array initializer of VREF peripheral base pointers */
13886 #define VREF_BASE_PTRS { VREF }
13887
13888 /* ----------------------------------------------------------------------------
13889 -- VREF - Register accessor macros
13890 ---------------------------------------------------------------------------- */
13891
13892 /*!
13893 * @addtogroup VREF_Register_Accessor_Macros VREF - Register accessor macros
13894 * @{
13895 */
13896
13897
13898 /* VREF - Register instance definitions */
13899 /* VREF */
13900 #define VREF_TRM VREF_TRM_REG(VREF)
13901 #define VREF_SC VREF_SC_REG(VREF)
13902
13903 /*!
13904 * @}
13905 */ /* end of group VREF_Register_Accessor_Macros */
13906
13907
13908 /*!
13909 * @}
13910 */ /* end of group VREF_Peripheral_Access_Layer */
13911
13912
13913 /* ----------------------------------------------------------------------------
13914 -- WDOG Peripheral Access Layer
13915 ---------------------------------------------------------------------------- */
13916
13917 /*!
13918 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
13919 * @{
13920 */
13921
13922 /** WDOG - Register Layout Typedef */
13923 typedef struct {
13924 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
13925 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
13926 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
13927 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
13928 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
13929 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
13930 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
13931 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
13932 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
13933 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
13934 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
13935 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
13936 } WDOG_Type, *WDOG_MemMapPtr;
13937
13938 /* ----------------------------------------------------------------------------
13939 -- WDOG - Register accessor macros
13940 ---------------------------------------------------------------------------- */
13941
13942 /*!
13943 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
13944 * @{
13945 */
13946
13947
13948 /* WDOG - Register accessors */
13949 #define WDOG_STCTRLH_REG(base) ((base)->STCTRLH)
13950 #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL)
13951 #define WDOG_TOVALH_REG(base) ((base)->TOVALH)
13952 #define WDOG_TOVALL_REG(base) ((base)->TOVALL)
13953 #define WDOG_WINH_REG(base) ((base)->WINH)
13954 #define WDOG_WINL_REG(base) ((base)->WINL)
13955 #define WDOG_REFRESH_REG(base) ((base)->REFRESH)
13956 #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK)
13957 #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH)
13958 #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL)
13959 #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT)
13960 #define WDOG_PRESC_REG(base) ((base)->PRESC)
13961
13962 /*!
13963 * @}
13964 */ /* end of group WDOG_Register_Accessor_Macros */
13965
13966
13967 /* ----------------------------------------------------------------------------
13968 -- WDOG Register Masks
13969 ---------------------------------------------------------------------------- */
13970
13971 /*!
13972 * @addtogroup WDOG_Register_Masks WDOG Register Masks
13973 * @{
13974 */
13975
13976 /* STCTRLH Bit Fields */
13977 #define WDOG_STCTRLH_WDOGEN_MASK 0x1u
13978 #define WDOG_STCTRLH_WDOGEN_SHIFT 0
13979 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u
13980 #define WDOG_STCTRLH_CLKSRC_SHIFT 1
13981 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u
13982 #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2
13983 #define WDOG_STCTRLH_WINEN_MASK 0x8u
13984 #define WDOG_STCTRLH_WINEN_SHIFT 3
13985 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u
13986 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4
13987 #define WDOG_STCTRLH_DBGEN_MASK 0x20u
13988 #define WDOG_STCTRLH_DBGEN_SHIFT 5
13989 #define WDOG_STCTRLH_STOPEN_MASK 0x40u
13990 #define WDOG_STCTRLH_STOPEN_SHIFT 6
13991 #define WDOG_STCTRLH_WAITEN_MASK 0x80u
13992 #define WDOG_STCTRLH_WAITEN_SHIFT 7
13993 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u
13994 #define WDOG_STCTRLH_TESTWDOG_SHIFT 10
13995 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u
13996 #define WDOG_STCTRLH_TESTSEL_SHIFT 11
13997 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u
13998 #define WDOG_STCTRLH_BYTESEL_SHIFT 12
13999 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_STCTRLH_BYTESEL_SHIFT))&WDOG_STCTRLH_BYTESEL_MASK)
14000 #define WDOG_STCTRLH_DISTESTWDOG_MASK 0x4000u
14001 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT 14
14002 /* STCTRLL Bit Fields */
14003 #define WDOG_STCTRLL_INTFLG_MASK 0x8000u
14004 #define WDOG_STCTRLL_INTFLG_SHIFT 15
14005 /* TOVALH Bit Fields */
14006 #define WDOG_TOVALH_TOVALHIGH_MASK 0xFFFFu
14007 #define WDOG_TOVALH_TOVALHIGH_SHIFT 0
14008 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALH_TOVALHIGH_SHIFT))&WDOG_TOVALH_TOVALHIGH_MASK)
14009 /* TOVALL Bit Fields */
14010 #define WDOG_TOVALL_TOVALLOW_MASK 0xFFFFu
14011 #define WDOG_TOVALL_TOVALLOW_SHIFT 0
14012 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TOVALL_TOVALLOW_SHIFT))&WDOG_TOVALL_TOVALLOW_MASK)
14013 /* WINH Bit Fields */
14014 #define WDOG_WINH_WINHIGH_MASK 0xFFFFu
14015 #define WDOG_WINH_WINHIGH_SHIFT 0
14016 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINH_WINHIGH_SHIFT))&WDOG_WINH_WINHIGH_MASK)
14017 /* WINL Bit Fields */
14018 #define WDOG_WINL_WINLOW_MASK 0xFFFFu
14019 #define WDOG_WINL_WINLOW_SHIFT 0
14020 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_WINL_WINLOW_SHIFT))&WDOG_WINL_WINLOW_MASK)
14021 /* REFRESH Bit Fields */
14022 #define WDOG_REFRESH_WDOGREFRESH_MASK 0xFFFFu
14023 #define WDOG_REFRESH_WDOGREFRESH_SHIFT 0
14024 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_REFRESH_WDOGREFRESH_SHIFT))&WDOG_REFRESH_WDOGREFRESH_MASK)
14025 /* UNLOCK Bit Fields */
14026 #define WDOG_UNLOCK_WDOGUNLOCK_MASK 0xFFFFu
14027 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT 0
14028 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x))<<WDOG_UNLOCK_WDOGUNLOCK_SHIFT))&WDOG_UNLOCK_WDOGUNLOCK_MASK)
14029 /* TMROUTH Bit Fields */
14030 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK 0xFFFFu
14031 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT 0
14032 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTH_TIMEROUTHIGH_SHIFT))&WDOG_TMROUTH_TIMEROUTHIGH_MASK)
14033 /* TMROUTL Bit Fields */
14034 #define WDOG_TMROUTL_TIMEROUTLOW_MASK 0xFFFFu
14035 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT 0
14036 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x))<<WDOG_TMROUTL_TIMEROUTLOW_SHIFT))&WDOG_TMROUTL_TIMEROUTLOW_MASK)
14037 /* RSTCNT Bit Fields */
14038 #define WDOG_RSTCNT_RSTCNT_MASK 0xFFFFu
14039 #define WDOG_RSTCNT_RSTCNT_SHIFT 0
14040 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x))<<WDOG_RSTCNT_RSTCNT_SHIFT))&WDOG_RSTCNT_RSTCNT_MASK)
14041 /* PRESC Bit Fields */
14042 #define WDOG_PRESC_PRESCVAL_MASK 0x700u
14043 #define WDOG_PRESC_PRESCVAL_SHIFT 8
14044 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x))<<WDOG_PRESC_PRESCVAL_SHIFT))&WDOG_PRESC_PRESCVAL_MASK)
14045
14046 /*!
14047 * @}
14048 */ /* end of group WDOG_Register_Masks */
14049
14050
14051 /* WDOG - Peripheral instance base addresses */
14052 /** Peripheral WDOG base address */
14053 #define WDOG_BASE (0x40052000u)
14054 /** Peripheral WDOG base pointer */
14055 #define WDOG ((WDOG_Type *)WDOG_BASE)
14056 #define WDOG_BASE_PTR (WDOG)
14057 /** Array initializer of WDOG peripheral base addresses */
14058 #define WDOG_BASE_ADDRS { WDOG_BASE }
14059 /** Array initializer of WDOG peripheral base pointers */
14060 #define WDOG_BASE_PTRS { WDOG }
14061 /** Interrupt vectors for the WDOG peripheral type */
14062 #define WDOG_IRQS { Watchdog_IRQn }
14063
14064 /* ----------------------------------------------------------------------------
14065 -- WDOG - Register accessor macros
14066 ---------------------------------------------------------------------------- */
14067
14068 /*!
14069 * @addtogroup WDOG_Register_Accessor_Macros WDOG - Register accessor macros
14070 * @{
14071 */
14072
14073
14074 /* WDOG - Register instance definitions */
14075 /* WDOG */
14076 #define WDOG_STCTRLH WDOG_STCTRLH_REG(WDOG)
14077 #define WDOG_STCTRLL WDOG_STCTRLL_REG(WDOG)
14078 #define WDOG_TOVALH WDOG_TOVALH_REG(WDOG)
14079 #define WDOG_TOVALL WDOG_TOVALL_REG(WDOG)
14080 #define WDOG_WINH WDOG_WINH_REG(WDOG)
14081 #define WDOG_WINL WDOG_WINL_REG(WDOG)
14082 #define WDOG_REFRESH WDOG_REFRESH_REG(WDOG)
14083 #define WDOG_UNLOCK WDOG_UNLOCK_REG(WDOG)
14084 #define WDOG_TMROUTH WDOG_TMROUTH_REG(WDOG)
14085 #define WDOG_TMROUTL WDOG_TMROUTL_REG(WDOG)
14086 #define WDOG_RSTCNT WDOG_RSTCNT_REG(WDOG)
14087 #define WDOG_PRESC WDOG_PRESC_REG(WDOG)
14088
14089 /*!
14090 * @}
14091 */ /* end of group WDOG_Register_Accessor_Macros */
14092
14093
14094 /*!
14095 * @}
14096 */ /* end of group WDOG_Peripheral_Access_Layer */
14097
14098
14099 /*
14100 ** End of section using anonymous unions
14101 */
14102
14103 #if defined(__ARMCC_VERSION)
14104 #pragma pop
14105 #elif defined(__CWCC__)
14106 #pragma pop
14107 #elif defined(__GNUC__)
14108 /* leave anonymous unions enabled */
14109 #elif defined(__IAR_SYSTEMS_ICC__)
14110 #pragma language=default
14111 #else
14112 #error Not supported compiler type
14113 #endif
14114
14115 /*!
14116 * @}
14117 */ /* end of group Peripheral_access_layer */
14118
14119
14120 /* ----------------------------------------------------------------------------
14121 -- Backward Compatibility
14122 ---------------------------------------------------------------------------- */
14123
14124 /*!
14125 * @addtogroup Backward_Compatibility_Symbols Backward Compatibility
14126 * @{
14127 */
14128
14129 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
14130 #define DMA_EARS This_symbol_has_been_deprecated
14131 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
14132 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
14133 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
14134 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
14135 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
14136 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
14137 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
14138 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
14139 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
14140 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
14141 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
14142 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
14143 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
14144 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
14145 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
14146 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
14147 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
14148 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
14149 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
14150 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
14151 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
14152 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
14153 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
14154 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
14155 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
14156 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
14157 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
14158 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
14159 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
14160 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
14161 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
14162 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
14163 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
14164 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
14165 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
14166 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
14167 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
14168 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
14169 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
14170 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
14171 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
14172 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
14173 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
14174 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
14175 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
14176 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
14177 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
14178 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
14179 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
14180 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
14181 #define MCG_C9 This_symbol_has_been_deprecated
14182 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
14183 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
14184 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
14185 #define MCM_PLACR This_symbol_has_been_deprecated
14186 #define ADC_BASES ADC_BASE_PTRS
14187 #define AIPS_BASES AIPS_BASE_PTRS
14188 #define AXBS_BASES AXBS_BASE_PTRS
14189 #define CAN_BASES CAN_BASE_PTRS
14190 #define CAU_BASES CAU_BASE_PTRS
14191 #define CMP_BASES CMP_BASE_PTRS
14192 #define CMT_BASES CMT_BASE_PTRS
14193 #define CRC_BASES CRC_BASE_PTRS
14194 #define DAC_BASES DAC_BASE_PTRS
14195 #define DMA_BASES DMA_BASE_PTRS
14196 #define DMAMUX_BASES DMAMUX_BASE_PTRS
14197 #define ENET_BASES ENET_BASE_PTRS
14198 #define EWM_BASES EWM_BASE_PTRS
14199 #define FB_BASES FB_BASE_PTRS
14200 #define FMC_BASES FMC_BASE_PTRS
14201 #define FTFE_BASES FTFE_BASE_PTRS
14202 #define FTM_BASES FTM_BASE_PTRS
14203 #define GPIO_BASES GPIO_BASE_PTRS
14204 #define I2C_BASES I2C_BASE_PTRS
14205 #define I2S_BASES I2S_BASE_PTRS
14206 #define LLWU_BASES LLWU_BASE_PTRS
14207 #define LPTMR_BASES LPTMR_BASE_PTRS
14208 #define MCG_BASES MCG_BASE_PTRS
14209 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
14210 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
14211 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
14212 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
14213 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
14214 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
14215 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
14216 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
14217 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
14218 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
14219 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
14220 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
14221 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
14222 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
14223 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
14224 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
14225 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
14226 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
14227 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
14228 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
14229 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
14230 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
14231 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
14232 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
14233 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
14234 #define MCM_BASES MCM_BASE_PTRS
14235 #define MPU_BASES MPU_BASE_PTRS
14236 #define NV_BASES NV_BASE_PTRS
14237 #define OSC_BASES OSC_BASE_PTRS
14238 #define PDB_BASES PDB_BASE_PTRS
14239 #define PIT_BASES PIT_BASE_PTRS
14240 #define PMC_BASES PMC_BASE_PTRS
14241 #define PORT_BASES PORT_BASE_PTRS
14242 #define RCM_BASES RCM_BASE_PTRS
14243 #define RFSYS_BASES RFSYS_BASE_PTRS
14244 #define RFVBAT_BASES RFVBAT_BASE_PTRS
14245 #define RNG_BASES RNG_BASE_PTRS
14246 #define RTC_BASES RTC_BASE_PTRS
14247 #define SDHC_BASES SDHC_BASE_PTRS
14248 #define SIM_BASES SIM_BASE_PTRS
14249 #define SMC_BASES SMC_BASE_PTRS
14250 #define SPI_BASES SPI_BASE_PTRS
14251 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
14252 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
14253 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
14254 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
14255 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
14256 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
14257 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
14258 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
14259 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
14260 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
14261 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
14262 #define UART_BASES UART_BASE_PTRS
14263 #define USB_BASES USB_BASE_PTRS
14264 #define USBDCD_BASES USBDCD_BASE_PTRS
14265 #define VREF_BASES VREF_BASE_PTRS
14266 #define WDOG_BASES WDOG_BASE_PTRS
14267 #define DMA_EARS_REG(base) This_symbol_has_been_deprecated
14268 #define DMA_EARS This_symbol_has_been_deprecated
14269 #define DMA_EARS_EDREQ_0_MASK This_symbol_has_been_deprecated
14270 #define DMA_EARS_EDREQ_0_SHIFT This_symbol_has_been_deprecated
14271 #define DMA_EARS_EDREQ_1_MASK This_symbol_has_been_deprecated
14272 #define DMA_EARS_EDREQ_1_SHIFT This_symbol_has_been_deprecated
14273 #define DMA_EARS_EDREQ_2_MASK This_symbol_has_been_deprecated
14274 #define DMA_EARS_EDREQ_2_SHIFT This_symbol_has_been_deprecated
14275 #define DMA_EARS_EDREQ_3_MASK This_symbol_has_been_deprecated
14276 #define DMA_EARS_EDREQ_3_SHIFT This_symbol_has_been_deprecated
14277 #define DMA_EARS_EDREQ_4_MASK This_symbol_has_been_deprecated
14278 #define DMA_EARS_EDREQ_4_SHIFT This_symbol_has_been_deprecated
14279 #define DMA_EARS_EDREQ_5_MASK This_symbol_has_been_deprecated
14280 #define DMA_EARS_EDREQ_5_SHIFT This_symbol_has_been_deprecated
14281 #define DMA_EARS_EDREQ_6_MASK This_symbol_has_been_deprecated
14282 #define DMA_EARS_EDREQ_6_SHIFT This_symbol_has_been_deprecated
14283 #define DMA_EARS_EDREQ_7_MASK This_symbol_has_been_deprecated
14284 #define DMA_EARS_EDREQ_7_SHIFT This_symbol_has_been_deprecated
14285 #define DMA_EARS_EDREQ_8_MASK This_symbol_has_been_deprecated
14286 #define DMA_EARS_EDREQ_8_SHIFT This_symbol_has_been_deprecated
14287 #define DMA_EARS_EDREQ_9_MASK This_symbol_has_been_deprecated
14288 #define DMA_EARS_EDREQ_9_SHIFT This_symbol_has_been_deprecated
14289 #define DMA_EARS_EDREQ_10_MASK This_symbol_has_been_deprecated
14290 #define DMA_EARS_EDREQ_10_SHIFT This_symbol_has_been_deprecated
14291 #define DMA_EARS_EDREQ_11_MASK This_symbol_has_been_deprecated
14292 #define DMA_EARS_EDREQ_11_SHIFT This_symbol_has_been_deprecated
14293 #define DMA_EARS_EDREQ_12_MASK This_symbol_has_been_deprecated
14294 #define DMA_EARS_EDREQ_12_SHIFT This_symbol_has_been_deprecated
14295 #define DMA_EARS_EDREQ_13_MASK This_symbol_has_been_deprecated
14296 #define DMA_EARS_EDREQ_13_SHIFT This_symbol_has_been_deprecated
14297 #define DMA_EARS_EDREQ_14_MASK This_symbol_has_been_deprecated
14298 #define DMA_EARS_EDREQ_14_SHIFT This_symbol_has_been_deprecated
14299 #define DMA_EARS_EDREQ_15_MASK This_symbol_has_been_deprecated
14300 #define DMA_EARS_EDREQ_15_SHIFT This_symbol_has_been_deprecated
14301 #define ENET_RMON_T_DROP_REG(base) This_symbol_has_been_deprecated
14302 #define ENET_IEEE_T_DROP_REG(base) This_symbol_has_been_deprecated
14303 #define ENET_IEEE_T_SQE_REG(base) This_symbol_has_been_deprecated
14304 #define ENET_RMON_R_RESVD_0_REG(base) This_symbol_has_been_deprecated
14305 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
14306 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
14307 #define ENET_RMON_T_DROP This_symbol_has_been_deprecated
14308 #define ENET_IEEE_T_DROP This_symbol_has_been_deprecated
14309 #define ENET_IEEE_T_SQE This_symbol_has_been_deprecated
14310 #define ENET_RMON_R_RESVD_0 This_symbol_has_been_deprecated
14311 #define MCG_C9_REG(base) This_symbol_has_been_deprecated
14312 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
14313 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
14314 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
14315 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
14316 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
14317 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
14318 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
14319 #define MCG_C9 This_symbol_has_been_deprecated
14320 #define MCM_PLACR_REG(base) This_symbol_has_been_deprecated
14321 #define MCM_PLACR_ARB_MASK This_symbol_has_been_deprecated
14322 #define MCM_PLACR_ARB_SHIFT This_symbol_has_been_deprecated
14323 #define MCM_PLACR This_symbol_has_been_deprecated
14324 #define ADC_BASES ADC_BASE_PTRS
14325 #define AIPS_BASES AIPS_BASE_PTRS
14326 #define AXBS_BASES AXBS_BASE_PTRS
14327 #define CAN_BASES CAN_BASE_PTRS
14328 #define CAU_BASES CAU_BASE_PTRS
14329 #define CMP_BASES CMP_BASE_PTRS
14330 #define CMT_BASES CMT_BASE_PTRS
14331 #define CRC_BASES CRC_BASE_PTRS
14332 #define DAC_BASES DAC_BASE_PTRS
14333 #define DMA_BASES DMA_BASE_PTRS
14334 #define DMAMUX_BASES DMAMUX_BASE_PTRS
14335 #define ENET_BASES ENET_BASE_PTRS
14336 #define EWM_BASES EWM_BASE_PTRS
14337 #define FB_BASES FB_BASE_PTRS
14338 #define FMC_BASES FMC_BASE_PTRS
14339 #define FTFE_BASES FTFE_BASE_PTRS
14340 #define FTM_BASES FTM_BASE_PTRS
14341 #define GPIO_BASES GPIO_BASE_PTRS
14342 #define I2C_BASES I2C_BASE_PTRS
14343 #define I2S_BASES I2S_BASE_PTRS
14344 #define LLWU_BASES LLWU_BASE_PTRS
14345 #define LPTMR_BASES LPTMR_BASE_PTRS
14346 #define MCG_BASES MCG_BASE_PTRS
14347 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
14348 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
14349 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
14350 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
14351 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
14352 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
14353 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
14354 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
14355 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
14356 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
14357 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
14358 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
14359 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
14360 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
14361 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
14362 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
14363 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
14364 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
14365 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
14366 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
14367 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
14368 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
14369 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
14370 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
14371 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
14372 #define MCM_BASES MCM_BASE_PTRS
14373 #define MPU_BASES MPU_BASE_PTRS
14374 #define NV_BASES NV_BASE_PTRS
14375 #define OSC_BASES OSC_BASE_PTRS
14376 #define PDB_BASES PDB_BASE_PTRS
14377 #define PIT_BASES PIT_BASE_PTRS
14378 #define PMC_BASES PMC_BASE_PTRS
14379 #define PORT_BASES PORT_BASE_PTRS
14380 #define RCM_BASES RCM_BASE_PTRS
14381 #define RFSYS_BASES RFSYS_BASE_PTRS
14382 #define RFVBAT_BASES RFVBAT_BASE_PTRS
14383 #define RNG_BASES RNG_BASE_PTRS
14384 #define RTC_BASES RTC_BASE_PTRS
14385 #define SDHC_BASES SDHC_BASE_PTRS
14386 #define SIM_BASES SIM_BASE_PTRS
14387 #define SMC_BASES SMC_BASE_PTRS
14388 #define SPI_BASES SPI_BASE_PTRS
14389 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
14390 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
14391 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
14392 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
14393 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
14394 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
14395 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
14396 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
14397 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
14398 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
14399 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
14400 #define UART_BASES UART_BASE_PTRS
14401 #define USB_BASES USB_BASE_PTRS
14402 #define USBDCD_BASES USBDCD_BASE_PTRS
14403 #define VREF_BASES VREF_BASE_PTRS
14404 #define WDOG_BASES WDOG_BASE_PTRS
14405
14406 /*!
14407 * @}
14408 */ /* end of group Backward_Compatibility_Symbols */
14409
14410
14411 #else /* #if !defined(MK64F12_H_) */
14412 /* There is already included the same memory map. Check if it is compatible (has the same major version) */
14413 #if (MCU_MEM_MAP_VERSION != 0x0200u)
14414 #if (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING))
14415 #warning There are included two not compatible versions of memory maps. Please check possible differences.
14416 #endif /* (!defined(MCU_MEM_MAP_SUPPRESS_VERSION_WARNING)) */
14417 #endif /* (MCU_MEM_MAP_VERSION != 0x0200u) */
14418 #endif /* #if !defined(MK64F12_H_) */
14419
14420 /* MK64F12.h, eof. */
custom keymap for my minivan; forked from http://github.com/evangs/tmk_keyboard
Imprint / Impressum