tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.c

   1 /*
   2 ** ###################################################################
   3 **     Processor:           MK64FN1M0VMD12
   4 **     Compilers:           Keil ARM C/C++ Compiler
   5 **                          Freescale C/C++ for Embedded ARM
   6 **                          GNU C Compiler
   7 **                          GNU C Compiler - CodeSourcery Sourcery G++
   8 **                          IAR ANSI C/C++ Compiler for ARM
   9 **
  10 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
  11 **     Version:             rev. 2.5, 2014-02-10
  12 **     Build:               b140611
  13 **
  14 **     Abstract:
  15 **         Provides a system configuration function and a global variable that
  16 **         contains the system frequency. It configures the device and initializes
  17 **         the oscillator (PLL) that is part of the microcontroller device.
  18 **
  19 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  20 **     All rights reserved.
  21 **
  22 **     Redistribution and use in source and binary forms, with or without modification,
  23 **     are permitted provided that the following conditions are met:
  24 **
  25 **     o Redistributions of source code must retain the above copyright notice, this list
  26 **       of conditions and the following disclaimer.
  27 **
  28 **     o Redistributions in binary form must reproduce the above copyright notice, this
  29 **       list of conditions and the following disclaimer in the documentation and/or
  30 **       other materials provided with the distribution.
  31 **
  32 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  33 **       contributors may be used to endorse or promote products derived from this
  34 **       software without specific prior written permission.
  35 **
  36 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  37 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  38 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  40 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  41 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  42 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  43 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  45 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46 **
  47 **     http:                 www.freescale.com
  48 **     mail:                 support@freescale.com
  49 **
  50 **     Revisions:
  51 **     - rev. 1.0 (2013-08-12)
  52 **         Initial version.
  53 **     - rev. 2.0 (2013-10-29)
  54 **         Register accessor macros added to the memory map.
  55 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  56 **         Startup file for gcc has been updated according to CMSIS 3.2.
  57 **         System initialization updated.
  58 **         MCG - registers updated.
  59 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  60 **     - rev. 2.1 (2013-10-30)
  61 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  62 **     - rev. 2.2 (2013-12-09)
  63 **         DMA - EARS register removed.
  64 **         AIPS0, AIPS1 - MPRA register updated.
  65 **     - rev. 2.3 (2014-01-24)
  66 **         Update according to reference manual rev. 2
  67 **         ENET, MCG, MCM, SIM, USB - registers updated
  68 **     - rev. 2.4 (2014-02-10)
  69 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  70 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  71 **     - rev. 2.5 (2014-02-10)
  72 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  73 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  74 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  75 **
  76 ** ###################################################################
  77 */
  78
  79 /*!
  80  * @file MK64F12
  81  * @version 2.5
  82  * @date 2014-02-10
  83  * @brief Device specific configuration file for MK64F12 (implementation file)
  84  *
  85  * Provides a system configuration function and a global variable that contains
  86  * the system frequency. It configures the device and initializes the oscillator
  87  * (PLL) that is part of the microcontroller device.
  88  */
  89
  90 #include <stdint.h>
  91 #include "cmsis.h"
  92
  93
  94
  95 /* ----------------------------------------------------------------------------
  96    -- Core clock
  97    ---------------------------------------------------------------------------- */
  98
  99 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
 100
 101 /* ----------------------------------------------------------------------------
 102    -- SystemInit()
 103    ---------------------------------------------------------------------------- */
 104
 105 void SystemInit (void) {
 106 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
 107   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
 108 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
 109 #if (DISABLE_WDOG)
 110   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
 111   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
 112   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
 113   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
 114   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
 115   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
 116                  WDOG_STCTRLH_WAITEN_MASK |
 117                  WDOG_STCTRLH_STOPEN_MASK |
 118                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
 119                  WDOG_STCTRLH_CLKSRC_MASK |
 120                  0x0100U;
 121 #endif /* (DISABLE_WDOG) */
 122   if((RCM->SRS0 & RCM_SRS0_WAKEUP_MASK) != 0x00U)
 123   {
 124     if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0x00U)
 125     {
 126        PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* Release hold with ACKISO:  Only has an effect if recovering from VLLSx.*/
 127     }
 128   } else {
 129 #ifdef SYSTEM_RTC_CR_VALUE
 130     SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
 131     if ((RTC_CR & RTC_CR_OSCE_MASK) == 0x00U) { /* Only if the OSCILLATOR is not already enabled */
 132       RTC_CR = (uint32_t)((RTC_CR & (uint32_t)~(uint32_t)(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK)) | (uint32_t)SYSTEM_RTC_CR_VALUE);
 133       RTC_CR |= (uint32_t)RTC_CR_OSCE_MASK;
 134       RTC_CR &= (uint32_t)~(uint32_t)RTC_CR_CLKO_MASK;
 135     }
 136 #endif
 137   }
 138
 139   /* Power mode protection initialization */
 140 #ifdef SYSTEM_SMC_PMPROT_VALUE
 141   SMC->PMPROT = SYSTEM_SMC_PMPROT_VALUE;
 142 #endif
 143
 144   /* System clock initialization */
 145   /* Internal reference clock trim initialization */
 146 #if defined(SLOW_TRIM_ADDRESS)
 147   if ( *((uint8_t*)SLOW_TRIM_ADDRESS) != 0xFFU) {                              /* Skip if non-volatile flash memory is erased */
 148     MCG->C3 = *((uint8_t*)SLOW_TRIM_ADDRESS);
 149   #endif /* defined(SLOW_TRIM_ADDRESS) */
 150   #if defined(SLOW_FINE_TRIM_ADDRESS)
 151     MCG->C4 = (MCG->C4 & ~(MCG_C4_SCFTRIM_MASK)) | ((*((uint8_t*) SLOW_FINE_TRIM_ADDRESS)) & MCG_C4_SCFTRIM_MASK);
 152   #endif
 153   #if defined(FAST_TRIM_ADDRESS)
 154     MCG->C4 = (MCG->C4 & ~(MCG_C4_FCTRIM_MASK)) |((*((uint8_t*) FAST_TRIM_ADDRESS)) & MCG_C4_FCTRIM_MASK);
 155   #endif
 156   #if defined(FAST_FINE_TRIM_ADDRESS)
 157     MCG->C2 = (MCG->C2 & ~(MCG_C2_FCFTRIM_MASK)) | ((*((uint8_t*)FAST_TRIM_ADDRESS)) & MCG_C2_FCFTRIM_MASK);
 158   #endif /* defined(FAST_FINE_TRIM_ADDRESS) */
 159 #if defined(SLOW_TRIM_ADDRESS)
 160   }
 161   #endif /* defined(SLOW_TRIM_ADDRESS) */
 162
 163   /* Set system prescalers and clock sources */
 164   SIM->CLKDIV1 = SYSTEM_SIM_CLKDIV1_VALUE; /* Set system prescalers */
 165   SIM->SOPT1 = ((SIM->SOPT1) & (uint32_t)(~(SIM_SOPT1_OSC32KSEL_MASK))) | ((SYSTEM_SIM_SOPT1_VALUE) & (SIM_SOPT1_OSC32KSEL_MASK)); /* Set 32 kHz clock source (ERCLK32K) */
 166   SIM->SOPT2 = ((SIM->SOPT2) & (uint32_t)(~(SIM_SOPT2_PLLFLLSEL_MASK))) | ((SYSTEM_SIM_SOPT2_VALUE) & (SIM_SOPT2_PLLFLLSEL_MASK)); /* Selects the high frequency clock for various peripheral clocking options. */
 167 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 168   /* Set MCG and OSC */
 169 #if  ((((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || ((((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)))
 170   /* SIM_SCGC5: PORTA=1 */
 171   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 172   /* PORTA_PCR18: ISF=0,MUX=0 */
 173   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 174   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
 175   /* PORTA_PCR19: ISF=0,MUX=0 */
 176   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 177   }
 178 #endif
 179   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
 180   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
 181   /* Check that the source of the FLL reference clock is the requested one. */
 182   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 183     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
 184     }
 185   } else {
 186     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 187     }
 188   }
 189   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
 190   MCG->C4 = ((SYSTEM_MCG_C4_VALUE) & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
 191   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
 192   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
 193   #if (MCG_MODE == MCG_MODE_BLPI)
 194   /* BLPI specific */
 195   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 196   #endif
 197
 198 #else /* MCG_MODE */
 199   /* Set MCG and OSC */
 200 #if  (((SYSTEM_OSC_CR_VALUE) & OSC_CR_ERCLKEN_MASK) != 0x00U) || (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)
 201   /* SIM_SCGC5: PORTA=1 */
 202   SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
 203   /* PORTA_PCR18: ISF=0,MUX=0 */
 204   PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 205   if (((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) {
 206   /* PORTA_PCR19: ISF=0,MUX=0 */
 207   PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
 208   }
 209 #endif
 210   MCG->SC = SYSTEM_MCG_SC_VALUE;       /* Set SC (fast clock internal reference divider) */
 211   MCG->C2 = (MCG->C2 & (uint8_t)(~(MCG_C2_FCFTRIM_MASK))) | (SYSTEM_MCG_C2_VALUE & (uint8_t)(~(MCG_C2_LP_MASK))); /* Set C2 (freq. range, ext. and int. reference selection etc. excluding trim bits; low power bit is set later) */
 212   OSC->CR = SYSTEM_OSC_CR_VALUE;       /* Set OSC_CR (OSCERCLK enable, oscillator capacitor load) */
 213   MCG->C7 = SYSTEM_MCG_C7_VALUE;       /* Set C7 (OSC Clock Select) */
 214   #if (MCG_MODE == MCG_MODE_PEE)
 215   MCG->C1 = (SYSTEM_MCG_C1_VALUE) | MCG_C1_CLKS(0x02); /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) - PBE mode*/
 216   #else
 217   MCG->C1 = SYSTEM_MCG_C1_VALUE;       /* Set C1 (clock source selection, FLL ext. reference divider, int. reference enable etc.) */
 218   #endif
 219   if ((((SYSTEM_MCG_C2_VALUE) & MCG_C2_EREFS_MASK) != 0x00U) && (((SYSTEM_MCG_C7_VALUE) & MCG_C7_OSCSEL_MASK) == 0x00U)) {
 220     while((MCG->S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
 221     }
 222   }
 223   /* Check that the source of the FLL reference clock is the requested one. */
 224   if (((SYSTEM_MCG_C1_VALUE) & MCG_C1_IREFS_MASK) != 0x00U) {
 225     while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) {
 226     }
 227   } else {
 228     while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) {
 229     }
 230   }
 231   MCG->C4 = ((SYSTEM_MCG_C4_VALUE)  & (uint8_t)(~(MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK))) | (MCG->C4 & (MCG_C4_FCTRIM_MASK | MCG_C4_SCFTRIM_MASK)); /* Set C4 (FLL output; trim values not changed) */
 232 #endif /* MCG_MODE */
 233
 234   /* Common for all MCG modes */
 235
 236   /* PLL clock can be used to generate clock for some devices regardless of clock generator (MCGOUTCLK) mode. */
 237   MCG->C5 = (SYSTEM_MCG_C5_VALUE) & (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK)); /* Set C5 (PLL settings, PLL reference divider etc.) */
 238   MCG->C6 = (SYSTEM_MCG_C6_VALUE) & (uint8_t)~(MCG_C6_PLLS_MASK); /* Set C6 (PLL select, VCO divider etc.) */
 239   if ((SYSTEM_MCG_C5_VALUE) & MCG_C5_PLLCLKEN0_MASK) {
 240     MCG->C5 |= MCG_C5_PLLCLKEN0_MASK;  /* PLL clock enable in mode other than PEE or PBE */
 241   }
 242   /* BLPE, PEE and PBE MCG mode specific */
 243
 244 #if (MCG_MODE == MCG_MODE_BLPE)
 245   MCG->C2 |= (MCG_C2_LP_MASK);         /* Disable FLL and PLL in bypass mode */
 246 #elif ((MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_PEE))
 247   MCG->C6 |= (MCG_C6_PLLS_MASK);       /* Set C6 (PLL select, VCO divider etc.) */
 248   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL is locked*/
 249   }
 250   #if (MCG_MODE == MCG_MODE_PEE)
 251   MCG->C1 &= (uint8_t)~(MCG_C1_CLKS_MASK);
 252   #endif
 253 #endif
 254 #if ((MCG_MODE == MCG_MODE_FEI) || (MCG_MODE == MCG_MODE_FEE))
 255   while((MCG->S & MCG_S_CLKST_MASK) != 0x00U) { /* Wait until output of the FLL is selected */
 256   }
 257 #elif ((MCG_MODE == MCG_MODE_FBI) || (MCG_MODE == MCG_MODE_BLPI))
 258   while((MCG->S & MCG_S_CLKST_MASK) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
 259   }
 260 #elif ((MCG_MODE == MCG_MODE_FBE) || (MCG_MODE == MCG_MODE_PBE) || (MCG_MODE == MCG_MODE_BLPE))
 261   while((MCG->S & MCG_S_CLKST_MASK) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
 262   }
 263 #elif (MCG_MODE == MCG_MODE_PEE)
 264   while((MCG->S & MCG_S_CLKST_MASK) != 0x0CU) { /* Wait until output of the PLL is selected */
 265   }
 266 #endif
 267 #if (((SYSTEM_SMC_PMCTRL_VALUE) & SMC_PMCTRL_RUNM_MASK) == (0x02U << SMC_PMCTRL_RUNM_SHIFT))
 268   SMC->PMCTRL = (uint8_t)((SYSTEM_SMC_PMCTRL_VALUE) & (SMC_PMCTRL_RUNM_MASK)); /* Enable VLPR mode */
 269   while(SMC->PMSTAT != 0x04U) {        /* Wait until the system is in VLPR mode */
 270   }
 271 #endif
 272
 273 #if defined(SYSTEM_SIM_CLKDIV2_VALUE)
 274   SIM->CLKDIV2 = ((SIM->CLKDIV2) & (uint32_t)(~(SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK))) | ((SYSTEM_SIM_CLKDIV2_VALUE) & (SIM_CLKDIV2_USBFRAC_MASK | SIM_CLKDIV2_USBDIV_MASK)); /* Selects the USB clock divider. */
 275 #endif
 276
 277   /* PLL loss of lock interrupt request initialization */
 278   if (((SYSTEM_MCG_C6_VALUE) & MCG_C6_LOLIE0_MASK) != 0U) {
 279     NVIC_EnableIRQ(MCG_IRQn);          /* Enable PLL loss of lock interrupt request */
 280   }
 281 }
 282
 283 /* ----------------------------------------------------------------------------
 284    -- SystemCoreClockUpdate()
 285    ---------------------------------------------------------------------------- */
 286
 287 void SystemCoreClockUpdate (void) {
 288   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
 289   uint16_t Divider;
 290
 291   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
 292     /* Output of FLL or PLL is selected */
 293     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
 294       /* FLL is selected */
 295       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
 296         /* External reference clock is selected */
 297         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
 298         case 0x00U:
 299           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
 300           break;
 301         case 0x01U:
 302           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 303           break;
 304         case 0x02U:
 305         default:
 306           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
 307           break;
 308         }
 309         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
 310           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
 311           case 0x38U:
 312             Divider = 1536U;
 313             break;
 314           case 0x30U:
 315             Divider = 1280U;
 316             break;
 317           default:
 318             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 319             break;
 320           }
 321         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
 322           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
 323         }
 324         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
 325       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 326         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
 327       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
 328       /* Select correct multiplier to calculate the MCG output clock  */
 329       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
 330         case 0x00U:
 331           MCGOUTClock *= 640U;
 332           break;
 333         case 0x20U:
 334           MCGOUTClock *= 1280U;
 335           break;
 336         case 0x40U:
 337           MCGOUTClock *= 1920U;
 338           break;
 339         case 0x60U:
 340           MCGOUTClock *= 2560U;
 341           break;
 342         case 0x80U:
 343           MCGOUTClock *= 732U;
 344           break;
 345         case 0xA0U:
 346           MCGOUTClock *= 1464U;
 347           break;
 348         case 0xC0U:
 349           MCGOUTClock *= 2197U;
 350           break;
 351         case 0xE0U:
 352           MCGOUTClock *= 2929U;
 353           break;
 354         default:
 355           break;
 356       }
 357     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 358       /* PLL is selected */
 359       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
 360       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
 361       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
 362       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
 363     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
 364   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
 365     /* Internal reference clock is selected */
 366     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
 367       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
 368     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 369       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
 370       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
 371     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
 372   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
 373     /* External reference clock is selected */
 374     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
 375     case 0x00U:
 376       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
 377       break;
 378     case 0x01U:
 379       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
 380       break;
 381     case 0x02U:
 382     default:
 383       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
 384       break;
 385     }
 386   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 387     /* Reserved value */
 388     return;
 389   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
 390   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
 391 }