tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_MCU_K64F/system_MK64F12.h

   1 /*
   2 ** ###################################################################
   3 **     Processor:           MK64FN1M0VMD12
   4 **     Compilers:           Keil ARM C/C++ Compiler
   5 **                          Freescale C/C++ for Embedded ARM
   6 **                          GNU C Compiler
   7 **                          GNU C Compiler - CodeSourcery Sourcery G++
   8 **                          IAR ANSI C/C++ Compiler for ARM
   9 **
  10 **     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
  11 **     Version:             rev. 2.5, 2014-02-10
  12 **     Build:               b140611
  13 **
  14 **     Abstract:
  15 **         Provides a system configuration function and a global variable that
  16 **         contains the system frequency. It configures the device and initializes
  17 **         the oscillator (PLL) that is part of the microcontroller device.
  18 **
  19 **     Copyright (c) 2014 Freescale Semiconductor, Inc.
  20 **     All rights reserved.
  21 **
  22 **     Redistribution and use in source and binary forms, with or without modification,
  23 **     are permitted provided that the following conditions are met:
  24 **
  25 **     o Redistributions of source code must retain the above copyright notice, this list
  26 **       of conditions and the following disclaimer.
  27 **
  28 **     o Redistributions in binary form must reproduce the above copyright notice, this
  29 **       list of conditions and the following disclaimer in the documentation and/or
  30 **       other materials provided with the distribution.
  31 **
  32 **     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
  33 **       contributors may be used to endorse or promote products derived from this
  34 **       software without specific prior written permission.
  35 **
  36 **     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  37 **     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  38 **     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  39 **     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
  40 **     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  41 **     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  42 **     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  43 **     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  44 **     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  45 **     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  46 **
  47 **     http:                 www.freescale.com
  48 **     mail:                 support@freescale.com
  49 **
  50 **     Revisions:
  51 **     - rev. 1.0 (2013-08-12)
  52 **         Initial version.
  53 **     - rev. 2.0 (2013-10-29)
  54 **         Register accessor macros added to the memory map.
  55 **         Symbols for Processor Expert memory map compatibility added to the memory map.
  56 **         Startup file for gcc has been updated according to CMSIS 3.2.
  57 **         System initialization updated.
  58 **         MCG - registers updated.
  59 **         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
  60 **     - rev. 2.1 (2013-10-30)
  61 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
  62 **     - rev. 2.2 (2013-12-09)
  63 **         DMA - EARS register removed.
  64 **         AIPS0, AIPS1 - MPRA register updated.
  65 **     - rev. 2.3 (2014-01-24)
  66 **         Update according to reference manual rev. 2
  67 **         ENET, MCG, MCM, SIM, USB - registers updated
  68 **     - rev. 2.4 (2014-02-10)
  69 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  70 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  71 **     - rev. 2.5 (2014-02-10)
  72 **         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
  73 **         Update of SystemInit() and SystemCoreClockUpdate() functions.
  74 **         Module access macro module_BASES replaced by module_BASE_PTRS.
  75 **
  76 ** ###################################################################
  77 */
  78
  79 /*!
  80  * @file MK64F12
  81  * @version 2.5
  82  * @date 2014-02-10
  83  * @brief Device specific configuration file for MK64F12 (header file)
  84  *
  85  * Provides a system configuration function and a global variable that contains
  86  * the system frequency. It configures the device and initializes the oscillator
  87  * (PLL) that is part of the microcontroller device.
  88  */
  89
  90 #ifndef SYSTEM_MK64F12_H_
  91 #define SYSTEM_MK64F12_H_                        /**< Symbol preventing repeated inclusion */
  92
  93 #ifdef __cplusplus
  94 extern "C" {
  95 #endif
  96
  97 #include <stdint.h>
  98
  99
 100 #define DISABLE_WDOG                   1
 101
 102 #ifndef CLOCK_SETUP
 103   #define CLOCK_SETUP                  4
 104 #endif
 105
 106 /* MCG mode constants */
 107
 108 #define MCG_MODE_FEI                   0U
 109 #define MCG_MODE_FBI                   1U
 110 #define MCG_MODE_BLPI                  2U
 111 #define MCG_MODE_FEE                   3U
 112 #define MCG_MODE_FBE                   4U
 113 #define MCG_MODE_BLPE                  5U
 114 #define MCG_MODE_PBE                   6U
 115 #define MCG_MODE_PEE                   7U
 116
 117 /* Predefined clock setups
 118    0 ... Default  part configuration
 119          Multipurpose Clock Generator (MCG) in FEI mode.
 120          Reference clock source for MCG module: Slow internal reference clock
 121          Core clock = 20.97152MHz
 122          Bus clock  = 20.97152MHz
 123    1 ... Maximum achievable clock frequency configuration
 124          Multipurpose Clock Generator (MCG) in PEE mode.
 125          Reference clock source for MCG module: System oscillator 0 reference clock
 126          Core clock = 120MHz
 127          Bus clock  = 60MHz
 128    2 ... Chip internaly clocked, ready for Very Low Power Run mode.
 129          Multipurpose Clock Generator (MCG) in BLPI mode.
 130          Reference clock source for MCG module: Fast internal reference clock
 131          Core clock = 4MHz
 132          Bus clock  = 4MHz
 133    3 ... Chip externally clocked, ready for Very Low Power Run mode.
 134          Multipurpose Clock Generator (MCG) in BLPE mode.
 135          Reference clock source for MCG module: RTC oscillator reference clock
 136          Core clock = 0.032768MHz
 137          Bus clock  = 0.032768MHz
 138    4 ... USB clock setup
 139          Multipurpose Clock Generator (MCG) in PEE mode.
 140          Reference clock source for MCG module: System oscillator 0 reference clock
 141          Core clock = 120MHz
 142          Bus clock  = 60MHz
 143  */
 144
 145 /* Define clock source values */
 146
 147 #define CPU_XTAL_CLK_HZ                50000000u           /* Value of the external crystal or oscillator clock frequency in Hz */
 148 #define CPU_XTAL32k_CLK_HZ             32768u              /* Value of the external 32k crystal or oscillator clock frequency in Hz */
 149 #define CPU_INT_SLOW_CLK_HZ            32768u              /* Value of the slow internal oscillator clock frequency in Hz  */
 150 #define CPU_INT_FAST_CLK_HZ            4000000u            /* Value of the fast internal oscillator clock frequency in Hz  */
 151 #define CPU_INT_IRC_CLK_HZ             48000000u           /* Value of the 48M internal oscillator clock frequency in Hz  */
 152
 153 /* RTC oscillator setting */
 154 /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
 155 #define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
 156
 157 /* Low power mode enable */
 158 /* SMC_PMPROT: AVLP=1,ALLS=1,AVLLS=1 */
 159 #define SYSTEM_SMC_PMPROT_VALUE        0x2AU               /* SMC_PMPROT */
 160
 161 /* Internal reference clock trim */
 162 /* #undef SLOW_TRIM_ADDRESS */                             /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
 163 /* #undef SLOW_FINE_TRIM_ADDRESS */                        /* Slow oscillator not trimmed. Commented out for MISRA compliance. */
 164 /* #undef FAST_TRIM_ADDRESS */                             /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
 165 /* #undef FAST_FINE_TRIM_ADDRESS */                        /* Fast oscillator not trimmed. Commented out for MISRA compliance. */
 166
 167 #if (CLOCK_SETUP == 0)
 168   #define DEFAULT_SYSTEM_CLOCK         20971520u           /* Default System clock value */
 169   #define MCG_MODE                     MCG_MODE_FEI /* Clock generator mode */
 170   /* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 171   #define SYSTEM_MCG_C1_VALUE          0x06U               /* MCG_C1 */
 172   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
 173   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
 174   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 175   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 176   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 177   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 178 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 179   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 180 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 181   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 182 /* MCG_C7: OSCSEL=0 */
 183   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 184 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 185   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
 186 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
 187   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 188 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=1,OUTDIV4=1 */
 189   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00110000U         /* SIM_CLKDIV1 */
 190 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
 191   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 192 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=0,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 193   #define SYSTEM_SIM_SOPT2_VALUE       0x00U               /* SIM_SOPT2 */
 194 #elif (CLOCK_SETUP == 1)
 195   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
 196   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
 197   /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 198   #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
 199   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
 200   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
 201   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 202   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 203   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 204   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 205 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
 206   #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
 207 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
 208   #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
 209 /* MCG_C7: OSCSEL=0 */
 210   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 211 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 212   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 213 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
 214   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 215 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
 216   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
 217 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
 218   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 219 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 220   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 221 #elif (CLOCK_SETUP == 2)
 222   #define DEFAULT_SYSTEM_CLOCK         4000000u            /* Default System clock value */
 223   #define MCG_MODE                     MCG_MODE_BLPI /* Clock generator mode */
 224   /* MCG_C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
 225   #define SYSTEM_MCG_C1_VALUE          0x46U               /* MCG_C1 */
 226   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
 227   #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
 228   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 229   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 230   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 231   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 232 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 233   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 234 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 235   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 236 /* MCG_C7: OSCSEL=0 */
 237   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 238 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 239   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 240 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
 241   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 242 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=4 */
 243   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00040000U         /* SIM_CLKDIV1 */
 244 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
 245   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 246 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 247   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
 248 #elif (CLOCK_SETUP == 3)
 249   #define DEFAULT_SYSTEM_CLOCK         32768u              /* Default System clock value */
 250   #define MCG_MODE                     MCG_MODE_BLPE /* Clock generator mode */
 251   /* MCG_C1: CLKS=2,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 252   #define SYSTEM_MCG_C1_VALUE          0x82U               /* MCG_C1 */
 253   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=1,IRCS=1 */
 254   #define SYSTEM_MCG_C2_VALUE          0x23U               /* MCG_C2 */
 255   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 256   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 257   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=1,LOCS0=0 */
 258   #define SYSTEM_MCG_SC_VALUE          0x02U               /* MCG_SC */
 259 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
 260   #define SYSTEM_MCG_C5_VALUE          0x00U               /* MCG_C5 */
 261 /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
 262   #define SYSTEM_MCG_C6_VALUE          0x00U               /* MCG_C6 */
 263 /* MCG_C7: OSCSEL=1 */
 264   #define SYSTEM_MCG_C7_VALUE          0x01U               /* MCG_C7 */
 265 /* OSC_CR: ERCLKEN=0,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 266   #define SYSTEM_OSC_CR_VALUE          0x00U               /* OSC_CR */
 267 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
 268   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 269 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=0,OUTDIV3=0,OUTDIV4=0 */
 270   #define SYSTEM_SIM_CLKDIV1_VALUE     0x00U               /* SIM_CLKDIV1 */
 271 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
 272   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 273 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=3,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 274   #define SYSTEM_SIM_SOPT2_VALUE       0x00030000U         /* SIM_SOPT2 */
 275 #elif (CLOCK_SETUP == 4)
 276   #define DEFAULT_SYSTEM_CLOCK         120000000u          /* Default System clock value */
 277   #define MCG_MODE                     MCG_MODE_PEE /* Clock generator mode */
 278   /* MCG_C1: CLKS=0,FRDIV=7,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
 279   #define SYSTEM_MCG_C1_VALUE          0x3AU               /* MCG_C1 */
 280   /* MCG_C2: LOCRE0=0,FCFTRIM=0,RANGE=2,HGO=0,EREFS=0,LP=0,IRCS=0 */
 281   #define SYSTEM_MCG_C2_VALUE          0x20U               /* MCG_C2 */
 282   /* MCG_C4: DMX32=0,DRST_DRS=0,FCTRIM=0,SCFTRIM=0 */
 283   #define SYSTEM_MCG_C4_VALUE          0x00U               /* MCG_C4 */
 284   /* MCG_SC: ATME=0,ATMS=0,ATMF=0,FLTPRSRV=0,FCRDIV=0,LOCS0=0 */
 285   #define SYSTEM_MCG_SC_VALUE          0x00U               /* MCG_SC */
 286 /* MCG_C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0x13 */
 287   #define SYSTEM_MCG_C5_VALUE          0x13U               /* MCG_C5 */
 288 /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0x18 */
 289   #define SYSTEM_MCG_C6_VALUE          0x58U               /* MCG_C6 */
 290 /* MCG_C7: OSCSEL=0 */
 291   #define SYSTEM_MCG_C7_VALUE          0x00U               /* MCG_C7 */
 292 /* OSC_CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
 293   #define SYSTEM_OSC_CR_VALUE          0x80U               /* OSC_CR */
 294 /* SMC_PMCTRL: LPWUI=0,RUNM=0,STOPA=0,STOPM=0 */
 295   #define SYSTEM_SMC_PMCTRL_VALUE      0x00U               /* SMC_PMCTRL */
 296 /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=1,OUTDIV4=4 */
 297   #define SYSTEM_SIM_CLKDIV1_VALUE     0x01140000U         /* SIM_CLKDIV1 */
 298 /* SIM_CLKDIV2: USBDIV=4,USBFRAC=1 */
 299   #define SYSTEM_SIM_CLKDIV2_VALUE     0x09U               /* SIM_CLKDIV2 */
 300 /* SIM_SOPT1: USBREGEN=0,USBSSTBY=0,USBVSTBY=0,OSC32KSEL=2,RAMSIZE=0 */
 301   #define SYSTEM_SIM_SOPT1_VALUE       0x00080000U         /* SIM_SOPT1 */
 302 /* SIM_SOPT2: SDHCSRC=0,TIMESRC=0,RMIISRC=0,USBSRC=0,PLLFLLSEL=1,TRACECLKSEL=0,PTD7PAD=0,FBSL=0,CLKOUTSEL=0,RTCCLKOUTSEL=0 */
 303   #define SYSTEM_SIM_SOPT2_VALUE       0x00010000U         /* SIM_SOPT2 */
 304 #endif
 305
 306 /**
 307  * @brief System clock frequency (core clock)
 308  *
 309  * The system clock frequency supplied to the SysTick timer and the processor
 310  * core clock. This variable can be used by the user application to setup the
 311  * SysTick timer or configure other parameters. It may also be used by debugger to
 312  * query the frequency of the debug timer or configure the trace clock speed
 313  * SystemCoreClock is initialized with a correct predefined value.
 314  */
 315 extern uint32_t SystemCoreClock;
 316
 317 /**
 318  * @brief Setup the microcontroller system.
 319  *
 320  * Typically this function configures the oscillator (PLL) that is part of the
 321  * microcontroller device. For systems with variable clock speed it also updates
 322  * the variable SystemCoreClock. SystemInit is called from startup_device file.
 323  */
 324 void SystemInit (void);
 325
 326 /**
 327  * @brief Updates the SystemCoreClock variable.
 328  *
 329  * It must be called whenever the core clock is changed during program
 330  * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
 331  * the current core clock.
 332  */
 333 void SystemCoreClockUpdate (void);
 334
 335 #ifdef __cplusplus
 336 }
 337 #endif
 338
 339 #endif  /* #if !defined(SYSTEM_MK64F12_H_) */