1 /*******************************************************************************
2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Except as contained in this notice, the name of Maxim Integrated
23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
24 * Products, Inc. Branding Policy.
26 * The mere transfer of this software does not imply any licenses
27 * of trade secrets, proprietary technology, copyrights, patents,
28 * trademarks, maskwork rights, or any other form of intellectual
29 * property whatsoever. Maxim Integrated Products, Inc. retains all
31 *******************************************************************************
38 The HEAP starts at the end of the DATA section and grows upward.
40 The STACK starts at the end of the RAM and grows downward.
42 The HEAP and stack STACK are only checked at compile time:
43 (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
45 This is just a check for the bare minimum for the Heap+Stack area before
46 aborting compilation, it is not the run time limit:
47 Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
52 .equ Stack_Size, __STACK_SIZE
54 .equ Stack_Size, 0x00001000
60 .size __StackLimit, . - __StackLimit
62 .size __StackTop, . - __StackTop
67 .equ Heap_Size, __HEAP_SIZE
69 .equ Heap_Size, 0x00000C00
75 .size __HeapBase, . - __HeapBase
77 .size __HeapLimit, . - __HeapLimit
83 .long __StackTop /* Top of Stack */
84 .long Reset_Handler /* Reset Handler */
85 .long NMI_Handler /* NMI Handler */
86 .long HardFault_Handler /* Hard Fault Handler */
87 .long MemManage_Handler /* MPU Fault Handler */
88 .long BusFault_Handler /* Bus Fault Handler */
89 .long UsageFault_Handler /* Usage Fault Handler */
90 .long 0 /* Reserved */
91 .long 0 /* Reserved */
92 .long 0 /* Reserved */
93 .long 0 /* Reserved */
94 .long SVC_Handler /* SVCall Handler */
95 .long DebugMon_Handler /* Debug Monitor Handler */
96 .long 0 /* Reserved */
97 .long PendSV_Handler /* PendSV Handler */
98 .long SysTick_Handler /* SysTick Handler */
100 /* Externals interrupts */
101 .long UART0_IRQHandler /* 16: 1 UART0 */
102 .long UART1_IRQHandler /* 17: 2 UART1 */
103 .long I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
104 .long I2CS_IRQHandler /* 19: 4 I2C Slave */
105 .long USB_IRQHandler /* 20: 5 USB */
106 .long PMU_IRQHandler /* 21: 6 DMA */
107 .long AFE_IRQHandler /* 22: 7 AFE */
108 .long MAA_IRQHandler /* 23: 8 MAA */
109 .long AES_IRQHandler /* 24: 9 AES */
110 .long SPI0_IRQHandler /* 25:10 SPI0 */
111 .long SPI1_IRQHandler /* 26:11 SPI1 */
112 .long SPI2_IRQHandler /* 27:12 SPI2 */
113 .long TMR0_IRQHandler /* 28:13 Timer32-0 */
114 .long TMR1_IRQHandler /* 29:14 Timer32-1 */
115 .long TMR2_IRQHandler /* 30:15 Timer32-1 */
116 .long TMR3_IRQHandler /* 31:16 Timer32-2 */
117 .long RSVD0_IRQHandler /* 32:17 RSVD */
118 .long RSVD1_IRQHandler /* 33:18 RSVD */
119 .long DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
120 .long DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
121 .long DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
122 .long DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
123 .long ADC_IRQHandler /* 38:23 ADC */
124 .long FLC_IRQHandler /* 39:24 Flash Controller */
125 .long PWRMAN_IRQHandler /* 40:25 PWRMAN */
126 .long CLKMAN_IRQHandler /* 41:26 CLKMAN */
127 .long RTC0_IRQHandler /* 42:27 RTC INT0 */
128 .long RTC1_IRQHandler /* 43:28 RTC INT1 */
129 .long RTC2_IRQHandler /* 44:29 RTC INT2 */
130 .long RTC3_IRQHandler /* 45:30 RTC INT3 */
131 .long WDT0_IRQHandler /* 46:31 WATCHDOG0 */
132 .long WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
133 .long WDT1_IRQHandler /* 48:33 WATCHDOG1 */
134 .long WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
135 .long GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
136 .long GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
137 .long GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
138 .long GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
139 .long GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
140 .long GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
141 .long GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
142 .long GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
143 .long TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
144 .long TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
145 .long TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
146 .long TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
147 .long I2CM1_IRQHandler /* 62:47 I2C Master 1 */
155 .type Reset_Handler, %function
157 /* Loop to copy data from read only memory to RAM. The ranges
158 * of copy from/to are specified by following symbols evaluated in
160 * __etext: End of code section, i.e., begin of data sections to copy from.
161 * __data_start__/__data_end__: RAM address range that data should be
162 * copied to. Both must be aligned to 4 bytes boundary. */
165 ldr r2, =__data_start__
166 ldr r3, =__data_end__
173 blt .Lflash_to_ram_loop
175 .Lflash_to_ram_loop_end:
182 .size Reset_Handler, . - Reset_Handler
185 /* Macro to define default handlers. Default handler
186 * will be weak symbol and just dead loops. They can be
187 * overwritten by other handlers */
188 .macro def_default_handler handler_name
192 .type \handler_name, %function
195 .size \handler_name, . - \handler_name
198 def_default_handler NMI_Handler
199 def_default_handler HardFault_Handler
200 def_default_handler MemManage_Handler
201 def_default_handler BusFault_Handler
202 def_default_handler UsageFault_Handler
203 def_default_handler SVC_Handler
204 def_default_handler DebugMon_Handler
205 def_default_handler PendSV_Handler
206 def_default_handler SysTick_Handler
207 def_default_handler Default_Handler
209 .macro def_irq_default_handler handler_name
211 .set \handler_name, Default_Handler
214 def_irq_default_handler UART0_IRQHandler /* 16: 1 UART0 */
215 def_irq_default_handler UART1_IRQHandler /* 17: 2 UART1 */
216 def_irq_default_handler I2CM0_IRQHandler /* 18: 3 I2C Master 0 */
217 def_irq_default_handler I2CS_IRQHandler /* 19: 4 I2C Slave */
218 def_irq_default_handler USB_IRQHandler /* 20: 5 USB */
219 def_irq_default_handler PMU_IRQHandler /* 21: 6 DMA */
220 def_irq_default_handler AFE_IRQHandler /* 22: 7 AFE */
221 def_irq_default_handler MAA_IRQHandler /* 23: 8 MAA */
222 def_irq_default_handler AES_IRQHandler /* 24: 9 AES */
223 def_irq_default_handler SPI0_IRQHandler /* 25:10 SPI0 */
224 def_irq_default_handler SPI1_IRQHandler /* 26:11 SPI1 */
225 def_irq_default_handler SPI2_IRQHandler /* 27:12 SPI2 */
226 def_irq_default_handler TMR0_IRQHandler /* 28:13 Timer32-0 */
227 def_irq_default_handler TMR1_IRQHandler /* 29:14 Timer32-1 */
228 def_irq_default_handler TMR2_IRQHandler /* 30:15 Timer32-1 */
229 def_irq_default_handler TMR3_IRQHandler /* 31:16 Timer32-2 */
230 def_irq_default_handler RSVD0_IRQHandler /* 32:17 RSVD */
231 def_irq_default_handler RSVD1_IRQHandler /* 33:18 RSVD */
232 def_irq_default_handler DAC0_IRQHandler /* 34:19 DAC0 (12-bit DAC) */
233 def_irq_default_handler DAC1_IRQHandler /* 35:20 DAC1 (12-bit DAC) */
234 def_irq_default_handler DAC2_IRQHandler /* 36:21 DAC2 (8-bit DAC) */
235 def_irq_default_handler DAC3_IRQHandler /* 37:22 DAC3 (8-bit DAC) */
236 def_irq_default_handler ADC_IRQHandler /* 38:23 ADC */
237 def_irq_default_handler FLC_IRQHandler /* 39:24 Flash Controller */
238 def_irq_default_handler PWRMAN_IRQHandler /* 40:25 PWRMAN */
239 def_irq_default_handler CLKMAN_IRQHandler /* 41:26 CLKMAN */
240 def_irq_default_handler RTC0_IRQHandler /* 42:27 RTC INT0 */
241 def_irq_default_handler RTC1_IRQHandler /* 43:28 RTC INT1 */
242 def_irq_default_handler RTC2_IRQHandler /* 44:29 RTC INT2 */
243 def_irq_default_handler RTC3_IRQHandler /* 45:30 RTC INT3 */
244 def_irq_default_handler WDT0_IRQHandler /* 46:31 WATCHDOG0 */
245 def_irq_default_handler WDT0_P_IRQHandler /* 47:32 WATCHDOG0 PRE-WINDOW */
246 def_irq_default_handler WDT1_IRQHandler /* 48:33 WATCHDOG1 */
247 def_irq_default_handler WDT1_P_IRQHandler /* 49:34 WATCHDOG1 PRE-WINDOW */
248 def_irq_default_handler GPIO_P0_IRQHandler /* 50:35 GPIO Port 0 */
249 def_irq_default_handler GPIO_P1_IRQHandler /* 51:36 GPIO Port 1 */
250 def_irq_default_handler GPIO_P2_IRQHandler /* 52:37 GPIO Port 2 */
251 def_irq_default_handler GPIO_P3_IRQHandler /* 53:38 GPIO Port 3 */
252 def_irq_default_handler GPIO_P4_IRQHandler /* 54:39 GPIO Port 4 */
253 def_irq_default_handler GPIO_P5_IRQHandler /* 55:40 GPIO Port 5 */
254 def_irq_default_handler GPIO_P6_IRQHandler /* 56:41 GPIO Port 6 */
255 def_irq_default_handler GPIO_P7_IRQHandler /* 57:42 GPIO Port 7 */
256 def_irq_default_handler TMR16_0_IRQHandler /* 58:43 Timer16-s0 */
257 def_irq_default_handler TMR16_1_IRQHandler /* 59:44 Timer16-s1 */
258 def_irq_default_handler TMR16_2_IRQHandler /* 60:45 Timer16-s2 */
259 def_irq_default_handler TMR16_3_IRQHandler /* 61:46 Timer16-s3 */
260 def_irq_default_handler I2CM1_IRQHandler /* 62:47 I2C Master 1 */