tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/flc_regs.h

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
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   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  17  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
  18  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
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  22  * Except as contained in this notice, the name of Maxim Integrated
  23  * Products, Inc. shall not be used except as stated in the Maxim Integrated
  24  * Products, Inc. Branding Policy.
  25  *
  26  * The mere transfer of this software does not imply any licenses
  27  * of trade secrets, proprietary technology, copyrights, patents,
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  29  * property whatsoever. Maxim Integrated Products, Inc. retains all
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  32  */
  33
  34 #ifndef _MXC_FLC_REGS_H
  35 #define _MXC_FLC_REGS_H
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  flc_regs.h
  45  * @addtogroup flc FLC
  46  * @{
  47  */
  48 /*                                          Offset   Register Description
  49                                             ======   ======================================================= */
  50 typedef struct {
  51     __IO uint32_t faddr;                /*  0x0000   Flash Operation Address                                 */
  52     __IO uint32_t fckdiv;               /*  0x0004   Flash Clock Rate Divisor                                */
  53     __IO uint32_t ctrl;                 /*  0x0008   Flash Control Register                                  */
  54     __I uint32_t rsv000C[6];            /*  0x000C                                                           */
  55     __IO uint32_t intr;                 /*  0x0024   Flash Controller Interrupt Flags and Enable/Disable 0   */
  56     __I uint32_t rsv0028[2];            /*  0x0028                                                           */
  57     __IO uint32_t fdata;                /*  0x0030   Flash Operation Data Register                           */
  58     __I uint32_t rsv0034[7];            /*  0x0034                                                           */
  59     __IO uint32_t perform;              /*  0x0050   Flash Performance Settings                              */
  60     __I uint32_t rsv0054[11];           /*  0x0054                                                           */
  61     __IO uint32_t status;               /*  0x0080   Security Status Flags                                   */
  62     __I uint32_t rsv0084;               /*  0x0084                                                           */
  63     __IO uint32_t security;             /*  0x0088   Flash Controller Security Settings                      */
  64     __I uint32_t rsv008C[4];            /*  0x008C                                                           */
  65     __IO uint32_t bypass;               /*  0x009C   Status Flags for DSB Operations                         */
  66     __IO uint32_t user_option;          /*  0x0100   Used to set DSB Access code and Auto-Lock in info block */
  67     __I uint32_t rsv0104[15];           /*  0x0104                                                           */
  68     __IO uint32_t ctrl2;                /*  0x0140   Flash Control Register 2                                */
  69     __IO uint32_t intfl1;               /*  0x0144   Interrupt Flags Register 1                              */
  70     __IO uint32_t inten1;               /*  0x0148   Interrupt Enable/Disable Register 1                     */
  71     __I uint32_t rsv014C;               /*  0x014C                                                           */
  72     __IO uint32_t disable_xr0;          /*  0x0150   Disable Flash Page Exec/Read Register 0                 */
  73     __IO uint32_t disable_xr1;          /*  0x0154   Disable Flash Page Exec/Read Register 1                 */
  74     __IO uint32_t disable_xr2;          /*  0x0158   Disable Flash Page Exec/Read Register 2                 */
  75     __IO uint32_t disable_xr3;          /*  0x015C   Disable Flash Page Exec/Read Register 3                 */
  76     __IO uint32_t disable_we0;          /*  0x0160   Disable Flash Page Write/Erase Register 0               */
  77     __IO uint32_t disable_we1;          /*  0x0164   Disable Flash Page Write/Erase Register 1               */
  78     __IO uint32_t disable_we2;          /*  0x0168   Disable Flash Page Write/Erase Register 2               */
  79     __IO uint32_t disable_we3;          /*  0x016C   Disable Flash Page Write/Erase Register 3               */
  80 } mxc_flc_regs_t;
  81
  82 /*
  83    Register offsets for module FLC.
  84 */
  85 #define MXC_R_FLC_OFFS_FADDR                          ((uint32_t)0x00000000UL)
  86 #define MXC_R_FLC_OFFS_FCKDIV                         ((uint32_t)0x00000004UL)
  87 #define MXC_R_FLC_OFFS_CTRL                           ((uint32_t)0x00000008UL)
  88 #define MXC_R_FLC_OFFS_INTR                           ((uint32_t)0x00000024UL)
  89 #define MXC_R_FLC_OFFS_FDATA                          ((uint32_t)0x00000030UL)
  90 #define MXC_R_FLC_OFFS_PERFORM                        ((uint32_t)0x00000050UL)
  91 #define MXC_R_FLC_OFFS_STATUS                         ((uint32_t)0x00000080UL)
  92 #define MXC_R_FLC_OFFS_SECURITY                       ((uint32_t)0x00000088UL)
  93 #define MXC_R_FLC_OFFS_BYPASS                         ((uint32_t)0x0000009CUL)
  94 #define MXC_R_FLC_OFFS_USER_OPTION                    ((uint32_t)0x00000100UL)
  95 #define MXC_R_FLC_OFFS_CTRL2                          ((uint32_t)0x00000140UL)
  96 #define MXC_R_FLC_OFFS_INTFL1                         ((uint32_t)0x00000144UL)
  97 #define MXC_R_FLC_OFFS_INTEN1                         ((uint32_t)0x00000148UL)
  98 #define MXC_R_FLC_OFFS_DISABLE_XR0                    ((uint32_t)0x00000150UL)
  99 #define MXC_R_FLC_OFFS_DISABLE_XR1                    ((uint32_t)0x00000154UL)
 100 #define MXC_R_FLC_OFFS_DISABLE_XR2                    ((uint32_t)0x00000158UL)
 101 #define MXC_R_FLC_OFFS_DISABLE_XR3                    ((uint32_t)0x0000015CUL)
 102 #define MXC_R_FLC_OFFS_DISABLE_WE0                    ((uint32_t)0x00000160UL)
 103 #define MXC_R_FLC_OFFS_DISABLE_WE1                    ((uint32_t)0x00000164UL)
 104 #define MXC_R_FLC_OFFS_DISABLE_WE2                    ((uint32_t)0x00000168UL)
 105 #define MXC_R_FLC_OFFS_DISABLE_WE3                    ((uint32_t)0x0000016CUL)
 106
 107 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE               ((uint8_t)0x55)
 108 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE               ((uint8_t)0xAA)
 109
 110 #define MXC_V_FLC_FLSH_UNLOCK_KEY                     ((uint8_t)0x2)
 111
 112 /*
 113    Field positions and masks for module FLC.
 114 */
 115 #define MXC_F_FLC_FADDR_FADDR_POS                     0
 116 #define MXC_F_FLC_FADDR_FADDR                         ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
 117
 118 #define MXC_F_FLC_FCKDIV_FCKDIV_POS                   0
 119 #define MXC_F_FLC_FCKDIV_FCKDIV                       ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
 120
 121 #define MXC_F_FLC_CTRL_WRITE_POS                      0
 122 #define MXC_F_FLC_CTRL_WRITE                          ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
 123 #define MXC_F_FLC_CTRL_MASS_ERASE_POS                 1
 124 #define MXC_F_FLC_CTRL_MASS_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
 125 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS                 2
 126 #define MXC_F_FLC_CTRL_PAGE_ERASE                     ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
 127 #define MXC_F_FLC_CTRL_ERASE_CODE_POS                 8
 128 #define MXC_F_FLC_CTRL_ERASE_CODE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
 129 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS          16
 130 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
 131 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS               17
 132 #define MXC_F_FLC_CTRL_WRITE_ENABLE                   ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
 133 #define MXC_F_FLC_CTRL_PENDING_POS                    24
 134 #define MXC_F_FLC_CTRL_PENDING                        ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
 135 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS           25
 136 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID               ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
 137 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS            27
 138 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE                ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
 139 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS                28
 140 #define MXC_F_FLC_CTRL_FLSH_UNLOCK                    ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
 141
 142 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS           0
 143 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
 144 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS         1
 145 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
 146 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS           9
 147 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE               ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
 148 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS         10
 149 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
 150
 151 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS       8
 152 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN           ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
 153 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS             0
 154 #define MXC_F_FLC_PERFORM_DELAY_SE_EN                 ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
 155
 156 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS        0
 157 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
 158 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS        1
 159 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC            ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
 160 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS                3
 161 #define MXC_F_FLC_STATUS_AUTO_LOCK                    ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
 162
 163 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS          0
 164 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE              ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
 165 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS        8
 166 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK            ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
 167 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS          31
 168 #define MXC_F_FLC_SECURITY_SECURITY_LOCK              ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
 169
 170 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS    0
 171 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE        ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
 172 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS          1
 173 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE              ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
 174 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
 175 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE     ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
 176 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS       3
 177 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE           ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
 178
 179 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS                 0
 180 #define MXC_F_FLC_CTRL2_FLASH_LVE                     ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
 181 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS           8
 182 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL               ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
 183
 184 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS        0
 185 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
 186 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS       1
 187 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
 188 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS        2
 189 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
 190 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS         3
 191 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
 192
 193 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS        0
 194 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
 195 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS       1
 196 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR           ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
 197 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS        2
 198 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED            ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
 199 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS         3
 200 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE             ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
 201
 202 #ifdef __cplusplus
 203 }
 204 #endif
 205
 206 /**
 207 * @}
 208 */
 209
 210 #endif   /* _MXC_FLC_REGS_H_ */