tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32600/tpu_regs.h

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  33
  34 #ifndef _MXC_TPU_REGS_H_
  35 #define _MXC_TPU_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  tpu_regs.h
  45  * @addtogroup tpu TPU
  46  * @{
  47  */
  48
  49 /*                                               Offset   Register Description
  50                                                  ======   ================================================== */
  51 typedef struct {
  52     __I uint32_t rsv0000;                    /*  0x0000   Reserved                                          */
  53     __I uint32_t rsv0004;                    /*  0x0004   Reserved - PUF Control (Deprecated)               */
  54     __I uint32_t rsv0008;                    /*  0x0008   Reserved - PUF Output (Deprecated)                */
  55     __I uint32_t rsv000C[125];               /*  0x000C                                                     */
  56     __IO uint32_t prng_user_entropy;         /*  0x0200   PRNG User Entropy Value                           */
  57     __IO uint32_t prng_rnd_num;              /*  0x0204   PRNG Random Number Output                         */
  58 } mxc_tpu_regs_t;
  59
  60 /*                                               Offset   Register Description
  61                                                  ======   ================================================= */
  62 typedef struct {
  63     __IO uint32_t status;                    /*  0x0000   Dynamic Tamper Sensor Status                      */
  64     __IO uint32_t ctrl0;                     /*  0x0004   Dynamic Tamper Sensor Control 0                   */
  65     __IO uint32_t ctrl1;                     /*  0x0008   Dynamic Tamper Sensor Control 1                   */
  66     __IO uint32_t sks0;                      /*  0x0010   TPU Secure Key Storage Register 0                 */
  67     __IO uint32_t sks1;                      /*  0x0014   TPU Secure Key Storage Register 0                 */
  68     __IO uint32_t sks2;                      /*  0x0018   TPU Secure Key Storage Register 0                 */
  69     __IO uint32_t sks3;                      /*  0x001C   TPU Secure Key Storage Register 0                 */
  70 } mxc_tpu_tsr_regs_t;
  71
  72 /*
  73    Register offsets for module TPU.
  74 */
  75 #define MXC_R_TPU_OFFS_PRNG_USER_ENTROPY    ((uint32_t)0x00000200UL)
  76 #define MXC_R_TPU_OFFS_PRNG_RND_NUM         ((uint32_t)0x00000204UL)
  77 #define MXC_R_TPU_TSR_OFFS_STATUS           ((uint32_t)0x00000000UL)
  78 #define MXC_R_TPU_TSR_OFFS_CTRL0            ((uint32_t)0x00000004UL)
  79 #define MXC_R_TPU_TSR_OFFS_CTRL1            ((uint32_t)0x00000008UL)
  80 #define MXC_R_TPU_TSR_OFFS_SKS0             ((uint32_t)0x00000010UL)
  81 #define MXC_R_TPU_TSR_OFFS_SKS1             ((uint32_t)0x00000014UL)
  82 #define MXC_R_TPU_TSR_OFFS_SKS2             ((uint32_t)0x00000018UL)
  83 #define MXC_R_TPU_TSR_OFFS_SKS3             ((uint32_t)0x0000001CUL)
  84
  85
  86 /*
  87    Field positions and masks for module TPU.
  88 */
  89 #define MXC_F_TPU_CTRL0_ERR_THR_POS         0
  90 #define MXC_F_TPU_CTRL0_ERR_THR             ((uint32_t)(0x0000001FUL << MXC_F_TPU_CTRL0_ERR_THR_POS))
  91 #define MXC_F_TPU_CTRL0_OUT_FREQ_POS        5
  92 #define MXC_F_TPU_CTRL0_OUT_FREQ            ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_OUT_FREQ_POS))
  93 #define MXC_F_TPU_CTRL0_CLOCK_DIV_POS       8
  94 #define MXC_F_TPU_CTRL0_CLOCK_DIV           ((uint32_t)(0x00000007UL << MXC_F_TPU_CTRL0_CLOCK_DIV_POS))
  95 #define MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS     14
  96 #define MXC_F_TPU_CTRL0_RTC_TX_BUSY         ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_RTC_TX_BUSY_POS))
  97 #define MXC_F_TPU_CTRL0_LOCK_POS            15
  98 #define MXC_F_TPU_CTRL0_LOCK                ((uint32_t)(0x00000001UL << MXC_F_TPU_CTRL0_LOCK_POS))
  99
 100 #ifdef __cplusplus
 101 }
 102 #endif
 103
 104 /**
 105 * @}
 106 */
 107
 108 #endif   /* _MXC_TPU_REGS_H_ */