tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/max32610.h

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  16  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  17  * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
  18  * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Except as contained in this notice, the name of Maxim Integrated
  23  * Products, Inc. shall not be used except as stated in the Maxim Integrated
  24  * Products, Inc. Branding Policy.
  25  *
  26  * The mere transfer of this software does not imply any licenses
  27  * of trade secrets, proprietary technology, copyrights, patents,
  28  * trademarks, maskwork rights, or any other form of intellectual
  29  * property whatsoever. Maxim Integrated Products, Inc. retains all
  30  * ownership rights.
  31  *******************************************************************************
  32  */
  33
  34 #ifndef _MAX32610_H_
  35 #define _MAX32610_H_
  36
  37 #include <stdint.h>
  38
  39 typedef enum IRQn_Type {
  40     NonMaskableInt_IRQn = -14,
  41     HardFault_IRQn = -13,
  42     MemoryManagement_IRQn = -12,
  43     BusFault_IRQn = -11,
  44     UsageFault_IRQn = -10,
  45     SVCall_IRQn = -5,
  46     DebugMonitor_IRQn = -4,
  47     PendSV_IRQn = -2,
  48     SysTick_IRQn = -1,
  49
  50     /* Externals interrupts */
  51     UART0_IRQn = 0,      /* 16:01 UART0 */
  52     UART1_IRQn,          /* 17: 2 UART1 */
  53     I2CM0_IRQn,          /* 18: 3 I2C Master 0 */
  54     I2CS_IRQn,           /* 19: 4 I2C Slave */
  55     USB_IRQn,            /* 20: 5 USB */
  56     PMU_IRQn,            /* 21: 6 DMA */
  57     AFE_IRQn,            /* 22: 7 AFE */
  58     MAA_IRQn,            /* 23: 8 MAA */
  59     AES_IRQn,            /* 24: 9 AES */
  60     SPI0_IRQn,           /* 25:10 SPI0 */
  61     SPI1_IRQn,           /* 26:11 SPI1 */
  62     SPI2_IRQn,           /* 27:12 SPI2 */
  63     TMR0_IRQn,           /* 28:13 Timer32-0 */
  64     TMR1_IRQn,           /* 29:14 Timer32-1 */
  65     TMR2_IRQn,           /* 30:15 Timer32-1 */
  66     TMR3_IRQn,           /* 31:16 Timer32-2 */
  67     RSVD0_IRQn,          /* 32:17 RSVD */
  68     RSVD1_IRQn,          /* 33:18 RSVD */
  69     DAC0_IRQn,           /* 34:19 DAC0  (12-bit DAC) */
  70     DAC1_IRQn,           /* 35:20 DAC1  (12-bit DAC) */
  71     DAC2_IRQn,           /* 36:21 DAC2  (8-bit DAC) */
  72     DAC3_IRQn,           /* 37:22 DAC3  (8-bit DAC) */
  73     ADC_IRQn,            /* 38:23 ADC */
  74     FLC_IRQn,            /* 39:24 Flash Controller */
  75     PWRMAN_IRQn,         /* 40:25 PWRMAN */
  76     CLKMAN_IRQn,         /* 41:26 CLKMAN */
  77     RTC0_IRQn,           /* 42:27 RTC INT0 */
  78     RTC1_IRQn,           /* 43:28 RTC INT1 */
  79     RTC2_IRQn,           /* 44:29 RTC INT2 */
  80     RTC3_IRQn,           /* 45:30 RTC INT3 */
  81     WDT0_IRQn,           /* 46:31 WATCHDOG0 */
  82     WDT0_P_IRQn,         /* 47:32 WATCHDOG0 PRE-WINDOW */
  83     WDT1_IRQn,           /* 48:33 WATCHDOG1 */
  84     WDT1_P_IRQn,         /* 49:34 WATCHDOG1 PRE-WINDOW */
  85     GPIO_P0_IRQn,        /* 50:35 GPIO Port 0  */
  86     GPIO_P1_IRQn,        /* 51:36 GPIO Port 1  */
  87     GPIO_P2_IRQn,        /* 52:37 GPIO Port 2  */
  88     GPIO_P3_IRQn,        /* 53:38 GPIO Port 3  */
  89     GPIO_P4_IRQn,        /* 54:39 GPIO Port 4  */
  90     GPIO_P5_IRQn,        /* 55:40 GPIO Port 5  */
  91     GPIO_P6_IRQn,        /* 56:41 GPIO Port 6  */
  92     GPIO_P7_IRQn,        /* 57:42 GPIO Port 7  */
  93     TMR16_0_IRQn,        /* 58:43 Timer16-s0 */
  94     TMR16_1_IRQn,        /* 59:44 Timer16-s1 */
  95     TMR16_2_IRQn,        /* 60:45 Timer16-s2 */
  96     TMR16_3_IRQn,        /* 61:46 Timer16-s3 */
  97     I2CM1_IRQn,          /* 62:47 I2C Master 1 */
  98     MXC_IRQ_EXT_COUNT,
  99 } IRQn_Type;
 100
 101 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
 102
 103 /* ================================================================================ */
 104 /* ================      Processor and Core Peripheral Section     ================ */
 105 /* ================================================================================ */
 106
 107 #define __NVIC_PRIO_BITS          3         /*!< Number of Bits used for Priority Levels         */
 108
 109 #include <core_cm3.h>                       /* Processor and core peripherals */
 110 #include "system_max32610.h"                /* System Header */
 111
 112
 113 /* ================================================================================ */
 114 /* ==================       Device Specific Memory Section       ================== */
 115 /* ================================================================================ */
 116
 117 #define MXC_FLASH_MEM_BASE    0x00000000UL
 118 #define MXC_FLASH_PAGE_SIZE   0x1000        // 256 x 128b = 4KB
 119 #define MXC_FLASH_MEM_SIZE    0x00040000UL
 120 #define MXC_SYS_MEM_BASE      0x20000000UL
 121
 122 /* ================================================================================ */
 123 /* ================       Device Specific Peripheral Section       ================ */
 124 /* ================================================================================ */
 125
 126 /*******************************************************************************/
 127 /*                                            General Purpose I/O Ports (GPIO) */
 128
 129
 130 #define MXC_BASE_GPIO                   ((uint32_t)0x40000000UL)
 131 #define MXC_GPIO                        ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
 132 #define MXC_BASE_GPIO_BITBAND           ((uint32_t)0x42000000UL)
 133
 134 #define MXC_GPIO_GET_IRQ(i)             (((unsigned int)i) + GPIO_P0_IRQn)
 135
 136
 137 /*******************************************************************************/
 138 /*                                                      Pulse Train Generation */
 139
 140 #define MXC_CFG_PT_INSTANCES             (13)
 141
 142 #define MXC_BASE_PTG                     ((uint32_t)0x40001000UL)
 143 #define MXC_PTG                          ((mxc_ptg_regs_t *)MXC_BASE_PTG)
 144 #define MXC_BASE_PT                      ((uint32_t)0x40001008UL)
 145 #define MXC_PT                           ((mxc_pt_regs_t *)MXC_BASE_PT)
 146 #define MXC_BASE_PT0                     ((uint32_t)0x40001008UL)
 147 #define MXC_PT0                          ((mxc_pt_regs_t *)MXC_BASE_PT0)
 148 #define MXC_BASE_PT1                     ((uint32_t)0x40001010UL)
 149 #define MXC_PT1                          ((mxc_pt_regs_t *)MXC_BASE_PT1)
 150 #define MXC_BASE_PT2                     ((uint32_t)0x40001018UL)
 151 #define MXC_PT2                          ((mxc_pt_regs_t *)MXC_BASE_PT2)
 152 #define MXC_BASE_PT3                     ((uint32_t)0x40001020UL)
 153 #define MXC_PT3                          ((mxc_pt_regs_t *)MXC_BASE_PT3)
 154 #define MXC_BASE_PT4                     ((uint32_t)0x40001028UL)
 155 #define MXC_PT4                          ((mxc_pt_regs_t *)MXC_BASE_PT4)
 156 #define MXC_BASE_PT5                     ((uint32_t)0x40001030UL)
 157 #define MXC_PT5                          ((mxc_pt_regs_t *)MXC_BASE_PT5)
 158 #define MXC_BASE_PT6                     ((uint32_t)0x40001038UL)
 159 #define MXC_PT6                          ((mxc_pt_regs_t *)MXC_BASE_PT6)
 160 #define MXC_BASE_PT7                     ((uint32_t)0x40001040UL)
 161 #define MXC_PT7                          ((mxc_pt_regs_t *)MXC_BASE_PT7)
 162
 163 /*                                       PT12, PT13, PT14 are not used         */
 164
 165 /*******************************************************************************/
 166 /*                                                        CRC-16/CRC-32 Engine */
 167
 168 #define MXC_BASE_CRC                    ((uint32_t)0x40010000UL)
 169 #define MXC_CRC_REGS                    ((mxc_crc_regs_t *)MXC_BASE_CRC)
 170
 171 #define MXC_BASE_CRC_DATA               ((uint32_t)0x4010B000UL)
 172 #define MXC_CRC_DATA                    ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
 173
 174 /*******************************************************************************/
 175 /*                                                 Trust Protection Unit (TPU) */
 176
 177 #define MXC_BASE_TPU                     ((uint32_t)0x40011000UL)
 178 #define MXC_TPU                          ((mxc_tpu_regs_t *)MXC_BASE_TPU)
 179
 180 #define MXC_BASE_TPU_TSR                 ((uint32_t)0x40011C00UL)
 181 #define MXC_TPU_TSR                      ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
 182
 183 /*******************************************************************************/
 184 /*                                                    AES Cryptographic Engine */
 185
 186 #define MXC_BASE_AES                     ((uint32_t)0x40011400UL)
 187 #define MXC_AES                          ((mxc_aes_regs_t *)MXC_BASE_AES)
 188
 189 #define MXC_BASE_AES_MEM                 ((uint32_t)0x4010A000UL)
 190 #define MXC_AES_MEM                      ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
 191
 192
 193 /*******************************************************************************/
 194 /*                                                    MAA Cryptographic Engine */
 195
 196 #define MXC_BASE_MAA                     ((uint32_t)0x40011800UL)
 197 #define MXC_MAA                          ((mxc_maa_regs_t *)MXC_BASE_MAA)
 198
 199 #define MXC_BASE_MAA_MEM                 ((uint32_t)0x4010A800UL)
 200 #define MXC_MAA_MEM                      ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
 201
 202 /*******************************************************************************/
 203 /*                                                    32-Bit PWM Timer/Counter */
 204
 205 #define MXC_CFG_TMR_INSTANCES            (4)
 206
 207 #define MXC_BASE_TMR0                    ((uint32_t)0x40012000UL)
 208 #define MXC_BASE_TMR0_BITBAND            ((uint32_t)0x42240000UL)
 209 #define MXC_TMR0                         ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
 210
 211 #define MXC_BASE_TMR1                    ((uint32_t)0x40013000UL)
 212 #define MXC_BASE_TMR1_BITBAND            ((uint32_t)0x42260000UL)
 213 #define MXC_TMR1                         ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
 214
 215 #define MXC_BASE_TMR2                    ((uint32_t)0x40014000UL)
 216 #define MXC_BASE_TMR2_BITBAND            ((uint32_t)0x42280000UL)
 217 #define MXC_TMR2                         ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
 218
 219 #define MXC_BASE_TMR3                    ((uint32_t)0x40015000UL)
 220 #define MXC_BASE_TMR3_BITBAND            ((uint32_t)0x422A0000UL)
 221 #define MXC_TMR3                         ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
 222
 223
 224 #define MXC_TMR_GET_IRQ_32(i)            ((i) == 0 ? TMR0_IRQn :    \
 225                                           (i) == 1 ? TMR1_IRQn :    \
 226                                           (i) == 2 ? TMR2_IRQn :    \
 227                                           (i) == 3 ? TMR3_IRQn : 0)
 228
 229 #define MXC_TMR_GET_IRQ_16(i)            ((i) == 0 ? TMR0_IRQn :    \
 230                                           (i) == 1 ? TMR1_IRQn :    \
 231                                           (i) == 2 ? TMR2_IRQn :    \
 232                                           (i) == 3 ? TMR3_IRQn :    \
 233                                           (i) == 4 ? TMR16_0_IRQn :    \
 234                                           (i) == 5 ? TMR16_1_IRQn :    \
 235                                           (i) == 6 ? TMR16_2_IRQn :    \
 236                                           (i) == 7 ? TMR16_3_IRQn : 0)
 237
 238 #define MXC_TMR_GET_BASE(i)              ((i) == 0 ? MXC_BASE_TMR0 : \
 239                                           (i) == 1 ? MXC_BASE_TMR1 : \
 240                                           (i) == 2 ? MXC_BASE_TMR2 : \
 241                                           (i) == 3 ? MXC_BASE_TMR3 : 0)
 242
 243 #define MXC_TMR_GET_TMR(i)               ((i) == 0 ? MXC_TMR0 : \
 244                                           (i) == 1 ? MXC_TMR1 : \
 245                                           (i) == 2 ? MXC_TMR2 : \
 246                                           (i) == 3 ? MXC_TMR3 : 0)
 247 /*******************************************************************************/
 248 /*                                                              Watchdog Timer */
 249
 250 #define MXC_CFG_WDT_INSTANCES            (2)
 251
 252 #define MXC_BASE_WDT0                    ((uint32_t)0x40021000UL)
 253 #define MXC_BASE_WDT0_BITBAND            ((uint32_t)0x42420000UL)
 254 #define MXC_WDT0                         ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
 255
 256 #define MXC_BASE_WDT1                    ((uint32_t)0x40022000UL)
 257 #define MXC_BASE_WDT1_BITBAND            ((uint32_t)0x42440000UL)
 258 #define MXC_WDT1                         ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
 259
 260 #define MXC_WDT_GET_IRQ(i)               ((i) == 0 ? WDT0_IRQn : \
 261                                           (i) == 1 ? WDT1_IRQn : 0)
 262
 263 #define MXC_WDT_GET_IRQ_P(i)             ((i) == 0 ? WDT0_P_IRQn : \
 264                                           (i) == 1 ? WDT1_P_IRQn : 0)
 265
 266 #define MXC_WDT_GET_BASE(i)              ((i) == 0 ? MXC_BASE_WDT0 : \
 267                                           (i) == 1 ? MXC_BASE_WDT1 : 0)
 268
 269 #define MXC_WDT_GET_WDT(i)               ((i) == 0 ? MXC_WDT0 : \
 270                                           (i) == 1 ? MXC_WDT1 : 0)
 271
 272 /*******************************************************************************/
 273 /*                                                               SPI Interface */
 274
 275 #define MXC_CFG_SPI_INSTANCES            (3)
 276 #define MXC_CFG_SPI_FIFO_DEPTH           (16)
 277
 278 #define MXC_BASE_SPI0                    ((uint32_t)0x40030000UL)
 279 #define MXC_SPI0                         ((mxc_spi_regs_t *)MXC_BASE_SPI0)
 280
 281 #define MXC_BASE_SPI0_TXFIFO             ((uint32_t)0x40100000UL)
 282 #define MXC_SPI0_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
 283 #define MXC_BASE_SPI0_RXFIFO             ((uint32_t)0x40100800UL)
 284 #define MXC_SPI0_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
 285
 286 #define MXC_BASE_SPI1                    ((uint32_t)0x40031000UL)
 287 #define MXC_SPI1                         ((mxc_spi_regs_t *)MXC_BASE_SPI1)
 288
 289 #define MXC_BASE_SPI1_TXFIFO             ((uint32_t)0x40101000UL)
 290 #define MXC_SPI1_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
 291 #define MXC_BASE_SPI1_RXFIFO             ((uint32_t)0x40101800UL)
 292 #define MXC_SPI1_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
 293
 294 #define MXC_BASE_SPI2                    ((uint32_t)0x40032000UL)
 295 #define MXC_SPI2                         ((mxc_spi_regs_t *)MXC_BASE_SPI2)
 296
 297 #define MXC_BASE_SPI2_TXFIFO             ((uint32_t)0x40102000UL)
 298 #define MXC_SPI2_TXFIFO                  ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
 299 #define MXC_BASE_SPI2_RXFIFO             ((uint32_t)0x40102800UL)
 300 #define MXC_SPI2_RXFIFO                  ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
 301
 302
 303 #define MXC_SPI_GET_IRQ(i)               ((i) == 0 ? SPI0_IRQn :       \
 304                                           (i) == 1 ? SPI1_IRQn :       \
 305                                           (i) == 2 ? SPI2_IRQn : 0)
 306
 307 #define MXC_SPI_GET_BASE(i)              ((i) == 0 ? MXC_BASE_SPI0 :      \
 308                                           (i) == 1 ? MXC_BASE_SPI1 :      \
 309                                           (i) == 2 ? MXC_BASE_SPI2 : 0)
 310
 311 #define MXC_SPI_GET_SPI(i)               ((i) == 0 ? MXC_SPI0 :      \
 312                                           (i) == 1 ? MXC_SPI1 :      \
 313                                           (i) == 2 ? MXC_SPI2 : 0)
 314
 315 #define MXC_SPI_GET_RXFIFO(i)            ((i) == 0 ? MXC_SPI0_RXFIFO :      \
 316                                           (i) == 1 ? MXC_SPI1_RXFIFO :      \
 317                                           (i) == 2 ? MXC_SPI2_RXFIFO : 0)
 318
 319 #define MXC_SPI_GET_TXFIFO(i)            ((i) == 0 ? MXC_SPI0_TXFIFO :      \
 320                                           (i) == 1 ? MXC_SPI1_TXFIFO :      \
 321                                           (i) == 2 ? MXC_SPI2_TXFIFO : 0)
 322
 323 #define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
 324 #define MXC_SPI_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00003000) >> 12)
 325
 326
 327 /*******************************************************************************/
 328 /*                                                              UART Interface */
 329
 330 #define MXC_CFG_UART_INSTANCES           (2)
 331
 332 #define MXC_BASE_UART0                   ((uint32_t)0x40038000UL)
 333 #define MXC_BASE_UART0_BITBAND           ((uint32_t)0x42700000UL)
 334 #define MXC_UART0                        ((mxc_uart_regs_t *)MXC_BASE_UART0)
 335
 336 #define MXC_BASE_UART1                   ((uint32_t)0x40039000UL)
 337 #define MXC_BASE_UART1_BITBAND           ((uint32_t)0x42720000UL)
 338 #define MXC_UART1                        ((mxc_uart_regs_t *)MXC_BASE_UART1)
 339
 340
 341 #define MXC_UART_GET_IRQ(i)              ((i) == 0 ? UART0_IRQn :      \
 342                                           (i) == 1 ? UART1_IRQn : 0)
 343
 344 #define MXC_UART_GET_BASE(i)             ((i) == 0 ? MXC_BASE_UART0 :     \
 345                                           (i) == 1 ? MXC_BASE_UART1 : 0)
 346
 347 #define MXC_UART_GET_UART(i)             ((i) == 0 ? MXC_UART0 :     \
 348                                           (i) == 1 ? MXC_UART1 : 0)
 349
 350 #define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
 351 #define MXC_UART_BASE_TO_INSTANCE(base)     (((uint32_t)(base) & 0x00001000) >> 12)
 352
 353
 354 /*******************************************************************************/
 355 /*                                                        I2C Master Interface */
 356
 357 #define MXC_CFG_I2CM_INSTANCES           (2)
 358
 359 #define MXC_BASE_I2CM0                   ((uint32_t)0x40040000UL)
 360 #define MXC_BASE_I2CM0_BITBAND           ((uint32_t)0x42800000UL)
 361 #define MXC_I2CM0                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
 362 #define MXC_BASE_I2CM0_TX_FIFO           ((uint32_t)0x40103000UL)
 363 #define MXC_BASE_I2CM0_RX_FIFO           ((uint32_t)0x40103800UL)
 364
 365 #define MXC_BASE_I2CM1                   ((uint32_t)0x40042000UL)
 366 #define MXC_BASE_I2CM1_BITBAND           ((uint32_t)0x42840000UL)
 367 #define MXC_I2CM1                        ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
 368 #define MXC_BASE_I2CM1_TX_FIFO           ((uint32_t)0x4010D000UL)
 369 #define MXC_BASE_I2CM1_RX_FIFO           ((uint32_t)0x4010D800UL)
 370
 371 #define MXC_I2CM_GET_IRQ(i)              ((i) == 0 ? I2CM0_IRQn :      \
 372                                           (i) == 1 ? I2CM1_IRQn : 0)
 373
 374 #define MXC_I2CM_GET_BASE(i)             ((i) == 0 ? MXC_BASE_I2CM0 :     \
 375                                           (i) == 1 ? MXC_BASE_I2CM1 : 0)
 376
 377 #define MXC_I2CM_GET_I2CM(i)             ((i) == 0 ? MXC_I2CM0 :     \
 378                                           (i) == 1 ? MXC_I2CM1 : 0)
 379
 380 #define MXC_I2CM_GET_BASE_TX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO :  \
 381                                           (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
 382
 383 #define MXC_I2CM_GET_BASE_RX_FIFO(i)     ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO :  \
 384                                           (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
 385
 386 #define MXC_I2CM_INSTANCE_TO_BASE(instance)   (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
 387 #define MXC_I2CM_BASE_TO_INSTANCE(base)       (((uint32_t)(base) & 0x00002000) >> 13)
 388
 389
 390 /*******************************************************************************/
 391 /*                                                         I2C Slave Interface */
 392
 393 #define MXC_CFG_I2CS_INSTANCES           (1)
 394
 395 #define MXC_BASE_I2CS0                   ((uint32_t)0x40041000UL)
 396 #define MXC_BASE_I2CS0_BITBAND           ((uint32_t)0x42820000UL)
 397 #define MXC_I2CS0                        ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
 398
 399 #define MXC_BASE_I2CS0_FIFO              ((uint32_t)0x40104000UL)
 400 #define MXC_I2CS0_FIFO                   ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
 401
 402
 403
 404 /*******************************************************************************/
 405 /*                                                                        DACs */
 406
 407 #define MXC_CFG_DAC_INSTANCES            (4)
 408 #define MXC_CFG_DAC_FIFO_DEPTH           (32)
 409
 410 #define MXC_BASE_DAC0                    ((uint32_t)0x40050000UL)
 411 #define MXC_DAC0                         ((mxc_dac_regs_t *)MXC_BASE_DAC0)
 412 #define MXC_BASE_DAC0_FIFO               ((uint32_t)0x40105000UL)
 413 #define MXC_DAC0_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
 414 #define MXC_DAC0_WIDTH                   ((uint8_t)(2))
 415
 416 #define MXC_BASE_DAC1                    ((uint32_t)0x40051000UL)
 417 #define MXC_DAC1                         ((mxc_dac_regs_t *)MXC_BASE_DAC1)
 418 #define MXC_BASE_DAC1_FIFO               ((uint32_t)0x40106000UL)
 419 #define MXC_DAC1_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
 420 #define MXC_DAC1_WIDTH                   ((uint8_t)(2))
 421
 422 #define MXC_BASE_DAC2                    ((uint32_t)0x40052000UL)
 423 #define MXC_DAC2                         ((mxc_dac_regs_t *)MXC_BASE_DAC2)
 424 #define MXC_BASE_DAC2_FIFO               ((uint32_t)0x40107000UL)
 425 #define MXC_DAC2_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
 426 #define MXC_DAC2_WIDTH                   ((uint8_t)(1))
 427
 428 #define MXC_BASE_DAC3                    ((uint32_t)0x40053000UL)
 429 #define MXC_DAC3                         ((mxc_dac_regs_t *)MXC_BASE_DAC3)
 430 #define MXC_BASE_DAC3_FIFO               ((uint32_t)0x40108000UL)
 431 #define MXC_DAC3_FIFO                    ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
 432 #define MXC_DAC3_WIDTH                   ((uint8_t)(1))
 433
 434
 435 #define MXC_DAC_GET_IRQ(i)               ((i) == 0 ? DAC0_IRQn :     \
 436                                           (i) == 1 ? DAC1_IRQn :     \
 437                                           (i) == 2 ? DAC2_IRQn :     \
 438                                           (i) == 3 ? DAC3_IRQn : 0)
 439
 440
 441 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
 442                              i == 1 ? MXC_BASE_DAC1 : \
 443                              i == 2 ? MXC_BASE_DAC2 : \
 444                              i == 3 ? MXC_BASE_DAC3 : 0)
 445
 446 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
 447                              i == 1 ? MXC_BASE_DAC1_FIFO : \
 448                              i == 2 ? MXC_BASE_DAC2_FIFO  : \
 449                              i == 3 ? MXC_BASE_DAC3_FIFO  : 0)
 450
 451 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
 452                                      i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
 453                                      i == 2 ? PMU_IRQ_DAC2_FIFO_AE  : \
 454                                      i == 3 ? PMU_IRQ_DAC3_FIFO_AE  : 0)
 455
 456 #define MXC_DAC_GET_DAC(i)  (i == 0 ? MXC_DAC0 : \
 457                              i == 1 ? MXC_DAC1 : \
 458                              i == 2 ? MXC_DAC2 : \
 459                              i == 3 ? MXC_DAC3 : 0)
 460
 461 #define MXC_DAC_GET_WIDTH(i)  (i == 0 ? MXC_DAC0_WIDTH : \
 462                                i == 1 ? MXC_DAC1_WIDTH : \
 463                                i == 2 ? MXC_DAC2_WIDTH : \
 464                                i == 3 ? MXC_DAC3_WIDTH : 0)
 465
 466
 467 /*******************************************************************************/
 468 /*                                                            Analog Front End */
 469
 470 #define MXC_BASE_AFE                     ((uint32_t)0x4005401CUL)
 471 #define MXC_AFE                          ((mxc_afe_regs_t *)MXC_BASE_AFE)
 472
 473
 474
 475 /*******************************************************************************/
 476 /*                                                                         ADC */
 477
 478 #define MXC_CFG_ADC_FIFO_DEPTH           ((uint32_t)(32))
 479
 480 #define MXC_BASE_ADC                     ((uint32_t)0x40054000UL)
 481 #define MXC_ADC                          ((mxc_adc_regs_t *)MXC_BASE_ADC)
 482
 483 #define MXC_BASE_ADCCFG                  ((uint32_t)0x40054038UL)
 484 #define MXC_ADCCFG                       ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
 485
 486 #define MXC_BASE_ADC_FIFO                ((uint32_t)0x40109000UL)
 487 #define MXC_ADC_FIFO                     ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
 488
 489
 490
 491 /*******************************************************************************/
 492 /*                  Peripheral Management Unit (PMU) - formerly DMA Controller */
 493
 494 #define MXC_CFG_PMU_CHANNELS             (6)
 495
 496 #define MXC_BASE_PMU0                    ((uint32_t)0x40070000UL)
 497 #define MXC_PMU0                         ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
 498 #define MXC_BASE_PMU1                    ((uint32_t)0x40070020UL)
 499 #define MXC_PMU1                         ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
 500 #define MXC_BASE_PMU2                    ((uint32_t)0x40070040UL)
 501 #define MXC_PMU2                         ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
 502 #define MXC_BASE_PMU3                    ((uint32_t)0x40070060UL)
 503 #define MXC_PMU3                         ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
 504 #define MXC_BASE_PMU4                    ((uint32_t)0x40070080UL)
 505 #define MXC_PMU4                         ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
 506 #define MXC_BASE_PMU5                    ((uint32_t)0x400700A0UL)
 507 #define MXC_PMU5                         ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
 508
 509 #define MXC_BASE_PMU_BITBAND            ((uint32_t)0x42E00000UL)
 510 #define MXC_BASE_PMU_BITBAND_CHOFFSET   ((uint32_t)0x00000400UL)
 511 /*******************************************************************************/
 512
 513 typedef enum {
 514     PMU_IRQ_DAC0_FIFO_AE,
 515     PMU_IRQ_DAC1_FIFO_AE,
 516     PMU_IRQ_DAC2_FIFO_AE,
 517     PMU_IRQ_DAC3_FIFO_AE,
 518     PMU_IRQ_DAC0_DONE,
 519     PMU_IRQ_DAC1_DONE,
 520     PMU_IRQ_DAC2_DONE,
 521     PMU_IRQ_DAC3_DONE,
 522     PMU_IRQ_ADC_FIFO_AF,
 523     PMU_IRQ_ADC_DONE,
 524     PMU_IRQ_I2C_MST0_DONE,
 525     PMU_IRQ_I2C_MST1_DONE,
 526     PMU_IRQ_SPI0_RSLTS_DONE,
 527     PMU_IRQ_SPI1_RSLTS_DONE,
 528     PMU_IRQ_SPI2_RSLTS_DONE,
 529     PMU_IRQ_MAA_DONE,
 530     PMU_IRQ_SPI0_TX_FIFO_AE,
 531     PMU_IRQ_SPI0_RSLTS_FIFO_AF,
 532     PMU_IRQ_SPI1_TX_FIFO_AE,
 533     PMU_IRQ_SPI1_RSLTS_FIFO_AF,
 534     PMU_IRQ_SPI2_TX_FIFO_AE,
 535     PMU_IRQ_SPI3_RSLTS_FIFO_AF,
 536     PMU_IRQ_I2C_MST0_TRANS_FIFO,
 537     PMU_IRQ_I2C_MST0_RSLT_FIFO,
 538     PMU_IRQ_I2C_MST1_TRANS_FIFO,
 539     PMU_IRQ_I2C_MST2_RSLT_FIFO,
 540     PMU_IRQ_I2C_SLV_TRANS_FIFO,
 541     PMU_IRQ_I2C_SLV_RSLT_FIFO,
 542     PMU_IRQ_UART0_TX_FIFO,
 543     PMU_IRQ_UART0_RX_FIFO,
 544     PMU_IRQ_UART1_TX_FIFO,
 545     PMU_IRQ_UART1_RX_FIFO,
 546     PMU_IRQ_SPI0_EXCP,
 547     PMU_IRQ_SPI1_EXCP,
 548     PMU_IRQ_SPI2_EXCP,
 549     PMU_IRQ_RSVD0,
 550     PMU_IRQ_I2C_MST0_EXCP,
 551     PMU_IRQ_I2C_MST1_EXCP,
 552     PMU_IRQ_I2C_SLV_EXCP,
 553     PMU_IRQ_RSVD1,
 554     PMU_IRQ_GPIO0,
 555     PMU_IRQ_GPIO1,
 556     PMU_IRQ_GPIO2,
 557     PMU_IRQ_GPIO3,
 558     PMU_IRQ_GPIO4,
 559     PMU_IRQ_GPIO5,
 560     PMU_IRQ_GPIO6,
 561     PMU_IRQ_GPIO7,
 562     PMU_IRQ_GPIO8,
 563     PMU_IRQ_AFE_COMP_NMI,
 564     PMU_IRQ_AES_ENGINE,
 565 } pmu_int_mask_t;
 566
 567 /*******************************************************************************/
 568 /*                                                                         USB */
 569
 570 #define MXC_BASE_USB                     ((uint32_t)0x4010C000UL)
 571 #define MXC_USB                          ((mxc_usb_regs_t *)MXC_BASE_USB)
 572
 573 #define MXC_USB_MAX_PACKET               (64)
 574 #define MXC_USB_NUM_EP                   (8)
 575
 576
 577 /*******************************************************************************/
 578 /*                                                Instruction Cache Controller */
 579
 580 #define MXC_BASE_ICC                     ((uint32_t)0x40080000UL)
 581 #define MXC_ICC                          ((mxc_icc_regs_t *)MXC_BASE_ICC)
 582
 583 /*                                                              System Manager */
 584
 585 #define MXC_BASE_SYSMAN                 ((uint32_t)0x40090000UL)
 586
 587 /*******************************************************************************/
 588 /*                                                               Clock Manager */
 589
 590 #define MXC_BASE_CLKMAN                  ((uint32_t)0x40090400UL)
 591 #define MXC_CLKMAN                       ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
 592
 593
 594 /*******************************************************************************/
 595 /*                                                               Power Manager */
 596
 597 #define MXC_BASE_PWRMAN                  ((uint32_t)0x40090800UL)
 598 #define MXC_PWRMAN                       ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
 599
 600 /*******************************************************************************/
 601 /*                                                                 I/O Manager */
 602
 603 #define MXC_BASE_IOMAN                   ((uint32_t)0x40090C00UL)
 604 #define MXC_IOMAN                        ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
 605
 606
 607 /*******************************************************************************/
 608 /*                                                           RTC: Timer/Alarms */
 609
 610 #define MXC_BASE_RTCTMR                 ((uint32_t)0x40090A00UL)
 611 #define MXC_RTCTMR                       ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
 612
 613 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn :    \
 614                                i == 1 ? RTC1_IRQn :    \
 615                                i == 2 ? RTC2_IRQn :    \
 616                                i == 3 ? RTC3_IRQn : 0)
 617
 618 #define MXC_BASE_RTCCFG                  ((uint32_t)0x40090A70UL)
 619 #define MXC_RTCCFG                       ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
 620 /*******************************************************************************/
 621 /*                                                        RTC: Power Sequencer */
 622
 623 #define MXC_BASE_PWRSEQ                  ((uint32_t)0x40090A30UL)
 624 #define MXC_PWRSEQ                       ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
 625
 626 /*******************************************************************************/
 627 /*                                                       Trim Shadow Registers */
 628
 629 #define MXC_BASE_TRIM                    ((uint32_t)0x400E0000UL)
 630 #define MXC_TRIM                         ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
 631
 632 /*******************************************************************************/
 633 /*                                          Flash Memory Controller / Security */
 634
 635 #define MXC_BASE_FLC                     ((uint32_t)0x400F0000UL)
 636 #define MXC_FLC                          ((mxc_flc_regs_t *)MXC_BASE_FLC)
 637 #define MXC_BASE_FLC_BITBAND             ((uint32_t)0x43E00000UL)
 638 #define MXC_FLC_PAGE_SIZE_SHIFT          11
 639 #define MXC_FLC_PAGE_SIZE                (1 << MXC_FLC_PAGE_SIZE_SHIFT)
 640 #define MXC_FLC_PAGE_ERASE_MSK           ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
 641
 642 /*******************************************************************************/
 643
 644 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
 645
 646 /*******************************************************************************/
 647
 648 #define BITBAND(reg, bit)        ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
 649 #define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0
 650 #define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1
 651 #define BITBAND_GetBit(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
 652
 653 /*******************************************************************************/
 654
 655 #endif  /* _MAX32610_H_ */