tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrman_regs.h

   1 /*******************************************************************************
   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
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  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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  32  */
  33
  34 #ifndef _MXC_PWRMAN_REGS_H_
  35 #define _MXC_PWRMAN_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  pwrman_regs.h
  45  * @addtogroup pwrman PWRMAN
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines PAD Modes for Wake Up Detection.
  51  */
  52 typedef enum {
  53     /** WUD Mode for Selected PAD = Clear/Activate */
  54     MXC_E_PWRMAN_PAD_MODE_CLEAR_SET,
  55     /** WUD Mode for Selected PAD = Set WUD Act Hi/Set WUD Act Lo */
  56     MXC_E_PWRMAN_PAD_MODE_ACT_HI_LO,
  57     /** WUD Mode for Selected PAD = Set Weak Hi/ Set Weak Lo */
  58     MXC_E_PWRMAN_PAD_MODE_WEAK_HI_LO,
  59     /** WUD Mode for Selected PAD = No pad state change */
  60     MXC_E_PWRMAN_PAD_MODE_NONE
  61 } mxc_pwrman_pad_mode_t;
  62
  63 /*                                          Offset   Register Description
  64                                             ======   =========================================== */
  65 typedef struct {
  66     __IO uint32_t pwr_rst_ctrl;         /*  0x0000   Power Reset Control and Status              */
  67     __IO uint32_t intfl;                /*  0x0004   Interrupt Flags                             */
  68     __IO uint32_t inten;                /*  0x0008   Interrupt Enable/Disable Controls           */
  69     __IO uint32_t svm_events;           /*  0x000C   SVM Event Status Flags (read-only)          */
  70     __IO uint32_t wud_ctrl;             /*  0x0010   Wake-Up Detect Control                      */
  71     __IO uint32_t wud_pulse0;           /*  0x0014   WUD Pulse To Mode Bit 0                     */
  72     __IO uint32_t wud_pulse1;           /*  0x0018   WUD Pulse To Mode Bit 1                     */
  73     __I uint32_t rsv001C[5];            /*  0x001C                                               */
  74
  75     __IO uint32_t wud_seen0;            /*  0x0030   Wake-up Detect Status for P0/P1/P2/P3       */
  76     __IO uint32_t wud_seen1;            /*  0x0034   Wake-up Detect Status for P4/P5/P6/P7       */
  77     __IO uint32_t die_type;             /*  0x0038   Die ID Register (Device Type)               */
  78     __IO uint32_t base_part_num;        /*  0x003C   Base Part Number                            */
  79     __IO uint32_t mask_id0;             /*  0x0040   Mask ID Register 0                          */
  80     __IO uint32_t mask_id1;             /*  0x0044   Mask ID Register 1                          */
  81     __IO uint32_t peripheral_reset;     /*  0x0048   Peripheral Reset Control Register           */
  82 } mxc_pwrman_regs_t;
  83
  84 /*
  85    Register offsets for module PWRMAN.
  86 */
  87 #define MXC_R_PWRMAN_OFFS_PWR_RST_CTRL          ((uint32_t)0x00000000UL)
  88 #define MXC_R_PWRMAN_OFFS_INTFL                 ((uint32_t)0x00000004UL)
  89 #define MXC_R_PWRMAN_OFFS_INTEN                 ((uint32_t)0x00000008UL)
  90 #define MXC_R_PWRMAN_OFFS_SVM_EVENTS            ((uint32_t)0x0000000CUL)
  91 #define MXC_R_PWRMAN_OFFS_WUD_CTRL              ((uint32_t)0x00000010UL)
  92 #define MXC_R_PWRMAN_OFFS_WUD_PULSE0            ((uint32_t)0x00000014UL)
  93 #define MXC_R_PWRMAN_OFFS_WUD_PULSE1            ((uint32_t)0x00000018UL)
  94 #define MXC_R_PWRMAN_OFFS_WUD_SEEN0             ((uint32_t)0x00000030UL)
  95 #define MXC_R_PWRMAN_OFFS_WUD_SEEN1             ((uint32_t)0x00000034UL)
  96 #define MXC_R_PWRMAN_OFFS_DIE_TYPE              ((uint32_t)0x00000038UL)
  97 #define MXC_R_PWRMAN_OFFS_BASE_PART_NUM         ((uint32_t)0x0000003CUL)
  98 #define MXC_R_PWRMAN_OFFS_MASK_ID0              ((uint32_t)0x00000040UL)
  99 #define MXC_R_PWRMAN_OFFS_MASK_ID1              ((uint32_t)0x00000044UL)
 100 #define MXC_R_PWRMAN_OFFS_PERIPHERAL_RESET      ((uint32_t)0x00000048UL)
 101
 102 /*
 103    Field positions and masks for module PWRMAN.
 104 */
 105 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS          0
 106 #define MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE              ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FLASH_ACTIVE_POS))
 107 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS           1
 108 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRAM_ACTIVE_POS))
 109 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS           2
 110 #define MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED_POS))
 111 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS             3
 112 #define MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_IO_ACTIVE_POS))
 113 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS           4
 114 #define MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED               ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_USB_POWERED_POS))
 115 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS       5
 116 #define MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_PULLUPS_ENABLED_POS))
 117 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS        8
 118 #define MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FIRMWARE_RESET_POS))
 119 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS      9
 120 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_RESET_POS))
 121 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS             12
 122 #define MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WUD_CLEAR_POS))
 123 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS         16
 124 #define MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_TAMPER_DETECT_POS))
 125 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS     17
 126 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN         ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_SYSMAN_POS))
 127 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS      18
 128 #define MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT          ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_WATCHDOG_TIMEOUT_POS))
 129 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS        19
 130 #define MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_FW_COMMAND_ARM_POS))
 131 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS            20
 132 #define MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_ARM_LOCKUP_POS))
 133 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS       21
 134 #define MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_SRSTN_ASSERTION_POS))
 135 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS                   22
 136 #define MXC_F_PWRMAN_PWR_RST_CTRL_POR                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_POR_POS))
 137 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS        31
 138 #define MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE            ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PWR_RST_CTRL_LOW_POWER_MODE_POS))
 139
 140 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS                 0
 141 #define MXC_F_PWRMAN_INTFL_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V1_8_WARNING_POS))
 142 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS                 1
 143 #define MXC_F_PWRMAN_INTFL_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_WARNING_POS))
 144 #define MXC_F_PWRMAN_INTFL_RTC_WARNING_POS                  2
 145 #define MXC_F_PWRMAN_INTFL_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_RTC_WARNING_POS))
 146 #define MXC_F_PWRMAN_INTFL_V3_3_RESET_POS                   3
 147 #define MXC_F_PWRMAN_INTFL_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_V3_3_RESET_POS))
 148 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS                 4
 149 #define MXC_F_PWRMAN_INTFL_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTFL_VDDA_WARNING_POS))
 150
 151 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS                 0
 152 #define MXC_F_PWRMAN_INTEN_V1_8_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V1_8_WARNING_POS))
 153 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS                 1
 154 #define MXC_F_PWRMAN_INTEN_V3_3_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_WARNING_POS))
 155 #define MXC_F_PWRMAN_INTEN_RTC_WARNING_POS                  2
 156 #define MXC_F_PWRMAN_INTEN_RTC_WARNING                      ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_RTC_WARNING_POS))
 157 #define MXC_F_PWRMAN_INTEN_V3_3_RESET_POS                   3
 158 #define MXC_F_PWRMAN_INTEN_V3_3_RESET                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_V3_3_RESET_POS))
 159 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS                 4
 160 #define MXC_F_PWRMAN_INTEN_VDDA_WARNING                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_INTEN_VDDA_WARNING_POS))
 161
 162 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS            0
 163 #define MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V1_8_WARNING_POS))
 164 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS            1
 165 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_WARNING_POS))
 166 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS             2
 167 #define MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_RTC_WARNING_POS))
 168 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS              3
 169 #define MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_V3_3_RESET_POS))
 170 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS            4
 171 #define MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_SVM_EVENTS_VDDA_WARNING_POS))
 172
 173 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS                0
 174 #define MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT                    ((uint32_t)(0x0000003FUL << MXC_F_PWRMAN_WUD_CTRL_PAD_SELECT_POS))
 175 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS                  8
 176 #define MXC_F_PWRMAN_WUD_CTRL_PAD_MODE                      ((uint32_t)(0x00000003UL << MXC_F_PWRMAN_WUD_CTRL_PAD_MODE_POS))
 177 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS                 12
 178 #define MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL                     ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_CTRL_CLEAR_ALL_POS))
 179
 180 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS                    0
 181 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO0                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO0_POS))
 182 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS                    1
 183 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO1                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO1_POS))
 184 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS                    2
 185 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO2                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO2_POS))
 186 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS                    3
 187 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO3                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO3_POS))
 188 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS                    4
 189 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO4                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO4_POS))
 190 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS                    5
 191 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO5                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO5_POS))
 192 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS                    6
 193 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO6                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO6_POS))
 194 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS                    7
 195 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO7                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO7_POS))
 196 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS                    8
 197 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO8                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO8_POS))
 198 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS                    9
 199 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO9                        ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO9_POS))
 200 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS                   10
 201 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO10                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO10_POS))
 202 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS                   11
 203 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO11                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO11_POS))
 204 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS                   12
 205 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO12                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO12_POS))
 206 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS                   13
 207 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO13                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO13_POS))
 208 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS                   14
 209 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO14                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO14_POS))
 210 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS                   15
 211 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO15                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO15_POS))
 212 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS                   16
 213 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO16                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO16_POS))
 214 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS                   17
 215 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO17                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO17_POS))
 216 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS                   18
 217 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO18                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO18_POS))
 218 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS                   19
 219 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO19                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO19_POS))
 220 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS                   20
 221 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO20                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO20_POS))
 222 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS                   21
 223 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO21                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO21_POS))
 224 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS                   22
 225 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO22                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO22_POS))
 226 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS                   23
 227 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO23                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO23_POS))
 228 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS                   24
 229 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO24                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO24_POS))
 230 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS                   25
 231 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO25                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO25_POS))
 232 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS                   26
 233 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO26                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO26_POS))
 234 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS                   27
 235 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO27                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO27_POS))
 236 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS                   28
 237 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO28                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO28_POS))
 238 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS                   29
 239 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO29                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO29_POS))
 240 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS                   30
 241 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO30                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO30_POS))
 242 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS                   31
 243 #define MXC_F_PWRMAN_WUD_SEEN0_GPIO31                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN0_GPIO31_POS))
 244
 245 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS                   0
 246 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO32                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO32_POS))
 247 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS                   1
 248 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO33                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO33_POS))
 249 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS                   2
 250 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO34                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO34_POS))
 251 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS                   3
 252 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO35                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO35_POS))
 253 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS                   4
 254 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO36                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO36_POS))
 255 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS                   5
 256 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO37                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO37_POS))
 257 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS                   6
 258 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO38                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO38_POS))
 259 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS                   7
 260 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO39                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO39_POS))
 261 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS                   8
 262 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO40                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO40_POS))
 263 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS                   9
 264 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO41                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO41_POS))
 265 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS                   10
 266 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO42                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO42_POS))
 267 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS                   11
 268 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO43                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO43_POS))
 269 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS                   12
 270 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO44                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO44_POS))
 271 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS                   13
 272 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO45                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO45_POS))
 273 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS                   14
 274 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO46                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO46_POS))
 275 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS                   15
 276 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO47                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO47_POS))
 277 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS                   16
 278 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO48                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO48_POS))
 279 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS                   17
 280 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO49                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO49_POS))
 281 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS                   18
 282 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO50                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO50_POS))
 283 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS                   19
 284 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO51                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO51_POS))
 285 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS                   20
 286 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO52                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO52_POS))
 287 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS                   21
 288 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO53                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO53_POS))
 289 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS                   22
 290 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO54                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO54_POS))
 291 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS                   23
 292 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO55                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO55_POS))
 293 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS                   24
 294 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO56                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO56_POS))
 295 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS                   25
 296 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO57                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO57_POS))
 297 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS                   26
 298 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO58                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO58_POS))
 299 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS                   27
 300 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO59                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO59_POS))
 301 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS                   28
 302 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO60                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO60_POS))
 303 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS                   29
 304 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO61                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO61_POS))
 305 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS                   30
 306 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO62                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO62_POS))
 307 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS                   31
 308 #define MXC_F_PWRMAN_WUD_SEEN1_GPIO63                       ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_WUD_SEEN1_GPIO63_POS))
 309
 310 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS     0
 311 #define MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER         ((uint32_t)(0x0000FFFFUL << MXC_F_PWRMAN_BASE_PART_NUM_BASE_PART_NUMBER_POS))
 312 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS       28
 313 #define MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_BASE_PART_NUM_PACKAGE_SELECT_POS))
 314
 315 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS               0
 316 #define MXC_F_PWRMAN_MASK_ID0_REVISION_ID                   ((uint32_t)(0x0000000FUL << MXC_F_PWRMAN_MASK_ID0_REVISION_ID_POS))
 317 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS                   4
 318 #define MXC_F_PWRMAN_MASK_ID0_MASK_ID                       ((uint32_t)(0x0FFFFFFFUL << MXC_F_PWRMAN_MASK_ID0_MASK_ID_POS))
 319
 320 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS                   0
 321 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID                       ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_POS))
 322 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS            31
 323 #define MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_MASK_ID1_MASK_ID_ENABLE_POS))
 324
 325 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS             0
 326 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART0_POS))
 327 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS             1
 328 #define MXC_F_PWRMAN_PERIPHERAL_RESET_UART1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_UART1_POS))
 329 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS            2
 330 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER0_POS))
 331 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS            3
 332 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER1_POS))
 333 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS            4
 334 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER2_POS))
 335 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS            5
 336 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3                ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TIMER3_POS))
 337 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS         6
 338 #define MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0             ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_WATCHDOG0_POS))
 339 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS               7
 340 #define MXC_F_PWRMAN_PERIPHERAL_RESET_USB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_USB_POS))
 341 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS               8
 342 #define MXC_F_PWRMAN_PERIPHERAL_RESET_ADC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_ADC_POS))
 343 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS              9
 344 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC0_POS))
 345 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS              10
 346 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC1_POS))
 347 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS              11
 348 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC2_POS))
 349 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS              12
 350 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DAC3_POS))
 351 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS               13
 352 #define MXC_F_PWRMAN_PERIPHERAL_RESET_DMA                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_DMA_POS))
 353 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS               14
 354 #define MXC_F_PWRMAN_PERIPHERAL_RESET_LCD                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_LCD_POS))
 355 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS              15
 356 #define MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_GPIO_POS))
 357 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS       16
 358 #define MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN           ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_PULSE_TRAIN_POS))
 359 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS              17
 360 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI0_POS))
 361 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS              18
 362 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI1_POS))
 363 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS              19
 364 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SPI2_POS))
 365 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS             20
 366 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM0_POS))
 367 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS             21
 368 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1                 ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CM1_POS))
 369 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS              22
 370 #define MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS                  ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_I2CS_POS))
 371 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS               23
 372 #define MXC_F_PWRMAN_PERIPHERAL_RESET_CRC                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_CRC_POS))
 373 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS               24
 374 #define MXC_F_PWRMAN_PERIPHERAL_RESET_TPU                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_TPU_POS))
 375 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS               25
 376 #define MXC_F_PWRMAN_PERIPHERAL_RESET_SSB                   ((uint32_t)(0x00000001UL << MXC_F_PWRMAN_PERIPHERAL_RESET_SSB_POS))
 377
 378 #ifdef __cplusplus
 379 }
 380 #endif
 381
 382 /**
 383 * @}
 384 */
 385
 386 #endif /* _MXC_PWRMAN_REGS_H_ */