tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/wdt_regs.h

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  33
  34 #ifndef _MXC_WDT_REGS_H_
  35 #define _MXC_WDT_REGS_H_
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  wdt_regs.h
  45  * @addtogroup wdt WDT
  46  * @{
  47  */
  48
  49 /**
  50  * @brief Defines watchdog timer periods
  51  */
  52 typedef enum {
  53     /** 2^31 cycle period */
  54     MXC_E_WDT_PERIOD_2_31_CLKS = 0,
  55     /** 2^30 cycle period */
  56     MXC_E_WDT_PERIOD_2_30_CLKS,
  57     /** 2^29 cycle period */
  58     MXC_E_WDT_PERIOD_2_29_CLKS,
  59     /** 2^28 cycle period */
  60     MXC_E_WDT_PERIOD_2_28_CLKS,
  61     /** 2^27 cycle period */
  62     MXC_E_WDT_PERIOD_2_27_CLKS,
  63     /** 2^26 cycle period */
  64     MXC_E_WDT_PERIOD_2_26_CLKS,
  65     /** 2^25 cycle period */
  66     MXC_E_WDT_PERIOD_2_25_CLKS,
  67     /** 2^24 cycle period */
  68     MXC_E_WDT_PERIOD_2_24_CLKS,
  69     /** 2^23 cycle period */
  70     MXC_E_WDT_PERIOD_2_23_CLKS,
  71     /** 2^22 cycle period */
  72     MXC_E_WDT_PERIOD_2_22_CLKS,
  73     /** 2^21 cycle period */
  74     MXC_E_WDT_PERIOD_2_21_CLKS,
  75     /** 2^20 cycle period */
  76     MXC_E_WDT_PERIOD_2_20_CLKS,
  77     /** 2^19 cycle period */
  78     MXC_E_WDT_PERIOD_2_19_CLKS,
  79     /** 2^18 cycle period */
  80     MXC_E_WDT_PERIOD_2_18_CLKS,
  81     /** 2^17 cycle period */
  82     MXC_E_WDT_PERIOD_2_17_CLKS,
  83     /** 2^16 cycle period */
  84     MXC_E_WDT_PERIOD_2_16_CLKS,
  85 } mxc_wdt_period_t;
  86
  87 /*                                  Offset   Register Description
  88                                     ======   ================================================ */
  89 typedef struct {
  90     __IO uint32_t ctrl;         /*  0x0000   Watchdog Timer Control Register                  */
  91     __IO uint32_t clear;        /*  0x0004   Watchdog Clear Register (Feed Dog)               */
  92     __IO uint32_t int_rst_fl;   /*  0x0008   Watchdog Interrupt/Reset Flags                   */
  93     __IO uint32_t int_rst_en;   /*  0x000C   Interrupt/Reset Enable/Disable Controls          */
  94     __I uint32_t rsv0010;       /*  0x0010                                                    */
  95     __IO uint32_t lock_ctrl;    /*  0x0014   Lock Register Setting for WDT CTRL               */
  96 } mxc_wdt_regs_t;
  97
  98 /*
  99    Register offsets for module WDT.
 100 */
 101 #define MXC_R_WDT_OFFS_CTRL                       ((uint32_t)0x00000000UL)
 102 #define MXC_R_WDT_OFFS_CLEAR                      ((uint32_t)0x00000004UL)
 103 #define MXC_R_WDT_OFFS_INT_RST_FL                 ((uint32_t)0x00000008UL)
 104 #define MXC_R_WDT_OFFS_INT_RST_EN                 ((uint32_t)0x0000000CUL)
 105 #define MXC_R_WDT_OFFS_LOCK_CTRL                  ((uint32_t)0x00000014UL)
 106
 107 #define MXC_V_WDT_WDLOCK_LOCK_KEY                 ((uint8_t)0x24)
 108 #define MXC_V_WDT_WDLOCK_UNLOCK_KEY               ((uint8_t)0x42)
 109
 110
 111 /*
 112    Field positions and masks for module WDT.
 113 */
 114 #define MXC_F_WDT_CTRL_INT_PERIOD_POS       0
 115 #define MXC_F_WDT_CTRL_INT_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_INT_PERIOD_POS))
 116 #define MXC_F_WDT_CTRL_RST_PERIOD_POS       4
 117 #define MXC_F_WDT_CTRL_RST_PERIOD           ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_RST_PERIOD_POS))
 118 #define MXC_F_WDT_CTRL_EN_TIMER_POS         8
 119 #define MXC_F_WDT_CTRL_EN_TIMER             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_TIMER_POS))
 120 #define MXC_F_WDT_CTRL_EN_CLOCK_POS         9
 121 #define MXC_F_WDT_CTRL_EN_CLOCK             ((uint32_t)(0x00000001UL << MXC_F_WDT_CTRL_EN_CLOCK_POS))
 122 #define MXC_F_WDT_CTRL_WAIT_PERIOD_POS      12
 123 #define MXC_F_WDT_CTRL_WAIT_PERIOD          ((uint32_t)(0x0000000FUL << MXC_F_WDT_CTRL_WAIT_PERIOD_POS))
 124
 125 #define MXC_F_WDT_FLAGS_TIMEOUT_POS         0
 126 #define MXC_F_WDT_FLAGS_TIMEOUT             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_TIMEOUT_POS))
 127 #define MXC_F_WDT_FLAGS_PRE_WIN_POS         1
 128 #define MXC_F_WDT_FLAGS_PRE_WIN             ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_PRE_WIN_POS))
 129 #define MXC_F_WDT_FLAGS_RESET_OUT_POS       2
 130 #define MXC_F_WDT_FLAGS_RESET_OUT           ((uint32_t)(0x00000001UL << MXC_F_WDT_FLAGS_RESET_OUT_POS))
 131
 132 #define MXC_F_WDT_ENABLE_TIMEOUT_POS        0
 133 #define MXC_F_WDT_ENABLE_TIMEOUT            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_TIMEOUT_POS))
 134 #define MXC_F_WDT_ENABLE_PRE_WIN_POS        1
 135 #define MXC_F_WDT_ENABLE_PRE_WIN            ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_PRE_WIN_POS))
 136 #define MXC_F_WDT_ENABLE_RESET_OUT_POS      2
 137 #define MXC_F_WDT_ENABLE_RESET_OUT          ((uint32_t)(0x00000001UL << MXC_F_WDT_ENABLE_RESET_OUT_POS))
 138
 139 #define MXC_F_WDT_LOCK_CTRL_WDLOCK_POS      0
 140 #define MXC_F_WDT_LOCK_CTRL_WDLOCK          ((uint32_t)(0x000000FFUL << MXC_F_WDT_LOCK_CTRL_WDLOCK_POS))
 141
 142 #ifdef __cplusplus
 143 }
 144 #endif
 145
 146 /**
 147 * @}
 148 */
 149
 150 #endif   /* _MXC_WDT_REGS_H_ */