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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/nrf51_bitfields.h
1 /* Copyright (c) 2013, Nordic Semiconductor ASA 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 7 * * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 10 * * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 14 * * Neither the name of Nordic Semiconductor ASA nor the names of its 15 * contributors may be used to endorse or promote products derived from 16 * this software without specific prior written permission. 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 25 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 #ifndef __NRF51_BITS_H 31 #define __NRF51_BITS_H 33 /*lint ++flb "Enter library region */ 38 /* Description: Accelerated Address Resolver. */ 40 /* Register: AAR_INTENSET */ 41 /* Description: Interrupt enable set register. */ 43 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */ 44 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 45 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 46 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 47 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 48 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 50 /* Bit 1 : Enable interrupt on RESOLVED event. */ 51 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 52 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 53 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 54 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 55 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ 57 /* Bit 0 : Enable interrupt on END event. */ 58 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 59 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ 60 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 61 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 62 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 64 /* Register: AAR_INTENCLR */ 65 /* Description: Interrupt enable clear register. */ 67 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */ 68 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ 69 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ 70 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 71 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 72 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 74 /* Bit 1 : Disable interrupt on RESOLVED event. */ 75 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ 76 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ 77 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ 78 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ 79 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ 81 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 82 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 83 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 84 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 85 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 86 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 88 /* Register: AAR_STATUS */ 89 /* Description: Resolution status. */ 91 /* Bits 3..0 : The IRK used last time an address was resolved. */ 92 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 93 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ 95 /* Register: AAR_ENABLE */ 96 /* Description: Enable AAR. */ 98 /* Bits 1..0 : Enable AAR. */ 99 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 100 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 101 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ 102 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ 104 /* Register: AAR_NIRK */ 105 /* Description: Number of Identity root Keys in the IRK data structure. */ 107 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ 108 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ 109 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ 111 /* Register: AAR_POWER */ 112 /* Description: Peripheral power control. */ 114 /* Bit 0 : Peripheral power control. */ 115 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 116 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 117 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 118 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 121 /* Peripheral: ADC */ 122 /* Description: Analog to digital converter. */ 124 /* Register: ADC_INTENSET */ 125 /* Description: Interrupt enable set register. */ 127 /* Bit 0 : Enable interrupt on END event. */ 128 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ 129 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ 130 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 131 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 132 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 134 /* Register: ADC_INTENCLR */ 135 /* Description: Interrupt enable clear register. */ 137 /* Bit 0 : Disable interrupt on END event. */ 138 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ 139 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 140 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 141 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 142 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 144 /* Register: ADC_BUSY */ 145 /* Description: ADC busy register. */ 147 /* Bit 0 : ADC busy register. */ 148 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ 149 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ 150 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ 151 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ 153 /* Register: ADC_ENABLE */ 154 /* Description: ADC enable. */ 156 /* Bits 1..0 : ADC enable. */ 157 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 158 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 159 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ 160 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ 162 /* Register: ADC_CONFIG */ 163 /* Description: ADC configuration register. */ 165 /* Bits 17..16 : ADC external reference pin selection. */ 166 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ 167 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 168 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ 169 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ 170 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ 172 /* Bits 15..8 : ADC analog pin selection. */ 173 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 174 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 175 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ 176 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ 177 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ 178 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ 179 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ 180 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ 181 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ 182 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ 183 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ 185 /* Bits 6..5 : ADC reference selection. */ 186 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ 187 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 188 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ 189 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ 190 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ 191 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ 193 /* Bits 4..2 : ADC input selection. */ 194 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ 195 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ 196 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ 197 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ 198 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ 199 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ 200 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ 202 /* Bits 1..0 : ADC resolution. */ 203 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ 204 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ 205 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ 206 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ 207 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ 209 /* Register: ADC_RESULT */ 210 /* Description: Result of ADC conversion. */ 212 /* Bits 9..0 : Result of ADC conversion. */ 213 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 214 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 216 /* Register: ADC_POWER */ 217 /* Description: Peripheral power control. */ 219 /* Bit 0 : Peripheral power control. */ 220 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 221 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 222 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 223 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 226 /* Peripheral: AMLI */ 227 /* Description: AHB Multi-Layer Interface. */ 229 /* Register: AMLI_RAMPRI_CPU0 */ 230 /* Description: Configurable priority configuration register for CPU0. */ 232 /* Bits 31..28 : Configuration field for RAM block 7. */ 233 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 234 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 235 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 236 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 237 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 238 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 239 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 240 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 241 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 244 /* Bits 27..24 : Configuration field for RAM block 6. */ 245 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 246 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 247 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 248 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 249 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 250 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 251 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 252 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 253 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 256 /* Bits 23..20 : Configuration field for RAM block 5. */ 257 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 258 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 259 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 260 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 261 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 262 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 263 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 264 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 265 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 268 /* Bits 19..16 : Configuration field for RAM block 4. */ 269 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 270 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 271 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 272 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 273 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 274 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 275 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 276 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 277 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 280 /* Bits 15..12 : Configuration field for RAM block 3. */ 281 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 282 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 283 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 284 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 285 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 286 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 287 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 288 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 289 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 292 /* Bits 11..8 : Configuration field for RAM block 2. */ 293 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 294 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 295 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 296 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 297 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 298 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 299 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 300 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 301 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 304 /* Bits 7..4 : Configuration field for RAM block 1. */ 305 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 306 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 307 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 308 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 309 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 310 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 311 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 312 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 313 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 316 /* Bits 3..0 : Configuration field for RAM block 0. */ 317 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 318 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 319 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 320 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 321 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 322 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 323 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 324 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 325 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 328 /* Register: AMLI_RAMPRI_SPIS1 */ 329 /* Description: Configurable priority configuration register for SPIS1. */ 331 /* Bits 31..28 : Configuration field for RAM block 7. */ 332 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 333 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 334 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 335 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 336 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 337 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 338 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 340 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 343 /* Bits 27..24 : Configuration field for RAM block 6. */ 344 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 345 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 346 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 347 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 348 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 349 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 350 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 352 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 355 /* Bits 23..20 : Configuration field for RAM block 5. */ 356 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 357 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 358 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 359 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 360 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 361 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 362 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 364 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 367 /* Bits 19..16 : Configuration field for RAM block 4. */ 368 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 369 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 370 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 371 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 372 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 373 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 374 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 376 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 379 /* Bits 15..12 : Configuration field for RAM block 3. */ 380 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 381 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 382 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 383 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 384 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 385 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 386 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 388 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 391 /* Bits 11..8 : Configuration field for RAM block 2. */ 392 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 393 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 394 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 395 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 396 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 397 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 398 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 400 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 403 /* Bits 7..4 : Configuration field for RAM block 1. */ 404 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 405 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 406 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 407 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 408 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 409 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 410 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 412 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 415 /* Bits 3..0 : Configuration field for RAM block 0. */ 416 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 417 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 418 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 419 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 420 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 421 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 422 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 424 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 427 /* Register: AMLI_RAMPRI_RADIO */ 428 /* Description: Configurable priority configuration register for RADIO. */ 430 /* Bits 31..28 : Configuration field for RAM block 7. */ 431 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 432 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 433 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 434 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 435 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 436 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 437 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 438 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 439 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 442 /* Bits 27..24 : Configuration field for RAM block 6. */ 443 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 444 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 445 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 446 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 447 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 448 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 449 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 450 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 451 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 454 /* Bits 23..20 : Configuration field for RAM block 5. */ 455 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 456 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 457 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 458 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 459 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 460 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 461 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 462 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 463 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 466 /* Bits 19..16 : Configuration field for RAM block 4. */ 467 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 468 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 469 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 470 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 471 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 472 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 473 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 474 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 475 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 478 /* Bits 15..12 : Configuration field for RAM block 3. */ 479 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 480 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 481 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 482 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 483 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 484 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 485 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 486 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 487 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 490 /* Bits 11..8 : Configuration field for RAM block 2. */ 491 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 492 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 493 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 494 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 495 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 496 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 497 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 498 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 499 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 502 /* Bits 7..4 : Configuration field for RAM block 1. */ 503 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 504 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 505 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 506 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 507 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 508 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 509 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 510 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 511 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 514 /* Bits 3..0 : Configuration field for RAM block 0. */ 515 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 516 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 517 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 518 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 519 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 520 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 521 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 522 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 523 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 526 /* Register: AMLI_RAMPRI_ECB */ 527 /* Description: Configurable priority configuration register for ECB. */ 529 /* Bits 31..28 : Configuration field for RAM block 7. */ 530 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 531 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 532 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 533 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 534 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 535 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 536 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 537 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 538 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 539 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 541 /* Bits 27..24 : Configuration field for RAM block 6. */ 542 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 543 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 544 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 545 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 546 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 547 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 548 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 549 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 550 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 551 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 553 /* Bits 23..20 : Configuration field for RAM block 5. */ 554 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 555 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 556 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 557 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 558 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 559 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 560 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 561 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 562 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 563 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 565 /* Bits 19..16 : Configuration field for RAM block 4. */ 566 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 567 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 568 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 569 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 570 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 571 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 572 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 573 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 574 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 575 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 577 /* Bits 15..12 : Configuration field for RAM block 3. */ 578 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 579 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 580 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 581 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 582 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 583 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 584 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 585 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 586 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 587 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 589 /* Bits 11..8 : Configuration field for RAM block 2. */ 590 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 591 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 592 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 593 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 594 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 595 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 596 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 597 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 598 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 599 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 601 /* Bits 7..4 : Configuration field for RAM block 1. */ 602 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 603 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 604 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 605 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 606 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 607 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 608 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 609 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 610 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 611 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 613 /* Bits 3..0 : Configuration field for RAM block 0. */ 614 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 615 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 616 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 617 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 618 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 619 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 620 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 621 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 622 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 623 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 625 /* Register: AMLI_RAMPRI_CCM */ 626 /* Description: Configurable priority configuration register for CCM. */ 628 /* Bits 31..28 : Configuration field for RAM block 7. */ 629 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 630 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 631 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 632 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 633 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 634 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 635 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 636 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 637 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 638 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 640 /* Bits 27..24 : Configuration field for RAM block 6. */ 641 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 642 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 643 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 644 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 645 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 646 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 647 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 648 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 649 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 650 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 652 /* Bits 23..20 : Configuration field for RAM block 5. */ 653 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 654 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 655 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 656 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 657 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 658 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 659 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 660 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 661 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 662 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 664 /* Bits 19..16 : Configuration field for RAM block 4. */ 665 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 666 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 667 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 668 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 669 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 670 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 671 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 672 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 673 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 674 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 676 /* Bits 15..12 : Configuration field for RAM block 3. */ 677 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 678 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 679 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 680 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 681 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 682 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 683 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 684 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 685 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 686 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 688 /* Bits 11..8 : Configuration field for RAM block 2. */ 689 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 690 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 691 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 692 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 693 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 694 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 695 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 696 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 697 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 698 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 700 /* Bits 7..4 : Configuration field for RAM block 1. */ 701 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 702 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 703 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 704 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 705 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 706 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 707 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 708 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 709 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 710 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 712 /* Bits 3..0 : Configuration field for RAM block 0. */ 713 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 714 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 715 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 716 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 717 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 718 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 719 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 720 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 721 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 722 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 724 /* Register: AMLI_RAMPRI_AAR */ 725 /* Description: Configurable priority configuration register for AAR. */ 727 /* Bits 31..28 : Configuration field for RAM block 7. */ 728 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ 729 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ 730 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ 731 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ 732 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ 733 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ 734 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ 735 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ 736 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ 737 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ 739 /* Bits 27..24 : Configuration field for RAM block 6. */ 740 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ 741 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ 742 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ 743 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ 744 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ 745 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ 746 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ 747 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ 748 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ 749 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ 751 /* Bits 23..20 : Configuration field for RAM block 5. */ 752 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ 753 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ 754 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ 755 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ 756 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ 757 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ 758 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ 759 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ 760 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ 761 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ 763 /* Bits 19..16 : Configuration field for RAM block 4. */ 764 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ 765 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ 766 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ 767 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ 768 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ 769 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ 770 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ 771 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ 772 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ 773 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ 775 /* Bits 15..12 : Configuration field for RAM block 3. */ 776 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ 777 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ 778 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ 779 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ 780 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ 781 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ 782 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ 783 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ 784 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ 785 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ 787 /* Bits 11..8 : Configuration field for RAM block 2. */ 788 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ 789 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ 790 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ 791 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ 792 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ 793 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ 794 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ 795 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ 796 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ 797 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ 799 /* Bits 7..4 : Configuration field for RAM block 1. */ 800 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ 801 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ 802 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ 803 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ 804 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ 805 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ 806 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ 807 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ 808 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ 809 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ 811 /* Bits 3..0 : Configuration field for RAM block 0. */ 812 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ 813 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ 814 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ 815 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ 816 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ 817 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ 818 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ 819 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ 820 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ 821 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ 823 /* Peripheral: CCM */ 824 /* Description: AES CCM Mode Encryption. */ 826 /* Register: CCM_SHORTS */ 827 /* Description: Shortcuts for the CCM. */ 829 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ 830 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ 831 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ 832 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ 833 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ 835 /* Register: CCM_INTENSET */ 836 /* Description: Interrupt enable set register. */ 838 /* Bit 2 : Enable interrupt on ERROR event. */ 839 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 840 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 841 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 842 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 843 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 845 /* Bit 1 : Enable interrupt on ENDCRYPT event. */ 846 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 847 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 848 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 849 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 850 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ 852 /* Bit 0 : Enable interrupt on ENDKSGEN event. */ 853 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 854 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 855 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 856 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 857 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ 859 /* Register: CCM_INTENCLR */ 860 /* Description: Interrupt enable clear register. */ 862 /* Bit 2 : Disable interrupt on ERROR event. */ 863 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ 864 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 865 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 866 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 867 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 869 /* Bit 1 : Disable interrupt on ENDCRYPT event. */ 870 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ 871 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ 872 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ 873 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ 874 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ 876 /* Bit 0 : Disable interrupt on ENDKSGEN event. */ 877 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ 878 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ 879 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ 880 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ 881 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ 883 /* Register: CCM_MICSTATUS */ 884 /* Description: CCM RX MIC check result. */ 886 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ 887 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ 888 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ 889 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ 890 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ 892 /* Register: CCM_ENABLE */ 893 /* Description: CCM enable. */ 895 /* Bits 1..0 : CCM enable. */ 896 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 897 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 898 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ 899 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ 901 /* Register: CCM_MODE */ 902 /* Description: Operation mode. */ 904 /* Bit 0 : CCM mode operation. */ 905 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 906 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 907 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ 908 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ 910 /* Register: CCM_POWER */ 911 /* Description: Peripheral power control. */ 913 /* Bit 0 : Peripheral power control. */ 914 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 915 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 916 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 917 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 920 /* Peripheral: CLOCK */ 921 /* Description: Clock control. */ 923 /* Register: CLOCK_INTENSET */ 924 /* Description: Interrupt enable set register. */ 926 /* Bit 4 : Enable interrupt on CTTO event. */ 927 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 928 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ 929 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 930 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 931 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ 933 /* Bit 3 : Enable interrupt on DONE event. */ 934 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ 935 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ 936 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 937 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 938 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ 940 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ 941 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 942 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 943 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 944 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 945 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 947 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ 948 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 949 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 950 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 951 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 952 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ 954 /* Register: CLOCK_INTENCLR */ 955 /* Description: Interrupt enable clear register. */ 957 /* Bit 4 : Disable interrupt on CTTO event. */ 958 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ 959 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ 960 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ 961 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ 962 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ 964 /* Bit 3 : Disable interrupt on DONE event. */ 965 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ 966 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ 967 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ 968 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ 969 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ 971 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ 972 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ 973 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ 974 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 975 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 976 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 978 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ 979 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ 980 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ 981 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ 982 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ 983 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ 985 /* Register: CLOCK_HFCLKRUN */ 986 /* Description: Task HFCLKSTART trigger status. */ 988 /* Bit 0 : Task HFCLKSTART trigger status. */ 989 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 990 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 991 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ 992 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ 994 /* Register: CLOCK_HFCLKSTAT */ 995 /* Description: High frequency clock status. */ 997 /* Bit 16 : State for the HFCLK. */ 998 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 999 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1000 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ 1001 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ 1003 /* Bit 0 : Active clock source for the HF clock. */ 1004 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1005 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1006 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ 1007 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ 1009 /* Register: CLOCK_LFCLKRUN */ 1010 /* Description: Task LFCLKSTART triggered status. */ 1012 /* Bit 0 : Task LFCLKSTART triggered status. */ 1013 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ 1014 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ 1015 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ 1016 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ 1018 /* Register: CLOCK_LFCLKSTAT */ 1019 /* Description: Low frequency clock status. */ 1021 /* Bit 16 : State for the LF clock. */ 1022 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ 1023 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ 1024 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ 1025 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ 1027 /* Bits 1..0 : Active clock source for the LF clock. */ 1028 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ 1029 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ 1030 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ 1031 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ 1032 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ 1034 /* Register: CLOCK_LFCLKSRCCOPY */ 1035 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 1037 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ 1038 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ 1039 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ 1040 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 1041 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 1042 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 1044 /* Register: CLOCK_LFCLKSRC */ 1045 /* Description: Clock source for the LFCLK clock. */ 1047 /* Bits 1..0 : Clock source. */ 1048 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ 1049 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ 1050 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ 1051 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ 1052 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ 1054 /* Register: CLOCK_CTIV */ 1055 /* Description: Calibration timer interval. */ 1057 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ 1058 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ 1059 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ 1061 /* Register: CLOCK_XTALFREQ */ 1062 /* Description: Crystal frequency. */ 1064 /* Bits 7..0 : External Xtal frequency selection. */ 1065 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 1066 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 1067 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ 1068 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ 1071 /* Peripheral: ECB */ 1072 /* Description: AES ECB Mode Encryption. */ 1074 /* Register: ECB_INTENSET */ 1075 /* Description: Interrupt enable set register. */ 1077 /* Bit 1 : Enable interrupt on ERRORECB event. */ 1078 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1079 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1080 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 1081 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 1082 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ 1084 /* Bit 0 : Enable interrupt on ENDECB event. */ 1085 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1086 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1087 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 1088 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 1089 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ 1091 /* Register: ECB_INTENCLR */ 1092 /* Description: Interrupt enable clear register. */ 1094 /* Bit 1 : Disable interrupt on ERRORECB event. */ 1095 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ 1096 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ 1097 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ 1098 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ 1099 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ 1101 /* Bit 0 : Disable interrupt on ENDECB event. */ 1102 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ 1103 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ 1104 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ 1105 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ 1106 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ 1108 /* Register: ECB_POWER */ 1109 /* Description: Peripheral power control. */ 1111 /* Bit 0 : Peripheral power control. */ 1112 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 1113 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 1114 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 1115 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 1118 /* Peripheral: FICR */ 1119 /* Description: Factory Information Configuration. */ 1121 /* Register: FICR_PPFC */ 1122 /* Description: Pre-programmed factory code present. */ 1124 /* Bits 7..0 : Pre-programmed factory code present. */ 1125 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ 1126 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ 1127 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ 1128 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ 1130 /* Register: FICR_CONFIGID */ 1131 /* Description: Configuration identifier. */ 1133 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ 1134 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ 1135 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ 1137 /* Bits 15..0 : Hardware Identification Number. */ 1138 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ 1139 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ 1141 /* Register: FICR_DEVICEADDRTYPE */ 1142 /* Description: Device address type. */ 1144 /* Bit 0 : Device address type. */ 1145 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ 1146 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ 1147 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ 1148 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ 1150 /* Register: FICR_OVERRIDEEN */ 1151 /* Description: Radio calibration override enable. */ 1153 /* Bit 3 : Override default values for BLE_1Mbit mode. */ 1154 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ 1155 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ 1156 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ 1157 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ 1159 /* Bit 0 : Override default values for NRF_1Mbit mode. */ 1160 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ 1161 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ 1162 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ 1163 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ 1165 /* Register: FICR_INFO_PART */ 1166 /* Description: Part code */ 1168 /* Bits 31..0 : Part code */ 1169 #define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */ 1170 #define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */ 1171 #define FICR_INFO_PART_PART_N51822 (0x51822UL) /*!< nRF51822 */ 1172 #define FICR_INFO_PART_PART_N51422 (0x51422UL) /*!< nRF51422 */ 1173 #define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1175 /* Register: FICR_INFO_VARIANT */ 1176 /* Description: Part variant */ 1178 /* Bits 31..0 : Part variant */ 1179 #define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */ 1180 #define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */ 1181 #define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /*!< nRF51-C (XLR3) */ 1182 #define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /*!< nRF51-D (L3) */ 1183 #define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /*!< nRF51-E (XLR3P) */ 1184 #define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1186 /* Register: FICR_INFO_PACKAGE */ 1187 /* Description: Package option */ 1189 /* Bits 31..0 : Package option */ 1190 #define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */ 1191 #define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */ 1192 #define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /*!< 48-pin QFN with 31 GPIO */ 1193 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /*!< nRF51x22 CDxx - WLCSP 56 balls */ 1194 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /*!< nRF51x22 CExx - WLCSP 62 balls */ 1195 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /*!< nRF51x22 CFxx - WLCSP 62 balls */ 1196 #define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /*!< nRF51x22 CTxx - WLCSP 62 balls */ 1197 #define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1199 /* Register: FICR_INFO_RAM */ 1200 /* Description: RAM variant */ 1202 /* Bits 31..0 : RAM variant */ 1203 #define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */ 1204 #define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */ 1205 #define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1206 #define FICR_INFO_RAM_RAM_K16 (16UL) /*!< 16 kByte RAM. */ 1207 #define FICR_INFO_RAM_RAM_K32 (32UL) /*!< 32 kByte RAM. */ 1209 /* Register: FICR_INFO_FLASH */ 1210 /* Description: Flash variant */ 1212 /* Bits 31..0 : Flash variant */ 1213 #define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */ 1214 #define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */ 1215 #define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */ 1216 #define FICR_INFO_FLASH_FLASH_K128 (128UL) /*!< 128 kByte FLASH. */ 1217 #define FICR_INFO_FLASH_FLASH_K256 (256UL) /*!< 256 kByte FLASH. */ 1220 /* Peripheral: GPIO */ 1221 /* Description: General purpose input and output. */ 1223 /* Register: GPIO_OUT */ 1224 /* Description: Write GPIO port. */ 1226 /* Bit 31 : Pin 31. */ 1227 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1228 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1229 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ 1230 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ 1232 /* Bit 30 : Pin 30. */ 1233 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1234 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1235 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ 1236 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ 1238 /* Bit 29 : Pin 29. */ 1239 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1240 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1241 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ 1242 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ 1244 /* Bit 28 : Pin 28. */ 1245 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1246 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1247 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ 1248 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ 1250 /* Bit 27 : Pin 27. */ 1251 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1252 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1253 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ 1254 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ 1256 /* Bit 26 : Pin 26. */ 1257 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1258 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1259 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ 1260 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ 1262 /* Bit 25 : Pin 25. */ 1263 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1264 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1265 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ 1266 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ 1268 /* Bit 24 : Pin 24. */ 1269 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1270 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1271 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ 1272 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ 1274 /* Bit 23 : Pin 23. */ 1275 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1276 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1277 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ 1278 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ 1280 /* Bit 22 : Pin 22. */ 1281 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1282 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1283 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ 1284 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ 1286 /* Bit 21 : Pin 21. */ 1287 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1288 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1289 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ 1290 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ 1292 /* Bit 20 : Pin 20. */ 1293 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1294 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1295 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ 1296 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ 1298 /* Bit 19 : Pin 19. */ 1299 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1300 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1301 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ 1302 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ 1304 /* Bit 18 : Pin 18. */ 1305 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1306 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1307 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ 1308 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ 1310 /* Bit 17 : Pin 17. */ 1311 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1312 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1313 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ 1314 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ 1316 /* Bit 16 : Pin 16. */ 1317 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1318 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1319 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ 1320 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ 1322 /* Bit 15 : Pin 15. */ 1323 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1324 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1325 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ 1326 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ 1328 /* Bit 14 : Pin 14. */ 1329 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1330 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1331 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ 1332 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ 1334 /* Bit 13 : Pin 13. */ 1335 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1336 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1337 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ 1338 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ 1340 /* Bit 12 : Pin 12. */ 1341 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1342 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1343 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ 1344 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ 1346 /* Bit 11 : Pin 11. */ 1347 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1348 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1349 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ 1350 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ 1352 /* Bit 10 : Pin 10. */ 1353 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1354 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1355 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ 1356 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ 1358 /* Bit 9 : Pin 9. */ 1359 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1360 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1361 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ 1362 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ 1364 /* Bit 8 : Pin 8. */ 1365 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1366 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1367 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ 1368 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ 1370 /* Bit 7 : Pin 7. */ 1371 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1372 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1373 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ 1374 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ 1376 /* Bit 6 : Pin 6. */ 1377 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1378 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1379 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ 1380 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ 1382 /* Bit 5 : Pin 5. */ 1383 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1384 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1385 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ 1386 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ 1388 /* Bit 4 : Pin 4. */ 1389 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1390 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1391 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ 1392 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ 1394 /* Bit 3 : Pin 3. */ 1395 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1396 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1397 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ 1398 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ 1400 /* Bit 2 : Pin 2. */ 1401 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1402 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1403 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ 1404 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ 1406 /* Bit 1 : Pin 1. */ 1407 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1408 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1409 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ 1410 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ 1412 /* Bit 0 : Pin 0. */ 1413 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1414 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1415 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ 1416 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ 1418 /* Register: GPIO_OUTSET */ 1419 /* Description: Set individual bits in GPIO port. */ 1421 /* Bit 31 : Pin 31. */ 1422 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1423 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1424 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ 1425 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ 1426 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ 1428 /* Bit 30 : Pin 30. */ 1429 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1430 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1431 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ 1432 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ 1433 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ 1435 /* Bit 29 : Pin 29. */ 1436 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1437 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1438 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ 1439 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ 1440 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ 1442 /* Bit 28 : Pin 28. */ 1443 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1444 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1445 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ 1446 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ 1447 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ 1449 /* Bit 27 : Pin 27. */ 1450 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1451 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1452 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ 1453 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ 1454 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ 1456 /* Bit 26 : Pin 26. */ 1457 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1458 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1459 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ 1460 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ 1461 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ 1463 /* Bit 25 : Pin 25. */ 1464 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1465 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1466 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ 1467 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ 1468 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ 1470 /* Bit 24 : Pin 24. */ 1471 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1472 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1473 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ 1474 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ 1475 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ 1477 /* Bit 23 : Pin 23. */ 1478 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1479 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1480 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ 1481 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ 1482 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ 1484 /* Bit 22 : Pin 22. */ 1485 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1486 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1487 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ 1488 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ 1489 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ 1491 /* Bit 21 : Pin 21. */ 1492 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1493 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1494 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ 1495 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ 1496 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ 1498 /* Bit 20 : Pin 20. */ 1499 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1500 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1501 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ 1502 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ 1503 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ 1505 /* Bit 19 : Pin 19. */ 1506 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1507 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1508 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ 1509 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ 1510 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ 1512 /* Bit 18 : Pin 18. */ 1513 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1514 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1515 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ 1516 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ 1517 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ 1519 /* Bit 17 : Pin 17. */ 1520 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1521 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1522 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ 1523 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ 1524 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ 1526 /* Bit 16 : Pin 16. */ 1527 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1528 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1529 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ 1530 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ 1531 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ 1533 /* Bit 15 : Pin 15. */ 1534 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1535 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1536 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ 1537 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ 1538 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ 1540 /* Bit 14 : Pin 14. */ 1541 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1542 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1543 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ 1544 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ 1545 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ 1547 /* Bit 13 : Pin 13. */ 1548 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1549 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1550 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ 1551 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ 1552 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ 1554 /* Bit 12 : Pin 12. */ 1555 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1556 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1557 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ 1558 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ 1559 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ 1561 /* Bit 11 : Pin 11. */ 1562 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1563 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1564 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ 1565 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ 1566 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ 1568 /* Bit 10 : Pin 10. */ 1569 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1570 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1571 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ 1572 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ 1573 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ 1575 /* Bit 9 : Pin 9. */ 1576 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1577 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1578 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ 1579 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ 1580 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ 1582 /* Bit 8 : Pin 8. */ 1583 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1584 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1585 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ 1586 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ 1587 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ 1589 /* Bit 7 : Pin 7. */ 1590 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1591 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1592 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ 1593 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ 1594 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ 1596 /* Bit 6 : Pin 6. */ 1597 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1598 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1599 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ 1600 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ 1601 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ 1603 /* Bit 5 : Pin 5. */ 1604 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1605 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1606 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ 1607 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ 1608 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ 1610 /* Bit 4 : Pin 4. */ 1611 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1612 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1613 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ 1614 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ 1615 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ 1617 /* Bit 3 : Pin 3. */ 1618 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1619 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1620 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ 1621 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ 1622 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ 1624 /* Bit 2 : Pin 2. */ 1625 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1626 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1627 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ 1628 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ 1629 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ 1631 /* Bit 1 : Pin 1. */ 1632 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1633 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1634 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ 1635 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ 1636 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ 1638 /* Bit 0 : Pin 0. */ 1639 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1640 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1641 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ 1642 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ 1643 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ 1645 /* Register: GPIO_OUTCLR */ 1646 /* Description: Clear individual bits in GPIO port. */ 1648 /* Bit 31 : Pin 31. */ 1649 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1650 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1651 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ 1652 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ 1653 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ 1655 /* Bit 30 : Pin 30. */ 1656 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1657 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1658 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ 1659 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ 1660 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ 1662 /* Bit 29 : Pin 29. */ 1663 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1664 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1665 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ 1666 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ 1667 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ 1669 /* Bit 28 : Pin 28. */ 1670 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1671 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1672 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ 1673 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ 1674 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ 1676 /* Bit 27 : Pin 27. */ 1677 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1678 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1679 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ 1680 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ 1681 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ 1683 /* Bit 26 : Pin 26. */ 1684 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1685 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1686 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ 1687 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ 1688 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ 1690 /* Bit 25 : Pin 25. */ 1691 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1692 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1693 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ 1694 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ 1695 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ 1697 /* Bit 24 : Pin 24. */ 1698 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1699 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1700 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ 1701 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ 1702 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ 1704 /* Bit 23 : Pin 23. */ 1705 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1706 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1707 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ 1708 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ 1709 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ 1711 /* Bit 22 : Pin 22. */ 1712 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1713 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1714 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ 1715 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ 1716 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ 1718 /* Bit 21 : Pin 21. */ 1719 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1720 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1721 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ 1722 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ 1723 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ 1725 /* Bit 20 : Pin 20. */ 1726 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1727 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1728 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ 1729 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ 1730 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ 1732 /* Bit 19 : Pin 19. */ 1733 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1734 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1735 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ 1736 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ 1737 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ 1739 /* Bit 18 : Pin 18. */ 1740 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1741 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1742 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ 1743 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ 1744 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ 1746 /* Bit 17 : Pin 17. */ 1747 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1748 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1749 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ 1750 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ 1751 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ 1753 /* Bit 16 : Pin 16. */ 1754 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1755 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1756 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ 1757 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ 1758 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ 1760 /* Bit 15 : Pin 15. */ 1761 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1762 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1763 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ 1764 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ 1765 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ 1767 /* Bit 14 : Pin 14. */ 1768 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1769 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1770 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ 1771 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ 1772 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ 1774 /* Bit 13 : Pin 13. */ 1775 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1776 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1777 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ 1778 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ 1779 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ 1781 /* Bit 12 : Pin 12. */ 1782 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1783 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1784 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ 1785 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ 1786 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ 1788 /* Bit 11 : Pin 11. */ 1789 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1790 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1791 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ 1792 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ 1793 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ 1795 /* Bit 10 : Pin 10. */ 1796 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 1797 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 1798 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ 1799 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ 1800 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ 1802 /* Bit 9 : Pin 9. */ 1803 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 1804 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 1805 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ 1806 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ 1807 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ 1809 /* Bit 8 : Pin 8. */ 1810 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 1811 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 1812 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ 1813 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ 1814 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ 1816 /* Bit 7 : Pin 7. */ 1817 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 1818 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 1819 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ 1820 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ 1821 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ 1823 /* Bit 6 : Pin 6. */ 1824 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 1825 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 1826 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ 1827 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ 1828 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ 1830 /* Bit 5 : Pin 5. */ 1831 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 1832 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 1833 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ 1834 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ 1835 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ 1837 /* Bit 4 : Pin 4. */ 1838 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 1839 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 1840 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ 1841 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ 1842 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ 1844 /* Bit 3 : Pin 3. */ 1845 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 1846 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 1847 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ 1848 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ 1849 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ 1851 /* Bit 2 : Pin 2. */ 1852 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 1853 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 1854 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ 1855 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ 1856 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ 1858 /* Bit 1 : Pin 1. */ 1859 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 1860 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 1861 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ 1862 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ 1863 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ 1865 /* Bit 0 : Pin 0. */ 1866 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 1867 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 1868 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ 1869 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ 1870 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ 1872 /* Register: GPIO_IN */ 1873 /* Description: Read GPIO port. */ 1875 /* Bit 31 : Pin 31. */ 1876 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 1877 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 1878 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ 1879 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ 1881 /* Bit 30 : Pin 30. */ 1882 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 1883 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 1884 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ 1885 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ 1887 /* Bit 29 : Pin 29. */ 1888 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 1889 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 1890 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ 1891 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ 1893 /* Bit 28 : Pin 28. */ 1894 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 1895 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 1896 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ 1897 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ 1899 /* Bit 27 : Pin 27. */ 1900 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 1901 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 1902 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ 1903 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ 1905 /* Bit 26 : Pin 26. */ 1906 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 1907 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 1908 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ 1909 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ 1911 /* Bit 25 : Pin 25. */ 1912 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 1913 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 1914 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ 1915 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ 1917 /* Bit 24 : Pin 24. */ 1918 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 1919 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 1920 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ 1921 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ 1923 /* Bit 23 : Pin 23. */ 1924 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 1925 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 1926 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ 1927 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ 1929 /* Bit 22 : Pin 22. */ 1930 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 1931 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 1932 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ 1933 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ 1935 /* Bit 21 : Pin 21. */ 1936 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 1937 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 1938 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ 1939 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ 1941 /* Bit 20 : Pin 20. */ 1942 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 1943 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 1944 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ 1945 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ 1947 /* Bit 19 : Pin 19. */ 1948 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 1949 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 1950 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ 1951 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ 1953 /* Bit 18 : Pin 18. */ 1954 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 1955 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 1956 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ 1957 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ 1959 /* Bit 17 : Pin 17. */ 1960 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 1961 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 1962 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ 1963 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ 1965 /* Bit 16 : Pin 16. */ 1966 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 1967 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 1968 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ 1969 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ 1971 /* Bit 15 : Pin 15. */ 1972 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 1973 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 1974 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ 1975 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ 1977 /* Bit 14 : Pin 14. */ 1978 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 1979 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 1980 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ 1981 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ 1983 /* Bit 13 : Pin 13. */ 1984 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 1985 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 1986 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ 1987 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ 1989 /* Bit 12 : Pin 12. */ 1990 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 1991 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 1992 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ 1993 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ 1995 /* Bit 11 : Pin 11. */ 1996 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 1997 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 1998 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ 1999 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ 2001 /* Bit 10 : Pin 10. */ 2002 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2003 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2004 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ 2005 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ 2007 /* Bit 9 : Pin 9. */ 2008 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2009 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2010 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ 2011 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ 2013 /* Bit 8 : Pin 8. */ 2014 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2015 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2016 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ 2017 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ 2019 /* Bit 7 : Pin 7. */ 2020 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2021 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2022 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ 2023 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ 2025 /* Bit 6 : Pin 6. */ 2026 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2027 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2028 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ 2029 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ 2031 /* Bit 5 : Pin 5. */ 2032 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2033 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2034 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ 2035 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ 2037 /* Bit 4 : Pin 4. */ 2038 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2039 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2040 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ 2041 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ 2043 /* Bit 3 : Pin 3. */ 2044 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2045 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2046 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ 2047 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ 2049 /* Bit 2 : Pin 2. */ 2050 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2051 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2052 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ 2053 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ 2055 /* Bit 1 : Pin 1. */ 2056 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2057 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2058 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ 2059 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ 2061 /* Bit 0 : Pin 0. */ 2062 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2063 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2064 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ 2065 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ 2067 /* Register: GPIO_DIR */ 2068 /* Description: Direction of GPIO pins. */ 2070 /* Bit 31 : Pin 31. */ 2071 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2072 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2073 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ 2074 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ 2076 /* Bit 30 : Pin 30. */ 2077 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2078 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2079 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ 2080 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ 2082 /* Bit 29 : Pin 29. */ 2083 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2084 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2085 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ 2086 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ 2088 /* Bit 28 : Pin 28. */ 2089 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2090 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2091 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ 2092 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ 2094 /* Bit 27 : Pin 27. */ 2095 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2096 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2097 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ 2098 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ 2100 /* Bit 26 : Pin 26. */ 2101 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2102 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2103 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ 2104 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ 2106 /* Bit 25 : Pin 25. */ 2107 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2108 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2109 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ 2110 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ 2112 /* Bit 24 : Pin 24. */ 2113 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2114 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2115 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ 2116 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ 2118 /* Bit 23 : Pin 23. */ 2119 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2120 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2121 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ 2122 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ 2124 /* Bit 22 : Pin 22. */ 2125 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2126 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2127 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ 2128 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ 2130 /* Bit 21 : Pin 21. */ 2131 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2132 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2133 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ 2134 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ 2136 /* Bit 20 : Pin 20. */ 2137 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2138 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2139 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ 2140 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ 2142 /* Bit 19 : Pin 19. */ 2143 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2144 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2145 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ 2146 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ 2148 /* Bit 18 : Pin 18. */ 2149 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2150 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2151 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ 2152 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ 2154 /* Bit 17 : Pin 17. */ 2155 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2156 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2157 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ 2158 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ 2160 /* Bit 16 : Pin 16. */ 2161 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2162 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2163 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ 2164 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ 2166 /* Bit 15 : Pin 15. */ 2167 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2168 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2169 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ 2170 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ 2172 /* Bit 14 : Pin 14. */ 2173 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2174 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2175 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ 2176 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ 2178 /* Bit 13 : Pin 13. */ 2179 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2180 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2181 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ 2182 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ 2184 /* Bit 12 : Pin 12. */ 2185 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2186 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2187 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ 2188 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ 2190 /* Bit 11 : Pin 11. */ 2191 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2192 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2193 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ 2194 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ 2196 /* Bit 10 : Pin 10. */ 2197 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2198 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2199 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ 2200 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ 2202 /* Bit 9 : Pin 9. */ 2203 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2204 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2205 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ 2206 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ 2208 /* Bit 8 : Pin 8. */ 2209 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2210 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2211 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ 2212 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ 2214 /* Bit 7 : Pin 7. */ 2215 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2216 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2217 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ 2218 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ 2220 /* Bit 6 : Pin 6. */ 2221 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2222 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2223 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ 2224 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ 2226 /* Bit 5 : Pin 5. */ 2227 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2228 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2229 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ 2230 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ 2232 /* Bit 4 : Pin 4. */ 2233 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2234 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2235 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ 2236 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ 2238 /* Bit 3 : Pin 3. */ 2239 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2240 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2241 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ 2242 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ 2244 /* Bit 2 : Pin 2. */ 2245 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2246 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2247 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ 2248 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ 2250 /* Bit 1 : Pin 1. */ 2251 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2252 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2253 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ 2254 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ 2256 /* Bit 0 : Pin 0. */ 2257 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2258 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2259 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ 2260 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ 2262 /* Register: GPIO_DIRSET */ 2263 /* Description: DIR set register. */ 2265 /* Bit 31 : Set as output pin 31. */ 2266 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2267 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2268 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ 2269 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ 2270 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ 2272 /* Bit 30 : Set as output pin 30. */ 2273 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2274 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2275 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ 2276 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ 2277 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ 2279 /* Bit 29 : Set as output pin 29. */ 2280 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2281 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2282 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ 2283 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ 2284 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ 2286 /* Bit 28 : Set as output pin 28. */ 2287 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2288 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2289 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ 2290 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ 2291 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ 2293 /* Bit 27 : Set as output pin 27. */ 2294 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2295 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2296 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ 2297 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ 2298 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ 2300 /* Bit 26 : Set as output pin 26. */ 2301 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2302 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2303 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ 2304 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ 2305 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ 2307 /* Bit 25 : Set as output pin 25. */ 2308 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2309 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2310 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ 2311 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ 2312 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ 2314 /* Bit 24 : Set as output pin 24. */ 2315 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2316 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2317 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ 2318 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ 2319 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ 2321 /* Bit 23 : Set as output pin 23. */ 2322 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2323 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2324 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ 2325 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ 2326 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ 2328 /* Bit 22 : Set as output pin 22. */ 2329 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2330 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2331 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ 2332 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ 2333 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ 2335 /* Bit 21 : Set as output pin 21. */ 2336 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2337 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2338 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ 2339 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ 2340 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ 2342 /* Bit 20 : Set as output pin 20. */ 2343 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2344 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2345 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ 2346 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ 2347 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ 2349 /* Bit 19 : Set as output pin 19. */ 2350 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2351 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2352 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ 2353 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ 2354 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ 2356 /* Bit 18 : Set as output pin 18. */ 2357 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2358 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2359 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ 2360 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ 2361 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ 2363 /* Bit 17 : Set as output pin 17. */ 2364 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2365 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2366 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ 2367 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ 2368 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ 2370 /* Bit 16 : Set as output pin 16. */ 2371 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2372 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2373 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ 2374 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ 2375 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ 2377 /* Bit 15 : Set as output pin 15. */ 2378 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2379 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2380 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ 2381 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ 2382 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ 2384 /* Bit 14 : Set as output pin 14. */ 2385 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2386 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2387 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ 2388 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ 2389 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ 2391 /* Bit 13 : Set as output pin 13. */ 2392 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2393 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2394 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ 2395 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ 2396 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ 2398 /* Bit 12 : Set as output pin 12. */ 2399 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2400 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2401 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ 2402 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ 2403 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ 2405 /* Bit 11 : Set as output pin 11. */ 2406 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2407 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2408 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ 2409 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ 2410 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ 2412 /* Bit 10 : Set as output pin 10. */ 2413 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2414 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2415 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ 2416 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ 2417 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ 2419 /* Bit 9 : Set as output pin 9. */ 2420 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2421 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2422 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ 2423 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ 2424 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ 2426 /* Bit 8 : Set as output pin 8. */ 2427 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2428 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2429 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ 2430 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ 2431 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ 2433 /* Bit 7 : Set as output pin 7. */ 2434 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2435 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2436 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ 2437 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ 2438 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ 2440 /* Bit 6 : Set as output pin 6. */ 2441 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2442 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2443 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ 2444 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ 2445 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ 2447 /* Bit 5 : Set as output pin 5. */ 2448 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2449 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2450 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ 2451 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ 2452 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ 2454 /* Bit 4 : Set as output pin 4. */ 2455 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2456 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2457 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ 2458 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ 2459 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ 2461 /* Bit 3 : Set as output pin 3. */ 2462 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2463 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2464 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ 2465 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ 2466 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ 2468 /* Bit 2 : Set as output pin 2. */ 2469 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2470 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2471 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ 2472 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ 2473 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ 2475 /* Bit 1 : Set as output pin 1. */ 2476 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2477 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2478 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ 2479 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ 2480 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ 2482 /* Bit 0 : Set as output pin 0. */ 2483 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2484 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2485 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ 2486 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ 2487 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ 2489 /* Register: GPIO_DIRCLR */ 2490 /* Description: DIR clear register. */ 2492 /* Bit 31 : Set as input pin 31. */ 2493 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ 2494 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ 2495 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ 2496 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ 2497 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ 2499 /* Bit 30 : Set as input pin 30. */ 2500 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ 2501 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ 2502 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ 2503 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ 2504 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ 2506 /* Bit 29 : Set as input pin 29. */ 2507 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ 2508 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ 2509 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ 2510 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ 2511 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ 2513 /* Bit 28 : Set as input pin 28. */ 2514 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ 2515 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ 2516 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ 2517 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ 2518 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ 2520 /* Bit 27 : Set as input pin 27. */ 2521 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ 2522 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ 2523 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ 2524 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ 2525 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ 2527 /* Bit 26 : Set as input pin 26. */ 2528 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ 2529 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ 2530 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ 2531 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ 2532 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ 2534 /* Bit 25 : Set as input pin 25. */ 2535 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ 2536 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ 2537 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ 2538 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ 2539 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ 2541 /* Bit 24 : Set as input pin 24. */ 2542 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ 2543 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ 2544 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ 2545 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ 2546 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ 2548 /* Bit 23 : Set as input pin 23. */ 2549 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ 2550 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ 2551 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ 2552 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ 2553 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ 2555 /* Bit 22 : Set as input pin 22. */ 2556 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ 2557 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ 2558 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ 2559 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ 2560 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ 2562 /* Bit 21 : Set as input pin 21. */ 2563 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ 2564 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ 2565 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ 2566 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ 2567 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ 2569 /* Bit 20 : Set as input pin 20. */ 2570 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ 2571 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ 2572 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ 2573 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ 2574 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ 2576 /* Bit 19 : Set as input pin 19. */ 2577 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ 2578 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ 2579 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ 2580 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ 2581 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ 2583 /* Bit 18 : Set as input pin 18. */ 2584 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ 2585 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ 2586 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ 2587 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ 2588 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ 2590 /* Bit 17 : Set as input pin 17. */ 2591 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ 2592 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ 2593 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ 2594 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ 2595 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ 2597 /* Bit 16 : Set as input pin 16. */ 2598 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ 2599 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ 2600 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ 2601 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ 2602 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ 2604 /* Bit 15 : Set as input pin 15. */ 2605 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ 2606 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ 2607 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ 2608 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ 2609 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ 2611 /* Bit 14 : Set as input pin 14. */ 2612 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ 2613 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ 2614 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ 2615 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ 2616 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ 2618 /* Bit 13 : Set as input pin 13. */ 2619 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ 2620 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ 2621 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ 2622 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ 2623 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ 2625 /* Bit 12 : Set as input pin 12. */ 2626 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ 2627 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ 2628 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ 2629 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ 2630 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ 2632 /* Bit 11 : Set as input pin 11. */ 2633 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ 2634 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ 2635 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ 2636 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ 2637 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ 2639 /* Bit 10 : Set as input pin 10. */ 2640 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ 2641 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ 2642 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ 2643 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ 2644 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ 2646 /* Bit 9 : Set as input pin 9. */ 2647 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ 2648 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ 2649 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ 2650 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ 2651 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ 2653 /* Bit 8 : Set as input pin 8. */ 2654 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ 2655 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ 2656 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ 2657 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ 2658 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ 2660 /* Bit 7 : Set as input pin 7. */ 2661 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ 2662 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ 2663 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ 2664 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ 2665 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ 2667 /* Bit 6 : Set as input pin 6. */ 2668 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ 2669 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ 2670 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ 2671 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ 2672 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ 2674 /* Bit 5 : Set as input pin 5. */ 2675 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ 2676 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ 2677 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ 2678 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ 2679 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ 2681 /* Bit 4 : Set as input pin 4. */ 2682 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ 2683 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ 2684 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ 2685 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ 2686 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ 2688 /* Bit 3 : Set as input pin 3. */ 2689 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ 2690 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ 2691 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ 2692 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ 2693 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ 2695 /* Bit 2 : Set as input pin 2. */ 2696 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ 2697 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ 2698 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ 2699 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ 2700 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ 2702 /* Bit 1 : Set as input pin 1. */ 2703 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ 2704 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ 2705 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ 2706 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ 2707 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ 2709 /* Bit 0 : Set as input pin 0. */ 2710 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ 2711 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ 2712 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ 2713 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ 2714 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ 2716 /* Register: GPIO_PIN_CNF */ 2717 /* Description: Configuration of GPIO pins. */ 2719 /* Bits 17..16 : Pin sensing mechanism. */ 2720 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ 2721 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ 2722 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ 2723 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ 2724 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ 2726 /* Bits 10..8 : Drive configuration. */ 2727 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ 2728 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ 2729 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ 2730 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ 2731 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ 2732 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ 2733 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ 2734 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ 2735 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ 2736 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ 2738 /* Bits 3..2 : Pull-up or -down configuration. */ 2739 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ 2740 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ 2741 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ 2742 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ 2743 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ 2745 /* Bit 1 : Connect or disconnect input path. */ 2746 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ 2747 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ 2748 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ 2749 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ 2751 /* Bit 0 : Pin direction. */ 2752 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ 2753 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ 2754 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ 2755 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ 2758 /* Peripheral: GPIOTE */ 2759 /* Description: GPIO tasks and events. */ 2761 /* Register: GPIOTE_INTENSET */ 2762 /* Description: Interrupt enable set register. */ 2764 /* Bit 31 : Enable interrupt on PORT event. */ 2765 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ 2766 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ 2767 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 2768 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 2769 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ 2771 /* Bit 3 : Enable interrupt on IN[3] event. */ 2772 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ 2773 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ 2774 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 2775 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 2776 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ 2778 /* Bit 2 : Enable interrupt on IN[2] event. */ 2779 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ 2780 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ 2781 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 2782 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 2783 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ 2785 /* Bit 1 : Enable interrupt on IN[1] event. */ 2786 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ 2787 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ 2788 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 2789 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 2790 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ 2792 /* Bit 0 : Enable interrupt on IN[0] event. */ 2793 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ 2794 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ 2795 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 2796 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 2797 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ 2799 /* Register: GPIOTE_INTENCLR */ 2800 /* Description: Interrupt enable clear register. */ 2802 /* Bit 31 : Disable interrupt on PORT event. */ 2803 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ 2804 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ 2805 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ 2806 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ 2807 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ 2809 /* Bit 3 : Disable interrupt on IN[3] event. */ 2810 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ 2811 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ 2812 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ 2813 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ 2814 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ 2816 /* Bit 2 : Disable interrupt on IN[2] event. */ 2817 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ 2818 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ 2819 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ 2820 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ 2821 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ 2823 /* Bit 1 : Disable interrupt on IN[1] event. */ 2824 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ 2825 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ 2826 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ 2827 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ 2828 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ 2830 /* Bit 0 : Disable interrupt on IN[0] event. */ 2831 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ 2832 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ 2833 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ 2834 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ 2835 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ 2837 /* Register: GPIOTE_CONFIG */ 2838 /* Description: Channel configuration registers. */ 2840 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ 2841 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ 2842 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ 2843 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ 2844 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ 2846 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ 2847 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ 2848 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ 2849 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ 2850 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ 2851 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ 2853 /* Bits 12..8 : Pin select. */ 2854 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ 2855 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ 2857 /* Bits 1..0 : Mode */ 2858 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ 2859 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ 2860 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ 2861 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ 2862 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ 2864 /* Register: GPIOTE_POWER */ 2865 /* Description: Peripheral power control. */ 2867 /* Bit 0 : Peripheral power control. */ 2868 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 2869 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 2870 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 2871 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 2874 /* Peripheral: LPCOMP */ 2875 /* Description: Low power comparator. */ 2877 /* Register: LPCOMP_SHORTS */ 2878 /* Description: Shortcuts for the LPCOMP. */ 2880 /* Bit 4 : Shortcut between CROSS event and STOP task. */ 2881 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ 2882 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ 2883 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2884 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2886 /* Bit 3 : Shortcut between UP event and STOP task. */ 2887 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ 2888 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ 2889 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2890 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2892 /* Bit 2 : Shortcut between DOWN event and STOP task. */ 2893 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ 2894 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ 2895 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2896 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2898 /* Bit 1 : Shortcut between RADY event and STOP task. */ 2899 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ 2900 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ 2901 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 2902 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 2904 /* Bit 0 : Shortcut between READY event and SAMPLE task. */ 2905 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ 2906 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ 2907 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ 2908 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ 2910 /* Register: LPCOMP_INTENSET */ 2911 /* Description: Interrupt enable set register. */ 2913 /* Bit 3 : Enable interrupt on CROSS event. */ 2914 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 2915 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ 2916 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 2917 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 2918 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ 2920 /* Bit 2 : Enable interrupt on UP event. */ 2921 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ 2922 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ 2923 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ 2924 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ 2925 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ 2927 /* Bit 1 : Enable interrupt on DOWN event. */ 2928 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 2929 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ 2930 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 2931 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 2932 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ 2934 /* Bit 0 : Enable interrupt on READY event. */ 2935 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 2936 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 2937 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 2938 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 2939 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 2941 /* Register: LPCOMP_INTENCLR */ 2942 /* Description: Interrupt enable clear register. */ 2944 /* Bit 3 : Disable interrupt on CROSS event. */ 2945 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ 2946 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ 2947 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ 2948 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ 2949 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ 2951 /* Bit 2 : Disable interrupt on UP event. */ 2952 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ 2953 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ 2954 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ 2955 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ 2956 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ 2958 /* Bit 1 : Disable interrupt on DOWN event. */ 2959 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ 2960 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ 2961 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ 2962 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ 2963 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ 2965 /* Bit 0 : Disable interrupt on READY event. */ 2966 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 2967 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 2968 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 2969 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 2970 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 2972 /* Register: LPCOMP_RESULT */ 2973 /* Description: Result of last compare. */ 2975 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */ 2976 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ 2977 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ 2978 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ 2979 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ 2981 /* Register: LPCOMP_ENABLE */ 2982 /* Description: Enable the LPCOMP. */ 2984 /* Bits 1..0 : Enable or disable LPCOMP. */ 2985 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 2986 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 2987 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ 2988 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ 2990 /* Register: LPCOMP_PSEL */ 2991 /* Description: Input pin select. */ 2993 /* Bits 2..0 : Analog input pin select. */ 2994 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ 2995 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ 2996 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ 2997 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ 2998 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ 2999 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ 3000 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ 3001 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ 3002 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ 3003 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ 3005 /* Register: LPCOMP_REFSEL */ 3006 /* Description: Reference select. */ 3008 /* Bits 2..0 : Reference select. */ 3009 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ 3010 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ 3011 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ 3012 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ 3013 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ 3014 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ 3015 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ 3016 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ 3017 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ 3018 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ 3020 /* Register: LPCOMP_EXTREFSEL */ 3021 /* Description: External reference select. */ 3023 /* Bit 0 : External analog reference pin selection. */ 3024 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ 3025 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ 3026 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ 3027 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ 3029 /* Register: LPCOMP_ANADETECT */ 3030 /* Description: Analog detect configuration. */ 3032 /* Bits 1..0 : Analog detect configuration. */ 3033 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ 3034 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ 3035 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ 3036 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ 3037 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ 3039 /* Register: LPCOMP_POWER */ 3040 /* Description: Peripheral power control. */ 3042 /* Bit 0 : Peripheral power control. */ 3043 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 3044 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 3045 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 3046 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 3049 /* Peripheral: MPU */ 3050 /* Description: Memory Protection Unit. */ 3052 /* Register: MPU_PERR0 */ 3053 /* Description: Configuration of peripherals in mpu regions. */ 3055 /* Bit 31 : PPI region configuration. */ 3056 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ 3057 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ 3058 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3059 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3061 /* Bit 30 : NVMC region configuration. */ 3062 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ 3063 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ 3064 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3065 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3067 /* Bit 19 : LPCOMP region configuration. */ 3068 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ 3069 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 3070 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3071 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3073 /* Bit 18 : QDEC region configuration. */ 3074 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ 3075 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ 3076 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3077 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3079 /* Bit 17 : RTC1 region configuration. */ 3080 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ 3081 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ 3082 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3083 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3085 /* Bit 16 : WDT region configuration. */ 3086 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ 3087 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ 3088 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3089 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3091 /* Bit 15 : CCM and AAR region configuration. */ 3092 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ 3093 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ 3094 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3095 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3097 /* Bit 14 : ECB region configuration. */ 3098 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ 3099 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ 3100 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3101 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3103 /* Bit 13 : RNG region configuration. */ 3104 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ 3105 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ 3106 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3107 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3109 /* Bit 12 : TEMP region configuration. */ 3110 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ 3111 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ 3112 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3113 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3115 /* Bit 11 : RTC0 region configuration. */ 3116 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ 3117 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ 3118 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3119 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3121 /* Bit 10 : TIMER2 region configuration. */ 3122 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ 3123 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ 3124 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3125 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3127 /* Bit 9 : TIMER1 region configuration. */ 3128 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ 3129 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ 3130 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3131 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3133 /* Bit 8 : TIMER0 region configuration. */ 3134 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ 3135 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ 3136 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3137 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3139 /* Bit 7 : ADC region configuration. */ 3140 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ 3141 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ 3142 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3143 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3145 /* Bit 6 : GPIOTE region configuration. */ 3146 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ 3147 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ 3148 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3149 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3151 /* Bit 4 : SPI1 and TWI1 region configuration. */ 3152 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ 3153 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ 3154 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3155 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3157 /* Bit 3 : SPI0 and TWI0 region configuration. */ 3158 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ 3159 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ 3160 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3161 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3163 /* Bit 2 : UART0 region configuration. */ 3164 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ 3165 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ 3166 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3167 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3169 /* Bit 1 : RADIO region configuration. */ 3170 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ 3171 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ 3172 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3173 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3175 /* Bit 0 : POWER_CLOCK region configuration. */ 3176 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ 3177 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ 3178 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ 3179 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ 3181 /* Register: MPU_PROTENSET0 */ 3182 /* Description: Erase and write protection bit enable set register. */ 3184 /* Bit 31 : Protection enable for region 31. */ 3185 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ 3186 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ 3187 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ 3188 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ 3189 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ 3191 /* Bit 30 : Protection enable for region 30. */ 3192 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ 3193 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ 3194 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ 3195 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ 3196 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ 3198 /* Bit 29 : Protection enable for region 29. */ 3199 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ 3200 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ 3201 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ 3202 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ 3203 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ 3205 /* Bit 28 : Protection enable for region 28. */ 3206 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ 3207 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ 3208 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ 3209 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ 3210 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ 3212 /* Bit 27 : Protection enable for region 27. */ 3213 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ 3214 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ 3215 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ 3216 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ 3217 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ 3219 /* Bit 26 : Protection enable for region 26. */ 3220 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ 3221 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ 3222 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ 3223 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ 3224 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ 3226 /* Bit 25 : Protection enable for region 25. */ 3227 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ 3228 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ 3229 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ 3230 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ 3231 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ 3233 /* Bit 24 : Protection enable for region 24. */ 3234 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ 3235 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ 3236 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ 3237 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ 3238 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ 3240 /* Bit 23 : Protection enable for region 23. */ 3241 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ 3242 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ 3243 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ 3244 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ 3245 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ 3247 /* Bit 22 : Protection enable for region 22. */ 3248 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ 3249 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ 3250 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ 3251 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ 3252 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ 3254 /* Bit 21 : Protection enable for region 21. */ 3255 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ 3256 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ 3257 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ 3258 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ 3259 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ 3261 /* Bit 20 : Protection enable for region 20. */ 3262 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ 3263 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ 3264 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ 3265 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ 3266 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ 3268 /* Bit 19 : Protection enable for region 19. */ 3269 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ 3270 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ 3271 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ 3272 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ 3273 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ 3275 /* Bit 18 : Protection enable for region 18. */ 3276 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ 3277 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ 3278 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ 3279 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ 3280 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ 3282 /* Bit 17 : Protection enable for region 17. */ 3283 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ 3284 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ 3285 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ 3286 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ 3287 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ 3289 /* Bit 16 : Protection enable for region 16. */ 3290 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ 3291 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ 3292 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ 3293 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ 3294 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ 3296 /* Bit 15 : Protection enable for region 15. */ 3297 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ 3298 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ 3299 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ 3300 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ 3301 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ 3303 /* Bit 14 : Protection enable for region 14. */ 3304 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ 3305 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ 3306 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ 3307 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ 3308 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ 3310 /* Bit 13 : Protection enable for region 13. */ 3311 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ 3312 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ 3313 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ 3314 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ 3315 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ 3317 /* Bit 12 : Protection enable for region 12. */ 3318 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ 3319 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ 3320 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ 3321 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ 3322 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ 3324 /* Bit 11 : Protection enable for region 11. */ 3325 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ 3326 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ 3327 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ 3328 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ 3329 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ 3331 /* Bit 10 : Protection enable for region 10. */ 3332 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ 3333 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ 3334 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ 3335 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ 3336 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ 3338 /* Bit 9 : Protection enable for region 9. */ 3339 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ 3340 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ 3341 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ 3342 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ 3343 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ 3345 /* Bit 8 : Protection enable for region 8. */ 3346 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ 3347 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ 3348 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ 3349 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ 3350 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ 3352 /* Bit 7 : Protection enable for region 7. */ 3353 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ 3354 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ 3355 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ 3356 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ 3357 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ 3359 /* Bit 6 : Protection enable for region 6. */ 3360 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ 3361 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ 3362 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ 3363 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ 3364 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ 3366 /* Bit 5 : Protection enable for region 5. */ 3367 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ 3368 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ 3369 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ 3370 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ 3371 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ 3373 /* Bit 4 : Protection enable for region 4. */ 3374 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ 3375 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ 3376 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ 3377 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ 3378 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ 3380 /* Bit 3 : Protection enable for region 3. */ 3381 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ 3382 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ 3383 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ 3384 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ 3385 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ 3387 /* Bit 2 : Protection enable for region 2. */ 3388 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ 3389 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ 3390 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ 3391 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ 3392 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ 3394 /* Bit 1 : Protection enable for region 1. */ 3395 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ 3396 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ 3397 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ 3398 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ 3399 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ 3401 /* Bit 0 : Protection enable for region 0. */ 3402 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ 3403 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ 3404 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ 3405 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ 3406 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ 3408 /* Register: MPU_PROTENSET1 */ 3409 /* Description: Erase and write protection bit enable set register. */ 3411 /* Bit 31 : Protection enable for region 63. */ 3412 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ 3413 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ 3414 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ 3415 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ 3416 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ 3418 /* Bit 30 : Protection enable for region 62. */ 3419 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ 3420 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ 3421 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ 3422 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ 3423 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ 3425 /* Bit 29 : Protection enable for region 61. */ 3426 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ 3427 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ 3428 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ 3429 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ 3430 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ 3432 /* Bit 28 : Protection enable for region 60. */ 3433 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ 3434 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ 3435 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ 3436 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ 3437 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ 3439 /* Bit 27 : Protection enable for region 59. */ 3440 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ 3441 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ 3442 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ 3443 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ 3444 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ 3446 /* Bit 26 : Protection enable for region 58. */ 3447 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ 3448 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ 3449 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ 3450 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ 3451 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ 3453 /* Bit 25 : Protection enable for region 57. */ 3454 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ 3455 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ 3456 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ 3457 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ 3458 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ 3460 /* Bit 24 : Protection enable for region 56. */ 3461 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ 3462 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ 3463 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ 3464 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ 3465 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ 3467 /* Bit 23 : Protection enable for region 55. */ 3468 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ 3469 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ 3470 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ 3471 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ 3472 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ 3474 /* Bit 22 : Protection enable for region 54. */ 3475 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ 3476 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ 3477 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ 3478 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ 3479 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ 3481 /* Bit 21 : Protection enable for region 53. */ 3482 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ 3483 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ 3484 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ 3485 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ 3486 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ 3488 /* Bit 20 : Protection enable for region 52. */ 3489 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ 3490 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ 3491 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ 3492 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ 3493 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ 3495 /* Bit 19 : Protection enable for region 51. */ 3496 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ 3497 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ 3498 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ 3499 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ 3500 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ 3502 /* Bit 18 : Protection enable for region 50. */ 3503 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ 3504 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ 3505 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ 3506 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ 3507 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ 3509 /* Bit 17 : Protection enable for region 49. */ 3510 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ 3511 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ 3512 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ 3513 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ 3514 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ 3516 /* Bit 16 : Protection enable for region 48. */ 3517 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ 3518 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ 3519 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ 3520 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ 3521 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ 3523 /* Bit 15 : Protection enable for region 47. */ 3524 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ 3525 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ 3526 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ 3527 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ 3528 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ 3530 /* Bit 14 : Protection enable for region 46. */ 3531 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ 3532 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ 3533 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ 3534 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ 3535 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ 3537 /* Bit 13 : Protection enable for region 45. */ 3538 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ 3539 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ 3540 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ 3541 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ 3542 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ 3544 /* Bit 12 : Protection enable for region 44. */ 3545 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ 3546 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ 3547 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ 3548 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ 3549 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ 3551 /* Bit 11 : Protection enable for region 43. */ 3552 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ 3553 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ 3554 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ 3555 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ 3556 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ 3558 /* Bit 10 : Protection enable for region 42. */ 3559 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ 3560 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ 3561 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ 3562 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ 3563 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ 3565 /* Bit 9 : Protection enable for region 41. */ 3566 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ 3567 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ 3568 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ 3569 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ 3570 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ 3572 /* Bit 8 : Protection enable for region 40. */ 3573 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ 3574 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ 3575 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ 3576 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ 3577 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ 3579 /* Bit 7 : Protection enable for region 39. */ 3580 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ 3581 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ 3582 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ 3583 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ 3584 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ 3586 /* Bit 6 : Protection enable for region 38. */ 3587 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ 3588 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ 3589 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ 3590 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ 3591 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ 3593 /* Bit 5 : Protection enable for region 37. */ 3594 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ 3595 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ 3596 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ 3597 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ 3598 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ 3600 /* Bit 4 : Protection enable for region 36. */ 3601 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ 3602 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ 3603 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ 3604 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ 3605 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ 3607 /* Bit 3 : Protection enable for region 35. */ 3608 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ 3609 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ 3610 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ 3611 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ 3612 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ 3614 /* Bit 2 : Protection enable for region 34. */ 3615 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ 3616 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ 3617 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ 3618 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ 3619 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ 3621 /* Bit 1 : Protection enable for region 33. */ 3622 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ 3623 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ 3624 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ 3625 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ 3626 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ 3628 /* Bit 0 : Protection enable for region 32. */ 3629 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ 3630 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ 3631 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ 3632 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ 3633 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ 3635 /* Register: MPU_DISABLEINDEBUG */ 3636 /* Description: Disable erase and write protection mechanism in debug mode. */ 3638 /* Bit 0 : Disable protection mechanism in debug mode. */ 3639 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ 3640 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ 3641 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ 3642 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ 3644 /* Register: MPU_PROTBLOCKSIZE */ 3645 /* Description: Erase and write protection block size. */ 3647 /* Bits 1..0 : Erase and write protection block size. */ 3648 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ 3649 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ 3650 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ 3653 /* Peripheral: NVMC */ 3654 /* Description: Non Volatile Memory Controller. */ 3656 /* Register: NVMC_READY */ 3657 /* Description: Ready flag. */ 3659 /* Bit 0 : NVMC ready. */ 3660 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ 3661 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ 3662 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ 3663 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ 3665 /* Register: NVMC_CONFIG */ 3666 /* Description: Configuration register. */ 3668 /* Bits 1..0 : Program write enable. */ 3669 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ 3670 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ 3671 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ 3672 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ 3673 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ 3675 /* Register: NVMC_ERASEALL */ 3676 /* Description: Register for erasing all non-volatile user memory. */ 3678 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ 3679 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ 3680 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ 3681 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ 3682 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ 3684 /* Register: NVMC_ERASEUICR */ 3685 /* Description: Register for start erasing User Information Congfiguration Registers. */ 3687 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */ 3688 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ 3689 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ 3690 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ 3691 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ 3694 /* Peripheral: POWER */ 3695 /* Description: Power Control. */ 3697 /* Register: POWER_INTENSET */ 3698 /* Description: Interrupt enable set register. */ 3700 /* Bit 2 : Enable interrupt on POFWARN event. */ 3701 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3702 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3703 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 3704 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 3705 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ 3707 /* Register: POWER_INTENCLR */ 3708 /* Description: Interrupt enable clear register. */ 3710 /* Bit 2 : Disable interrupt on POFWARN event. */ 3711 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ 3712 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ 3713 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ 3714 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ 3715 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ 3717 /* Register: POWER_RESETREAS */ 3718 /* Description: Reset reason. */ 3720 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ 3721 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ 3722 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ 3724 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ 3725 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ 3726 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ 3728 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ 3729 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ 3730 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ 3732 /* Bit 3 : Reset from CPU lock-up detected. */ 3733 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ 3734 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ 3736 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ 3737 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ 3738 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ 3740 /* Bit 1 : Reset from watchdog detected. */ 3741 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ 3742 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ 3744 /* Bit 0 : Reset from pin-reset detected. */ 3745 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ 3746 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ 3748 /* Register: POWER_RAMSTATUS */ 3749 /* Description: Ram status register. */ 3751 /* Bit 3 : RAM block 3 status. */ 3752 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ 3753 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ 3754 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ 3755 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ 3757 /* Bit 2 : RAM block 2 status. */ 3758 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ 3759 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ 3760 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ 3761 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ 3763 /* Bit 1 : RAM block 1 status. */ 3764 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ 3765 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ 3766 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ 3767 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ 3769 /* Bit 0 : RAM block 0 status. */ 3770 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ 3771 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ 3772 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ 3773 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ 3775 /* Register: POWER_SYSTEMOFF */ 3776 /* Description: System off register. */ 3778 /* Bit 0 : Enter system off mode. */ 3779 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ 3780 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ 3781 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ 3783 /* Register: POWER_POFCON */ 3784 /* Description: Power failure configuration. */ 3786 /* Bits 2..1 : Set threshold level. */ 3787 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ 3788 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ 3789 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ 3790 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ 3791 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ 3792 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ 3794 /* Bit 0 : Power failure comparator enable. */ 3795 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ 3796 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ 3797 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ 3798 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ 3800 /* Register: POWER_GPREGRET */ 3801 /* Description: General purpose retention register. This register is a retained register. */ 3803 /* Bits 7..0 : General purpose retention register. */ 3804 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ 3805 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ 3807 /* Register: POWER_RAMON */ 3808 /* Description: Ram on/off. */ 3810 /* Bit 17 : RAM block 1 behaviour in OFF mode. */ 3811 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ 3812 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ 3813 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ 3814 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ 3816 /* Bit 16 : RAM block 0 behaviour in OFF mode. */ 3817 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ 3818 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ 3819 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ 3820 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ 3822 /* Bit 1 : RAM block 1 behaviour in ON mode. */ 3823 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ 3824 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ 3825 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ 3826 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ 3828 /* Bit 0 : RAM block 0 behaviour in ON mode. */ 3829 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ 3830 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ 3831 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ 3832 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ 3834 /* Register: POWER_RESET */ 3835 /* Description: Pin reset functionality configuration register. This register is a retained register. */ 3837 /* Bit 0 : Enable or disable pin reset in debug interface mode. */ 3838 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ 3839 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ 3840 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ 3841 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ 3843 /* Register: POWER_RAMONB */ 3844 /* Description: Ram on/off. */ 3846 /* Bit 17 : RAM block 3 behaviour in OFF mode. */ 3847 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ 3848 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ 3849 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ 3850 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ 3852 /* Bit 16 : RAM block 2 behaviour in OFF mode. */ 3853 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ 3854 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ 3855 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ 3856 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ 3858 /* Bit 1 : RAM block 3 behaviour in ON mode. */ 3859 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ 3860 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ 3861 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ 3862 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ 3864 /* Bit 0 : RAM block 2 behaviour in ON mode. */ 3865 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ 3866 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ 3867 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ 3868 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ 3870 /* Register: POWER_DCDCEN */ 3871 /* Description: DCDC converter enable configuration register. */ 3873 /* Bit 0 : Enable DCDC converter. */ 3874 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ 3875 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ 3876 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ 3877 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ 3879 /* Register: POWER_DCDCFORCE */ 3880 /* Description: DCDC power-up force register. */ 3882 /* Bit 1 : DCDC power-up force on. */ 3883 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ 3884 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ 3885 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ 3886 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ 3888 /* Bit 0 : DCDC power-up force off. */ 3889 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ 3890 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ 3891 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ 3892 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ 3895 /* Peripheral: PPI */ 3896 /* Description: PPI controller. */ 3898 /* Register: PPI_CHEN */ 3899 /* Description: Channel enable. */ 3901 /* Bit 31 : Enable PPI channel 31. */ 3902 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ 3903 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ 3904 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ 3905 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ 3907 /* Bit 30 : Enable PPI channel 30. */ 3908 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ 3909 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ 3910 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ 3911 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ 3913 /* Bit 29 : Enable PPI channel 29. */ 3914 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ 3915 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ 3916 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ 3917 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ 3919 /* Bit 28 : Enable PPI channel 28. */ 3920 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ 3921 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ 3922 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ 3923 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ 3925 /* Bit 27 : Enable PPI channel 27. */ 3926 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ 3927 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ 3928 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ 3929 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ 3931 /* Bit 26 : Enable PPI channel 26. */ 3932 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ 3933 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ 3934 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ 3935 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ 3937 /* Bit 25 : Enable PPI channel 25. */ 3938 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ 3939 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ 3940 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ 3941 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ 3943 /* Bit 24 : Enable PPI channel 24. */ 3944 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ 3945 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ 3946 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ 3947 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ 3949 /* Bit 23 : Enable PPI channel 23. */ 3950 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ 3951 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ 3952 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ 3953 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ 3955 /* Bit 22 : Enable PPI channel 22. */ 3956 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ 3957 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ 3958 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ 3959 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ 3961 /* Bit 21 : Enable PPI channel 21. */ 3962 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ 3963 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ 3964 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ 3965 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ 3967 /* Bit 20 : Enable PPI channel 20. */ 3968 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ 3969 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ 3970 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ 3971 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ 3973 /* Bit 15 : Enable PPI channel 15. */ 3974 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ 3975 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ 3976 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ 3977 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ 3979 /* Bit 14 : Enable PPI channel 14. */ 3980 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ 3981 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ 3982 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ 3983 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ 3985 /* Bit 13 : Enable PPI channel 13. */ 3986 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ 3987 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ 3988 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ 3989 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ 3991 /* Bit 12 : Enable PPI channel 12. */ 3992 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ 3993 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ 3994 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ 3995 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ 3997 /* Bit 11 : Enable PPI channel 11. */ 3998 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ 3999 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ 4000 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ 4001 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ 4003 /* Bit 10 : Enable PPI channel 10. */ 4004 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4005 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ 4006 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ 4007 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ 4009 /* Bit 9 : Enable PPI channel 9. */ 4010 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4011 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ 4012 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ 4013 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ 4015 /* Bit 8 : Enable PPI channel 8. */ 4016 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4017 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ 4018 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ 4019 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ 4021 /* Bit 7 : Enable PPI channel 7. */ 4022 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4023 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ 4024 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ 4025 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ 4027 /* Bit 6 : Enable PPI channel 6. */ 4028 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4029 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ 4030 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ 4031 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ 4033 /* Bit 5 : Enable PPI channel 5. */ 4034 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4035 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ 4036 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ 4037 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ 4039 /* Bit 4 : Enable PPI channel 4. */ 4040 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4041 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ 4042 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ 4043 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ 4045 /* Bit 3 : Enable PPI channel 3. */ 4046 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4047 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ 4048 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ 4049 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ 4051 /* Bit 2 : Enable PPI channel 2. */ 4052 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4053 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ 4054 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ 4055 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ 4057 /* Bit 1 : Enable PPI channel 1. */ 4058 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4059 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ 4060 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ 4061 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ 4063 /* Bit 0 : Enable PPI channel 0. */ 4064 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4065 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ 4066 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ 4067 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ 4069 /* Register: PPI_CHENSET */ 4070 /* Description: Channel enable set. */ 4072 /* Bit 31 : Enable PPI channel 31. */ 4073 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4074 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ 4075 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ 4076 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ 4077 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ 4079 /* Bit 30 : Enable PPI channel 30. */ 4080 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4081 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ 4082 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ 4083 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ 4084 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ 4086 /* Bit 29 : Enable PPI channel 29. */ 4087 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4088 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ 4089 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ 4090 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ 4091 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ 4093 /* Bit 28 : Enable PPI channel 28. */ 4094 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4095 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ 4096 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ 4097 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ 4098 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ 4100 /* Bit 27 : Enable PPI channel 27. */ 4101 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4102 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ 4103 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ 4104 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ 4105 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ 4107 /* Bit 26 : Enable PPI channel 26. */ 4108 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4109 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ 4110 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ 4111 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ 4112 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ 4114 /* Bit 25 : Enable PPI channel 25. */ 4115 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4116 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ 4117 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ 4118 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ 4119 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ 4121 /* Bit 24 : Enable PPI channel 24. */ 4122 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4123 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ 4124 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ 4125 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ 4126 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ 4128 /* Bit 23 : Enable PPI channel 23. */ 4129 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4130 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ 4131 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ 4132 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ 4133 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ 4135 /* Bit 22 : Enable PPI channel 22. */ 4136 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4137 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ 4138 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ 4139 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ 4140 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ 4142 /* Bit 21 : Enable PPI channel 21. */ 4143 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4144 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ 4145 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ 4146 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ 4147 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ 4149 /* Bit 20 : Enable PPI channel 20. */ 4150 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4151 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ 4152 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ 4153 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ 4154 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ 4156 /* Bit 15 : Enable PPI channel 15. */ 4157 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4158 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ 4159 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ 4160 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ 4161 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ 4163 /* Bit 14 : Enable PPI channel 14. */ 4164 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4165 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ 4166 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ 4167 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ 4168 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ 4170 /* Bit 13 : Enable PPI channel 13. */ 4171 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4172 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ 4173 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ 4174 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ 4175 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ 4177 /* Bit 12 : Enable PPI channel 12. */ 4178 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4179 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ 4180 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ 4181 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ 4182 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ 4184 /* Bit 11 : Enable PPI channel 11. */ 4185 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4186 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ 4187 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ 4188 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ 4189 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ 4191 /* Bit 10 : Enable PPI channel 10. */ 4192 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4193 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ 4194 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ 4195 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ 4196 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ 4198 /* Bit 9 : Enable PPI channel 9. */ 4199 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4200 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ 4201 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ 4202 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ 4203 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ 4205 /* Bit 8 : Enable PPI channel 8. */ 4206 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4207 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ 4208 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ 4209 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ 4210 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ 4212 /* Bit 7 : Enable PPI channel 7. */ 4213 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4214 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ 4215 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ 4216 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ 4217 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ 4219 /* Bit 6 : Enable PPI channel 6. */ 4220 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4221 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ 4222 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ 4223 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ 4224 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ 4226 /* Bit 5 : Enable PPI channel 5. */ 4227 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4228 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ 4229 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ 4230 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ 4231 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ 4233 /* Bit 4 : Enable PPI channel 4. */ 4234 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4235 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ 4236 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ 4237 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ 4238 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ 4240 /* Bit 3 : Enable PPI channel 3. */ 4241 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4242 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ 4243 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ 4244 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ 4245 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ 4247 /* Bit 2 : Enable PPI channel 2. */ 4248 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4249 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ 4250 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ 4251 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ 4252 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ 4254 /* Bit 1 : Enable PPI channel 1. */ 4255 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4256 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ 4257 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ 4258 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ 4259 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ 4261 /* Bit 0 : Enable PPI channel 0. */ 4262 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4263 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ 4264 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ 4265 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ 4266 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ 4268 /* Register: PPI_CHENCLR */ 4269 /* Description: Channel enable clear. */ 4271 /* Bit 31 : Disable PPI channel 31. */ 4272 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4273 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ 4274 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ 4275 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ 4276 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ 4278 /* Bit 30 : Disable PPI channel 30. */ 4279 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4280 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ 4281 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ 4282 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ 4283 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ 4285 /* Bit 29 : Disable PPI channel 29. */ 4286 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4287 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ 4288 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ 4289 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ 4290 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ 4292 /* Bit 28 : Disable PPI channel 28. */ 4293 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4294 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ 4295 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ 4296 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ 4297 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ 4299 /* Bit 27 : Disable PPI channel 27. */ 4300 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4301 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ 4302 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ 4303 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ 4304 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ 4306 /* Bit 26 : Disable PPI channel 26. */ 4307 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4308 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ 4309 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ 4310 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ 4311 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ 4313 /* Bit 25 : Disable PPI channel 25. */ 4314 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4315 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ 4316 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ 4317 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ 4318 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ 4320 /* Bit 24 : Disable PPI channel 24. */ 4321 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4322 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ 4323 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ 4324 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ 4325 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ 4327 /* Bit 23 : Disable PPI channel 23. */ 4328 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4329 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ 4330 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ 4331 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ 4332 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ 4334 /* Bit 22 : Disable PPI channel 22. */ 4335 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4336 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ 4337 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ 4338 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ 4339 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ 4341 /* Bit 21 : Disable PPI channel 21. */ 4342 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4343 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ 4344 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ 4345 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ 4346 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ 4348 /* Bit 20 : Disable PPI channel 20. */ 4349 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4350 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ 4351 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ 4352 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ 4353 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ 4355 /* Bit 15 : Disable PPI channel 15. */ 4356 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4357 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ 4358 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ 4359 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ 4360 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ 4362 /* Bit 14 : Disable PPI channel 14. */ 4363 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4364 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ 4365 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ 4366 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ 4367 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ 4369 /* Bit 13 : Disable PPI channel 13. */ 4370 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4371 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ 4372 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ 4373 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ 4374 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ 4376 /* Bit 12 : Disable PPI channel 12. */ 4377 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4378 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ 4379 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ 4380 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ 4381 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ 4383 /* Bit 11 : Disable PPI channel 11. */ 4384 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4385 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ 4386 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ 4387 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ 4388 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ 4390 /* Bit 10 : Disable PPI channel 10. */ 4391 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4392 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ 4393 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ 4394 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ 4395 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ 4397 /* Bit 9 : Disable PPI channel 9. */ 4398 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4399 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ 4400 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ 4401 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ 4402 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ 4404 /* Bit 8 : Disable PPI channel 8. */ 4405 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4406 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ 4407 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ 4408 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ 4409 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ 4411 /* Bit 7 : Disable PPI channel 7. */ 4412 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4413 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ 4414 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ 4415 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ 4416 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ 4418 /* Bit 6 : Disable PPI channel 6. */ 4419 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4420 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ 4421 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ 4422 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ 4423 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ 4425 /* Bit 5 : Disable PPI channel 5. */ 4426 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4427 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ 4428 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ 4429 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ 4430 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ 4432 /* Bit 4 : Disable PPI channel 4. */ 4433 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4434 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ 4435 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ 4436 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ 4437 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ 4439 /* Bit 3 : Disable PPI channel 3. */ 4440 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4441 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ 4442 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ 4443 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ 4444 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ 4446 /* Bit 2 : Disable PPI channel 2. */ 4447 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4448 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ 4449 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ 4450 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ 4451 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ 4453 /* Bit 1 : Disable PPI channel 1. */ 4454 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4455 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ 4456 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ 4457 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ 4458 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ 4460 /* Bit 0 : Disable PPI channel 0. */ 4461 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4462 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ 4463 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ 4464 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ 4465 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ 4467 /* Register: PPI_CHG */ 4468 /* Description: Channel group configuration. */ 4470 /* Bit 31 : Include CH31 in channel group. */ 4471 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ 4472 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ 4473 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ 4474 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ 4476 /* Bit 30 : Include CH30 in channel group. */ 4477 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ 4478 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ 4479 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ 4480 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ 4482 /* Bit 29 : Include CH29 in channel group. */ 4483 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ 4484 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ 4485 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ 4486 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ 4488 /* Bit 28 : Include CH28 in channel group. */ 4489 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ 4490 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ 4491 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ 4492 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ 4494 /* Bit 27 : Include CH27 in channel group. */ 4495 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ 4496 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ 4497 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ 4498 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ 4500 /* Bit 26 : Include CH26 in channel group. */ 4501 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ 4502 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ 4503 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ 4504 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ 4506 /* Bit 25 : Include CH25 in channel group. */ 4507 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ 4508 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ 4509 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ 4510 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ 4512 /* Bit 24 : Include CH24 in channel group. */ 4513 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ 4514 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ 4515 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ 4516 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ 4518 /* Bit 23 : Include CH23 in channel group. */ 4519 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ 4520 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ 4521 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ 4522 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ 4524 /* Bit 22 : Include CH22 in channel group. */ 4525 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ 4526 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ 4527 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ 4528 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ 4530 /* Bit 21 : Include CH21 in channel group. */ 4531 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ 4532 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ 4533 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ 4534 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ 4536 /* Bit 20 : Include CH20 in channel group. */ 4537 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ 4538 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ 4539 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ 4540 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ 4542 /* Bit 15 : Include CH15 in channel group. */ 4543 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ 4544 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ 4545 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ 4546 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ 4548 /* Bit 14 : Include CH14 in channel group. */ 4549 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ 4550 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ 4551 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ 4552 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ 4554 /* Bit 13 : Include CH13 in channel group. */ 4555 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ 4556 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ 4557 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ 4558 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ 4560 /* Bit 12 : Include CH12 in channel group. */ 4561 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ 4562 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ 4563 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ 4564 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ 4566 /* Bit 11 : Include CH11 in channel group. */ 4567 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ 4568 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ 4569 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ 4570 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ 4572 /* Bit 10 : Include CH10 in channel group. */ 4573 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ 4574 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ 4575 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ 4576 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ 4578 /* Bit 9 : Include CH9 in channel group. */ 4579 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ 4580 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ 4581 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ 4582 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ 4584 /* Bit 8 : Include CH8 in channel group. */ 4585 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ 4586 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ 4587 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ 4588 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ 4590 /* Bit 7 : Include CH7 in channel group. */ 4591 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ 4592 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ 4593 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ 4594 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ 4596 /* Bit 6 : Include CH6 in channel group. */ 4597 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ 4598 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ 4599 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ 4600 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ 4602 /* Bit 5 : Include CH5 in channel group. */ 4603 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ 4604 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ 4605 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ 4606 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ 4608 /* Bit 4 : Include CH4 in channel group. */ 4609 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ 4610 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ 4611 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ 4612 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ 4614 /* Bit 3 : Include CH3 in channel group. */ 4615 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ 4616 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ 4617 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ 4618 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ 4620 /* Bit 2 : Include CH2 in channel group. */ 4621 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ 4622 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ 4623 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ 4624 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ 4626 /* Bit 1 : Include CH1 in channel group. */ 4627 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ 4628 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ 4629 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ 4630 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ 4632 /* Bit 0 : Include CH0 in channel group. */ 4633 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ 4634 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ 4635 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ 4636 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ 4639 /* Peripheral: PU */ 4640 /* Description: Patch unit. */ 4642 /* Register: PU_PATCHADDR */ 4643 /* Description: Relative address of patch instructions. */ 4645 /* Bits 24..0 : Relative address of patch instructions. */ 4646 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */ 4647 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */ 4649 /* Register: PU_PATCHEN */ 4650 /* Description: Patch enable register. */ 4652 /* Bit 7 : Patch 7 enabled. */ 4653 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 4654 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 4655 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 4656 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 4658 /* Bit 6 : Patch 6 enabled. */ 4659 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 4660 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 4661 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 4662 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 4664 /* Bit 5 : Patch 5 enabled. */ 4665 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 4666 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 4667 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 4668 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 4670 /* Bit 4 : Patch 4 enabled. */ 4671 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 4672 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 4673 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 4674 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 4676 /* Bit 3 : Patch 3 enabled. */ 4677 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 4678 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 4679 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 4680 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 4682 /* Bit 2 : Patch 2 enabled. */ 4683 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 4684 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 4685 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 4686 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 4688 /* Bit 1 : Patch 1 enabled. */ 4689 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 4690 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 4691 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 4692 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 4694 /* Bit 0 : Patch 0 enabled. */ 4695 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 4696 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 4697 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 4698 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 4700 /* Register: PU_PATCHENSET */ 4701 /* Description: Patch enable register. */ 4703 /* Bit 7 : Patch 7 enabled. */ 4704 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 4705 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 4706 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 4707 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 4708 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */ 4710 /* Bit 6 : Patch 6 enabled. */ 4711 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 4712 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 4713 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 4714 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 4715 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */ 4717 /* Bit 5 : Patch 5 enabled. */ 4718 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 4719 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 4720 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 4721 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 4722 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */ 4724 /* Bit 4 : Patch 4 enabled. */ 4725 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 4726 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 4727 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 4728 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 4729 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */ 4731 /* Bit 3 : Patch 3 enabled. */ 4732 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 4733 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 4734 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 4735 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 4736 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */ 4738 /* Bit 2 : Patch 2 enabled. */ 4739 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 4740 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 4741 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 4742 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 4743 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */ 4745 /* Bit 1 : Patch 1 enabled. */ 4746 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 4747 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 4748 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 4749 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 4750 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */ 4752 /* Bit 0 : Patch 0 enabled. */ 4753 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 4754 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 4755 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 4756 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 4757 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */ 4759 /* Register: PU_PATCHENCLR */ 4760 /* Description: Patch disable register. */ 4762 /* Bit 7 : Patch 7 enabled. */ 4763 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */ 4764 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */ 4765 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */ 4766 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */ 4767 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */ 4769 /* Bit 6 : Patch 6 enabled. */ 4770 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */ 4771 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */ 4772 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */ 4773 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */ 4774 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */ 4776 /* Bit 5 : Patch 5 enabled. */ 4777 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */ 4778 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */ 4779 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */ 4780 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */ 4781 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */ 4783 /* Bit 4 : Patch 4 enabled. */ 4784 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */ 4785 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */ 4786 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */ 4787 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */ 4788 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */ 4790 /* Bit 3 : Patch 3 enabled. */ 4791 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */ 4792 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */ 4793 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */ 4794 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */ 4795 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */ 4797 /* Bit 2 : Patch 2 enabled. */ 4798 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */ 4799 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */ 4800 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */ 4801 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */ 4802 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */ 4804 /* Bit 1 : Patch 1 enabled. */ 4805 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */ 4806 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */ 4807 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */ 4808 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */ 4809 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */ 4811 /* Bit 0 : Patch 0 enabled. */ 4812 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */ 4813 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */ 4814 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */ 4815 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */ 4816 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */ 4819 /* Peripheral: QDEC */ 4820 /* Description: Rotary decoder. */ 4822 /* Register: QDEC_SHORTS */ 4823 /* Description: Shortcuts for the QDEC. */ 4825 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ 4826 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ 4827 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ 4828 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 4829 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 4831 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ 4832 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ 4833 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ 4834 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ 4835 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ 4837 /* Register: QDEC_INTENSET */ 4838 /* Description: Interrupt enable set register. */ 4840 /* Bit 2 : Enable interrupt on ACCOF event. */ 4841 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4842 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4843 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 4844 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 4845 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ 4847 /* Bit 1 : Enable interrupt on REPORTRDY event. */ 4848 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4849 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4850 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4851 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4852 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ 4854 /* Bit 0 : Enable interrupt on SAMPLERDY event. */ 4855 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4856 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4857 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 4858 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 4859 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ 4861 /* Register: QDEC_INTENCLR */ 4862 /* Description: Interrupt enable clear register. */ 4864 /* Bit 2 : Disable interrupt on ACCOF event. */ 4865 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ 4866 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ 4867 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ 4868 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ 4869 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ 4871 /* Bit 1 : Disable interrupt on REPORTRDY event. */ 4872 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ 4873 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ 4874 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ 4875 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ 4876 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ 4878 /* Bit 0 : Disable interrupt on SAMPLERDY event. */ 4879 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ 4880 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ 4881 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ 4882 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ 4883 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ 4885 /* Register: QDEC_ENABLE */ 4886 /* Description: Enable the QDEC. */ 4888 /* Bit 0 : Enable or disable QDEC. */ 4889 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 4890 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 4891 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ 4892 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ 4894 /* Register: QDEC_LEDPOL */ 4895 /* Description: LED output pin polarity. */ 4897 /* Bit 0 : LED output pin polarity. */ 4898 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ 4899 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ 4900 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ 4901 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ 4903 /* Register: QDEC_SAMPLEPER */ 4904 /* Description: Sample period. */ 4906 /* Bits 2..0 : Sample period. */ 4907 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ 4908 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ 4909 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ 4910 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ 4911 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ 4912 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ 4913 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ 4914 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ 4915 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ 4916 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ 4918 /* Register: QDEC_SAMPLE */ 4919 /* Description: Motion sample value. */ 4921 /* Bits 31..0 : Last sample taken in compliment to 2. */ 4922 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ 4923 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ 4925 /* Register: QDEC_REPORTPER */ 4926 /* Description: Number of samples to generate an EVENT_REPORTRDY. */ 4928 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ 4929 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ 4930 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ 4931 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ 4932 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ 4933 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ 4934 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ 4935 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ 4936 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ 4937 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ 4938 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ 4940 /* Register: QDEC_DBFEN */ 4941 /* Description: Enable debouncer input filters. */ 4943 /* Bit 0 : Enable debounce input filters. */ 4944 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ 4945 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ 4946 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ 4947 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ 4949 /* Register: QDEC_LEDPRE */ 4950 /* Description: Time LED is switched ON before the sample. */ 4952 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ 4953 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ 4954 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ 4956 /* Register: QDEC_ACCDBL */ 4957 /* Description: Accumulated double (error) transitions register. */ 4959 /* Bits 3..0 : Accumulated double (error) transitions. */ 4960 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ 4961 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ 4963 /* Register: QDEC_ACCDBLREAD */ 4964 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ 4966 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ 4967 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ 4968 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ 4970 /* Register: QDEC_POWER */ 4971 /* Description: Peripheral power control. */ 4973 /* Bit 0 : Peripheral power control. */ 4974 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 4975 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 4976 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 4977 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 4980 /* Peripheral: RADIO */ 4981 /* Description: The radio. */ 4983 /* Register: RADIO_SHORTS */ 4984 /* Description: Shortcuts for the radio. */ 4986 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ 4987 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ 4988 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ 4989 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ 4990 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ 4992 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ 4993 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ 4994 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ 4995 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ 4996 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ 4998 /* Bit 5 : Shortcut between END event and START task. */ 4999 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ 5000 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 5001 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ 5002 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ 5004 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ 5005 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ 5006 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ 5007 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ 5008 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ 5010 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */ 5011 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ 5012 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ 5013 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ 5014 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ 5016 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */ 5017 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ 5018 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ 5019 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ 5020 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ 5022 /* Bit 1 : Shortcut between END event and DISABLE task. */ 5023 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ 5024 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ 5025 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ 5026 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ 5028 /* Bit 0 : Shortcut between READY event and START task. */ 5029 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ 5030 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ 5031 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ 5032 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ 5034 /* Register: RADIO_INTENSET */ 5035 /* Description: Interrupt enable set register. */ 5037 /* Bit 10 : Enable interrupt on BCMATCH event. */ 5038 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 5039 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 5040 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 5041 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 5042 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ 5044 /* Bit 7 : Enable interrupt on RSSIEND event. */ 5045 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 5046 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 5047 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 5048 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 5049 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ 5051 /* Bit 6 : Enable interrupt on DEVMISS event. */ 5052 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 5053 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 5054 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 5055 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 5056 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ 5058 /* Bit 5 : Enable interrupt on DEVMATCH event. */ 5059 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 5060 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 5061 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 5062 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 5063 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ 5065 /* Bit 4 : Enable interrupt on DISABLED event. */ 5066 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 5067 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 5068 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 5069 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 5070 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ 5072 /* Bit 3 : Enable interrupt on END event. */ 5073 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ 5074 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ 5075 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 5076 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 5077 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 5079 /* Bit 2 : Enable interrupt on PAYLOAD event. */ 5080 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 5081 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 5082 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 5083 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 5084 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ 5086 /* Bit 1 : Enable interrupt on ADDRESS event. */ 5087 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 5088 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 5089 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 5090 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 5091 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ 5093 /* Bit 0 : Enable interrupt on READY event. */ 5094 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ 5095 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 5096 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5097 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5098 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 5100 /* Register: RADIO_INTENCLR */ 5101 /* Description: Interrupt enable clear register. */ 5103 /* Bit 10 : Disable interrupt on BCMATCH event. */ 5104 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ 5105 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ 5106 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 5107 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 5108 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 5110 /* Bit 7 : Disable interrupt on RSSIEND event. */ 5111 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ 5112 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ 5113 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ 5114 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ 5115 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ 5117 /* Bit 6 : Disable interrupt on DEVMISS event. */ 5118 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ 5119 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ 5120 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ 5121 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ 5122 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ 5124 /* Bit 5 : Disable interrupt on DEVMATCH event. */ 5125 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ 5126 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ 5127 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ 5128 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ 5129 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ 5131 /* Bit 4 : Disable interrupt on DISABLED event. */ 5132 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ 5133 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ 5134 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ 5135 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ 5136 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ 5138 /* Bit 3 : Disable interrupt on END event. */ 5139 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ 5140 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 5141 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 5142 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 5143 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 5145 /* Bit 2 : Disable interrupt on PAYLOAD event. */ 5146 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ 5147 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ 5148 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ 5149 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ 5150 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ 5152 /* Bit 1 : Disable interrupt on ADDRESS event. */ 5153 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ 5154 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 5155 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ 5156 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ 5157 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ 5159 /* Bit 0 : Disable interrupt on READY event. */ 5160 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ 5161 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 5162 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5163 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5164 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 5166 /* Register: RADIO_CRCSTATUS */ 5167 /* Description: CRC status of received packet. */ 5169 /* Bit 0 : CRC status of received packet. */ 5170 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ 5171 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ 5172 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ 5173 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ 5175 /* Register: RADIO_CD */ 5176 /* Description: Carrier detect. */ 5178 /* Bit 0 : Carrier detect. */ 5179 #define RADIO_CD_CD_Pos (0UL) /*!< Position of CD field. */ 5180 #define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /*!< Bit mask of CD field. */ 5182 /* Register: RADIO_RXMATCH */ 5183 /* Description: Received address. */ 5185 /* Bits 2..0 : Logical address in which previous packet was received. */ 5186 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ 5187 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ 5189 /* Register: RADIO_RXCRC */ 5190 /* Description: Received CRC. */ 5192 /* Bits 23..0 : CRC field of previously received packet. */ 5193 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ 5194 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ 5196 /* Register: RADIO_DAI */ 5197 /* Description: Device address match index. */ 5199 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ 5200 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ 5201 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ 5203 /* Register: RADIO_FREQUENCY */ 5204 /* Description: Frequency. */ 5206 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ 5207 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 5208 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 5210 /* Register: RADIO_TXPOWER */ 5211 /* Description: Output power. */ 5213 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */ 5214 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ 5215 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ 5216 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ 5217 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ 5218 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ 5219 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ 5220 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ 5221 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ 5222 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ 5223 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ 5225 /* Register: RADIO_MODE */ 5226 /* Description: Data rate and modulation. */ 5228 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ 5229 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 5230 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 5231 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ 5232 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ 5233 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ 5234 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ 5236 /* Register: RADIO_PCNF0 */ 5237 /* Description: Packet configuration 0. */ 5239 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ 5240 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ 5241 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ 5243 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ 5244 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ 5245 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ 5247 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ 5248 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ 5249 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ 5251 /* Register: RADIO_PCNF1 */ 5252 /* Description: Packet configuration 1. */ 5254 /* Bit 25 : Packet whitening enable. */ 5255 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ 5256 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ 5257 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ 5258 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ 5260 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */ 5261 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ 5262 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ 5263 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ 5264 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ 5266 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ 5267 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ 5268 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ 5270 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ 5271 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ 5272 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ 5274 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */ 5275 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ 5276 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ 5278 /* Register: RADIO_PREFIX0 */ 5279 /* Description: Prefixes bytes for logical addresses 0 to 3. */ 5281 /* Bits 31..24 : Address prefix 3. Decision point: START task. */ 5282 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ 5283 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ 5285 /* Bits 23..16 : Address prefix 2. Decision point: START task. */ 5286 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ 5287 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ 5289 /* Bits 15..8 : Address prefix 1. Decision point: START task. */ 5290 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ 5291 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ 5293 /* Bits 7..0 : Address prefix 0. Decision point: START task. */ 5294 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ 5295 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ 5297 /* Register: RADIO_PREFIX1 */ 5298 /* Description: Prefixes bytes for logical addresses 4 to 7. */ 5300 /* Bits 31..24 : Address prefix 7. Decision point: START task. */ 5301 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ 5302 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ 5304 /* Bits 23..16 : Address prefix 6. Decision point: START task. */ 5305 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ 5306 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ 5308 /* Bits 15..8 : Address prefix 5. Decision point: START task. */ 5309 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ 5310 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ 5312 /* Bits 7..0 : Address prefix 4. Decision point: START task. */ 5313 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ 5314 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ 5316 /* Register: RADIO_TXADDRESS */ 5317 /* Description: Transmit address select. */ 5319 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ 5320 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ 5321 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ 5323 /* Register: RADIO_RXADDRESSES */ 5324 /* Description: Receive address select. */ 5326 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ 5327 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ 5328 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ 5329 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ 5330 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ 5332 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ 5333 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ 5334 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ 5335 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ 5336 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ 5338 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ 5339 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ 5340 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ 5341 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ 5342 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ 5344 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ 5345 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ 5346 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ 5347 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ 5348 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ 5350 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ 5351 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ 5352 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ 5353 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ 5354 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ 5356 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ 5357 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ 5358 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ 5359 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ 5360 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ 5362 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ 5363 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ 5364 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ 5365 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ 5366 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ 5368 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ 5369 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ 5370 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ 5371 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ 5372 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ 5374 /* Register: RADIO_CRCCNF */ 5375 /* Description: CRC configuration. */ 5377 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ 5378 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ 5379 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ 5380 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ 5381 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ 5383 /* Bits 1..0 : CRC length. Decision point: START task. */ 5384 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ 5385 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ 5386 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ 5387 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ 5388 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ 5389 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ 5391 /* Register: RADIO_CRCPOLY */ 5392 /* Description: CRC polynomial. */ 5394 /* Bits 23..0 : CRC polynomial. Decision point: START task. */ 5395 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ 5396 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ 5398 /* Register: RADIO_CRCINIT */ 5399 /* Description: CRC initial value. */ 5401 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ 5402 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ 5403 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ 5405 /* Register: RADIO_TEST */ 5406 /* Description: Test features enable register. */ 5408 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ 5409 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ 5410 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ 5411 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ 5412 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ 5414 /* Bit 0 : Constant carrier. Decision point: TXEN task. */ 5415 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ 5416 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ 5417 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ 5418 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ 5420 /* Register: RADIO_TIFS */ 5421 /* Description: Inter Frame Spacing in microseconds. */ 5423 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ 5424 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ 5425 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ 5427 /* Register: RADIO_RSSISAMPLE */ 5428 /* Description: RSSI sample. */ 5430 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ 5431 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ 5432 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ 5434 /* Register: RADIO_STATE */ 5435 /* Description: Current radio state. */ 5437 /* Bits 3..0 : Current radio state. */ 5438 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ 5439 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ 5440 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ 5441 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ 5442 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ 5443 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ 5444 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ 5445 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ 5446 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ 5447 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ 5448 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ 5450 /* Register: RADIO_DATAWHITEIV */ 5451 /* Description: Data whitening initial value. */ 5453 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ 5454 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ 5455 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ 5457 /* Register: RADIO_DAP */ 5458 /* Description: Device address prefix. */ 5460 /* Bits 15..0 : Device address prefix. */ 5461 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ 5462 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ 5464 /* Register: RADIO_DACNF */ 5465 /* Description: Device address match configuration. */ 5467 /* Bit 15 : TxAdd for device address 7. */ 5468 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ 5469 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ 5471 /* Bit 14 : TxAdd for device address 6. */ 5472 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ 5473 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ 5475 /* Bit 13 : TxAdd for device address 5. */ 5476 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ 5477 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ 5479 /* Bit 12 : TxAdd for device address 4. */ 5480 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ 5481 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ 5483 /* Bit 11 : TxAdd for device address 3. */ 5484 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ 5485 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ 5487 /* Bit 10 : TxAdd for device address 2. */ 5488 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ 5489 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ 5491 /* Bit 9 : TxAdd for device address 1. */ 5492 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ 5493 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ 5495 /* Bit 8 : TxAdd for device address 0. */ 5496 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ 5497 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ 5499 /* Bit 7 : Enable or disable device address matching using device address 7. */ 5500 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ 5501 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ 5502 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ 5503 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ 5505 /* Bit 6 : Enable or disable device address matching using device address 6. */ 5506 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ 5507 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ 5508 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ 5509 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ 5511 /* Bit 5 : Enable or disable device address matching using device address 5. */ 5512 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ 5513 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ 5514 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ 5515 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ 5517 /* Bit 4 : Enable or disable device address matching using device address 4. */ 5518 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ 5519 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ 5520 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ 5521 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ 5523 /* Bit 3 : Enable or disable device address matching using device address 3. */ 5524 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ 5525 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ 5526 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ 5527 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ 5529 /* Bit 2 : Enable or disable device address matching using device address 2. */ 5530 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ 5531 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ 5532 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ 5533 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ 5535 /* Bit 1 : Enable or disable device address matching using device address 1. */ 5536 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ 5537 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ 5538 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ 5539 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ 5541 /* Bit 0 : Enable or disable device address matching using device address 0. */ 5542 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ 5543 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ 5544 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ 5545 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ 5547 /* Register: RADIO_OVERRIDE0 */ 5548 /* Description: Trim value override register 0. */ 5550 /* Bits 31..0 : Trim value override 0. */ 5551 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ 5552 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ 5554 /* Register: RADIO_OVERRIDE1 */ 5555 /* Description: Trim value override register 1. */ 5557 /* Bits 31..0 : Trim value override 1. */ 5558 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ 5559 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ 5561 /* Register: RADIO_OVERRIDE2 */ 5562 /* Description: Trim value override register 2. */ 5564 /* Bits 31..0 : Trim value override 2. */ 5565 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ 5566 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ 5568 /* Register: RADIO_OVERRIDE3 */ 5569 /* Description: Trim value override register 3. */ 5571 /* Bits 31..0 : Trim value override 3. */ 5572 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ 5573 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ 5575 /* Register: RADIO_OVERRIDE4 */ 5576 /* Description: Trim value override register 4. */ 5578 /* Bit 31 : Enable or disable override of default trim values. */ 5579 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ 5580 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5581 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ 5582 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ 5584 /* Bits 27..0 : Trim value override 4. */ 5585 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ 5586 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ 5588 /* Register: RADIO_POWER */ 5589 /* Description: Peripheral power control. */ 5591 /* Bit 0 : Peripheral power control. */ 5592 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5593 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5594 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5595 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5598 /* Peripheral: RNG */ 5599 /* Description: Random Number Generator. */ 5601 /* Register: RNG_SHORTS */ 5602 /* Description: Shortcuts for the RNG. */ 5604 /* Bit 0 : Shortcut between VALRDY event and STOP task. */ 5605 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ 5606 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ 5607 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 5608 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 5610 /* Register: RNG_INTENSET */ 5611 /* Description: Interrupt enable set register */ 5613 /* Bit 0 : Enable interrupt on VALRDY event. */ 5614 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 5615 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 5616 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5617 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5618 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ 5620 /* Register: RNG_INTENCLR */ 5621 /* Description: Interrupt enable clear register */ 5623 /* Bit 0 : Disable interrupt on VALRDY event. */ 5624 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ 5625 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ 5626 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ 5627 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ 5628 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ 5630 /* Register: RNG_CONFIG */ 5631 /* Description: Configuration register. */ 5633 /* Bit 0 : Digital error correction enable. */ 5634 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ 5635 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ 5636 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ 5637 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ 5639 /* Register: RNG_VALUE */ 5640 /* Description: RNG random number. */ 5642 /* Bits 7..0 : Generated random number. */ 5643 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ 5644 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ 5646 /* Register: RNG_POWER */ 5647 /* Description: Peripheral power control. */ 5649 /* Bit 0 : Peripheral power control. */ 5650 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5651 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5652 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5653 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5656 /* Peripheral: RTC */ 5657 /* Description: Real time counter 0. */ 5659 /* Register: RTC_INTENSET */ 5660 /* Description: Interrupt enable set register. */ 5662 /* Bit 19 : Enable interrupt on COMPARE[3] event. */ 5663 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5664 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5665 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 5666 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 5667 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 5669 /* Bit 18 : Enable interrupt on COMPARE[2] event. */ 5670 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5671 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5672 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 5673 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 5674 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 5676 /* Bit 17 : Enable interrupt on COMPARE[1] event. */ 5677 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5678 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5679 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 5680 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 5681 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 5683 /* Bit 16 : Enable interrupt on COMPARE[0] event. */ 5684 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5685 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5686 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 5687 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 5688 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 5690 /* Bit 1 : Enable interrupt on OVRFLW event. */ 5691 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5692 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5693 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 5694 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 5695 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ 5697 /* Bit 0 : Enable interrupt on TICK event. */ 5698 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5699 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5700 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 5701 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 5702 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ 5704 /* Register: RTC_INTENCLR */ 5705 /* Description: Interrupt enable clear register. */ 5707 /* Bit 19 : Disable interrupt on COMPARE[3] event. */ 5708 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5709 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5710 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 5711 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 5712 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 5714 /* Bit 18 : Disable interrupt on COMPARE[2] event. */ 5715 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5716 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5717 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 5718 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 5719 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 5721 /* Bit 17 : Disable interrupt on COMPARE[1] event. */ 5722 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5723 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5724 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 5725 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 5726 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 5728 /* Bit 16 : Disable interrupt on COMPARE[0] event. */ 5729 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5730 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5731 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 5732 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 5733 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 5735 /* Bit 1 : Disable interrupt on OVRFLW event. */ 5736 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5737 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5738 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ 5739 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ 5740 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ 5742 /* Bit 0 : Disable interrupt on TICK event. */ 5743 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 5744 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 5745 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ 5746 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ 5747 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ 5749 /* Register: RTC_EVTEN */ 5750 /* Description: Configures event enable routing to PPI for each RTC event. */ 5752 /* Bit 19 : COMPARE[3] event enable. */ 5753 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5754 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5755 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 5756 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 5758 /* Bit 18 : COMPARE[2] event enable. */ 5759 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5760 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5761 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 5762 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 5764 /* Bit 17 : COMPARE[1] event enable. */ 5765 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5766 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5767 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 5768 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 5770 /* Bit 16 : COMPARE[0] event enable. */ 5771 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5772 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5773 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 5774 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 5776 /* Bit 1 : OVRFLW event enable. */ 5777 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5778 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5779 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 5780 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 5782 /* Bit 0 : TICK event enable. */ 5783 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ 5784 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ 5785 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ 5786 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ 5788 /* Register: RTC_EVTENSET */ 5789 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ 5791 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ 5792 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5793 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5794 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 5795 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 5796 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ 5798 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ 5799 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5800 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5801 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 5802 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 5803 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ 5805 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ 5806 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5807 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5808 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 5809 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 5810 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ 5812 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ 5813 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5814 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5815 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 5816 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 5817 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ 5819 /* Bit 1 : Enable routing to PPI of OVRFLW event. */ 5820 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5821 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5822 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 5823 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 5824 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ 5826 /* Bit 0 : Enable routing to PPI of TICK event. */ 5827 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ 5828 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ 5829 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ 5830 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ 5831 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ 5833 /* Register: RTC_EVTENCLR */ 5834 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ 5836 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ 5837 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 5838 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 5839 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ 5840 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ 5841 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ 5843 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ 5844 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 5845 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 5846 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ 5847 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ 5848 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ 5850 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ 5851 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 5852 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 5853 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ 5854 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ 5855 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ 5857 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ 5858 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 5859 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 5860 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ 5861 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ 5862 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ 5864 /* Bit 1 : Disable routing to PPI of OVRFLW event. */ 5865 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ 5866 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ 5867 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ 5868 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ 5869 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ 5871 /* Bit 0 : Disable routing to PPI of TICK event. */ 5872 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ 5873 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ 5874 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ 5875 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ 5876 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ 5878 /* Register: RTC_COUNTER */ 5879 /* Description: Current COUNTER value. */ 5881 /* Bits 23..0 : Counter value. */ 5882 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ 5883 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ 5885 /* Register: RTC_PRESCALER */ 5886 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ 5888 /* Bits 11..0 : RTC PRESCALER value. */ 5889 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 5890 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 5892 /* Register: RTC_CC */ 5893 /* Description: Capture/compare registers. */ 5895 /* Bits 23..0 : Compare value. */ 5896 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ 5897 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ 5899 /* Register: RTC_POWER */ 5900 /* Description: Peripheral power control. */ 5902 /* Bit 0 : Peripheral power control. */ 5903 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5904 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5905 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5906 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 5909 /* Peripheral: SPI */ 5910 /* Description: SPI master 0. */ 5912 /* Register: SPI_INTENSET */ 5913 /* Description: Interrupt enable set register. */ 5915 /* Bit 2 : Enable interrupt on READY event. */ 5916 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ 5917 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ 5918 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5919 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5920 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ 5922 /* Register: SPI_INTENCLR */ 5923 /* Description: Interrupt enable clear register. */ 5925 /* Bit 2 : Disable interrupt on READY event. */ 5926 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ 5927 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ 5928 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ 5929 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ 5930 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ 5932 /* Register: SPI_ENABLE */ 5933 /* Description: Enable SPI. */ 5935 /* Bits 2..0 : Enable or disable SPI. */ 5936 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 5937 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 5938 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ 5939 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ 5941 /* Register: SPI_RXD */ 5942 /* Description: RX data. */ 5944 /* Bits 7..0 : RX data from last transfer. */ 5945 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 5946 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 5948 /* Register: SPI_TXD */ 5949 /* Description: TX data. */ 5951 /* Bits 7..0 : TX data for next transfer. */ 5952 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 5953 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 5955 /* Register: SPI_FREQUENCY */ 5956 /* Description: SPI frequency */ 5958 /* Bits 31..0 : SPI data rate. */ 5959 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 5960 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 5961 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ 5962 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ 5963 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ 5964 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ 5965 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ 5966 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ 5967 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ 5969 /* Register: SPI_CONFIG */ 5970 /* Description: Configuration register. */ 5972 /* Bit 2 : Serial clock (SCK) polarity. */ 5973 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 5974 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 5975 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 5976 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 5978 /* Bit 1 : Serial clock (SCK) phase. */ 5979 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 5980 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 5981 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 5982 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 5984 /* Bit 0 : Bit order. */ 5985 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 5986 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 5987 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 5988 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 5990 /* Register: SPI_POWER */ 5991 /* Description: Peripheral power control. */ 5993 /* Bit 0 : Peripheral power control. */ 5994 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 5995 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 5996 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 5997 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6000 /* Peripheral: SPIM */ 6001 /* Description: SPI master with easyDMA 1. */ 6003 /* Register: SPIM_SHORTS */ 6004 /* Description: Shortcuts for SPIM. */ 6006 /* Bit 17 : Shortcut between END event and START task. */ 6007 #define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */ 6008 #define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ 6009 #define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ 6010 #define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ 6012 /* Register: SPIM_INTENSET */ 6013 /* Description: Interrupt enable set register. */ 6015 /* Bit 19 : Enable interrupt on STARTED event. */ 6016 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 6017 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6018 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ 6019 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ 6020 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ 6022 /* Bit 8 : Enable interrupt on ENDTX event. */ 6023 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 6024 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 6025 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ 6026 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ 6027 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ 6029 /* Bit 6 : Enable interrupt on END event. */ 6030 #define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */ 6031 #define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */ 6032 #define SPIM_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 6033 #define SPIM_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 6034 #define SPIM_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 6036 /* Bit 4 : Enable interrupt on ENDRX event. */ 6037 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 6038 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 6039 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 6040 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 6041 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ 6043 /* Bit 1 : Enable interrupt on STOPPED event. */ 6044 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 6045 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6046 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 6047 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 6048 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ 6050 /* Register: SPIM_INTENCLR */ 6051 /* Description: Interrupt enable clear register. */ 6053 /* Bit 19 : Disable interrupt on STARTED event. */ 6054 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ 6055 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ 6056 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ 6057 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ 6058 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ 6060 /* Bit 8 : Disable interrupt on ENDTX event. */ 6061 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ 6062 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ 6063 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ 6064 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ 6065 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ 6067 /* Bit 6 : Disable interrupt on END event. */ 6068 #define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */ 6069 #define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 6070 #define SPIM_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 6071 #define SPIM_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 6072 #define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 6074 /* Bit 4 : Disable interrupt on ENDRX event. */ 6075 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ 6076 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ 6077 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ 6078 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ 6079 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ 6081 /* Bit 1 : Disable interrupt on STOPPED event. */ 6082 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 6083 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6084 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 6085 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 6086 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ 6088 /* Register: SPIM_ENABLE */ 6089 /* Description: Enable SPIM. */ 6091 /* Bits 3..0 : Enable or disable SPIM. */ 6092 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6093 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6094 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ 6095 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ 6097 /* Register: SPIM_RXDDATA */ 6098 /* Description: RXD register. */ 6100 /* Bits 7..0 : RX data received. Double buffered. */ 6101 #define SPIM_RXDDATA_RXD_Pos (0UL) /*!< Position of RXD field. */ 6102 #define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /*!< Bit mask of RXD field. */ 6104 /* Register: SPIM_TXDDATA */ 6105 /* Description: TXD register. */ 6107 /* Bits 7..0 : TX data to send. Double buffered. */ 6108 #define SPIM_TXDDATA_TXD_Pos (0UL) /*!< Position of TXD field. */ 6109 #define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /*!< Bit mask of TXD field. */ 6111 /* Register: SPIM_FREQUENCY */ 6112 /* Description: SPI frequency. */ 6114 /* Bits 31..0 : SPI master data rate. */ 6115 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 6116 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 6117 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ 6118 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ 6119 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ 6120 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ 6121 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ 6122 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ 6123 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ 6125 /* Register: SPIM_CONFIG */ 6126 /* Description: Configuration register. */ 6128 /* Bit 2 : Serial clock (SCK) polarity. */ 6129 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 6130 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 6131 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 6132 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 6134 /* Bit 1 : Serial clock (SCK) phase. */ 6135 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 6136 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 6137 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 6138 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 6140 /* Bit 0 : Bit order. */ 6141 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 6142 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 6143 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 6144 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 6146 /* Register: SPIM_ORC */ 6147 /* Description: Over-read character. */ 6149 /* Bits 7..0 : Over-read character. */ 6150 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 6151 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 6153 /* Register: SPIM_POWER */ 6154 /* Description: Peripheral power control. */ 6156 /* Bit 0 : Peripheral power control. */ 6157 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6158 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6159 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6160 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6162 /* Register: SPIM_RXD_PTR */ 6163 /* Description: Data pointer. */ 6165 /* Bits 31..0 : Data pointer. */ 6166 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6167 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6169 /* Register: SPIM_RXD_MAXCNT */ 6170 /* Description: Maximum number of buffer bytes to receive. */ 6172 /* Bits 7..0 : Maximum number of buffer bytes to receive. */ 6173 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6174 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6176 /* Register: SPIM_RXD_AMOUNT */ 6177 /* Description: Number of bytes received in the last transaction. */ 6179 /* Bits 7..0 : Number of bytes received in the last transaction. */ 6180 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6181 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6183 /* Register: SPIM_TXD_PTR */ 6184 /* Description: Data pointer. */ 6186 /* Bits 31..0 : Data pointer. */ 6187 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ 6188 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ 6190 /* Register: SPIM_TXD_MAXCNT */ 6191 /* Description: Maximum number of buffer bytes to send. */ 6193 /* Bits 7..0 : Maximum number of buffer bytes to send. */ 6194 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ 6195 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ 6197 /* Register: SPIM_TXD_AMOUNT */ 6198 /* Description: Number of bytes sent in the last transaction. */ 6200 /* Bits 7..0 : Number of bytes sent in the last transaction. */ 6201 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ 6202 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ 6205 /* Peripheral: SPIS */ 6206 /* Description: SPI slave 1. */ 6208 /* Register: SPIS_SHORTS */ 6209 /* Description: Shortcuts for SPIS. */ 6211 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */ 6212 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ 6213 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ 6214 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ 6215 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ 6217 /* Register: SPIS_INTENSET */ 6218 /* Description: Interrupt enable set register. */ 6220 /* Bit 10 : Enable interrupt on ACQUIRED event. */ 6221 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 6222 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 6223 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 6224 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 6225 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ 6227 /* Bit 1 : Enable interrupt on END event. */ 6228 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ 6229 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ 6230 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ 6231 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ 6232 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ 6234 /* Register: SPIS_INTENCLR */ 6235 /* Description: Interrupt enable clear register. */ 6237 /* Bit 10 : Disable interrupt on ACQUIRED event. */ 6238 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ 6239 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ 6240 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ 6241 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ 6242 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ 6244 /* Bit 1 : Disable interrupt on END event. */ 6245 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ 6246 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ 6247 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ 6248 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ 6249 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ 6251 /* Register: SPIS_SEMSTAT */ 6252 /* Description: Semaphore status. */ 6254 /* Bits 1..0 : Semaphore status. */ 6255 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ 6256 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ 6257 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ 6258 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ 6259 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ 6260 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ 6262 /* Register: SPIS_STATUS */ 6263 /* Description: Status from last transaction. */ 6265 /* Bit 1 : RX buffer overflow detected, and prevented. */ 6266 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ 6267 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ 6268 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ 6269 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ 6270 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ 6272 /* Bit 0 : TX buffer overread detected, and prevented. */ 6273 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ 6274 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ 6275 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ 6276 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ 6277 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ 6279 /* Register: SPIS_ENABLE */ 6280 /* Description: Enable SPIS. */ 6282 /* Bits 2..0 : Enable or disable SPIS. */ 6283 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6284 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6285 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ 6286 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ 6288 /* Register: SPIS_MAXRX */ 6289 /* Description: Maximum number of bytes in the receive buffer. */ 6291 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */ 6292 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ 6293 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ 6295 /* Register: SPIS_AMOUNTRX */ 6296 /* Description: Number of bytes received in last granted transaction. */ 6298 /* Bits 7..0 : Number of bytes received in last granted transaction. */ 6299 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ 6300 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ 6302 /* Register: SPIS_MAXTX */ 6303 /* Description: Maximum number of bytes in the transmit buffer. */ 6305 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ 6306 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ 6307 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ 6309 /* Register: SPIS_AMOUNTTX */ 6310 /* Description: Number of bytes transmitted in last granted transaction. */ 6312 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ 6313 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ 6314 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ 6316 /* Register: SPIS_CONFIG */ 6317 /* Description: Configuration register. */ 6319 /* Bit 2 : Serial clock (SCK) polarity. */ 6320 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ 6321 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ 6322 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ 6323 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ 6325 /* Bit 1 : Serial clock (SCK) phase. */ 6326 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ 6327 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ 6328 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ 6329 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ 6331 /* Bit 0 : Bit order. */ 6332 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ 6333 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ 6334 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ 6335 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ 6337 /* Register: SPIS_DEF */ 6338 /* Description: Default character. */ 6340 /* Bits 7..0 : Default character. */ 6341 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ 6342 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ 6344 /* Register: SPIS_ORC */ 6345 /* Description: Over-read character. */ 6347 /* Bits 7..0 : Over-read character. */ 6348 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ 6349 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ 6351 /* Register: SPIS_POWER */ 6352 /* Description: Peripheral power control. */ 6354 /* Bit 0 : Peripheral power control. */ 6355 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6356 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6357 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6358 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6361 /* Peripheral: TEMP */ 6362 /* Description: Temperature Sensor. */ 6364 /* Register: TEMP_INTENSET */ 6365 /* Description: Interrupt enable set register. */ 6367 /* Bit 0 : Enable interrupt on DATARDY event. */ 6368 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 6369 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 6370 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 6371 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 6372 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ 6374 /* Register: TEMP_INTENCLR */ 6375 /* Description: Interrupt enable clear register. */ 6377 /* Bit 0 : Disable interrupt on DATARDY event. */ 6378 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ 6379 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ 6380 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ 6381 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ 6382 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ 6384 /* Register: TEMP_POWER */ 6385 /* Description: Peripheral power control. */ 6387 /* Bit 0 : Peripheral power control. */ 6388 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6389 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6390 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6391 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6394 /* Peripheral: TIMER */ 6395 /* Description: Timer 0. */ 6397 /* Register: TIMER_SHORTS */ 6398 /* Description: Shortcuts for Timer. */ 6400 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */ 6401 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ 6402 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ 6403 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 6404 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 6406 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */ 6407 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ 6408 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ 6409 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 6410 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 6412 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */ 6413 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ 6414 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ 6415 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 6416 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 6418 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */ 6419 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ 6420 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ 6421 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 6422 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 6424 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ 6425 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ 6426 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ 6427 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 6428 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 6430 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ 6431 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ 6432 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ 6433 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 6434 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 6436 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ 6437 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ 6438 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ 6439 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 6440 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 6442 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ 6443 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ 6444 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ 6445 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ 6446 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ 6448 /* Register: TIMER_INTENSET */ 6449 /* Description: Interrupt enable set register. */ 6451 /* Bit 19 : Enable interrupt on COMPARE[3] */ 6452 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6453 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6454 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 6455 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 6456 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ 6458 /* Bit 18 : Enable interrupt on COMPARE[2] */ 6459 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6460 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6461 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 6462 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 6463 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ 6465 /* Bit 17 : Enable interrupt on COMPARE[1] */ 6466 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6467 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6468 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 6469 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 6470 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ 6472 /* Bit 16 : Enable interrupt on COMPARE[0] */ 6473 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6474 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6475 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 6476 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 6477 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ 6479 /* Register: TIMER_INTENCLR */ 6480 /* Description: Interrupt enable clear register. */ 6482 /* Bit 19 : Disable interrupt on COMPARE[3] */ 6483 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ 6484 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ 6485 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ 6486 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ 6487 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ 6489 /* Bit 18 : Disable interrupt on COMPARE[2] */ 6490 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ 6491 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ 6492 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ 6493 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ 6494 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ 6496 /* Bit 17 : Disable interrupt on COMPARE[1] */ 6497 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ 6498 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ 6499 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ 6500 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ 6501 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ 6503 /* Bit 16 : Disable interrupt on COMPARE[0] */ 6504 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ 6505 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ 6506 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ 6507 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ 6508 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ 6510 /* Register: TIMER_MODE */ 6511 /* Description: Timer Mode selection. */ 6513 /* Bit 0 : Select Normal or Counter mode. */ 6514 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ 6515 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ 6516 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ 6517 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ 6519 /* Register: TIMER_BITMODE */ 6520 /* Description: Sets timer behaviour. */ 6522 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ 6523 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ 6524 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ 6525 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ 6526 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ 6527 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ 6528 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ 6530 /* Register: TIMER_PRESCALER */ 6531 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ 6533 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ 6534 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ 6535 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ 6537 /* Register: TIMER_POWER */ 6538 /* Description: Peripheral power control. */ 6540 /* Bit 0 : Peripheral power control. */ 6541 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6542 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6543 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6544 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6547 /* Peripheral: TWI */ 6548 /* Description: Two-wire interface master 0. */ 6550 /* Register: TWI_SHORTS */ 6551 /* Description: Shortcuts for TWI. */ 6553 /* Bit 1 : Shortcut between BB event and the STOP task. */ 6554 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ 6555 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ 6556 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ 6557 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ 6559 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */ 6560 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ 6561 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ 6562 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ 6563 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ 6565 /* Register: TWI_INTENSET */ 6566 /* Description: Interrupt enable set register. */ 6568 /* Bit 18 : Enable interrupt on SUSPENDED event. */ 6569 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 6570 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 6571 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 6572 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 6573 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ 6575 /* Bit 14 : Enable interrupt on BB event. */ 6576 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ 6577 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ 6578 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ 6579 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ 6580 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ 6582 /* Bit 9 : Enable interrupt on ERROR event. */ 6583 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 6584 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 6585 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 6586 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 6587 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 6589 /* Bit 7 : Enable interrupt on TXDSENT event. */ 6590 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 6591 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 6592 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 6593 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 6594 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ 6596 /* Bit 2 : Enable interrupt on READY event. */ 6597 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 6598 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 6599 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 6600 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 6601 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ 6603 /* Bit 1 : Enable interrupt on STOPPED event. */ 6604 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 6605 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6606 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 6607 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 6608 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ 6610 /* Register: TWI_INTENCLR */ 6611 /* Description: Interrupt enable clear register. */ 6613 /* Bit 18 : Disable interrupt on SUSPENDED event. */ 6614 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ 6615 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ 6616 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ 6617 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ 6618 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ 6620 /* Bit 14 : Disable interrupt on BB event. */ 6621 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ 6622 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ 6623 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ 6624 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ 6625 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ 6627 /* Bit 9 : Disable interrupt on ERROR event. */ 6628 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 6629 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 6630 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 6631 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 6632 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 6634 /* Bit 7 : Disable interrupt on TXDSENT event. */ 6635 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ 6636 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ 6637 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ 6638 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ 6639 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ 6641 /* Bit 2 : Disable interrupt on RXDREADY event. */ 6642 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ 6643 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ 6644 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ 6645 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ 6646 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ 6648 /* Bit 1 : Disable interrupt on STOPPED event. */ 6649 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ 6650 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ 6651 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ 6652 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ 6653 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ 6655 /* Register: TWI_ERRORSRC */ 6656 /* Description: Two-wire error source. Write error field to 1 to clear error. */ 6658 /* Bit 2 : NACK received after sending a data byte. */ 6659 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ 6660 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ 6661 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ 6662 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ 6663 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ 6665 /* Bit 1 : NACK received after sending the address. */ 6666 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ 6667 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ 6668 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ 6669 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ 6670 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ 6672 /* Register: TWI_ENABLE */ 6673 /* Description: Enable two-wire master. */ 6675 /* Bits 2..0 : Enable or disable W2M */ 6676 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6677 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6678 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ 6679 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ 6681 /* Register: TWI_RXD */ 6682 /* Description: RX data register. */ 6684 /* Bits 7..0 : RX data from last transfer. */ 6685 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 6686 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 6688 /* Register: TWI_TXD */ 6689 /* Description: TX data register. */ 6691 /* Bits 7..0 : TX data for next transfer. */ 6692 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 6693 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 6695 /* Register: TWI_FREQUENCY */ 6696 /* Description: Two-wire frequency. */ 6698 /* Bits 31..0 : Two-wire master clock frequency. */ 6699 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ 6700 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ 6701 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ 6702 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ 6703 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ 6705 /* Register: TWI_ADDRESS */ 6706 /* Description: Address used in the two-wire transfer. */ 6708 /* Bits 6..0 : Two-wire address. */ 6709 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ 6710 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ 6712 /* Register: TWI_POWER */ 6713 /* Description: Peripheral power control. */ 6715 /* Bit 0 : Peripheral power control. */ 6716 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6717 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6718 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6719 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6722 /* Peripheral: UART */ 6723 /* Description: Universal Asynchronous Receiver/Transmitter. */ 6725 /* Register: UART_SHORTS */ 6726 /* Description: Shortcuts for UART. */ 6728 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */ 6729 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ 6730 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ 6731 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ 6732 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ 6734 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */ 6735 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ 6736 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ 6737 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ 6738 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ 6740 /* Register: UART_INTENSET */ 6741 /* Description: Interrupt enable set register. */ 6743 /* Bit 17 : Enable interrupt on RXTO event. */ 6744 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 6745 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ 6746 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 6747 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 6748 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ 6750 /* Bit 9 : Enable interrupt on ERROR event. */ 6751 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 6752 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ 6753 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 6754 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 6755 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ 6757 /* Bit 7 : Enable interrupt on TXRDY event. */ 6758 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 6759 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 6760 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 6761 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 6762 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 6764 /* Bit 2 : Enable interrupt on RXRDY event. */ 6765 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 6766 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 6767 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 6768 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 6769 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ 6771 /* Bit 1 : Enable interrupt on NCTS event. */ 6772 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 6773 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ 6774 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 6775 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 6776 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ 6778 /* Bit 0 : Enable interrupt on CTS event. */ 6779 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ 6780 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ 6781 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 6782 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 6783 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ 6785 /* Register: UART_INTENCLR */ 6786 /* Description: Interrupt enable clear register. */ 6788 /* Bit 17 : Disable interrupt on RXTO event. */ 6789 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ 6790 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ 6791 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ 6792 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ 6793 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ 6795 /* Bit 9 : Disable interrupt on ERROR event. */ 6796 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ 6797 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ 6798 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ 6799 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ 6800 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ 6802 /* Bit 7 : Disable interrupt on TXRDY event. */ 6803 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ 6804 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ 6805 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 6806 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 6807 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 6809 /* Bit 2 : Disable interrupt on RXRDY event. */ 6810 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ 6811 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ 6812 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ 6813 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ 6814 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ 6816 /* Bit 1 : Disable interrupt on NCTS event. */ 6817 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ 6818 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ 6819 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ 6820 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ 6821 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ 6823 /* Bit 0 : Disable interrupt on CTS event. */ 6824 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ 6825 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ 6826 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ 6827 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ 6828 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ 6830 /* Register: UART_ERRORSRC */ 6831 /* Description: Error source. Write error field to 1 to clear error. */ 6833 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ 6834 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ 6835 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ 6836 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ 6837 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ 6838 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ 6840 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ 6841 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ 6842 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ 6843 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ 6844 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ 6845 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ 6847 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ 6848 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 6849 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ 6850 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ 6851 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ 6852 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ 6854 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ 6855 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ 6856 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ 6857 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ 6858 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ 6859 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ 6861 /* Register: UART_ENABLE */ 6862 /* Description: Enable UART and acquire IOs. */ 6864 /* Bits 2..0 : Enable or disable UART and acquire IOs. */ 6865 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ 6866 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ 6867 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ 6868 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ 6870 /* Register: UART_RXD */ 6871 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ 6873 /* Bits 7..0 : RX data from previous transfer. Double buffered. */ 6874 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ 6875 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ 6877 /* Register: UART_TXD */ 6878 /* Description: TXD register. */ 6880 /* Bits 7..0 : TX data for transfer. */ 6881 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ 6882 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ 6884 /* Register: UART_BAUDRATE */ 6885 /* Description: UART Baudrate. */ 6887 /* Bits 31..0 : UART baudrate. */ 6888 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ 6889 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ 6890 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ 6891 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ 6892 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ 6893 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ 6894 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ 6895 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ 6896 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ 6897 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ 6898 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ 6899 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ 6900 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ 6901 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ 6902 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ 6903 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ 6904 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */ 6905 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ 6907 /* Register: UART_CONFIG */ 6908 /* Description: Configuration of parity and hardware flow control register. */ 6910 /* Bits 3..1 : Include parity bit. */ 6911 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ 6912 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ 6913 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ 6914 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ 6916 /* Bit 0 : Hardware flow control. */ 6917 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ 6918 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ 6919 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ 6920 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ 6922 /* Register: UART_POWER */ 6923 /* Description: Peripheral power control. */ 6925 /* Bit 0 : Peripheral power control. */ 6926 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 6927 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 6928 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 6929 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 6932 /* Peripheral: UICR */ 6933 /* Description: User Information Configuration. */ 6935 /* Register: UICR_RBPCONF */ 6936 /* Description: Readback protection configuration. */ 6938 /* Bits 15..8 : Readback protect all code in the device. */ 6939 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ 6940 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ 6941 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ 6942 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ 6944 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ 6945 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ 6946 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ 6947 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ 6948 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ 6950 /* Register: UICR_XTALFREQ */ 6951 /* Description: Reset value for CLOCK XTALFREQ register. */ 6953 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ 6954 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ 6955 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ 6956 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ 6957 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ 6959 /* Register: UICR_FWID */ 6960 /* Description: Firmware ID. */ 6962 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */ 6963 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ 6964 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ 6967 /* Peripheral: WDT */ 6968 /* Description: Watchdog Timer. */ 6970 /* Register: WDT_INTENSET */ 6971 /* Description: Interrupt enable set register. */ 6973 /* Bit 0 : Enable interrupt on TIMEOUT event. */ 6974 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 6975 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 6976 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 6977 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 6978 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ 6980 /* Register: WDT_INTENCLR */ 6981 /* Description: Interrupt enable clear register. */ 6983 /* Bit 0 : Disable interrupt on TIMEOUT event. */ 6984 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ 6985 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ 6986 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ 6987 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ 6988 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ 6990 /* Register: WDT_RUNSTATUS */ 6991 /* Description: Watchdog running status. */ 6993 /* Bit 0 : Watchdog running status. */ 6994 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ 6995 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ 6996 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ 6997 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ 6999 /* Register: WDT_REQSTATUS */ 7000 /* Description: Request status. */ 7002 /* Bit 7 : Request status for RR[7]. */ 7003 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ 7004 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ 7005 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ 7006 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ 7008 /* Bit 6 : Request status for RR[6]. */ 7009 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ 7010 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ 7011 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ 7012 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ 7014 /* Bit 5 : Request status for RR[5]. */ 7015 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ 7016 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ 7017 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ 7018 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ 7020 /* Bit 4 : Request status for RR[4]. */ 7021 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ 7022 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ 7023 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ 7024 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ 7026 /* Bit 3 : Request status for RR[3]. */ 7027 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ 7028 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ 7029 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ 7030 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ 7032 /* Bit 2 : Request status for RR[2]. */ 7033 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ 7034 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ 7035 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ 7036 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ 7038 /* Bit 1 : Request status for RR[1]. */ 7039 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ 7040 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ 7041 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ 7042 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ 7044 /* Bit 0 : Request status for RR[0]. */ 7045 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ 7046 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ 7047 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ 7048 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ 7050 /* Register: WDT_RREN */ 7051 /* Description: Reload request enable. */ 7053 /* Bit 7 : Enable or disable RR[7] register. */ 7054 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ 7055 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ 7056 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ 7057 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ 7059 /* Bit 6 : Enable or disable RR[6] register. */ 7060 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ 7061 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ 7062 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ 7063 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ 7065 /* Bit 5 : Enable or disable RR[5] register. */ 7066 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ 7067 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ 7068 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ 7069 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ 7071 /* Bit 4 : Enable or disable RR[4] register. */ 7072 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ 7073 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ 7074 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ 7075 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ 7077 /* Bit 3 : Enable or disable RR[3] register. */ 7078 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ 7079 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ 7080 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ 7081 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ 7083 /* Bit 2 : Enable or disable RR[2] register. */ 7084 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ 7085 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ 7086 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ 7087 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ 7089 /* Bit 1 : Enable or disable RR[1] register. */ 7090 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ 7091 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ 7092 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ 7093 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ 7095 /* Bit 0 : Enable or disable RR[0] register. */ 7096 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ 7097 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ 7098 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ 7099 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ 7101 /* Register: WDT_CONFIG */ 7102 /* Description: Configuration register. */ 7104 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ 7105 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ 7106 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ 7107 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ 7108 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ 7110 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ 7111 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ 7112 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ 7113 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ 7114 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ 7116 /* Register: WDT_RR */ 7117 /* Description: Reload requests registers. */ 7119 /* Bits 31..0 : Reload register. */ 7120 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ 7121 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ 7122 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ 7124 /* Register: WDT_POWER */ 7125 /* Description: Peripheral power control. */ 7127 /* Bit 0 : Peripheral power control. */ 7128 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ 7129 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ 7130 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ 7131 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ 7134 /*lint --flb "Leave library region" */
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