tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_ARM_STD/TARGET_LPC11U68/startup_LPC11U6x.s

   1 ;/**************************************************************************//**
   2 ; * @file     startup_LPC11U6x.s
   3 ; * @brief    CMSIS Cortex-M0+ Core Device Startup File for
   4 ; *           NXP LPC11U6x Device Series
   5 ; * @version  V1.00
   6 ; * @date     22. October 2013
   7 ; *
   8 ; * @note
   9 ; * Copyright (C) 2013 ARM Limited. All rights reserved.
  10 ; *
  11 ; * @par
  12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13 ; * processor based microcontrollers.  This file can be freely distributed
  14 ; * within development tools that are supporting such ARM based processors.
  15 ; *
  16 ; * @par
  17 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22 ; *
  23 ; ******************************************************************************/
  24
  25 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  26
  27 ; <h> Stack Configuration
  28 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  29 ; </h>
  30
  31                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  32                 EXPORT  __initial_sp
  33
  34 __initial_sp        EQU     0x10008000  ; Top of RAM from LPC1U68
  35
  36
  37 ; <h> Heap Configuration
  38 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  39 ; </h>
  40
  41 Heap_Size       EQU     0x00000000
  42
  43                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  44 __heap_base
  45 Heap_Mem        SPACE   Heap_Size
  46 __heap_limit
  47
  48
  49                 PRESERVE8
  50                 THUMB
  51
  52
  53 ; Vector Table Mapped to Address 0 at Reset
  54
  55                 AREA    RESET, DATA, READONLY
  56                 EXPORT  __Vectors
  57
  58 __Vectors       DCD     __initial_sp              ; Top of Stack
  59                 DCD     Reset_Handler             ; Reset Handler
  60                 DCD     NMI_Handler               ; NMI Handler
  61                 DCD     HardFault_Handler         ; Hard Fault Handler
  62                 DCD     0                         ; Reserved
  63                 DCD     0                         ; Reserved
  64                 DCD     0                         ; Reserved
  65                 DCD     0                         ; Reserved
  66                 DCD     0                         ; Reserved
  67                 DCD     0                         ; Reserved
  68                 DCD     0                         ; Reserved
  69                 DCD     SVC_Handler               ; SVCall Handler
  70                 DCD     0                         ; Reserved
  71                 DCD     0                         ; Reserved
  72                 DCD     PendSV_Handler            ; PendSV Handler
  73                 DCD     SysTick_Handler           ; SysTick Handler
  74
  75                 ; External Interrupts
  76                 DCD     PIN_INT0_IRQHandler       ; 16+ 0  GPIO pin interrupt 0
  77                 DCD     PIN_INT1_IRQHandler       ; 16+ 1  GPIO pin interrupt 1
  78                 DCD     PIN_INT2_IRQHandler       ; 16+ 2  GPIO pin interrupt 2
  79                 DCD     PIN_INT3_IRQHandler       ; 16+ 3  GPIO pin interrupt 3
  80                 DCD     PIN_INT4_IRQHandler       ; 16+ 4  GPIO pin interrupt 4
  81                 DCD     PIN_INT5_IRQHandler       ; 16+ 5  GPIO pin interrupt 5
  82                 DCD     PIN_INT6_IRQHandler       ; 16+ 6  GPIO pin interrupt 6
  83                 DCD     PIN_INT7_IRQHandler       ; 16+ 7  GPIO pin interrupt 7
  84                 DCD     GINT0_IRQHandler          ; 16+ 8  GPIO GROUP0 interrupt
  85                 DCD     GINT1_IRQHandler          ; 16+ 9  GPIO GROUP1 interrupt
  86                 DCD     I2C1_IRQHandler           ; 16+10  I2C1 interrupt
  87                 DCD     USART1_4_IRQHandler       ; 16+11  Combined USART1 and USART4 interrupts
  88                 DCD     USART2_3_IRQHandler       ; 16+12  Combined USART2 and USART3 interrupts
  89                 DCD     SCT0_1_IRQHandler         ; 16+13  Combined SCT0 and SCT1 interrupts
  90                 DCD     SSP1_IRQHandler           ; 16+14  SSP1 interrupt
  91                 DCD     I2C0_IRQHandler           ; 16+15  I2C0 interrupt
  92                 DCD     CT16B0_IRQHandler         ; 16+16  CT16B0 interrupt
  93                 DCD     CT16B1_IRQHandler         ; 16+17  CT16B1 interrupt
  94                 DCD     CT32B0_IRQHandler         ; 16+18  CT32B0 interrupt
  95                 DCD     CT32B1_IRQHandler         ; 16+19  CT32B1 interrupt
  96                 DCD     SSP0_IRQHandler           ; 16+20  SSP0 interrupt
  97                 DCD     USART0_IRQHandler         ; 16+21  USART0 interrupt
  98                 DCD     USB_IRQHandler            ; 16+22  USB interrupt
  99                 DCD     USB_FIQ_IRQHandler        ; 16+23  USB_FIQ interrupt
 100                 DCD     ADC_A_IRQHandler          ; 16+24  Combined ADC_A end-of-sequence A and threshold crossing interrupts
 101                 DCD     RTC_IRQHandler            ; 16+25  RTC interrupt
 102                 DCD     BOD_WDT_IRQHandler        ; 16+26  Combined BOD and WWDT interrupt
 103                 DCD     FLASH_IRQHandler          ; 16+27  Combined flash and EEPROM controller interrupts
 104                 DCD     DMA_IRQHandler            ; 16+28  DMA interrupt
 105                 DCD     ADC_B_IRQHandler          ; 16+29  Combined ADC_A end-of-sequence A and threshold crossing interrupts
 106                 DCD     USBWAKEUP_IRQHandler      ; 16+30  USB_WAKEUP interrupt
 107                 DCD     0                         ; 16+31  Reserved
 108
 109 ; <h> Code Read Protection
 110 ;   <o> Code Read Protection  <0xFFFFFFFF=>CRP Disabled
 111 ;                             <0x12345678=>CRP Level 1
 112 ;                             <0x87654321=>CRP Level 2
 113 ;                             <0x43218765=>CRP Level 3 (ARE YOU SURE?)
 114 ;                             <0x4E697370=>NO ISP (ARE YOU SURE?)
 115 ; </h>
 116                 IF      :LNOT::DEF:NO_CRP
 117                 AREA    |.ARM.__at_0x02FC|, CODE, READONLY
 118                 DCD     0xFFFFFFFF
 119                 ENDIF
 120
 121                 AREA    |.text|, CODE, READONLY
 122
 123
 124 ; Reset Handler
 125
 126 Reset_Handler   PROC
 127                 EXPORT  Reset_Handler             [WEAK]
 128                 IMPORT  SystemInit
 129                 IMPORT  __main
 130                 LDR     R0, =SystemInit
 131                 BLX     R0
 132                 LDR     R0, =__main
 133                 BX      R0
 134                 ENDP
 135
 136
 137 ; Dummy Exception Handlers (infinite loops which can be modified)
 138
 139 NMI_Handler     PROC
 140                 EXPORT  NMI_Handler               [WEAK]
 141                 B       .
 142                 ENDP
 143 HardFault_Handler\
 144                 PROC
 145                 EXPORT  HardFault_Handler         [WEAK]
 146                 B       .
 147                 ENDP
 148 SVC_Handler     PROC
 149                 EXPORT  SVC_Handler               [WEAK]
 150                 B       .
 151                 ENDP
 152 PendSV_Handler  PROC
 153                 EXPORT  PendSV_Handler            [WEAK]
 154                 B       .
 155                 ENDP
 156 SysTick_Handler PROC
 157                 EXPORT  SysTick_Handler           [WEAK]
 158                 B       .
 159                 ENDP
 160 Reserved_IRQHandler PROC
 161                 EXPORT  Reserved_IRQHandler       [WEAK]
 162                 B       .
 163                 ENDP
 164
 165 Default_Handler PROC
 166                 EXPORT  PIN_INT0_IRQHandler       [WEAK]
 167                 EXPORT  PIN_INT1_IRQHandler       [WEAK]
 168                 EXPORT  PIN_INT2_IRQHandler       [WEAK]
 169                 EXPORT  PIN_INT3_IRQHandler       [WEAK]
 170                 EXPORT  PIN_INT4_IRQHandler       [WEAK]
 171                 EXPORT  PIN_INT5_IRQHandler       [WEAK]
 172                 EXPORT  PIN_INT6_IRQHandler       [WEAK]
 173                 EXPORT  PIN_INT7_IRQHandler       [WEAK]
 174                 EXPORT  GINT0_IRQHandler          [WEAK]
 175                 EXPORT  GINT1_IRQHandler          [WEAK]
 176                 EXPORT  I2C1_IRQHandler           [WEAK]
 177                 EXPORT  USART1_4_IRQHandler       [WEAK]
 178                 EXPORT  USART2_3_IRQHandler       [WEAK]
 179                 EXPORT  SCT0_1_IRQHandler         [WEAK]
 180                 EXPORT  SSP1_IRQHandler           [WEAK]
 181                 EXPORT  I2C0_IRQHandler           [WEAK]
 182                 EXPORT  CT16B0_IRQHandler         [WEAK]
 183                 EXPORT  CT16B1_IRQHandler         [WEAK]
 184                 EXPORT  CT32B0_IRQHandler         [WEAK]
 185                 EXPORT  CT32B1_IRQHandler         [WEAK]
 186                 EXPORT  SSP0_IRQHandler           [WEAK]
 187                 EXPORT  USART0_IRQHandler         [WEAK]
 188                 EXPORT  USB_IRQHandler            [WEAK]
 189                 EXPORT  USB_FIQ_IRQHandler        [WEAK]
 190                 EXPORT  ADC_A_IRQHandler          [WEAK]
 191                 EXPORT  RTC_IRQHandler            [WEAK]
 192                 EXPORT  BOD_WDT_IRQHandler        [WEAK]
 193                 EXPORT  FLASH_IRQHandler          [WEAK]
 194                 EXPORT  DMA_IRQHandler            [WEAK]
 195                 EXPORT  ADC_B_IRQHandler          [WEAK]
 196                 EXPORT  USBWAKEUP_IRQHandler      [WEAK]
 197
 198 PIN_INT0_IRQHandler
 199 PIN_INT1_IRQHandler
 200 PIN_INT2_IRQHandler
 201 PIN_INT3_IRQHandler
 202 PIN_INT4_IRQHandler
 203 PIN_INT5_IRQHandler
 204 PIN_INT6_IRQHandler
 205 PIN_INT7_IRQHandler
 206 GINT0_IRQHandler
 207 GINT1_IRQHandler
 208 I2C1_IRQHandler
 209 USART1_4_IRQHandler
 210 USART2_3_IRQHandler
 211 SCT0_1_IRQHandler
 212 SSP1_IRQHandler
 213 I2C0_IRQHandler
 214 CT16B0_IRQHandler
 215 CT16B1_IRQHandler
 216 CT32B0_IRQHandler
 217 CT32B1_IRQHandler
 218 SSP0_IRQHandler
 219 USART0_IRQHandler
 220 USB_IRQHandler
 221 USB_FIQ_IRQHandler
 222 ADC_A_IRQHandler
 223 RTC_IRQHandler
 224 BOD_WDT_IRQHandler
 225 FLASH_IRQHandler
 226 DMA_IRQHandler
 227 ADC_B_IRQHandler
 228 USBWAKEUP_IRQHandler
 229
 230                 B       .
 231
 232                 ENDP
 233
 234
 235                 ALIGN
 236
 237
 238 ; User Initial Stack & Heap
 239
 240                 EXPORT  __initial_sp
 241                 EXPORT  __heap_base
 242                 EXPORT  __heap_limit
 243
 244                 END