tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11U6X/TOOLCHAIN_IAR/TARGET_LPC11U68/startup_LPC11U6X.s

   1 ;/*****************************************************************************
   2 ; * @file:    startup_LPC11u6x.s
   3 ; * @purpose: CMSIS Cortex-M0PLUS Core Device Startup File
   4 ; *           for the NXP LPC11u6x Device Series (manually edited)
   5 ; * @version: V1.00
   6 ; * @date:    19. October 2009
   7 ; *----------------------------------------------------------------------------
   8 ; *
   9 ; * Copyright (C) 2009 ARM Limited. All rights reserved.
  10 ; *
  11 ; * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
  12 ; * processor based microcontrollers.  This file can be freely distributed
  13 ; * within development tools that are supporting such ARM based processors.
  14 ; *
  15 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  16 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  17 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  18 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  19 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  20 ; *
  21 ; ******************************************************************************/
  22
  23 ;
  24 ; The modules in this file are included in the libraries, and may be replaced
  25 ; by any user-defined modules that define the PUBLIC symbol _program_start or
  26 ; a user defined start symbol.
  27 ; To override the cstartup defined in the library, simply add your modified
  28 ; version to the workbench project.
  29 ;
  30 ; The vector table is normally located at address 0.
  31 ; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
  32 ; The name "__vector_table" has special meaning for C-SPY:
  33 ; it is where the SP start value is found, and the NVIC vector
  34 ; table register (VTOR) is initialized to this address if != 0.
  35 ;
  36 ; Cortex-M version
  37 ;
  38
  39         MODULE  ?cstartup
  40
  41         ;; Forward declaration of sections.
  42         SECTION CSTACK:DATA:NOROOT(3)
  43
  44         SECTION .intvec:CODE:NOROOT(2)
  45
  46         EXTERN  __iar_program_start
  47         EXTERN  SystemInit
  48         PUBLIC  __vector_table
  49         PUBLIC  __vector_table_0x1c
  50         PUBLIC  __Vectors
  51         PUBLIC  __Vectors_End
  52         PUBLIC  __Vectors_Size
  53
  54         DATA
  55
  56 __vector_table
  57         DCD     sfe(CSTACK)
  58         DCD     Reset_Handler
  59
  60         DCD     NMI_Handler
  61         DCD     HardFault_Handler
  62         DCD     0
  63         DCD     0
  64         DCD     0
  65 __vector_table_0x1c
  66         DCD     0
  67         DCD     0
  68         DCD     0
  69         DCD     0
  70         DCD     SVC_Handler
  71         DCD     0
  72         DCD     0
  73         DCD     PendSV_Handler
  74         DCD     SysTick_Handler
  75
  76         DCD PIN_INT0_IRQHandler           ; Pin interrupt 0
  77         DCD PIN_INT1_IRQHandler           ; Pin interrupt 1
  78         DCD PIN_INT2_IRQHandler           ; Pin interrupt 2
  79         DCD PIN_INT3_IRQHandler           ; Pin interrupt 3
  80         DCD PIN_INT4_IRQHandler           ; Pin interrupt 4
  81         DCD PIN_INT5_IRQHandler           ; Pin interrupt 5
  82         DCD PIN_INT6_IRQHandler           ; Pin interrupt 6
  83         DCD PIN_INT7_IRQHandler           ; Pin interrupt 7
  84         DCD GINT0_IRQHandler              ; Port interrupt group 0
  85         DCD GINT1_IRQHandler              ; Port interrupt group 1
  86         DCD I2C1_IRQHandler               ; I2C1 interrupt
  87         DCD USART1_4_IRQHandler           ; USARTS 1 and 4 shared interrupt
  88         DCD USART2_3_IRQHandler           ; USARTS 2 and 3 shared interrupt
  89         DCD SCT0_1_IRQHandler             ; SCT 0 and 1 shared interrupt
  90         DCD SSP1_IRQHandler               ; SSP1 interrupt
  91         DCD I2C0_IRQHandler               ; I2C0 interrupt
  92         DCD CT16B0_IRQHandler          ; CT16B0 (16-bit Timer 0)
  93         DCD CT16B1_IRQHandler          ; CT16B1 (16-bit Timer 1)
  94         DCD CT32B0_IRQHandler          ; CT32B0 (32-bit Timer 0)
  95         DCD CT32B1_IRQHandler          ; CT32B0 (32-bit Timer 1)
  96         DCD SSP0_IRQHandler               ; SSP0 interrupt interrupt
  97         DCD USART0_IRQHandler             ; USART 0 interrupt interrupt
  98         DCD USB_IRQHandler                ; USB IRQ interrupt
  99         DCD USB_FIQ_IRQHandler                ; USB FIQ interrupt
 100         DCD ADC_A_IRQHandler               ; ADC A sequence (A/D Converter) interrupt
 101         DCD RTC_IRQHandler                ; RTC interrupt
 102         DCD BOD_WDT_IRQHandler            ; Shared BOD (Brownout Detect) and WDT interrupts
 103         DCD FLASH_IRQHandler                ; Flash Memory Controller interrupt
 104         DCD DMA_IRQHandler                ; DMA Controller interrupt
 105         DCD ADC_B_IRQHandler               ; ADC B sequence interrupt
 106         DCD USBWakeup_IRQHandler          ; USB wake-up interrupt
 107         DCD Reserved_IRQHandler
 108
 109 __Vectors_End
 110
 111 __Vectors       EQU   __vector_table
 112 __Vectors_Size  EQU     __Vectors_End - __Vectors
 113
 114
 115 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 116 ;;
 117 ;; Default interrupt handlers.
 118 ;;
 119         THUMB
 120         PUBWEAK Reset_Handler
 121         SECTION .text:CODE:NOROOT:REORDER(2)
 122 Reset_Handler
 123         LDR     R0, =SystemInit
 124         BLX     R0
 125         LDR     R0, =__iar_program_start
 126         BX      R0
 127
 128         PUBWEAK NMI_Handler
 129         SECTION .text:CODE:REORDER:NOROOT(1)
 130 NMI_Handler
 131         B .
 132
 133         PUBWEAK HardFault_Handler
 134         SECTION .text:CODE:REORDER:NOROOT(1)
 135 HardFault_Handler
 136         B .
 137
 138         PUBWEAK SVC_Handler
 139         SECTION .text:CODE:REORDER:NOROOT(1)
 140 SVC_Handler
 141         B .
 142
 143         PUBWEAK PendSV_Handler
 144         SECTION .text:CODE:REORDER:NOROOT(1)
 145 PendSV_Handler
 146         B .
 147
 148         PUBWEAK SysTick_Handler
 149         SECTION .text:CODE:REORDER:NOROOT(1)
 150 SysTick_Handler
 151         B .
 152
 153         PUBWEAK Reserved_IRQHandler
 154         SECTION .text:CODE:REORDER:NOROOT(1)
 155 Reserved_IRQHandler
 156         B .
 157
 158
 159                 PUBWEAK  PIN_INT0_IRQHandler
 160                 PUBWEAK  PIN_INT1_IRQHandler
 161                 PUBWEAK  PIN_INT2_IRQHandler
 162                 PUBWEAK  PIN_INT3_IRQHandler
 163                 PUBWEAK  PIN_INT4_IRQHandler
 164                 PUBWEAK  PIN_INT5_IRQHandler
 165                 PUBWEAK  PIN_INT6_IRQHandler
 166                 PUBWEAK  PIN_INT7_IRQHandler
 167                 PUBWEAK  GINT0_IRQHandler
 168                 PUBWEAK  GINT1_IRQHandler
 169                 PUBWEAK  I2C1_IRQHandler
 170                 PUBWEAK USART1_4_IRQHandler
 171                 PUBWEAK USART2_3_IRQHandler
 172                 PUBWEAK  SCT0_1_IRQHandler
 173                 PUBWEAK  SSP1_IRQHandler
 174                 PUBWEAK  I2C0_IRQHandler
 175                 PUBWEAK CT16B0_IRQHandler
 176                 PUBWEAK CT16B1_IRQHandler
 177                 PUBWEAK CT32B0_IRQHandler
 178                 PUBWEAK CT32B1_IRQHandler
 179                 PUBWEAK SSP0_IRQHandler
 180                 PUBWEAK USART0_IRQHandler
 181                 PUBWEAK USB_IRQHandler
 182                 PUBWEAK USB_FIQ_IRQHandler
 183                 PUBWEAK ADC_A_IRQHandler
 184                 PUBWEAK RTC_IRQHandler
 185                 PUBWEAK BOD_WDT_IRQHandler
 186                 PUBWEAK FLASH_IRQHandler
 187                 PUBWEAK DMA_IRQHandler
 188                 PUBWEAK ADC_B_IRQHandler
 189                 PUBWEAK USBWakeup_IRQHandler
 190
 191         SECTION .text:CODE:REORDER:NOROOT(1)
 192         THUMB
 193
 194 PIN_INT0_IRQHandler
 195 PIN_INT1_IRQHandler
 196 PIN_INT2_IRQHandler
 197 PIN_INT3_IRQHandler
 198 PIN_INT4_IRQHandler
 199 PIN_INT5_IRQHandler
 200 PIN_INT6_IRQHandler
 201 PIN_INT7_IRQHandler
 202 GINT0_IRQHandler
 203 GINT1_IRQHandler
 204 I2C1_IRQHandler
 205 USART1_4_IRQHandler
 206 USART2_3_IRQHandler
 207 SCT0_1_IRQHandler
 208 SSP1_IRQHandler
 209 I2C0_IRQHandler
 210 CT16B0_IRQHandler
 211 CT16B1_IRQHandler
 212 CT32B0_IRQHandler
 213 CT32B1_IRQHandler
 214 SSP0_IRQHandler
 215 USART0_IRQHandler
 216 USB_IRQHandler
 217 USB_FIQ_IRQHandler
 218 ADC_A_IRQHandler
 219 RTC_IRQHandler
 220 BOD_WDT_IRQHandler
 221 FLASH_IRQHandler
 222 DMA_IRQHandler
 223 ADC_B_IRQHandler
 224 USBWakeup_IRQHandler
 225 Default_Handler
 226         B Default_Handler
 227
 228         SECTION .crp:CODE:ROOT(2)
 229         DATA
 230 /* Code Read Protection
 231 NO_ISP  0x4E697370 -  Prevents sampling of pin PIO0_1 for entering ISP mode
 232 CRP1    0x12345678 - Write to RAM command cannot access RAM below 0x10000300.
 233                    - Copy RAM to flash command can not write to Sector 0.
 234                    - Erase command can erase Sector 0 only when all sectors
 235                      are selected for erase.
 236                    - Compare command is disabled.
 237                    - Read Memory command is disabled.
 238 CRP2    0x87654321 - Read Memory is disabled.
 239                    - Write to RAM is disabled.
 240                    - "Go" command is disabled.
 241                    - Copy RAM to flash is disabled.
 242                    - Compare is disabled.
 243 CRP3    0x43218765 - Access to chip via the SWD pins is disabled. ISP entry
 244                      by pulling PIO0_1 LOW is disabled if a valid user code is
 245                      present in flash sector 0.
 246 Caution: If CRP3 is selected, no future factory testing can be
 247 performed on the device.
 248 */
 249         DCD     0xFFFFFFFF
 250
 251         END