tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/LPC11xx.h

   1 /****************************************************************************
   2  *   $Id:: LPC11xx.h 9198 2012-05-29 usb00175                     $
   3  *   Project: NXP LPC11xx software example
   4  *
   5  *   Description:
   6  *     CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
   7  *     NXP LPC11xx Device Series
   8
   9  ****************************************************************************
  10  * Software that is described herein is for illustrative purposes only
  11 * which provides customers with programming information regarding the
  12 * products. This software is supplied "AS IS" without any warranties.
  13 * NXP Semiconductors assumes no responsibility or liability for the
  14 * use of the software, conveys no license or title under any patent,
  15 * copyright, or mask work right to the product. NXP Semiconductors
  16 * reserves the right to make changes in the software without
  17 * notification. NXP Semiconductors also make no representation or
  18 * warranty that such application will be suitable for the specified
  19 * use without further testing or modification.
  20
  21 * Permission to use, copy, modify, and distribute this software and its
  22 * documentation is hereby granted, under NXP Semiconductors'
  23 * relevant copyright in the software, without fee, provided that it
  24 * is used in conjunction with NXP Semiconductors microcontrollers.  This
  25 * copyright, permission, and disclaimer notice must appear in all copies of
  26 * this code.
  27
  28 ****************************************************************************/
  29 #ifndef __LPC11xx_H__
  30 #define __LPC11xx_H__
  31
  32 #ifdef __cplusplus
  33  extern "C" {
  34 #endif
  35
  36 /** @addtogroup LPC11xx_Definitions LPC11xx Definitions
  37   This file defines all structures and symbols for LPC11xx:
  38     - Registers and bitfields
  39     - peripheral base address
  40     - peripheral ID
  41     - PIO definitions
  42   @{
  43 */
  44
  45
  46 /******************************************************************************/
  47 /*                Processor and Core Peripherals                              */
  48 /******************************************************************************/
  49 /** @addtogroup LPC11xx_CMSIS LPC11xx CMSIS Definitions
  50   Configuration of the Cortex-M0 Processor and Core Peripherals
  51   @{
  52 */
  53
  54 /*
  55  * ==========================================================================
  56  * ---------- Interrupt Number Definition -----------------------------------
  57  * ==========================================================================
  58  */
  59 typedef enum IRQn
  60 {
  61 /******  Cortex-M0 Processor Exceptions Numbers ***************************************************/
  62   NonMaskableInt_IRQn           = -14,    /*!< 2 Non Maskable Interrupt                           */
  63   HardFault_IRQn                = -13,    /*!< 3 Cortex-M0 Hard Fault Interrupt                   */
  64   SVCall_IRQn                   = -5,     /*!< 11 Cortex-M0 SV Call Interrupt                     */
  65   PendSV_IRQn                   = -2,     /*!< 14 Cortex-M0 Pend SV Interrupt                     */
  66   SysTick_IRQn                  = -1,     /*!< 15 Cortex-M0 System Tick Interrupt                 */
  67
  68 /******  LPC11Cxx or LPC11xx Specific Interrupt Numbers *******************************************************/
  69   WAKEUP0_IRQn                  = 0,        /*!< All I/O pins can be used as wakeup source.       */
  70   WAKEUP1_IRQn                  = 1,        /*!< There are 13 pins in total for LPC11xx           */
  71   WAKEUP2_IRQn                  = 2,
  72   WAKEUP3_IRQn                  = 3,
  73   WAKEUP4_IRQn                  = 4,
  74   WAKEUP5_IRQn                  = 5,
  75   WAKEUP6_IRQn                  = 6,
  76   WAKEUP7_IRQn                  = 7,
  77   WAKEUP8_IRQn                  = 8,
  78   WAKEUP9_IRQn                  = 9,
  79   WAKEUP10_IRQn                 = 10,
  80   WAKEUP11_IRQn                 = 11,
  81   WAKEUP12_IRQn                 = 12,
  82   CAN_IRQn                      = 13,       /*!< CAN Interrupt                                    */
  83   SSP1_IRQn                     = 14,       /*!< SSP1 Interrupt                                   */
  84   I2C_IRQn                      = 15,       /*!< I2C Interrupt                                    */
  85   TIMER_16_0_IRQn               = 16,       /*!< 16-bit Timer0 Interrupt                          */
  86   TIMER_16_1_IRQn               = 17,       /*!< 16-bit Timer1 Interrupt                          */
  87   TIMER_32_0_IRQn               = 18,       /*!< 32-bit Timer0 Interrupt                          */
  88   TIMER_32_1_IRQn               = 19,       /*!< 32-bit Timer1 Interrupt                          */
  89   SSP0_IRQn                     = 20,       /*!< SSP0 Interrupt                                   */
  90   UART_IRQn                     = 21,       /*!< UART Interrupt                                   */
  91   Reserved0_IRQn                = 22,       /*!< Reserved Interrupt                               */
  92   Reserved1_IRQn                = 23,
  93   ADC_IRQn                      = 24,       /*!< A/D Converter Interrupt                          */
  94   WDT_IRQn                      = 25,       /*!< Watchdog timer Interrupt                         */
  95   BOD_IRQn                      = 26,       /*!< Brown Out Detect(BOD) Interrupt                  */
  96   FMC_IRQn                      = 27,       /*!< Flash Memory Controller Interrupt                */
  97   EINT3_IRQn                    = 28,       /*!< External Interrupt 3 Interrupt                   */
  98   EINT2_IRQn                    = 29,       /*!< External Interrupt 2 Interrupt                   */
  99   EINT1_IRQn                    = 30,       /*!< External Interrupt 1 Interrupt                   */
 100   EINT0_IRQn                    = 31,       /*!< External Interrupt 0 Interrupt                   */
 101 } IRQn_Type;
 102
 103 /*
 104  * ==========================================================================
 105  * ----------- Processor and Core Peripheral Section ------------------------
 106  * ==========================================================================
 107  */
 108
 109 /* Configuration of the Cortex-M0 Processor and Core Peripherals */
 110 #define __MPU_PRESENT             0         /*!< MPU present or not                               */
 111 #define __NVIC_PRIO_BITS          2         /*!< Number of Bits used for Priority Levels          */
 112 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
 113
 114 /*@}*/ /* end of group LPC11xx_CMSIS */
 115
 116
 117 #include "core_cm0.h"                       /* Cortex-M0 processor and core peripherals           */
 118 #include "system_LPC11xx.h"                 /* System Header                                      */
 119
 120
 121 /******************************************************************************/
 122 /*                Device Specific Peripheral Registers structures             */
 123 /******************************************************************************/
 124
 125 #if defined ( __CC_ARM   )
 126 #pragma anon_unions
 127 #endif
 128
 129 /*------------- System Control (SYSCON) --------------------------------------*/
 130 /** @addtogroup LPC11xx_SYSCON LPC11xx System Control Block
 131   @{
 132 */
 133 typedef struct
 134 {
 135   __IO uint32_t SYSMEMREMAP;            /*!< Offset: 0x000 System memory remap (R/W) */
 136   __IO uint32_t PRESETCTRL;             /*!< Offset: 0x004 Peripheral reset control (R/W) */
 137   __IO uint32_t SYSPLLCTRL;             /*!< Offset: 0x008 System PLL control (R/W) */
 138   __I uint32_t SYSPLLSTAT;             /*!< Offset: 0x00C System PLL status (R/ ) */
 139        uint32_t RESERVED0[4];
 140
 141   __IO uint32_t SYSOSCCTRL;             /*!< Offset: 0x020 System oscillator control (R/W) */
 142   __IO uint32_t WDTOSCCTRL;             /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
 143   __IO uint32_t IRCCTRL;                /*!< Offset: 0x028 IRC control (R/W) */
 144        uint32_t RESERVED1[1];
 145   __IO uint32_t SYSRSTSTAT;             /*!< Offset: 0x030 System reset status Register (R/ ) */
 146        uint32_t RESERVED2[3];
 147   __IO uint32_t SYSPLLCLKSEL;           /*!< Offset: 0x040 System PLL clock source select (R/W) */
 148   __IO uint32_t SYSPLLCLKUEN;           /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
 149        uint32_t RESERVED3[10];
 150
 151   __IO uint32_t MAINCLKSEL;             /*!< Offset: 0x070 Main clock source select (R/W) */
 152   __IO uint32_t MAINCLKUEN;             /*!< Offset: 0x074 Main clock source update enable (R/W) */
 153   __IO uint32_t SYSAHBCLKDIV;           /*!< Offset: 0x078 System AHB clock divider (R/W) */
 154        uint32_t RESERVED4[1];
 155
 156   __IO uint32_t SYSAHBCLKCTRL;          /*!< Offset: 0x080 System AHB clock control (R/W) */
 157        uint32_t RESERVED5[4];
 158   __IO uint32_t SSP0CLKDIV;             /*!< Offset: 0x094 SSP0 clock divider (R/W) */
 159   __IO uint32_t UARTCLKDIV;             /*!< Offset: 0x098 UART clock divider (R/W) */
 160   __IO uint32_t SSP1CLKDIV;             /*!< Offset: 0x09C SSP1 clock divider (R/W) */
 161        uint32_t RESERVED6[12];
 162
 163   __IO uint32_t WDTCLKSEL;              /*!< Offset: 0x0D0 WDT clock source select (R/W) */
 164   __IO uint32_t WDTCLKUEN;              /*!< Offset: 0x0D4 WDT clock source update enable (R/W) */
 165   __IO uint32_t WDTCLKDIV;              /*!< Offset: 0x0D8 WDT clock divider (R/W) */
 166        uint32_t RESERVED8[1];
 167   __IO uint32_t CLKOUTCLKSEL;           /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
 168   __IO uint32_t CLKOUTUEN;              /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
 169   __IO uint32_t CLKOUTDIV;              /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
 170        uint32_t RESERVED9[5];
 171
 172   __IO uint32_t PIOPORCAP0;             /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
 173   __IO uint32_t PIOPORCAP1;             /*!< Offset: 0x104 POR captured PIO status 1 (R/ ) */
 174        uint32_t RESERVED10[18];
 175   __IO uint32_t BODCTRL;                /*!< Offset: 0x150 BOD control (R/W) */
 176   __IO uint32_t SYSTCKCAL;              /*!< Offset: 0x154 System tick counter calibration (R/W) */
 177
 178        uint32_t RESERVED13[7];
 179   __IO uint32_t NMISRC;                 /*!< Offset: 0x174 NMI source selection register (R/W) */
 180        uint32_t RESERVED14[34];
 181
 182   __IO uint32_t STARTAPRP0;             /*!< Offset: 0x200 Start logic edge control Register 0 (R/W) */
 183   __IO uint32_t STARTERP0;              /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
 184   __O  uint32_t STARTRSRP0CLR;          /*!< Offset: 0x208 Start logic reset Register 0  ( /W) */
 185   __I uint32_t STARTSRP0;              /*!< Offset: 0x20C Start logic status Register 0 (R/) */
 186   __IO uint32_t STARTAPRP1;             /*!< Offset: 0x210 Start logic edge control Register 0 (R/W). (LPC11UXX only) */
 187   __IO uint32_t STARTERP1;              /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W). (LPC11UXX only) */
 188   __O  uint32_t STARTRSRP1CLR;          /*!< Offset: 0x218 Start logic reset Register 0  ( /W). (LPC11UXX only) */
 189   __IO uint32_t STARTSRP1;              /*!< Offset: 0x21C Start logic status Register 0 (R/W). (LPC11UXX only) */
 190        uint32_t RESERVED17[4];
 191
 192   __IO uint32_t PDSLEEPCFG;             /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
 193   __IO uint32_t PDAWAKECFG;             /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
 194   __IO uint32_t PDRUNCFG;               /*!< Offset: 0x238 Power-down configuration Register (R/W) */
 195        uint32_t RESERVED15[110];
 196   __I  uint32_t DEVICE_ID;              /*!< Offset: 0x3F4 Device ID (R/ ) */
 197 } LPC_SYSCON_TypeDef;
 198 /*@}*/ /* end of group LPC11xx_SYSCON */
 199
 200
 201 /*------------- Pin Connect Block (IOCON) --------------------------------*/
 202 /** @addtogroup LPC11xx_IOCON LPC11xx I/O Configuration Block
 203   @{
 204 */
 205 typedef struct
 206 {
 207   __IO uint32_t PIO2_6;                 /*!< Offset: 0x000 I/O configuration for pin PIO2_6 (R/W) */
 208        uint32_t RESERVED0[1];
 209   __IO uint32_t PIO2_0;                 /*!< Offset: 0x008 I/O configuration for pin PIO2_0/DTR/SSEL1 (R/W) */
 210   __IO uint32_t RESET_PIO0_0;           /*!< Offset: 0x00C I/O configuration for pin RESET/PIO0_0  (R/W) */
 211   __IO uint32_t PIO0_1;                 /*!< Offset: 0x010 I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2 (R/W) */
 212   __IO uint32_t PIO1_8;                 /*!< Offset: 0x014 I/O configuration for pin PIO1_8/CT16B1_CAP0 (R/W) */
 213   __IO uint32_t SSEL1_LOC;              /*!< Offset: 0x018 IOCON SSEL1 location register (IOCON_SSEL1_LOC, address 0x4004 4018) */
 214   __IO uint32_t PIO0_2;                 /*!< Offset: 0x01C I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 (R/W) */
 215
 216   __IO uint32_t PIO2_7;                 /*!< Offset: 0x020 I/O configuration for pin PIO2_7 (R/W) */
 217   __IO uint32_t PIO2_8;                 /*!< Offset: 0x024 I/O configuration for pin PIO2_8 (R/W) */
 218   __IO uint32_t PIO2_1;                 /*!< Offset: 0x028 I/O configuration for pin PIO2_1/nDSR/SCK1 (R/W) */
 219   __IO uint32_t PIO0_3;                 /*!< Offset: 0x02C I/O configuration for pin PIO0_3 (R/W) */
 220   __IO uint32_t PIO0_4;                 /*!< Offset: 0x030 I/O configuration for pin PIO0_4/SCL (R/W) */
 221   __IO uint32_t PIO0_5;                 /*!< Offset: 0x034 I/O configuration for pin PIO0_5/SDA (R/W) */
 222   __IO uint32_t PIO1_9;                 /*!< Offset: 0x038 I/O configuration for pin PIO1_9/CT16B1_MAT0 (R/W) */
 223   __IO uint32_t PIO3_4;                 /*!< Offset: 0x03C I/O configuration for pin PIO3_4 (R/W) */
 224
 225   __IO uint32_t PIO2_4;                 /*!< Offset: 0x040 I/O configuration for pin PIO2_4 (R/W) */
 226   __IO uint32_t PIO2_5;                 /*!< Offset: 0x044 I/O configuration for pin PIO2_5 (R/W) */
 227   __IO uint32_t PIO3_5;                 /*!< Offset: 0x048 I/O configuration for pin PIO3_5 (R/W) */
 228   __IO uint32_t PIO0_6;                 /*!< Offset: 0x04C I/O configuration for pin PIO0_6/SCK0 (R/W) */
 229   __IO uint32_t PIO0_7;                 /*!< Offset: 0x050 I/O configuration for pin PIO0_7/nCTS (R/W) */
 230   __IO uint32_t PIO2_9;                 /*!< Offset: 0x054 I/O configuration for pin PIO2_9 (R/W) */
 231   __IO uint32_t PIO2_10;                /*!< Offset: 0x058 I/O configuration for pin PIO2_10 (R/W) */
 232   __IO uint32_t PIO2_2;                 /*!< Offset: 0x05C I/O configuration for pin PIO2_2/DCD/MISO1 (R/W) */
 233
 234   __IO uint32_t PIO0_8;                 /*!< Offset: 0x060 I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 (R/W) */
 235   __IO uint32_t PIO0_9;                 /*!< Offset: 0x064 I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 (R/W) */
 236   __IO uint32_t SWCLK_PIO0_10;          /*!< Offset: 0x068 I/O configuration for pin SWCLK/PIO0_10/SCK0/CT16B0_MAT2 (R/W) */
 237   __IO uint32_t PIO1_10;                /*!< Offset: 0x06C I/O configuration for pin PIO1_10/AD6/CT16B1_MAT1 (R/W) */
 238   __IO uint32_t PIO2_11;                /*!< Offset: 0x070 I/O configuration for pin PIO2_11/SCK0 (R/W) */
 239   __IO uint32_t R_PIO0_11;              /*!< Offset: 0x074 I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 (R/W) */
 240   __IO uint32_t R_PIO1_0;               /*!< Offset: 0x078 I/O configuration for pin TMS/PIO1_0/AD1/CT32B1_CAP0 (R/W) */
 241   __IO uint32_t R_PIO1_1;               /*!< Offset: 0x07C I/O configuration for pin TDO/PIO1_1/AD2/CT32B1_MAT0 (R/W) */
 242
 243   __IO uint32_t R_PIO1_2;               /*!< Offset: 0x080 I/O configuration for pin nTRST/PIO1_2/AD3/CT32B1_MAT1 (R/W) */
 244   __IO uint32_t PIO3_0;                 /*!< Offset: 0x084 I/O configuration for pin PIO3_0/nDTR (R/W) */
 245   __IO uint32_t PIO3_1;                 /*!< Offset: 0x088 I/O configuration for pin PIO3_1/nDSR (R/W) */
 246   __IO uint32_t PIO2_3;                 /*!< Offset: 0x08C I/O configuration for pin PIO2_3/RI/MOSI1 (R/W) */
 247   __IO uint32_t SWDIO_PIO1_3;           /*!< Offset: 0x090 I/O configuration for pin SWDIO/PIO1_3/AD4/CT32B1_MAT2 (R/W) */
 248   __IO uint32_t PIO1_4;                 /*!< Offset: 0x094 I/O configuration for pin PIO1_4/AD5/CT32B1_MAT3 (R/W) */
 249   __IO uint32_t PIO1_11;                /*!< Offset: 0x098 I/O configuration for pin PIO1_11/AD7 (R/W) */
 250   __IO uint32_t PIO3_2;                 /*!< Offset: 0x09C I/O configuration for pin PIO3_2/nDCD (R/W) */
 251
 252   __IO uint32_t PIO1_5;                 /*!< Offset: 0x0A0 I/O configuration for pin PIO1_5/nRTS/CT32B0_CAP0 (R/W) */
 253   __IO uint32_t PIO1_6;                 /*!< Offset: 0x0A4 I/O configuration for pin PIO1_6/RXD/CT32B0_MAT0 (R/W) */
 254   __IO uint32_t PIO1_7;                 /*!< Offset: 0x0A8 I/O configuration for pin PIO1_7/TXD/CT32B0_MAT1 (R/W) */
 255   __IO uint32_t PIO3_3;                 /*!< Offset: 0x0AC I/O configuration for pin PIO3_3/nRI (R/W) */
 256   __IO uint32_t SCK_LOC;                /*!< Offset: 0x0B0 SCK pin location select Register (R/W) */
 257   __IO uint32_t DSR_LOC;                /*!< Offset: 0x0B4 DSR pin location select Register (R/W) */
 258   __IO uint32_t DCD_LOC;                /*!< Offset: 0x0B8 DCD pin location select Register (R/W) */
 259   __IO uint32_t RI_LOC;                 /*!< Offset: 0x0BC RI pin location Register (R/W) */
 260
 261   __IO uint32_t CT16B0_CAP0_LOC;        /*!< Offset: 0x0C0 IOCON CT16B0_CAP0 location register (IOCON_CT16B0_CAP0_LOC, address 0x4004 40C0) */
 262   __IO uint32_t SCK1_LOC;               /*!< Offset: 0x0C4 IOCON SCK1 location register (IOCON_SCK1_LOC, address 0x4004 40C4) */
 263   __IO uint32_t MISO1_LOC;              /*!< Offset: 0x0C8 IOCON MISO1 location register (IOCON_MISO1_LOC, address 0x4004 40C8) */
 264   __IO uint32_t MOSI1_LOC;              /*!< Offset: 0x0CC IOCON MOSI1 location register (IOCON_MOSI1_LOC, address 0x4004 40CC) */
 265   __IO uint32_t CT32B0_CAP0_LOC;        /*!< Offset: 0x0D0 IOCON CT32B0_CAP0 location register (IOCON_CT32B0_CAP0_LOC, address 0x4004 40D0) */
 266   __IO uint32_t RXD_LOC;                /*!< Offset: 0x0D4 IOCON RXD location register (IOCON_RXD_LOC, address 0x4004 40D4) */
 267 } LPC_IOCON_TypeDef;
 268 /*@}*/ /* end of group LPC11xx_IOCON */
 269
 270
 271 /*------------- Power Management Unit (PMU) --------------------------*/
 272 /** @addtogroup LPC11xx_PMU LPC11xx Power Management Unit
 273   @{
 274 */
 275 typedef struct
 276 {
 277   __IO uint32_t PCON;                   /*!< Offset: 0x000 Power control Register (R/W) */
 278   __IO uint32_t GPREG0;                 /*!< Offset: 0x004 General purpose Register 0 (R/W) */
 279   __IO uint32_t GPREG1;                 /*!< Offset: 0x008 General purpose Register 1 (R/W) */
 280   __IO uint32_t GPREG2;                 /*!< Offset: 0x00C General purpose Register 2 (R/W) */
 281   __IO uint32_t GPREG3;                 /*!< Offset: 0x010 General purpose Register 3 (R/W) */
 282   __IO uint32_t GPREG4;                 /*!< Offset: 0x014 General purpose Register 4 (R/W) */
 283 } LPC_PMU_TypeDef;
 284 /*@}*/ /* end of group LPC11xx_PMU */
 285
 286
 287
 288 // ------------------------------------------------------------------------------------------------
 289 // -----                                       FLASHCTRL                                      -----
 290 // ------------------------------------------------------------------------------------------------
 291
 292 typedef struct {                            /*!< (@ 0x4003C000) FLASHCTRL Structure    */
 293   __I  uint32_t RESERVED0[4];
 294   __IO uint32_t FLASHCFG;                   /*!< (@ 0x4003C010) Flash memory access time configuration register */
 295   __I  uint32_t RESERVED1[3];
 296   __IO uint32_t FMSSTART;                   /*!< (@ 0x4003C020) Signature start address register */
 297   __IO uint32_t FMSSTOP;                    /*!< (@ 0x4003C024) Signature stop-address register */
 298   __I  uint32_t RESERVED2[1];
 299   __I  uint32_t FMSW0;                      /*!< (@ 0x4003C02C) Word 0 [31:0]          */
 300   __I  uint32_t FMSW1;                      /*!< (@ 0x4003C030) Word 1 [63:32]         */
 301   __I  uint32_t FMSW2;                      /*!< (@ 0x4003C034) Word 2 [95:64]         */
 302   __I  uint32_t FMSW3;                      /*!< (@ 0x4003C038) Word 3 [127:96]        */
 303   __I  uint32_t RESERVED3[1001];
 304   __I  uint32_t FMSTAT;                     /*!< (@ 0x4003CFE0) Signature generation status register */
 305   __I  uint32_t RESERVED4[1];
 306   __IO uint32_t FMSTATCLR;                  /*!< (@ 0x4003CFE8) Signature generation status clear register */
 307 } LPC_FLASHCTRL_Type;
 308
 309
 310 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
 311 /** @addtogroup LPC11xx_GPIO LPC11xx General Purpose Input/Output
 312   @{
 313 */
 314 typedef struct
 315 {
 316   union {
 317     __IO uint32_t MASKED_ACCESS[4096];  /*!< Offset: 0x0000 to 0x3FFC Port data Register for pins PIOn_0 to PIOn_11 (R/W) */
 318     struct {
 319          uint32_t RESERVED0[4095];
 320     __IO uint32_t DATA;                 /*!< Offset: 0x3FFC Port data Register (R/W) */
 321     };
 322   };
 323        uint32_t RESERVED1[4096];
 324   __IO uint32_t DIR;                    /*!< Offset: 0x8000 Data direction Register (R/W) */
 325   __IO uint32_t IS;                     /*!< Offset: 0x8004 Interrupt sense Register (R/W) */
 326   __IO uint32_t IBE;                    /*!< Offset: 0x8008 Interrupt both edges Register (R/W) */
 327   __IO uint32_t IEV;                    /*!< Offset: 0x800C Interrupt event Register  (R/W) */
 328   __IO uint32_t IE;                     /*!< Offset: 0x8010 Interrupt mask Register (R/W) */
 329   __I uint32_t RIS;                    /*!< Offset: 0x8014 Raw interrupt status Register (R/ ) */
 330   __I uint32_t MIS;                    /*!< Offset: 0x8018 Masked interrupt status Register (R/ ) */
 331   __O uint32_t IC;                     /*!< Offset: 0x801C Interrupt clear Register (/W) */
 332 } LPC_GPIO_TypeDef;
 333 /*@}*/ /* end of group LPC11xx_GPIO */
 334
 335 /*------------- Timer (TMR) --------------------------------------------------*/
 336 /** @addtogroup LPC11xx_TMR LPC11xx 16/32-bit Counter/Timer
 337   @{
 338 */
 339 typedef struct
 340 {
 341   __IO uint32_t IR;                     /*!< Offset: 0x000 Interrupt Register (R/W) */
 342   __IO uint32_t TCR;                    /*!< Offset: 0x004 Timer Control Register (R/W) */
 343   __IO uint32_t TC;                     /*!< Offset: 0x008 Timer Counter Register (R/W) */
 344   __IO uint32_t PR;                     /*!< Offset: 0x00C Prescale Register (R/W) */
 345   __IO uint32_t PC;                     /*!< Offset: 0x010 Prescale Counter Register (R/W) */
 346   __IO uint32_t MCR;                    /*!< Offset: 0x014 Match Control Register (R/W) */
 347   union {
 348   __IO uint32_t MR[4];                  /*!< Offset: Match Register base */
 349   struct{
 350   __IO uint32_t MR0;                    /*!< Offset: 0x018 Match Register 0 (R/W) */
 351   __IO uint32_t MR1;                    /*!< Offset: 0x01C Match Register 1 (R/W) */
 352   __IO uint32_t MR2;                    /*!< Offset: 0x020 Match Register 2 (R/W) */
 353   __IO uint32_t MR3;                    /*!< Offset: 0x024 Match Register 3 (R/W) */
 354   };
 355   };
 356   __IO uint32_t CCR;                    /*!< Offset: 0x028 Capture Control Register (R/W) */
 357   __I  uint32_t CR0;                    /*!< Offset: 0x02C Capture Register 0 (R/ ) */
 358   __I  uint32_t CR1;                    /*!< Offset: 0x030 Capture Register 1 (R/ ) */
 359        uint32_t RESERVED1[2];
 360   __IO uint32_t EMR;                    /*!< Offset: 0x03C External Match Register (R/W) */
 361        uint32_t RESERVED2[12];
 362   __IO uint32_t CTCR;                   /*!< Offset: 0x070 Count Control Register (R/W) */
 363   __IO uint32_t PWMC;                   /*!< Offset: 0x074 PWM Control Register (R/W) */
 364 } LPC_TMR_TypeDef;
 365 /*@}*/ /* end of group LPC11xx_TMR */
 366
 367
 368 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
 369 /** @addtogroup LPC11xx_UART LPC11xx Universal Asynchronous Receiver/Transmitter
 370   @{
 371 */
 372 typedef struct
 373 {
 374   union {
 375   __I  uint32_t  RBR;                   /*!< Offset: 0x000 Receiver Buffer  Register (R/ ) */
 376   __O  uint32_t  THR;                   /*!< Offset: 0x000 Transmit Holding Register ( /W) */
 377   __IO uint32_t  DLL;                   /*!< Offset: 0x000 Divisor Latch LSB (R/W) */
 378   };
 379   union {
 380   __IO uint32_t  DLM;                   /*!< Offset: 0x004 Divisor Latch MSB (R/W) */
 381   __IO uint32_t  IER;                   /*!< Offset: 0x000 Interrupt Enable Register (R/W) */
 382   };
 383   union {
 384   __I  uint32_t  IIR;                   /*!< Offset: 0x008 Interrupt ID Register (R/ ) */
 385   __O  uint32_t  FCR;                   /*!< Offset: 0x008 FIFO Control Register ( /W) */
 386   };
 387   __IO uint32_t  LCR;                   /*!< Offset: 0x00C Line Control Register (R/W) */
 388   __IO uint32_t  MCR;                   /*!< Offset: 0x010 Modem control Register (R/W) */
 389   __I  uint32_t  LSR;                   /*!< Offset: 0x014 Line Status Register (R/ ) */
 390   __I  uint32_t  MSR;                   /*!< Offset: 0x018 Modem status Register (R/ ) */
 391   __IO uint32_t  SCR;                   /*!< Offset: 0x01C Scratch Pad Register (R/W) */
 392   __IO uint32_t  ACR;                   /*!< Offset: 0x020 Auto-baud Control Register (R/W) */
 393        uint32_t  RESERVED0;
 394   __IO uint32_t  FDR;                   /*!< Offset: 0x028 Fractional Divider Register (R/W) */
 395        uint32_t  RESERVED1;
 396   __IO uint32_t  TER;                   /*!< Offset: 0x030 Transmit Enable Register (R/W) */
 397        uint32_t  RESERVED2[6];
 398   __IO uint32_t  RS485CTRL;             /*!< Offset: 0x04C RS-485/EIA-485 Control Register (R/W) */
 399   __IO uint32_t  ADRMATCH;              /*!< Offset: 0x050 RS-485/EIA-485 address match Register (R/W) */
 400   __IO uint32_t  RS485DLY;              /*!< Offset: 0x054 RS-485/EIA-485 direction control delay Register (R/W) */
 401   __I  uint32_t  FIFOLVL;               /*!< Offset: 0x058 FIFO Level Register (R) */
 402 } LPC_UART_TypeDef;
 403 /*@}*/ /* end of group LPC11xx_UART */
 404
 405
 406 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
 407 /** @addtogroup LPC11xx_SSP LPC11xx Synchronous Serial Port
 408   @{
 409 */
 410 typedef struct
 411 {
 412   __IO uint32_t CR0;                    /*!< Offset: 0x000 Control Register 0 (R/W) */
 413   __IO uint32_t CR1;                    /*!< Offset: 0x004 Control Register 1 (R/W) */
 414   __IO uint32_t DR;                     /*!< Offset: 0x008 Data Register (R/W) */
 415   __I  uint32_t SR;                     /*!< Offset: 0x00C Status Registe (R/ ) */
 416   __IO uint32_t CPSR;                   /*!< Offset: 0x010 Clock Prescale Register (R/W) */
 417   __IO uint32_t IMSC;                   /*!< Offset: 0x014 Interrupt Mask Set and Clear Register (R/W) */
 418   __I uint32_t RIS;                    /*!< Offset: 0x018 Raw Interrupt Status Register (R/) */
 419   __I uint32_t MIS;                    /*!< Offset: 0x01C Masked Interrupt Status Register (R/) */
 420   __O uint32_t ICR;                    /*!< Offset: 0x020 SSPICR Interrupt Clear Register (/W) */
 421 } LPC_SSP_TypeDef;
 422 /*@}*/ /* end of group LPC11xx_SSP */
 423
 424
 425 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
 426 /** @addtogroup LPC11xx_I2C LPC11xx I2C-Bus Interface
 427   @{
 428 */
 429 typedef struct
 430 {
 431   __IO uint32_t CONSET;                 /*!< Offset: 0x000 I2C Control Set Register (R/W) */
 432   __I  uint32_t STAT;                   /*!< Offset: 0x004 I2C Status Register (R/ ) */
 433   __IO uint32_t DAT;                    /*!< Offset: 0x008 I2C Data Register (R/W) */
 434   __IO uint32_t ADR0;                   /*!< Offset: 0x00C I2C Slave Address Register 0 (R/W) */
 435   __IO uint32_t SCLH;                   /*!< Offset: 0x010 SCH Duty Cycle Register High Half Word (R/W) */
 436   __IO uint32_t SCLL;                   /*!< Offset: 0x014 SCL Duty Cycle Register Low Half Word (R/W) */
 437   __O  uint32_t CONCLR;                 /*!< Offset: 0x018 I2C Control Clear Register ( /W) */
 438   __IO uint32_t MMCTRL;                 /*!< Offset: 0x01C Monitor mode control register (R/W) */
 439   __IO uint32_t ADR1;                   /*!< Offset: 0x020 I2C Slave Address Register 1 (R/W) */
 440   __IO uint32_t ADR2;                   /*!< Offset: 0x024 I2C Slave Address Register 2 (R/W) */
 441   __IO uint32_t ADR3;                   /*!< Offset: 0x028 I2C Slave Address Register 3 (R/W) */
 442   __I  uint32_t DATA_BUFFER;            /*!< Offset: 0x02C Data buffer register ( /W) */
 443   __IO uint32_t MASK0;                  /*!< Offset: 0x030 I2C Slave address mask register 0 (R/W) */
 444   __IO uint32_t MASK1;                  /*!< Offset: 0x034 I2C Slave address mask register 1 (R/W) */
 445   __IO uint32_t MASK2;                  /*!< Offset: 0x038 I2C Slave address mask register 2 (R/W) */
 446   __IO uint32_t MASK3;                  /*!< Offset: 0x03C I2C Slave address mask register 3 (R/W) */
 447 } LPC_I2C_TypeDef;
 448 /*@}*/ /* end of group LPC11xx_I2C */
 449
 450
 451 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
 452 /** @addtogroup LPC11xx_WDT LPC11xx WatchDog Timer
 453   @{
 454 */
 455 typedef struct
 456 {
 457   __IO uint32_t MOD;                    /*!< Offset: 0x000 Watchdog mode register (R/W) */
 458   __IO uint32_t TC;                     /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
 459   __O  uint32_t FEED;                   /*!< Offset: 0x008 Watchdog feed sequence register (W) */
 460   __I  uint32_t TV;                     /*!< Offset: 0x00C Watchdog timer value register (R) */
 461        uint32_t RESERVED0;
 462   __IO uint32_t WARNINT;                                /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
 463   __IO uint32_t WINDOW;                                 /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
 464 } LPC_WDT_TypeDef;
 465 /*@}*/ /* end of group LPC11xx_WDT */
 466
 467
 468 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
 469 /** @addtogroup LPC11xx_ADC LPC11xx Analog-to-Digital Converter
 470   @{
 471 */
 472 typedef struct
 473 {
 474   __IO uint32_t CR;                     /*!< Offset: 0x000       A/D Control Register (R/W) */
 475   __IO uint32_t GDR;                    /*!< Offset: 0x004       A/D Global Data Register (R/W) */
 476        uint32_t RESERVED0;
 477   __IO uint32_t INTEN;                  /*!< Offset: 0x00C       A/D Interrupt Enable Register (R/W) */
 478   __IO uint32_t DR[8];                  /*!< Offset: 0x010-0x02C A/D Channel 0..7 Data Register (R/W) */
 479   __I  uint32_t STAT;                   /*!< Offset: 0x030       A/D Status Register (R/ ) */
 480 } LPC_ADC_TypeDef;
 481 /*@}*/ /* end of group LPC11xx_ADC */
 482
 483
 484 /*------------- CAN Controller (CAN) ----------------------------*/
 485 /** @addtogroup LPC11xx_CAN LPC11xx Controller Area Network(CAN)
 486   @{
 487 */
 488 typedef struct
 489 {
 490   __IO uint32_t CNTL;                           /* 0x000 */
 491   __IO uint32_t STAT;
 492   __IO uint32_t EC;
 493   __IO uint32_t BT;
 494   __IO uint32_t INT;
 495   __IO uint32_t TEST;
 496   __IO uint32_t BRPE;
 497        uint32_t RESERVED0;
 498   __IO uint32_t IF1_CMDREQ;                     /* 0x020 */
 499   __IO uint32_t IF1_CMDMSK;
 500   __IO uint32_t IF1_MSK1;
 501   __IO uint32_t IF1_MSK2;
 502   __IO uint32_t IF1_ARB1;
 503   __IO uint32_t IF1_ARB2;
 504   __IO uint32_t IF1_MCTRL;
 505   __IO uint32_t IF1_DA1;
 506   __IO uint32_t IF1_DA2;
 507   __IO uint32_t IF1_DB1;
 508   __IO uint32_t IF1_DB2;
 509        uint32_t RESERVED1[13];
 510   __IO uint32_t IF2_CMDREQ;                     /* 0x080 */
 511   __IO uint32_t IF2_CMDMSK;
 512   __IO uint32_t IF2_MSK1;
 513   __IO uint32_t IF2_MSK2;
 514   __IO uint32_t IF2_ARB1;
 515   __IO uint32_t IF2_ARB2;
 516   __IO uint32_t IF2_MCTRL;
 517   __IO uint32_t IF2_DA1;
 518   __IO uint32_t IF2_DA2;
 519   __IO uint32_t IF2_DB1;
 520   __IO uint32_t IF2_DB2;
 521        uint32_t RESERVED2[21];
 522   __I  uint32_t TXREQ1;                         /* 0x100 */
 523   __I  uint32_t TXREQ2;
 524        uint32_t RESERVED3[6];
 525   __I  uint32_t ND1;                            /* 0x120 */
 526   __I  uint32_t ND2;
 527        uint32_t RESERVED4[6];
 528   __I  uint32_t IR1;                            /* 0x140 */
 529   __I  uint32_t IR2;
 530        uint32_t RESERVED5[6];
 531   __I  uint32_t MSGV1;                          /* 0x160 */
 532   __I  uint32_t MSGV2;
 533        uint32_t RESERVED6[6];
 534   __IO uint32_t CLKDIV;                         /* 0x180 */
 535 } LPC_CAN_TypeDef;
 536 /*@}*/ /* end of group LPC11xx_CAN */
 537
 538 #if defined ( __CC_ARM   )
 539 #pragma no_anon_unions
 540 #endif
 541
 542 /******************************************************************************/
 543 /*                         Peripheral memory map                              */
 544 /******************************************************************************/
 545 /* Base addresses                                                             */
 546 #define LPC_FLASH_BASE        (0x00000000UL)
 547 #define LPC_RAM_BASE          (0x10000000UL)
 548 #define LPC_APB0_BASE         (0x40000000UL)
 549 #define LPC_AHB_BASE          (0x50000000UL)
 550
 551 /* APB0 peripherals                                                           */
 552 #define LPC_I2C_BASE          (LPC_APB0_BASE + 0x00000)
 553 #define LPC_WDT_BASE          (LPC_APB0_BASE + 0x04000)
 554 #define LPC_UART_BASE         (LPC_APB0_BASE + 0x08000)
 555 #define LPC_CT16B0_BASE       (LPC_APB0_BASE + 0x0C000)
 556 #define LPC_CT16B1_BASE       (LPC_APB0_BASE + 0x10000)
 557 #define LPC_CT32B0_BASE       (LPC_APB0_BASE + 0x14000)
 558 #define LPC_CT32B1_BASE       (LPC_APB0_BASE + 0x18000)
 559 #define LPC_ADC_BASE          (LPC_APB0_BASE + 0x1C000)
 560 #define LPC_PMU_BASE          (LPC_APB0_BASE + 0x38000)
 561 #define LPC_FLASHCTRL_BASE    (LPC_APB0_BASE + 0x3C000)
 562 #define LPC_SSP0_BASE         (LPC_APB0_BASE + 0x40000)
 563 #define LPC_IOCON_BASE        (LPC_APB0_BASE + 0x44000)
 564 #define LPC_SYSCON_BASE       (LPC_APB0_BASE + 0x48000)
 565 #define LPC_CAN_BASE          (LPC_APB0_BASE + 0x50000)
 566 #define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x58000)
 567
 568 /* AHB peripherals                                                            */
 569 #define LPC_GPIO_BASE         (LPC_AHB_BASE  + 0x00000)
 570 #define LPC_GPIO0_BASE        (LPC_AHB_BASE  + 0x00000)
 571 #define LPC_GPIO1_BASE        (LPC_AHB_BASE  + 0x10000)
 572 #define LPC_GPIO2_BASE        (LPC_AHB_BASE  + 0x20000)
 573 #define LPC_GPIO3_BASE        (LPC_AHB_BASE  + 0x30000)
 574
 575 /******************************************************************************/
 576 /*                         Peripheral declaration                             */
 577 /******************************************************************************/
 578 #define LPC_I2C               ((LPC_I2C_TypeDef    *) LPC_I2C_BASE   )
 579 #define LPC_WDT               ((LPC_WDT_TypeDef    *) LPC_WDT_BASE   )
 580 #define LPC_UART              ((LPC_UART_TypeDef   *) LPC_UART_BASE  )
 581 #define LPC_TMR16B0           ((LPC_TMR_TypeDef    *) LPC_CT16B0_BASE)
 582 #define LPC_TMR16B1           ((LPC_TMR_TypeDef    *) LPC_CT16B1_BASE)
 583 #define LPC_TMR32B0           ((LPC_TMR_TypeDef    *) LPC_CT32B0_BASE)
 584 #define LPC_TMR32B1           ((LPC_TMR_TypeDef    *) LPC_CT32B1_BASE)
 585 #define LPC_ADC               ((LPC_ADC_TypeDef    *) LPC_ADC_BASE   )
 586 #define LPC_PMU               ((LPC_PMU_TypeDef    *) LPC_PMU_BASE   )
 587 #define LPC_FLASHCTRL         ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
 588 #define LPC_SSP0              ((LPC_SSP_TypeDef    *) LPC_SSP0_BASE  )
 589 #define LPC_SSP1              ((LPC_SSP_TypeDef    *) LPC_SSP1_BASE  )
 590 #define LPC_CAN               ((LPC_CAN_TypeDef    *) LPC_CAN_BASE   )
 591 #define LPC_IOCON             ((LPC_IOCON_TypeDef  *) LPC_IOCON_BASE )
 592 #define LPC_SYSCON            ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
 593 #define LPC_GPIO0             ((LPC_GPIO_TypeDef   *) LPC_GPIO0_BASE )
 594 #define LPC_GPIO1             ((LPC_GPIO_TypeDef   *) LPC_GPIO1_BASE )
 595 #define LPC_GPIO2             ((LPC_GPIO_TypeDef   *) LPC_GPIO2_BASE )
 596 #define LPC_GPIO3             ((LPC_GPIO_TypeDef   *) LPC_GPIO3_BASE )
 597
 598 #ifdef __cplusplus
 599 }
 600 #endif
 601
 602 #endif  /* __LPC11xx_H__ */