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git.gir.st - tmk_keyboard.git/blob - tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC11XX_11CXX/TARGET_LPC11CXX/system_LPC11xx.c
1 /**************************************************************************//**
2 * @file system_LPC11xx.c
3 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File
4 * for the NXP LPC11xx/LPC11Cxx Devices
6 * @date 24. November 2010
9 * Copyright (C) 2009-2010 ARM Limited. All rights reserved.
12 * ARM Limited (ARM) is supplying this software for use with Cortex-M
13 * processor based microcontrollers. This file can be freely distributed
14 * within development tools that are supporting such ARM based processors.
17 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
18 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
20 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
21 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
23 ******************************************************************************/
30 //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
33 /*--------------------- Clock Configuration ----------------------------------
35 // <e> Clock Configuration
36 // <h> System Oscillator Control Register (SYSOSCCTRL)
37 // <o1.0> BYPASS: System Oscillator Bypass Enable
38 // <i> If enabled then PLL input (sys_osc_clk) is fed
39 // <i> directly from XTALIN and XTALOUT pins.
40 // <o1.9> FREQRANGE: System Oscillator Frequency Range
41 // <i> Determines frequency range for Low-power oscillator.
46 // <h> Watchdog Oscillator Control Register (WDTOSCCTRL)
47 // <o2.0..4> DIVSEL: Select Divider for Fclkana
48 // <i> wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL))
50 // <o2.5..8> FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana)
69 // <h> System PLL Control Register (SYSPLLCTRL)
70 // <i> F_clkout = M * F_clkin = F_CCO / (2 * P)
71 // <i> F_clkin must be in the range of 10 MHz to 25 MHz
72 // <i> F_CCO must be in the range of 156 MHz to 320 MHz
73 // <o3.0..4> MSEL: Feedback Divider Selection
76 // <o3.5..6> PSEL: Post Divider Selection
83 // <h> System PLL Clock Source Select Register (SYSPLLCLKSEL)
84 // <o4.0..1> SEL: System PLL Clock Source
85 // <0=> IRC Oscillator
86 // <1=> System Oscillator
91 // <h> Main Clock Source Select Register (MAINCLKSEL)
92 // <o5.0..1> SEL: Clock Source for Main Clock
93 // <0=> IRC Oscillator
94 // <1=> Input Clock to System PLL
95 // <2=> WDT Oscillator
96 // <3=> System PLL Clock Out
99 // <h> System AHB Clock Divider Register (SYSAHBCLKDIV)
100 // <o6.0..7> DIV: System AHB Clock Divider
101 // <i> Divides main clock to provide system clock to core, memories, and peripherals.
102 // <i> 0 = is disabled
107 #define CLOCK_SETUP 1
108 #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000
109 #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000
110 #define SYSPLLCTRL_Val 0x00000023 // Reset: 0x000
111 #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000
112 #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000
113 #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001
116 //-------- <<< end of configuration section >>> ------------------------------
119 /*----------------------------------------------------------------------------
120 Check the register settings
121 *----------------------------------------------------------------------------*/
122 #define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
123 #define CHECK_RSVD(val, mask) (val & mask)
125 /* Clock Configuration -------------------------------------------------------*/
126 #if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003))
127 #error "SYSOSCCTRL: Invalid values of reserved bits!"
130 #if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF))
131 #error "WDTOSCCTRL: Invalid values of reserved bits!"
134 #if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 2))
135 #error "SYSPLLCLKSEL: Value out of range!"
138 #if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF))
139 #error "SYSPLLCTRL: Invalid values of reserved bits!"
142 #if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003))
143 #error "MAINCLKSEL: Invalid values of reserved bits!"
146 #if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255))
147 #error "SYSAHBCLKDIV: Value out of range!"
151 /*----------------------------------------------------------------------------
153 *----------------------------------------------------------------------------*/
155 /*----------------------------------------------------------------------------
157 *----------------------------------------------------------------------------*/
158 #define __XTAL (12000000UL) /* Oscillator frequency */
159 #define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */
160 #define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */
163 #define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F)
164 #define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2)
166 #if (CLOCK_SETUP) /* Clock Setup */
168 #define __WDT_OSC_CLK ( 0) /* undefined */
169 #elif (__FREQSEL == 1)
170 #define __WDT_OSC_CLK ( 500000 / __DIVSEL)
171 #elif (__FREQSEL == 2)
172 #define __WDT_OSC_CLK ( 800000 / __DIVSEL)
173 #elif (__FREQSEL == 3)
174 #define __WDT_OSC_CLK (1100000 / __DIVSEL)
175 #elif (__FREQSEL == 4)
176 #define __WDT_OSC_CLK (1400000 / __DIVSEL)
177 #elif (__FREQSEL == 5)
178 #define __WDT_OSC_CLK (1600000 / __DIVSEL)
179 #elif (__FREQSEL == 6)
180 #define __WDT_OSC_CLK (1800000 / __DIVSEL)
181 #elif (__FREQSEL == 7)
182 #define __WDT_OSC_CLK (2000000 / __DIVSEL)
183 #elif (__FREQSEL == 8)
184 #define __WDT_OSC_CLK (2200000 / __DIVSEL)
185 #elif (__FREQSEL == 9)
186 #define __WDT_OSC_CLK (2400000 / __DIVSEL)
187 #elif (__FREQSEL == 10)
188 #define __WDT_OSC_CLK (2600000 / __DIVSEL)
189 #elif (__FREQSEL == 11)
190 #define __WDT_OSC_CLK (2700000 / __DIVSEL)
191 #elif (__FREQSEL == 12)
192 #define __WDT_OSC_CLK (2900000 / __DIVSEL)
193 #elif (__FREQSEL == 13)
194 #define __WDT_OSC_CLK (3100000 / __DIVSEL)
195 #elif (__FREQSEL == 14)
196 #define __WDT_OSC_CLK (3200000 / __DIVSEL)
198 #define __WDT_OSC_CLK (3400000 / __DIVSEL)
201 /* sys_pllclkin calculation */
202 #if ((SYSPLLCLKSEL_Val & 0x03) == 0)
203 #define __SYS_PLLCLKIN (__IRC_OSC_CLK)
204 #elif ((SYSPLLCLKSEL_Val & 0x03) == 1)
205 #define __SYS_PLLCLKIN (__SYS_OSC_CLK)
207 #define __SYS_PLLCLKIN (0)
210 #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1))
212 /* main clock calculation */
213 #if ((MAINCLKSEL_Val & 0x03) == 0)
214 #define __MAIN_CLOCK (__IRC_OSC_CLK)
215 #elif ((MAINCLKSEL_Val & 0x03) == 1)
216 #define __MAIN_CLOCK (__SYS_PLLCLKIN)
217 #elif ((MAINCLKSEL_Val & 0x03) == 2)
219 #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!"
221 #define __MAIN_CLOCK (__WDT_OSC_CLK)
223 #elif ((MAINCLKSEL_Val & 0x03) == 3)
224 #define __MAIN_CLOCK (__SYS_PLLCLKOUT)
226 #define __MAIN_CLOCK (0)
229 #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val)
232 #define __SYSTEM_CLOCK (__IRC_OSC_CLK)
233 #endif // CLOCK_SETUP
236 /*----------------------------------------------------------------------------
237 Clock Variable definitions
238 *----------------------------------------------------------------------------*/
239 uint32_t SystemCoreClock
= __SYSTEM_CLOCK
;/*!< System Clock Frequency (Core Clock)*/
242 /*----------------------------------------------------------------------------
244 *----------------------------------------------------------------------------*/
245 void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
247 uint32_t wdt_osc
= 0;
249 /* Determine clock frequency according to clock register values */
250 switch ((LPC_SYSCON
->WDTOSCCTRL
>> 5) & 0x0F) {
251 case 0: wdt_osc
= 0; break;
252 case 1: wdt_osc
= 500000; break;
253 case 2: wdt_osc
= 800000; break;
254 case 3: wdt_osc
= 1100000; break;
255 case 4: wdt_osc
= 1400000; break;
256 case 5: wdt_osc
= 1600000; break;
257 case 6: wdt_osc
= 1800000; break;
258 case 7: wdt_osc
= 2000000; break;
259 case 8: wdt_osc
= 2200000; break;
260 case 9: wdt_osc
= 2400000; break;
261 case 10: wdt_osc
= 2600000; break;
262 case 11: wdt_osc
= 2700000; break;
263 case 12: wdt_osc
= 2900000; break;
264 case 13: wdt_osc
= 3100000; break;
265 case 14: wdt_osc
= 3200000; break;
266 case 15: wdt_osc
= 3400000; break;
268 wdt_osc
/= ((LPC_SYSCON
->WDTOSCCTRL
& 0x1F) << 1) + 2;
270 switch (LPC_SYSCON
->MAINCLKSEL
& 0x03) {
271 case 0: /* Internal RC oscillator */
272 SystemCoreClock
= __IRC_OSC_CLK
;
274 case 1: /* Input Clock to System PLL */
275 switch (LPC_SYSCON
->SYSPLLCLKSEL
& 0x03) {
276 case 0: /* Internal RC oscillator */
277 SystemCoreClock
= __IRC_OSC_CLK
;
279 case 1: /* System oscillator */
280 SystemCoreClock
= __SYS_OSC_CLK
;
282 case 2: /* Reserved */
283 case 3: /* Reserved */
288 case 2: /* WDT Oscillator */
289 SystemCoreClock
= wdt_osc
;
291 case 3: /* System PLL Clock Out */
292 switch (LPC_SYSCON
->SYSPLLCLKSEL
& 0x03) {
293 case 0: /* Internal RC oscillator */
294 if (LPC_SYSCON
->SYSPLLCTRL
& 0x180) {
295 SystemCoreClock
= __IRC_OSC_CLK
;
297 SystemCoreClock
= __IRC_OSC_CLK
* ((LPC_SYSCON
->SYSPLLCTRL
& 0x01F) + 1);
300 case 1: /* System oscillator */
301 if (LPC_SYSCON
->SYSPLLCTRL
& 0x180) {
302 SystemCoreClock
= __SYS_OSC_CLK
;
304 SystemCoreClock
= __SYS_OSC_CLK
* ((LPC_SYSCON
->SYSPLLCTRL
& 0x01F) + 1);
307 case 2: /* Reserved */
308 case 3: /* Reserved */
315 SystemCoreClock
/= LPC_SYSCON
->SYSAHBCLKDIV
;
320 * Initialize the system
325 * @brief Setup the microcontroller system.
326 * Initialize the System.
328 void SystemInit (void) {
331 #if (CLOCK_SETUP) /* Clock Setup */
333 #if ((SYSPLLCLKSEL_Val & 0x03) == 1)
334 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 5); /* Power-up System Osc */
335 LPC_SYSCON
->SYSOSCCTRL
= SYSOSCCTRL_Val
;
336 for (i
= 0; i
< 200; i
++) __NOP();
339 LPC_SYSCON
->SYSPLLCLKSEL
= SYSPLLCLKSEL_Val
; /* Select PLL Input */
340 LPC_SYSCON
->SYSPLLCLKUEN
= 0x01; /* Update Clock Source */
341 LPC_SYSCON
->SYSPLLCLKUEN
= 0x00; /* Toggle Update Register */
342 LPC_SYSCON
->SYSPLLCLKUEN
= 0x01;
343 while (!(LPC_SYSCON
->SYSPLLCLKUEN
& 0x01)); /* Wait Until Updated */
344 #if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */
345 LPC_SYSCON
->SYSPLLCTRL
= SYSPLLCTRL_Val
;
346 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 7); /* Power-up SYSPLL */
347 while (!(LPC_SYSCON
->SYSPLLSTAT
& 0x01)); /* Wait Until PLL Locked */
350 #if (((MAINCLKSEL_Val & 0x03) == 2) )
351 LPC_SYSCON
->WDTOSCCTRL
= WDTOSCCTRL_Val
;
352 LPC_SYSCON
->PDRUNCFG
&= ~(1 << 6); /* Power-up WDT Clock */
353 for (i
= 0; i
< 200; i
++) __NOP();
356 LPC_SYSCON
->MAINCLKSEL
= MAINCLKSEL_Val
; /* Select PLL Clock Output */
357 LPC_SYSCON
->MAINCLKUEN
= 0x01; /* Update MCLK Clock Source */
358 LPC_SYSCON
->MAINCLKUEN
= 0x00; /* Toggle Update Register */
359 LPC_SYSCON
->MAINCLKUEN
= 0x01;
360 while (!(LPC_SYSCON
->MAINCLKUEN
& 0x01)); /* Wait Until Updated */
362 LPC_SYSCON
->SYSAHBCLKDIV
= SYSAHBCLKDIV_Val
;
364 /* System clock to the IOCON needs to be enabled or
365 most of the I/O related peripherals won't work. */
366 LPC_SYSCON
->SYSAHBCLKCTRL
|= (1<<16);