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Merge commit '1fe4406f374291ab2e86e95a97341fd9c475fcb8'
[tmk_keyboard.git] / tmk_core / tool / mbed / mbed-sdk / libraries / mbed / targets / cmsis / TARGET_NXP / TARGET_LPC15XX / LPC15xx.h
1
2 /****************************************************************************************************//**
3 * @file LPC15xx.h
4 *
5 * @brief CMSIS Cortex-M3 Peripheral Access Layer Header File for
6 * LPC15xx from .
7 *
8 * @version V0.3
9 * @date 17. July 2013
10 *
11 * @note Generated with SVDConv V2.80
12 * from CMSIS SVD File 'H2_v0.3.svd' Version 0.3,
13 *
14 * modified by Keil
15 * modified by ytsuboi
16 *******************************************************************************************************/
17
18
19
20 /** @addtogroup (null)
21 * @{
22 */
23
24 /** @addtogroup LPC15xx
25 * @{
26 */
27
28 #ifndef LPC15XX_H
29 #define LPC15XX_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* ------------------------- Interrupt Number Definition ------------------------ */
37
38 typedef enum {
39 /* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
40 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
41 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
42 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
43 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
44 and No Match */
45 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
46 related Fault */
47 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
52 /* --------------------- LPC15xx Specific Interrupt Numbers --------------------- */
53 WDT_IRQn = 0, /*!< 0 WDT */
54 BOD_IRQn = 1, /*!< 1 BOD */
55 FLASH_IRQn = 2, /*!< 2 FLASH */
56 EE_IRQn = 3, /*!< 3 EE */
57 DMA_IRQn = 4, /*!< 4 DMA */
58 GINT0_IRQn = 5, /*!< 5 GINT0 */
59 GINT1_IRQn = 6, /*!< 6 GINT1 */
60 PIN_INT0_IRQn = 7, /*!< 7 PIN_INT0 */
61 PIN_INT1_IRQn = 8, /*!< 8 PIN_INT1 */
62 PIN_INT2_IRQn = 9, /*!< 9 PIN_INT2 */
63 PIN_INT3_IRQn = 10, /*!< 10 PIN_INT3 */
64 PIN_INT4_IRQn = 11, /*!< 11 PIN_INT4 */
65 PIN_INT5_IRQn = 12, /*!< 12 PIN_INT5 */
66 PIN_INT6_IRQn = 13, /*!< 13 PIN_INT6 */
67 PIN_INT7_IRQn = 14, /*!< 14 PIN_INT7 */
68 RIT_IRQn = 15, /*!< 15 RIT */
69 SCT0_IRQn = 16, /*!< 16 SCT0 */
70 SCT1_IRQn = 17, /*!< 17 SCT1 */
71 SCT2_IRQn = 18, /*!< 18 SCT2 */
72 SCT3_IRQn = 19, /*!< 19 SCT3 */
73 MRT_IRQn = 20, /*!< 20 MRT */
74 UART0_IRQn = 21, /*!< 21 UART0 */
75 UART1_IRQn = 22, /*!< 22 UART1 */
76 UART2_IRQn = 23, /*!< 23 UART2 */
77 I2C0_IRQn = 24, /*!< 24 I2C0 */
78 SPI0_IRQn = 25, /*!< 25 SPI0 */
79 SPI1_IRQn = 26, /*!< 26 SPI1 */
80 C_CAN0_IRQn = 27, /*!< 27 C_CAN0 */
81 USB_IRQ_IRQn = 28, /*!< 28 USB_IRQ */
82 USB_FIQ_IRQn = 29, /*!< 29 USB_FIQ */
83 USBWAKEUP_IRQn = 30, /*!< 30 USBWAKEUP */
84 ADC0_SEQA_IRQn = 31, /*!< 31 ADC0_SEQA */
85 ADC0_SEQB_IRQn = 32, /*!< 32 ADC0_SEQB */
86 ADC0_THCMP_IRQn = 33, /*!< 33 ADC0_THCMP */
87 ADC0_OVR_IRQn = 34, /*!< 34 ADC0_OVR */
88 ADC1_SEQA_IRQn = 35, /*!< 35 ADC1_SEQA */
89 ADC1_SEQB_IRQn = 36, /*!< 36 ADC1_SEQB */
90 ADC1_THCMP_IRQn = 37, /*!< 37 ADC1_THCMP */
91 ADC1_OVR_IRQn = 38, /*!< 38 ADC1_OVR */
92 DAC_IRQn = 39, /*!< 39 DAC */
93 CMP0_IRQn = 40, /*!< 40 CMP0 */
94 CMP1_IRQn = 41, /*!< 41 CMP1 */
95 CMP2_IRQn = 42, /*!< 42 CMP2 */
96 CMP3_IRQn = 43, /*!< 43 CMP3 */
97 QEI_IRQn = 44, /*!< 44 QEI */
98 RTC_ALARM_IRQn = 45, /*!< 45 RTC_ALARM */
99 RTC_WAKE_IRQn = 46 /*!< 46 RTC_WAKE */
100 } IRQn_Type;
101
102
103 /** @addtogroup Configuration_of_CMSIS
104 * @{
105 */
106
107
108 /* ================================================================================ */
109 /* ================ Processor and Core Peripheral Section ================ */
110 /* ================================================================================ */
111
112 /* ----------------Configuration of the Cortex-M3 Processor and Core Peripherals---------------- */
113 #define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision */
114 #define __MPU_PRESENT 0 /*!< MPU present or not */
115 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
116 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
117 /** @} */ /* End of group Configuration_of_CMSIS */
118
119 #include "core_cm3.h" /*!< Cortex-M3 processor and core peripherals */
120 #include "system_LPC15xx.h" /*!< LPC15xx System */
121
122
123 /* ================================================================================ */
124 /* ================ Device Specific Peripheral Section ================ */
125 /* ================================================================================ */
126
127
128 /** @addtogroup Device_Peripheral_Registers
129 * @{
130 */
131
132
133 /* ------------------- Start of section using anonymous unions ------------------ */
134 #if defined(__CC_ARM)
135 #pragma push
136 #pragma anon_unions
137 #elif defined(__ICCARM__)
138 #pragma language=extended
139 #elif defined(__GNUC__)
140 /* anonymous unions are enabled by default */
141 #elif defined(__TMS470__)
142 /* anonymous unions are enabled by default */
143 #elif defined(__TASKING__)
144 #pragma warning 586
145 #else
146 #warning Not supported compiler type
147 #endif
148
149
150
151 /* ================================================================================ */
152 /* ================ GPIO_PORT ================ */
153 /* ================================================================================ */
154
155
156 /**
157 * @brief General Purpose I/O (GPIO) (GPIO_PORT)
158 */
159
160 typedef struct { /*!< GPIO_PORT Structure */
161 __IO uint8_t B[76]; /*!< Byte pin registers */
162 __I uint32_t RESERVED0[45];
163 __IO uint32_t W[76]; /*!< Word pin registers */
164 __I uint32_t RESERVED1[1908];
165 __IO uint32_t DIR[3]; /*!< Port Direction registers */
166 __I uint32_t RESERVED2[29];
167 __IO uint32_t MASK[3]; /*!< Port Mask register */
168 __I uint32_t RESERVED3[29];
169 __IO uint32_t PIN[3]; /*!< Port pin register */
170 __I uint32_t RESERVED4[29];
171 __IO uint32_t MPIN[3]; /*!< Masked port register */
172 __I uint32_t RESERVED5[29];
173 __IO uint32_t SET[3]; /*!< Write: Set port register Read: port output bits */
174 __I uint32_t RESERVED6[29];
175 __O uint32_t CLR[3]; /*!< Clear port */
176 __I uint32_t RESERVED7[29];
177 __O uint32_t NOT[3]; /*!< Toggle port */
178 } LPC_GPIO_PORT_Type;
179
180
181 /* ================================================================================ */
182 /* ================ DMA ================ */
183 /* ================================================================================ */
184
185
186 /**
187 * @brief DMA controller (DMA)
188 */
189
190 typedef struct { /*!< DMA Structure */
191 __IO uint32_t CTRL; /*!< DMA control. */
192 __I uint32_t INTSTAT; /*!< Interrupt status. */
193 __IO uint32_t SRAMBASE; /*!< SRAM address of the channel configuration table. */
194 __I uint32_t RESERVED0[5];
195 __IO uint32_t ENABLESET0; /*!< Channel Enable read and Set for all DMA channels. */
196 __I uint32_t RESERVED1;
197 __O uint32_t ENABLECLR0; /*!< Channel Enable Clear for all DMA channels. */
198 __I uint32_t RESERVED2;
199 __I uint32_t ACTIVE0; /*!< Channel Active status for all DMA channels. */
200 __I uint32_t RESERVED3;
201 __I uint32_t BUSY0; /*!< Channel Busy status for all DMA channels. */
202 __I uint32_t RESERVED4;
203 __IO uint32_t ERRINT0; /*!< Error Interrupt status for all DMA channels. */
204 __I uint32_t RESERVED5;
205 __IO uint32_t INTENSET0; /*!< Interrupt Enable read and Set for all DMA channels. */
206 __I uint32_t RESERVED6;
207 __O uint32_t INTENCLR0; /*!< Interrupt Enable Clear for all DMA channels. */
208 __I uint32_t RESERVED7;
209 __IO uint32_t INTA0; /*!< Interrupt A status for all DMA channels. */
210 __I uint32_t RESERVED8;
211 __IO uint32_t INTB0; /*!< Interrupt B status for all DMA channels. */
212 __I uint32_t RESERVED9;
213 __O uint32_t SETVALID0; /*!< Set ValidPending control bits for all DMA channels. */
214 __I uint32_t RESERVED10;
215 __O uint32_t SETTRIG0; /*!< Set Trigger control bits for all DMA channels. */
216 __I uint32_t RESERVED11;
217 __O uint32_t ABORT0; /*!< Channel Abort control for all DMA channels. */
218 __I uint32_t RESERVED12[225];
219 __IO uint32_t CFG0; /*!< Configuration register for DMA channel 0. */
220 __I uint32_t CTLSTAT0; /*!< Control and status register for DMA channel 0. */
221 __IO uint32_t XFERCFG0; /*!< Transfer configuration register for DMA channel 0. */
222 __I uint32_t RESERVED13;
223 __IO uint32_t CFG1; /*!< Configuration register for DMA channel 0. */
224 __I uint32_t CTLSTAT1; /*!< Control and status register for DMA channel 0. */
225 __IO uint32_t XFERCFG1; /*!< Transfer configuration register for DMA channel 0. */
226 __I uint32_t RESERVED14;
227 __IO uint32_t CFG2; /*!< Configuration register for DMA channel 0. */
228 __I uint32_t CTLSTAT2; /*!< Control and status register for DMA channel 0. */
229 __IO uint32_t XFERCFG2; /*!< Transfer configuration register for DMA channel 0. */
230 __I uint32_t RESERVED15;
231 __IO uint32_t CFG3; /*!< Configuration register for DMA channel 0. */
232 __I uint32_t CTLSTAT3; /*!< Control and status register for DMA channel 0. */
233 __IO uint32_t XFERCFG3; /*!< Transfer configuration register for DMA channel 0. */
234 __I uint32_t RESERVED16;
235 __IO uint32_t CFG4; /*!< Configuration register for DMA channel 0. */
236 __I uint32_t CTLSTAT4; /*!< Control and status register for DMA channel 0. */
237 __IO uint32_t XFERCFG4; /*!< Transfer configuration register for DMA channel 0. */
238 __I uint32_t RESERVED17;
239 __IO uint32_t CFG5; /*!< Configuration register for DMA channel 0. */
240 __I uint32_t CTLSTAT5; /*!< Control and status register for DMA channel 0. */
241 __IO uint32_t XFERCFG5; /*!< Transfer configuration register for DMA channel 0. */
242 __I uint32_t RESERVED18;
243 __IO uint32_t CFG6; /*!< Configuration register for DMA channel 0. */
244 __I uint32_t CTLSTAT6; /*!< Control and status register for DMA channel 0. */
245 __IO uint32_t XFERCFG6; /*!< Transfer configuration register for DMA channel 0. */
246 __I uint32_t RESERVED19;
247 __IO uint32_t CFG7; /*!< Configuration register for DMA channel 0. */
248 __I uint32_t CTLSTAT7; /*!< Control and status register for DMA channel 0. */
249 __IO uint32_t XFERCFG7; /*!< Transfer configuration register for DMA channel 0. */
250 __I uint32_t RESERVED20;
251 __IO uint32_t CFG8; /*!< Configuration register for DMA channel 0. */
252 __I uint32_t CTLSTAT8; /*!< Control and status register for DMA channel 0. */
253 __IO uint32_t XFERCFG8; /*!< Transfer configuration register for DMA channel 0. */
254 __I uint32_t RESERVED21;
255 __IO uint32_t CFG9; /*!< Configuration register for DMA channel 0. */
256 __I uint32_t CTLSTAT9; /*!< Control and status register for DMA channel 0. */
257 __IO uint32_t XFERCFG9; /*!< Transfer configuration register for DMA channel 0. */
258 __I uint32_t RESERVED22;
259 __IO uint32_t CFG10; /*!< Configuration register for DMA channel 0. */
260 __I uint32_t CTLSTAT10; /*!< Control and status register for DMA channel 0. */
261 __IO uint32_t XFERCFG10; /*!< Transfer configuration register for DMA channel 0. */
262 __I uint32_t RESERVED23;
263 __IO uint32_t CFG11; /*!< Configuration register for DMA channel 0. */
264 __I uint32_t CTLSTAT11; /*!< Control and status register for DMA channel 0. */
265 __IO uint32_t XFERCFG11; /*!< Transfer configuration register for DMA channel 0. */
266 __I uint32_t RESERVED24;
267 __IO uint32_t CFG12; /*!< Configuration register for DMA channel 0. */
268 __I uint32_t CTLSTAT12; /*!< Control and status register for DMA channel 0. */
269 __IO uint32_t XFERCFG12; /*!< Transfer configuration register for DMA channel 0. */
270 __I uint32_t RESERVED25;
271 __IO uint32_t CFG13; /*!< Configuration register for DMA channel 0. */
272 __I uint32_t CTLSTAT13; /*!< Control and status register for DMA channel 0. */
273 __IO uint32_t XFERCFG13; /*!< Transfer configuration register for DMA channel 0. */
274 __I uint32_t RESERVED26;
275 __IO uint32_t CFG14; /*!< Configuration register for DMA channel 0. */
276 __I uint32_t CTLSTAT14; /*!< Control and status register for DMA channel 0. */
277 __IO uint32_t XFERCFG14; /*!< Transfer configuration register for DMA channel 0. */
278 __I uint32_t RESERVED27;
279 __IO uint32_t CFG15; /*!< Configuration register for DMA channel 0. */
280 __I uint32_t CTLSTAT15; /*!< Control and status register for DMA channel 0. */
281 __IO uint32_t XFERCFG15; /*!< Transfer configuration register for DMA channel 0. */
282 __I uint32_t RESERVED28;
283 __IO uint32_t CFG16; /*!< Configuration register for DMA channel 0. */
284 __I uint32_t CTLSTAT16; /*!< Control and status register for DMA channel 0. */
285 __IO uint32_t XFERCFG16; /*!< Transfer configuration register for DMA channel 0. */
286 __I uint32_t RESERVED29;
287 __IO uint32_t CFG17; /*!< Configuration register for DMA channel 0. */
288 __I uint32_t CTLSTAT17; /*!< Control and status register for DMA channel 0. */
289 __IO uint32_t XFERCFG17; /*!< Transfer configuration register for DMA channel 0. */
290 } LPC_DMA_Type;
291
292
293 /* ================================================================================ */
294 /* ================ USB ================ */
295 /* ================================================================================ */
296
297
298 /**
299 * @brief USB device controller (USB)
300 */
301
302 typedef struct { /*!< USB Structure */
303 __IO uint32_t DEVCMDSTAT; /*!< USB Device Command/Status register */
304 __IO uint32_t INFO; /*!< USB Info register */
305 __IO uint32_t EPLISTSTART; /*!< USB EP Command/Status List start address */
306 __IO uint32_t DATABUFSTART; /*!< USB Data buffer start address */
307 __IO uint32_t LPM; /*!< Link Power Management register */
308 __IO uint32_t EPSKIP; /*!< USB Endpoint skip */
309 __IO uint32_t EPINUSE; /*!< USB Endpoint Buffer in use */
310 __IO uint32_t EPBUFCFG; /*!< USB Endpoint Buffer Configuration register */
311 __IO uint32_t INTSTAT; /*!< USB interrupt status register */
312 __IO uint32_t INTEN; /*!< USB interrupt enable register */
313 __IO uint32_t INTSETSTAT; /*!< USB set interrupt status register */
314 __IO uint32_t INTROUTING; /*!< USB interrupt routing register */
315 __I uint32_t RESERVED0;
316 __I uint32_t EPTOGGLE; /*!< USB Endpoint toggle register */
317 } LPC_USB_Type;
318
319
320 /* ================================================================================ */
321 /* ================ CRC ================ */
322 /* ================================================================================ */
323
324
325 /**
326 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
327 */
328
329 typedef struct { /*!< CRC Structure */
330 __IO uint32_t MODE; /*!< CRC mode register */
331 __IO uint32_t SEED; /*!< CRC seed register */
332
333 union {
334 __O uint32_t WR_DATA; /*!< CRC data register */
335 __I uint32_t SUM; /*!< CRC checksum register */
336 };
337 } LPC_CRC_Type;
338
339
340 /* ================================================================================ */
341 /* ================ SCT0 ================ */
342 /* ================================================================================ */
343
344
345 /**
346 * @brief Large State Configurable Timers 0/1 (SCT0/1) (SCT0)
347 */
348
349 typedef struct { /*!< SCT0 Structure */
350 __IO uint32_t CONFIG; /*!< SCT configuration register */
351 __IO uint32_t CTRL; /*!< SCT control register */
352 __IO uint32_t LIMIT; /*!< SCT limit register */
353 __IO uint32_t HALT; /*!< SCT halt condition register */
354 __IO uint32_t STOP; /*!< SCT stop condition register */
355 __IO uint32_t START; /*!< SCT start condition register */
356 __IO uint32_t DITHER; /*!< SCT dither condition register */
357 __I uint32_t RESERVED0[9];
358 __IO uint32_t COUNT; /*!< SCT counter register */
359 __IO uint32_t STATE; /*!< SCT state register */
360 __I uint32_t INPUT; /*!< SCT input register */
361 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
362 __IO uint32_t OUTPUT; /*!< SCT output register */
363 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
364 __IO uint32_t RES; /*!< SCT conflict resolution register */
365 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
366 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
367 __I uint32_t RESERVED1[35];
368 __IO uint32_t EVEN; /*!< SCT event enable register */
369 __IO uint32_t EVFLAG; /*!< SCT event flag register */
370 __IO uint32_t CONEN; /*!< SCT conflict enable register */
371 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
372
373 union {
374 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
375 REGMODE15 = 1 */
376 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 15; REGMOD0
377 to REGMODE15 = 0 */
378 };
379
380 union {
381 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
382 REGMODE15 = 1 */
383 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 15; REGMOD0
384 to REGMODE15 = 0 */
385 };
386
387 union {
388 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
389 REGMODE15 = 1 */
390 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 15; REGMOD0
391 to REGMODE15 = 0 */
392 };
393
394 union {
395 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
396 REGMODE15 = 1 */
397 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 15; REGMOD0
398 to REGMODE15 = 0 */
399 };
400
401 union {
402 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
403 REGMODE15 = 1 */
404 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 15; REGMOD0
405 to REGMODE15 = 0 */
406 };
407
408 union {
409 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
410 REGMODE15 = 1 */
411 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 15; REGMOD0
412 to REGMODE15 = 0 */
413 };
414
415 union {
416 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
417 REGMODE15 = 1 */
418 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 15; REGMOD0
419 to REGMODE15 = 0 */
420 };
421
422 union {
423 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 15; REGMOD0
424 to REGMODE15 = 0 */
425 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
426 REGMODE15 = 1 */
427 };
428
429 union {
430 __I uint32_t CAP8; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
431 REGMODE15 = 1 */
432 __IO uint32_t MATCH8; /*!< SCT match value register of match channels 0 to 15; REGMOD0
433 to REGMODE15 = 0 */
434 };
435
436 union {
437 __IO uint32_t MATCH9; /*!< SCT match value register of match channels 0 to 15; REGMOD0
438 to REGMODE15 = 0 */
439 __I uint32_t CAP9; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
440 REGMODE15 = 1 */
441 };
442
443 union {
444 __IO uint32_t MATCH10; /*!< SCT match value register of match channels 0 to 15; REGMOD0
445 to REGMODE15 = 0 */
446 __I uint32_t CAP10; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
447 REGMODE15 = 1 */
448 };
449
450 union {
451 __IO uint32_t MATCH11; /*!< SCT match value register of match channels 0 to 15; REGMOD0
452 to REGMODE15 = 0 */
453 __I uint32_t CAP11; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
454 REGMODE15 = 1 */
455 };
456
457 union {
458 __IO uint32_t MATCH12; /*!< SCT match value register of match channels 0 to 15; REGMOD0
459 to REGMODE15 = 0 */
460 __I uint32_t CAP12; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
461 REGMODE15 = 1 */
462 };
463
464 union {
465 __IO uint32_t MATCH13; /*!< SCT match value register of match channels 0 to 15; REGMOD0
466 to REGMODE15 = 0 */
467 __I uint32_t CAP13; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
468 REGMODE15 = 1 */
469 };
470
471 union {
472 __I uint32_t CAP14; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
473 REGMODE15 = 1 */
474 __IO uint32_t MATCH14; /*!< SCT match value register of match channels 0 to 15; REGMOD0
475 to REGMODE15 = 0 */
476 };
477
478 union {
479 __IO uint32_t MATCH15; /*!< SCT match value register of match channels 0 to 15; REGMOD0
480 to REGMODE15 = 0 */
481 __I uint32_t CAP15; /*!< SCT capture register of capture channel 0 to 15; REGMOD0 to
482 REGMODE15 = 1 */
483 };
484 __IO uint32_t FRACMAT0; /*!< Fractional match registers 0 to 5 for SCT match value registers
485 0 to 5. */
486 __IO uint32_t FRACMAT1; /*!< Fractional match registers 0 to 5 for SCT match value registers
487 0 to 5. */
488 __IO uint32_t FRACMAT2; /*!< Fractional match registers 0 to 5 for SCT match value registers
489 0 to 5. */
490 __IO uint32_t FRACMAT3; /*!< Fractional match registers 0 to 5 for SCT match value registers
491 0 to 5. */
492 __IO uint32_t FRACMAT4; /*!< Fractional match registers 0 to 5 for SCT match value registers
493 0 to 5. */
494 __IO uint32_t FRACMAT5; /*!< Fractional match registers 0 to 5 for SCT match value registers
495 0 to 5. */
496 __I uint32_t RESERVED2[42];
497
498 union {
499 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
500 = 1 */
501 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
502 = 0 */
503 };
504
505 union {
506 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
507 = 0 */
508 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
509 = 1 */
510 };
511
512 union {
513 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
514 = 0 */
515 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
516 = 1 */
517 };
518
519 union {
520 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
521 = 1 */
522 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
523 = 0 */
524 };
525
526 union {
527 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
528 = 1 */
529 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
530 = 0 */
531 };
532
533 union {
534 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
535 = 1 */
536 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
537 = 0 */
538 };
539
540 union {
541 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
542 = 0 */
543 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
544 = 1 */
545 };
546
547 union {
548 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
549 = 0 */
550 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
551 = 1 */
552 };
553
554 union {
555 __IO uint32_t CAPCTRL8; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
556 = 1 */
557 __IO uint32_t MATCHREL8; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
558 = 0 */
559 };
560
561 union {
562 __IO uint32_t CAPCTRL9; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
563 = 1 */
564 __IO uint32_t MATCHREL9; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
565 = 0 */
566 };
567
568 union {
569 __IO uint32_t CAPCTRL10; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
570 = 1 */
571 __IO uint32_t MATCHREL10; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
572 = 0 */
573 };
574
575 union {
576 __IO uint32_t CAPCTRL11; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
577 = 1 */
578 __IO uint32_t MATCHREL11; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
579 = 0 */
580 };
581
582 union {
583 __IO uint32_t MATCHREL12; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
584 = 0 */
585 __IO uint32_t CAPCTRL12; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
586 = 1 */
587 };
588
589 union {
590 __IO uint32_t MATCHREL13; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
591 = 0 */
592 __IO uint32_t CAPCTRL13; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
593 = 1 */
594 };
595
596 union {
597 __IO uint32_t CAPCTRL14; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
598 = 1 */
599 __IO uint32_t MATCHREL14; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
600 = 0 */
601 };
602
603 union {
604 __IO uint32_t CAPCTRL15; /*!< SCT capture control register 0 to 15; REGMOD0 = 1 to REGMODE15
605 = 1 */
606 __IO uint32_t MATCHREL15; /*!< SCT match reload value register 0 to 15; REGMOD0 = 0 to REGMODE15
607 = 0 */
608 };
609 __IO uint32_t FRACMATREL0; /*!< Fractional match reload registers 0 to 5 for SCT match value
610 registers 0 to 5. */
611 __IO uint32_t FRACMATREL1; /*!< Fractional match reload registers 0 to 5 for SCT match value
612 registers 0 to 5. */
613 __IO uint32_t FRACMATREL2; /*!< Fractional match reload registers 0 to 5 for SCT match value
614 registers 0 to 5. */
615 __IO uint32_t FRACMATREL3; /*!< Fractional match reload registers 0 to 5 for SCT match value
616 registers 0 to 5. */
617 __IO uint32_t FRACMATREL4; /*!< Fractional match reload registers 0 to 5 for SCT match value
618 registers 0 to 5. */
619 __IO uint32_t FRACMATREL5; /*!< Fractional match reload registers 0 to 5 for SCT match value
620 registers 0 to 5. */
621 __I uint32_t RESERVED3[42];
622 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
623 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
624 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
625 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
626 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
627 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
628 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
629 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
630 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
631 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
632 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
633 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
634 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
635 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
636 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
637 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
638 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
639 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
640 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
641 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
642 __IO uint32_t EV10_STATE; /*!< SCT event state register 0 */
643 __IO uint32_t EV10_CTRL; /*!< SCT event control register 0 */
644 __IO uint32_t EV11_STATE; /*!< SCT event state register 0 */
645 __IO uint32_t EV11_CTRL; /*!< SCT event control register 0 */
646 __IO uint32_t EV12_STATE; /*!< SCT event state register 0 */
647 __IO uint32_t EV12_CTRL; /*!< SCT event control register 0 */
648 __IO uint32_t EV13_STATE; /*!< SCT event state register 0 */
649 __IO uint32_t EV13_CTRL; /*!< SCT event control register 0 */
650 __IO uint32_t EV14_STATE; /*!< SCT event state register 0 */
651 __IO uint32_t EV14_CTRL; /*!< SCT event control register 0 */
652 __IO uint32_t EV15_STATE; /*!< SCT event state register 0 */
653 __IO uint32_t EV15_CTRL; /*!< SCT event control register 0 */
654 __I uint32_t RESERVED4[96];
655 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
656 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
657 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
658 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
659 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
660 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
661 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
662 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
663 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
664 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
665 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
666 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
667 __IO uint32_t OUT6_SET; /*!< SCT output 0 set register */
668 __IO uint32_t OUT6_CLR; /*!< SCT output 0 clear register */
669 __IO uint32_t OUT7_SET; /*!< SCT output 0 set register */
670 __IO uint32_t OUT7_CLR; /*!< SCT output 0 clear register */
671 __IO uint32_t OUT8_SET; /*!< SCT output 0 set register */
672 __IO uint32_t OUT8_CLR; /*!< SCT output 0 clear register */
673 __IO uint32_t OUT9_SET; /*!< SCT output 0 set register */
674 __IO uint32_t OUT9_CLR; /*!< SCT output 0 clear register */
675 } LPC_SCT0_Type;
676
677
678 /* ================================================================================ */
679 /* ================ SCT2 ================ */
680 /* ================================================================================ */
681
682
683 /**
684 * @brief Small State Configurable Timers 2/3 (SCT2/3) (SCT2)
685 */
686
687 typedef struct { /*!< SCT2 Structure */
688 __IO uint32_t CONFIG; /*!< SCT configuration register */
689 __IO uint32_t CTRL; /*!< SCT control register */
690 __IO uint32_t LIMIT; /*!< SCT limit register */
691 __IO uint32_t HALT; /*!< SCT halt condition register */
692 __IO uint32_t STOP; /*!< SCT stop condition register */
693 __IO uint32_t START; /*!< SCT start condition register */
694 __I uint32_t RESERVED0[10];
695 __IO uint32_t COUNT; /*!< SCT counter register */
696 __IO uint32_t STATE; /*!< SCT state register */
697 __I uint32_t INPUT; /*!< SCT input register */
698 __IO uint32_t REGMODE; /*!< SCT match/capture registers mode register */
699 __IO uint32_t OUTPUT; /*!< SCT output register */
700 __IO uint32_t OUTPUTDIRCTRL; /*!< SCT output counter direction control register */
701 __IO uint32_t RES; /*!< SCT conflict resolution register */
702 __IO uint32_t DMAREQ0; /*!< SCT DMA request 0 register */
703 __IO uint32_t DMAREQ1; /*!< SCT DMA request 1 register */
704 __I uint32_t RESERVED1[35];
705 __IO uint32_t EVEN; /*!< SCT event enable register */
706 __IO uint32_t EVFLAG; /*!< SCT event flag register */
707 __IO uint32_t CONEN; /*!< SCT conflict enable register */
708 __IO uint32_t CONFLAG; /*!< SCT conflict flag register */
709
710 union {
711 __I uint32_t CAP0; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
712 = 1 */
713 __IO uint32_t MATCH0; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
714 REGMODE7 = 0 */
715 };
716
717 union {
718 __I uint32_t CAP1; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
719 = 1 */
720 __IO uint32_t MATCH1; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
721 REGMODE7 = 0 */
722 };
723
724 union {
725 __I uint32_t CAP2; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
726 = 1 */
727 __IO uint32_t MATCH2; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
728 REGMODE7 = 0 */
729 };
730
731 union {
732 __IO uint32_t MATCH3; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
733 REGMODE7 = 0 */
734 __I uint32_t CAP3; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
735 = 1 */
736 };
737
738 union {
739 __I uint32_t CAP4; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
740 = 1 */
741 __IO uint32_t MATCH4; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
742 REGMODE7 = 0 */
743 };
744
745 union {
746 __IO uint32_t MATCH5; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
747 REGMODE7 = 0 */
748 __I uint32_t CAP5; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
749 = 1 */
750 };
751
752 union {
753 __I uint32_t CAP6; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
754 = 1 */
755 __IO uint32_t MATCH6; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
756 REGMODE7 = 0 */
757 };
758
759 union {
760 __I uint32_t CAP7; /*!< SCT capture register of capture channel 0 to 7; REGMOD0 to REGMODE7
761 = 1 */
762 __IO uint32_t MATCH7; /*!< SCT match value register of match channels 0 to 7; REGMOD0 to
763 REGMODE7 = 0 */
764 };
765 __I uint32_t RESERVED2[56];
766
767 union {
768 __IO uint32_t CAPCTRL0; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
769 = 1 */
770 __IO uint32_t MATCHREL0; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
771 = 0 */
772 };
773
774 union {
775 __IO uint32_t CAPCTRL1; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
776 = 1 */
777 __IO uint32_t MATCHREL1; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
778 = 0 */
779 };
780
781 union {
782 __IO uint32_t CAPCTRL2; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
783 = 1 */
784 __IO uint32_t MATCHREL2; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
785 = 0 */
786 };
787
788 union {
789 __IO uint32_t MATCHREL3; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
790 = 0 */
791 __IO uint32_t CAPCTRL3; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
792 = 1 */
793 };
794
795 union {
796 __IO uint32_t CAPCTRL4; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
797 = 1 */
798 __IO uint32_t MATCHREL4; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
799 = 0 */
800 };
801
802 union {
803 __IO uint32_t MATCHREL5; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
804 = 0 */
805 __IO uint32_t CAPCTRL5; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
806 = 1 */
807 };
808
809 union {
810 __IO uint32_t CAPCTRL6; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
811 = 1 */
812 __IO uint32_t MATCHREL6; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
813 = 0 */
814 };
815
816 union {
817 __IO uint32_t CAPCTRL7; /*!< SCT capture control register 0 to 7; REGMOD0 = 1 to REGMODE7
818 = 1 */
819 __IO uint32_t MATCHREL7; /*!< SCT match reload value register 0 to 7; REGMOD0 = 0 to REGMODE7
820 = 0 */
821 };
822 __I uint32_t RESERVED3[56];
823 __IO uint32_t EV0_STATE; /*!< SCT event state register 0 */
824 __IO uint32_t EV0_CTRL; /*!< SCT event control register 0 */
825 __IO uint32_t EV1_STATE; /*!< SCT event state register 0 */
826 __IO uint32_t EV1_CTRL; /*!< SCT event control register 0 */
827 __IO uint32_t EV2_STATE; /*!< SCT event state register 0 */
828 __IO uint32_t EV2_CTRL; /*!< SCT event control register 0 */
829 __IO uint32_t EV3_STATE; /*!< SCT event state register 0 */
830 __IO uint32_t EV3_CTRL; /*!< SCT event control register 0 */
831 __IO uint32_t EV4_STATE; /*!< SCT event state register 0 */
832 __IO uint32_t EV4_CTRL; /*!< SCT event control register 0 */
833 __IO uint32_t EV5_STATE; /*!< SCT event state register 0 */
834 __IO uint32_t EV5_CTRL; /*!< SCT event control register 0 */
835 __IO uint32_t EV6_STATE; /*!< SCT event state register 0 */
836 __IO uint32_t EV6_CTRL; /*!< SCT event control register 0 */
837 __IO uint32_t EV7_STATE; /*!< SCT event state register 0 */
838 __IO uint32_t EV7_CTRL; /*!< SCT event control register 0 */
839 __IO uint32_t EV8_STATE; /*!< SCT event state register 0 */
840 __IO uint32_t EV8_CTRL; /*!< SCT event control register 0 */
841 __IO uint32_t EV9_STATE; /*!< SCT event state register 0 */
842 __IO uint32_t EV9_CTRL; /*!< SCT event control register 0 */
843 __I uint32_t RESERVED4[108];
844 __IO uint32_t OUT0_SET; /*!< SCT output 0 set register */
845 __IO uint32_t OUT0_CLR; /*!< SCT output 0 clear register */
846 __IO uint32_t OUT1_SET; /*!< SCT output 0 set register */
847 __IO uint32_t OUT1_CLR; /*!< SCT output 0 clear register */
848 __IO uint32_t OUT2_SET; /*!< SCT output 0 set register */
849 __IO uint32_t OUT2_CLR; /*!< SCT output 0 clear register */
850 __IO uint32_t OUT3_SET; /*!< SCT output 0 set register */
851 __IO uint32_t OUT3_CLR; /*!< SCT output 0 clear register */
852 __IO uint32_t OUT4_SET; /*!< SCT output 0 set register */
853 __IO uint32_t OUT4_CLR; /*!< SCT output 0 clear register */
854 __IO uint32_t OUT5_SET; /*!< SCT output 0 set register */
855 __IO uint32_t OUT5_CLR; /*!< SCT output 0 clear register */
856 } LPC_SCT2_Type;
857
858
859 /* ================================================================================ */
860 /* ================ ADC0 ================ */
861 /* ================================================================================ */
862
863
864 /**
865 * @brief 12-bit ADC controller ADC0/1 (ADC0)
866 */
867
868 typedef struct { /*!< ADC0 Structure */
869 __IO uint32_t CTRL; /*!< A/D Control Register. Contains the clock divide value, enable
870 bits for each sequence and the A/D power-down bit. */
871 __IO uint32_t INSEL; /*!< A/D Input Select Register: Selects between external pin and
872 internal source for various channels */
873 __IO uint32_t SEQA_CTRL; /*!< A/D Conversion Sequence-A control Register: Controls triggering
874 and channel selection for conversion sequence-A. Also specifies
875 interrupt mode for sequence-A. */
876 __IO uint32_t SEQB_CTRL; /*!< A/D Conversion Sequence-B Control Register: Controls triggering
877 and channel selection for conversion sequence-B. Also specifies
878 interrupt mode for sequence-B. */
879 __IO uint32_t SEQA_GDAT; /*!< A/D Sequence-A Global Data Register. This register contains
880 the result of the most recent A/D conversion performed under
881 sequence-A */
882 __IO uint32_t SEQB_GDAT; /*!< A/D Sequence-B Global Data Register. This register contains
883 the result of the most recent A/D conversion performed under
884 sequence-B */
885 __I uint32_t RESERVED0[2];
886 __I uint32_t DAT[12]; /*!< A/D Channel 0 Data Register. This register contains the result
887 of the most recent conversion completed on channel 0. */
888 __IO uint32_t THR0_LOW; /*!< A/D Low Compare Threshold Register 0 : Contains the lower threshold
889 level for automatic threshold comparison for any channels linked
890 to threshold pair 0. */
891 __IO uint32_t THR1_LOW; /*!< A/D Low Compare Threshold Register 1: Contains the lower threshold
892 level for automatic threshold comparison for any channels linked
893 to threshold pair 1. */
894 __IO uint32_t THR0_HIGH; /*!< A/D High Compare Threshold Register 0: Contains the upper threshold
895 level for automatic threshold comparison for any channels linked
896 to threshold pair 0. */
897 __IO uint32_t THR1_HIGH; /*!< A/D High Compare Threshold Register 1: Contains the upper threshold
898 level for automatic threshold comparison for any channels linked
899 to threshold pair 1. */
900 __I uint32_t CHAN_THRSEL; /*!< A/D Channel-Threshold Select Register. Specifies which set of
901 threshold compare registers are to be used for each channel */
902 __IO uint32_t INTEN; /*!< A/D Interrupt Enable Register. This register contains enable
903 bits that enable the sequence-A, sequence-B, threshold compare
904 and data overrun interrupts to be generated. */
905 __I uint32_t FLAGS; /*!< A/D Flags Register. Contains the four interrupt request flags
906 and the individual component overrun and threshold-compare flags.
907 (The overrun bits replicate information stored in the result
908 registers). */
909 __IO uint32_t TRM; /*!< ADC trim register. */
910 } LPC_ADC0_Type;
911
912
913 /* ================================================================================ */
914 /* ================ DAC ================ */
915 /* ================================================================================ */
916
917
918 /**
919 * @brief 12-bit DAC Modification (DAC)
920 */
921
922 typedef struct { /*!< DAC Structure */
923 __IO uint32_t VAL; /*!< D/A Converter Value Register. This register contains the digital
924 value to be converted to analog. */
925 __IO uint32_t CTRL; /*!< DAC Control register. This register contains bits to configure
926 DAC operation and the interrupt/dma request flag. */
927 __IO uint32_t CNTVAL; /*!< DAC Counter Value register. This register contains the reload
928 value for the internal DAC DMA/Interrupt timer. */
929 } LPC_DAC_Type;
930
931
932 /* ================================================================================ */
933 /* ================ ACMP ================ */
934 /* ================================================================================ */
935
936
937 /**
938 * @brief Analog comparators ACMP0/1/2/3 (ACMP)
939 */
940
941 typedef struct { /*!< ACMP Structure */
942 __IO uint32_t CTRL; /*!< Comparator block control register */
943 __IO uint32_t CMP0; /*!< Comparator 0 source control */
944 __IO uint32_t CMPFILTR0; /*!< Comparator 0 pin filter set-up */
945 __IO uint32_t CMP1; /*!< Comparator 1 source control */
946 __IO uint32_t CMPFILTR1; /*!< Comparator 0 pin filter set-up */
947 __IO uint32_t CMP2; /*!< Comparator 2 source control */
948 __IO uint32_t CMPFILTR2; /*!< Comparator 0 pin filter set-up */
949 __IO uint32_t CMP3; /*!< Comparator 3 source control */
950 __IO uint32_t CMPFILTR3; /*!< Comparator 0 pin filter set-up */
951 } LPC_ACMP_Type;
952
953
954 /* ================================================================================ */
955 /* ================ INMUX ================ */
956 /* ================================================================================ */
957
958
959 /**
960 * @brief Input multiplexing (INMUX) (INMUX)
961 */
962
963 typedef struct { /*!< INMUX Structure */
964 __IO uint32_t SCT0_INMUX[7]; /*!< Pinmux register for SCT0 input 0 */
965 __I uint32_t RESERVED0;
966 __IO uint32_t SCT1_INMUX[7]; /*!< Pinmux register for SCT1 input 0 */
967 __I uint32_t RESERVED1;
968 __IO uint32_t SCT2_INMUX[3]; /*!< Pinmux register for SCT2 input 0 */
969 __I uint32_t RESERVED2[5];
970 __IO uint32_t SCT3_INMUX[3]; /*!< Pinmux register for SCT3 input 0 */
971 __I uint32_t RESERVED3[21];
972 __IO uint32_t PINTSEL[8]; /*!< Pin interrupt select register 0 */
973 __IO uint32_t DMA_ITRIG_INMUX[18]; /*!< Trigger input for DMA channel 0 select register. */
974 __I uint32_t RESERVED4[14];
975 __IO uint32_t FREQMEAS_REF; /*!< Clock selection for frequency measurement function reference
976 clock */
977 __IO uint32_t FREQMEAS_TARGET; /*!< Clock selection for frequency measurement function target clock */
978 } LPC_INMUX_Type;
979
980
981 /* ================================================================================ */
982 /* ================ RTC ================ */
983 /* ================================================================================ */
984
985
986 /**
987 * @brief Real-Time Clock (RTC) (RTC)
988 */
989
990 typedef struct { /*!< RTC Structure */
991 __IO uint32_t CTRL; /*!< RTC control register */
992 __IO uint32_t MATCH; /*!< RTC match register */
993 __IO uint32_t COUNT; /*!< RTC counter register */
994 __IO uint32_t WAKE; /*!< RTC high-resolution/wake-up timer control register */
995 } LPC_RTC_Type;
996
997
998 /* ================================================================================ */
999 /* ================ WWDT ================ */
1000 /* ================================================================================ */
1001
1002
1003 /**
1004 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
1005 */
1006
1007 typedef struct { /*!< WWDT Structure */
1008 __IO uint32_t MOD; /*!< Watchdog mode register. This register contains the basic mode
1009 and status of the Watchdog Timer. */
1010 __IO uint32_t TC; /*!< Watchdog timer constant register. This 24-bit register determines
1011 the time-out value. */
1012 __O uint32_t FEED; /*!< Watchdog feed sequence register. Writing 0xAA followed by 0x55
1013 to this register reloads the Watchdog timer with the value contained
1014 in WDTC. */
1015 __I uint32_t TV; /*!< Watchdog timer value register. This 24-bit register reads out
1016 the current value of the Watchdog timer. */
1017 __I uint32_t RESERVED0;
1018 __IO uint32_t WARNINT; /*!< Watchdog Warning Interrupt compare value. */
1019 __IO uint32_t WINDOW; /*!< Watchdog Window compare value. */
1020 } LPC_WWDT_Type;
1021
1022
1023 /* ================================================================================ */
1024 /* ================ SWM ================ */
1025 /* ================================================================================ */
1026
1027
1028 /**
1029 * @brief Switch Matrix (SWM) (SWM)
1030 */
1031
1032 typedef struct { /*!< SWM Structure */
1033 union {
1034 __IO uint32_t PINASSIGN[16];
1035 struct {
1036 __IO uint32_t PINASSIGN0; /*!< Pin assign register 0. Assign movable functions U0_TXD, U0_RXD,
1037 U0_RTS, U0_CTS. */
1038 __IO uint32_t PINASSIGN1; /*!< Pin assign register 1. Assign movable functions U0_SCLK, U1_TXD,
1039 U1_RXD, U1_RTS. */
1040 __IO uint32_t PINASSIGN2; /*!< Pin assign register 2. Assign movable functions U1_CTS, U1_SCLK,
1041 U2_TXD, U2_RXD. */
1042 __IO uint32_t PINASSIGN3; /*!< Pin assign register 3. Assign movable function . */
1043 __IO uint32_t PINASSIGN4; /*!< Pin assign register 4. Assign movable functions */
1044 __IO uint32_t PINASSIGN5; /*!< Pin assign register 5. Assign movable functions */
1045 __IO uint32_t PINASSIGN6; /*!< Pin assign register 6. Assign movable functions */
1046 __IO uint32_t PINASSIGN7; /*!< Pin assign register 7. Assign movable functions */
1047 __IO uint32_t PINASSIGN8; /*!< Pin assign register 8. Assign movable functions */
1048 __IO uint32_t PINASSIGN9; /*!< Pin assign register 9. Assign movable functions */
1049 __IO uint32_t PINASSIGN10; /*!< Pin assign register 10. Assign movable functions */
1050 __IO uint32_t PINASSIGN11; /*!< Pin assign register 11. Assign movable functions */
1051 __IO uint32_t PINASSIGN12; /*!< Pin assign register 12. Assign movable functions */
1052 __IO uint32_t PINASSIGN13; /*!< Pin assign register 13. Assign movable functions */
1053 __IO uint32_t PINASSIGN14; /*!< Pin assign register 14. Assign movable functions */
1054 __IO uint32_t PINASSIGN15; /*!< Pin assign register 15. Assign movable functions */
1055 };
1056 };
1057 __I uint32_t RESERVED0[96];
1058 __IO uint32_t PINENABLE0; /*!< Pin enable register 0. Enables fixed-pin functions */
1059 __IO uint32_t PINENABLE1; /*!< Pin enable register 0. Enables fixed-pin functions */
1060 } LPC_SWM_Type;
1061
1062
1063 /* ================================================================================ */
1064 /* ================ PMU ================ */
1065 /* ================================================================================ */
1066
1067
1068 /**
1069 * @brief Power Management Unit (PMU) (PMU)
1070 */
1071
1072 typedef struct { /*!< PMU Structure */
1073 __IO uint32_t PCON; /*!< Power control register */
1074 __IO uint32_t GPREG0; /*!< General purpose register 0 */
1075 __IO uint32_t GPREG1; /*!< General purpose register 0 */
1076 __IO uint32_t GPREG2; /*!< General purpose register 0 */
1077 __IO uint32_t GPREG3; /*!< General purpose register 0 */
1078 __IO uint32_t DPDCTRL; /*!< Deep power-down control register */
1079 } LPC_PMU_Type;
1080
1081
1082 /* ================================================================================ */
1083 /* ================ USART0 ================ */
1084 /* ================================================================================ */
1085
1086
1087 /**
1088 * @brief USART0 (USART0)
1089 */
1090
1091 typedef struct { /*!< USART0 Structure */
1092 __IO uint32_t CFG; /*!< USART Configuration register. Basic USART configuration settings
1093 that typically are not changed during operation. */
1094 __IO uint32_t CTRL; /*!< USART Control register. USART control settings that are more
1095 likely to change during operation. */
1096 __IO uint32_t STAT; /*!< USART Status register. The complete status value can be read
1097 here. Writing ones clears some bits in the register. Some bits
1098 can be cleared by writing a 1 to them. */
1099 __IO uint32_t INTENSET; /*!< Interrupt Enable read and Set register. Contains an individual
1100 interrupt enable bit for each potential USART interrupt. A complete
1101 value may be read from this register. Writing a 1 to any implemented
1102 bit position causes that bit to be set. */
1103 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. Allows clearing any combination
1104 of bits in the INTENSET register. Writing a 1 to any implemented
1105 bit position causes the corresponding bit to be cleared. */
1106 __I uint32_t RXDATA; /*!< Receiver Data register. Contains the last character received. */
1107 __I uint32_t RXDATASTAT; /*!< Receiver Data with Status register. Combines the last character
1108 received with the current USART receive status. Allows DMA or
1109 software to recover incoming data and status together. */
1110 __IO uint32_t TXDATA; /*!< Transmit Data register. Data to be transmitted is written here. */
1111 __IO uint32_t BRG; /*!< Baud Rate Generator register. 16-bit integer baud rate divisor
1112 value. */
1113 __I uint32_t INTSTAT; /*!< Interrupt status register. Reflects interrupts that are currently
1114 enabled. */
1115 } LPC_USART0_Type;
1116
1117
1118 /* ================================================================================ */
1119 /* ================ SPI0 ================ */
1120 /* ================================================================================ */
1121
1122
1123 /**
1124 * @brief SPI0 (SPI0)
1125 */
1126
1127 typedef struct { /*!< SPI0 Structure */
1128 __IO uint32_t CFG; /*!< SPI Configuration register */
1129 __IO uint32_t DLY; /*!< SPI Delay register */
1130 __IO uint32_t STAT; /*!< SPI Status. Some status flags can be cleared by writing a 1
1131 to that bit position */
1132 __IO uint32_t INTENSET; /*!< SPI Interrupt Enable read and Set. A complete value may be read
1133 from this register. Writing a 1 to any implemented bit position
1134 causes that bit to be set. */
1135 __O uint32_t INTENCLR; /*!< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit
1136 position causes the corresponding bit in INTENSET to be cleared. */
1137 __I uint32_t RXDAT; /*!< SPI Receive Data */
1138 __IO uint32_t TXDATCTL; /*!< SPI Transmit Data with Control */
1139 __IO uint32_t TXDAT; /*!< SPI Transmit Data with Control */
1140 __IO uint32_t TXCTL; /*!< SPI Transmit Control */
1141 __IO uint32_t DIV; /*!< SPI clock Divider */
1142 __I uint32_t INTSTAT; /*!< SPI Interrupt Status */
1143 } LPC_SPI0_Type;
1144
1145
1146 /* ================================================================================ */
1147 /* ================ I2C0 ================ */
1148 /* ================================================================================ */
1149
1150
1151 /**
1152 * @brief I2C-bus interface (I2C0)
1153 */
1154
1155 typedef struct { /*!< I2C0 Structure */
1156 __IO uint32_t CFG; /*!< Configuration for shared functions. */
1157 __IO uint32_t STAT; /*!< Status register for Master, Slave, and Monitor functions. */
1158 __IO uint32_t INTENSET; /*!< Interrupt Enable Set and read register. */
1159 __O uint32_t INTENCLR; /*!< Interrupt Enable Clear register. */
1160 __IO uint32_t TIMEOUT; /*!< Time-out value register. */
1161 __IO uint32_t DIV; /*!< Clock pre-divider for the entire I2C block. This determines
1162 what time increments are used for the MSTTIME and SLVTIME registers. */
1163 __I uint32_t INTSTAT; /*!< Interrupt Status register for Master, Slave, and Monitor functions. */
1164 __I uint32_t RESERVED0;
1165 __IO uint32_t MSTCTL; /*!< Master control register. */
1166 __IO uint32_t MSTTIME; /*!< Master timing configuration. */
1167 __IO uint32_t MSTDAT; /*!< Combined Master receiver and transmitter data register. */
1168 __I uint32_t RESERVED1[5];
1169 __IO uint32_t SLVCTL; /*!< Slave control register. */
1170 __IO uint32_t SLVDAT; /*!< Combined Slave receiver and transmitter data register. */
1171 __IO uint32_t SLVADR0; /*!< Slave address 0. */
1172 __IO uint32_t SLVADR1; /*!< Slave address 0. */
1173 __IO uint32_t SLVADR2; /*!< Slave address 0. */
1174 __IO uint32_t SLVADR3; /*!< Slave address 0. */
1175 __IO uint32_t SLVQUAL0; /*!< Slave Qualification for address 0. */
1176 __I uint32_t RESERVED2[9];
1177 __I uint32_t MONRXDAT; /*!< Monitor receiver data register. */
1178 } LPC_I2C0_Type;
1179
1180
1181 /* ================================================================================ */
1182 /* ================ QEI ================ */
1183 /* ================================================================================ */
1184
1185
1186 /**
1187 * @brief Quadrature Encoder Interface (QEI) (QEI)
1188 */
1189
1190 typedef struct { /*!< QEI Structure */
1191 __O uint32_t CON; /*!< Control register */
1192 __I uint32_t STAT; /*!< Encoder status register */
1193 __IO uint32_t CONF; /*!< Configuration register */
1194 __I uint32_t POS; /*!< Position register */
1195 __IO uint32_t MAXPOS; /*!< Maximum position register */
1196 __IO uint32_t CMPOS0; /*!< position compare register 0 */
1197 __IO uint32_t CMPOS1; /*!< position compare register 1 */
1198 __IO uint32_t CMPOS2; /*!< position compare register 2 */
1199 __I uint32_t INXCNT; /*!< Index count register */
1200 __IO uint32_t INXCMP0; /*!< Index compare register 0 */
1201 __IO uint32_t LOAD; /*!< Velocity timer reload register */
1202 __I uint32_t TIME; /*!< Velocity timer register */
1203 __I uint32_t VEL; /*!< Velocity counter register */
1204 __I uint32_t CAP; /*!< Velocity capture register */
1205 __IO uint32_t VELCOMP; /*!< Velocity compare register */
1206 __IO uint32_t FILTERPHA; /*!< Digital filter register on input phase A (QEI_A) */
1207 __IO uint32_t FILTERPHB; /*!< Digital filter register on input phase B (QEI_B) */
1208 __IO uint32_t FILTERINX; /*!< Digital filter register on input index (QEI_IDX) */
1209 __IO uint32_t WINDOW; /*!< Index acceptance window register */
1210 __IO uint32_t INXCMP1; /*!< Index compare register 1 */
1211 __IO uint32_t INXCMP2; /*!< Index compare register 2 */
1212 __I uint32_t RESERVED0[993];
1213 __O uint32_t IEC; /*!< Interrupt enable clear register */
1214 __O uint32_t IES; /*!< Interrupt enable set register */
1215 __I uint32_t INTSTAT; /*!< Interrupt status register */
1216 __O uint32_t IE; /*!< Interrupt enable clear register */
1217 __O uint32_t CLR; /*!< Interrupt status clear register */
1218 __O uint32_t SET; /*!< Interrupt status set register */
1219 } LPC_QEI_Type;
1220
1221
1222 /* ================================================================================ */
1223 /* ================ SYSCON ================ */
1224 /* ================================================================================ */
1225
1226
1227 /**
1228 * @brief System configuration (SYSCON) (SYSCON)
1229 */
1230
1231 typedef struct { /*!< SYSCON Structure */
1232 __IO uint32_t SYSMEMREMAP; /*!< System memory remap */
1233 __I uint32_t RESERVED0[4];
1234 __IO uint32_t SYSTCKCAL; /*!< System tick counter calibration */
1235 __I uint32_t RESERVED1;
1236 __IO uint32_t NMISRC; /*!< NMI Source Control */
1237 __I uint32_t RESERVED2[8];
1238 __IO uint32_t SYSRSTSTAT; /*!< System reset status register */
1239 __IO uint32_t PRESETCTRL0; /*!< Peripheral reset control 0 */
1240 __IO uint32_t PRESETCTRL1; /*!< Peripheral reset control 1 */
1241 __I uint32_t PIOPORCAP0; /*!< POR captured PIO status 0 */
1242 __I uint32_t PIOPORCAP1; /*!< POR captured PIO status 1 */
1243 __I uint32_t PIOPORCAP2; /*!< POR captured PIO status 2 */
1244 __I uint32_t RESERVED3[10];
1245 __IO uint32_t MAINCLKSELA; /*!< Main clock source select A */
1246 __IO uint32_t MAINCLKSELB; /*!< Main clock source select B */
1247 __IO uint32_t USBCLKSEL; /*!< USB clock source select */
1248 __IO uint32_t ADCASYNCCLKSEL; /*!< ADC asynchronous clock source select */
1249 __I uint32_t RESERVED4;
1250 __IO uint32_t CLKOUTSELA; /*!< CLKOUT clock source select A */
1251 __IO uint32_t CLKOUTSELB; /*!< CLKOUT clock source select B */
1252 __I uint32_t RESERVED5;
1253 __IO uint32_t SYSPLLCLKSEL; /*!< System PLL clock source select */
1254 __IO uint32_t USBPLLCLKSEL; /*!< USB PLL clock source select */
1255 __IO uint32_t SCTPLLCLKSEL; /*!< SCT PLL clock source select */
1256 __I uint32_t RESERVED6[5];
1257 __IO uint32_t SYSAHBCLKDIV; /*!< System clock divider */
1258 __IO uint32_t SYSAHBCLKCTRL0; /*!< System clock control 0 */
1259 __IO uint32_t SYSAHBCLKCTRL1; /*!< System clock control 1 */
1260 __IO uint32_t SYSTICKCLKDIV; /*!< SYSTICK clock divider */
1261 __IO uint32_t UARTCLKDIV; /*!< USART clock divider. Clock divider for the USART fractional
1262 baud rate generator. */
1263 __IO uint32_t IOCONCLKDIV; /*!< Peripheral clock to the IOCON block for programmable glitch
1264 filter */
1265 __IO uint32_t TRACECLKDIV; /*!< ARM trace clock divider */
1266 __I uint32_t RESERVED7[4];
1267 __IO uint32_t USBCLKDIV; /*!< USB clock divider */
1268 __IO uint32_t ADCASYNCCLKDIV; /*!< Asynchronous ADC clock divider */
1269 __I uint32_t RESERVED8;
1270 __IO uint32_t CLKOUTDIV; /*!< CLKOUT clock divider */
1271 __I uint32_t RESERVED9[11];
1272 __IO uint32_t FRGCTRL; /*!< USART fractional baud rate generator control */
1273 __IO uint32_t USBCLKCTRL; /*!< USB clock control */
1274 __IO uint32_t USBCLKST; /*!< USB clock status */
1275 __I uint32_t RESERVED10[19];
1276 __IO uint32_t BODCTRL; /*!< Brown-Out Detect */
1277 __I uint32_t RESERVED11;
1278 __IO uint32_t SYSOSCCTRL; /*!< System oscillator control */
1279 __I uint32_t RESERVED12;
1280 __IO uint32_t RTCOSCCTRL; /*!< RTC oscillator control */
1281 __I uint32_t RESERVED13;
1282 __IO uint32_t SYSPLLCTRL; /*!< System PLL control */
1283 __I uint32_t SYSPLLSTAT; /*!< System PLL status */
1284 __IO uint32_t USBPLLCTRL; /*!< USB PLL control */
1285 __I uint32_t USBPLLSTAT; /*!< USB PLL status */
1286 __IO uint32_t SCTPLLCTRL; /*!< SCT PLL control */
1287 __I uint32_t SCTPLLSTAT; /*!< SCT PLL status */
1288 __I uint32_t RESERVED14[21];
1289 __IO uint32_t PDAWAKECFG; /*!< Power-down states for wake-up from deep-sleep */
1290 __IO uint32_t PDRUNCFG; /*!< Power configuration register */
1291 __I uint32_t RESERVED15[3];
1292 __IO uint32_t STARTERP0; /*!< Start logic 0 wake-up enable register */
1293 __IO uint32_t STARTERP1; /*!< Start logic 1 wake-up enable register */
1294 } LPC_SYSCON_Type;
1295
1296
1297 /* ================================================================================ */
1298 /* ================ MRT ================ */
1299 /* ================================================================================ */
1300
1301
1302 /**
1303 * @brief Multi-Rate Timer (MRT) (MRT)
1304 */
1305
1306 typedef struct { /*!< MRT Structure */
1307 __IO uint32_t INTVAL0; /*!< MRT0 Time interval value register. This value is loaded into
1308 the TIMER0 register. */
1309 __I uint32_t TIMER0; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
1310 __IO uint32_t CTRL0; /*!< MRT0 Control register. This register controls the MRT0 modes. */
1311 __IO uint32_t STAT0; /*!< MRT0 Status register. */
1312 __IO uint32_t INTVAL1; /*!< MRT0 Time interval value register. This value is loaded into
1313 the TIMER0 register. */
1314 __I uint32_t TIMER1; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
1315 __IO uint32_t CTRL1; /*!< MRT0 Control register. This register controls the MRT0 modes. */
1316 __IO uint32_t STAT1; /*!< MRT0 Status register. */
1317 __IO uint32_t INTVAL2; /*!< MRT0 Time interval value register. This value is loaded into
1318 the TIMER0 register. */
1319 __I uint32_t TIMER2; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
1320 __IO uint32_t CTRL2; /*!< MRT0 Control register. This register controls the MRT0 modes. */
1321 __IO uint32_t STAT2; /*!< MRT0 Status register. */
1322 __IO uint32_t INTVAL3; /*!< MRT0 Time interval value register. This value is loaded into
1323 the TIMER0 register. */
1324 __I uint32_t TIMER3; /*!< MRT0 Timer register. This register reads the value of the down-counter. */
1325 __IO uint32_t CTRL3; /*!< MRT0 Control register. This register controls the MRT0 modes. */
1326 __IO uint32_t STAT3; /*!< MRT0 Status register. */
1327 __I uint32_t RESERVED0[45];
1328 __I uint32_t IDLE_CH; /*!< Idle channel register. This register returns the number of the
1329 first idle channel. */
1330 __IO uint32_t IRQ_FLAG; /*!< Global interrupt flag register */
1331 } LPC_MRT_Type;
1332
1333
1334 /* ================================================================================ */
1335 /* ================ PINT ================ */
1336 /* ================================================================================ */
1337
1338
1339 /**
1340 * @brief Pin interruptand pattern match (PINT) (PINT)
1341 */
1342
1343 typedef struct { /*!< PINT Structure */
1344 __IO uint32_t ISEL; /*!< Pin Interrupt Mode register */
1345 __IO uint32_t IENR; /*!< Pin interrupt level or rising edge interrupt enable register */
1346 __O uint32_t SIENR; /*!< Pin interrupt level or rising edge interrupt set register */
1347 __O uint32_t CIENR; /*!< Pin interrupt level (rising edge interrupt) clear register */
1348 __IO uint32_t IENF; /*!< Pin interrupt active level or falling edge interrupt enable
1349 register */
1350 __O uint32_t SIENF; /*!< Pin interrupt active level or falling edge interrupt set register */
1351 __O uint32_t CIENF; /*!< Pin interrupt active level or falling edge interrupt clear register */
1352 __IO uint32_t RISE; /*!< Pin interrupt rising edge register */
1353 __IO uint32_t FALL; /*!< Pin interrupt falling edge register */
1354 __IO uint32_t IST; /*!< Pin interrupt status register */
1355 __IO uint32_t PMCTRL; /*!< Pattern match interrupt control register */
1356 __IO uint32_t PMSRC; /*!< Pattern match interrupt bit-slice source register */
1357 __IO uint32_t PMCFG; /*!< Pattern match interrupt bit slice configuration register */
1358 } LPC_PINT_Type;
1359
1360
1361 /* ================================================================================ */
1362 /* ================ GINT0 ================ */
1363 /* ================================================================================ */
1364
1365
1366 /**
1367 * @brief Group interrupt 0/1 (GINT0/1) (GINT0)
1368 */
1369
1370 typedef struct { /*!< GINT0 Structure */
1371 __IO uint32_t CTRL; /*!< GPIO grouped interrupt control register */
1372 __I uint32_t RESERVED0[7];
1373 __IO uint32_t PORT_POL[3]; /*!< GPIO grouped interrupt port 0 polarity register */
1374 __I uint32_t RESERVED1[5];
1375 __IO uint32_t PORT_ENA[3]; /*!< GPIO grouped interrupt port 0 enable register */
1376 } LPC_GINT0_Type;
1377
1378
1379 /* ================================================================================ */
1380 /* ================ RIT ================ */
1381 /* ================================================================================ */
1382
1383
1384 /**
1385 * @brief Repetitive Interrupt Timer (RIT) (RIT)
1386 */
1387
1388 typedef struct { /*!< RIT Structure */
1389 __IO uint32_t COMPVAL; /*!< Compare value LSB register. Holds the 32 LSBs of the compare
1390 value. */
1391 __IO uint32_t MASK; /*!< Mask LSB register. This register holds the 32 LSB s of the mask
1392 value. A 1 written to any bit will force a compare on the corresponding
1393 bit of the counter and compare register. */
1394 __IO uint32_t CTRL; /*!< Control register. */
1395 __IO uint32_t COUNTER; /*!< Counter LSB register. 32 LSBs of the counter. */
1396 __IO uint32_t COMPVAL_H; /*!< Compare value MSB register. Holds the 16 MSBs of the compare
1397 value. */
1398 __IO uint32_t MASK_H; /*!< Mask MSB register. This register holds the 16 MSBs of the mask
1399 value. A 1 written to any bit will force a compare on the corresponding
1400 bit of the counter and compare register. */
1401 __I uint32_t RESERVED0;
1402 __IO uint32_t COUNTER_H; /*!< Counter MSB register. 16 MSBs of the counter. */
1403 } LPC_RIT_Type;
1404
1405
1406 /* ================================================================================ */
1407 /* ================ SCTIPU ================ */
1408 /* ================================================================================ */
1409
1410
1411 /**
1412 * @brief SCT Input Processing Unit (IPU) (SCTIPU)
1413 */
1414
1415 typedef struct { /*!< SCTIPU Structure */
1416 __IO uint32_t SAMPLE_CTRL; /*!< SCT IPU sample control register. Contains the input mux selects,
1417 latch/sample-enable mux selects, and sample overrride bits for
1418 the SAMPLE module. */
1419 __I uint32_t RESERVED0[7];
1420 __IO uint32_t ABORT_ENABLE0; /*!< SCT IPU abort enable register: Selects which input source contributes
1421 to ORed Abort Output 0. */
1422 __IO uint32_t ABORT_SOURCE0; /*!< SCT IPU abort source register: Status register indicating which
1423 input source caused abort output 0. */
1424 __I uint32_t RESERVED1[6];
1425 __IO uint32_t ABORT_ENABLE1; /*!< SCT IPU abort enable register: Selects which input source contributes
1426 to ORed Abort Output 0. */
1427 __IO uint32_t ABORT_SOURCE1; /*!< SCT IPU abort source register: Status register indicating which
1428 input source caused abort output 0. */
1429 __I uint32_t RESERVED2[6];
1430 __IO uint32_t ABORT_ENABLE2; /*!< SCT IPU abort enable register: Selects which input source contributes
1431 to ORed Abort Output 0. */
1432 __IO uint32_t ABORT_SOURCE2; /*!< SCT IPU abort source register: Status register indicating which
1433 input source caused abort output 0. */
1434 __I uint32_t RESERVED3[6];
1435 __IO uint32_t ABORT_ENABLE3; /*!< SCT IPU abort enable register: Selects which input source contributes
1436 to ORed Abort Output 0. */
1437 __IO uint32_t ABORT_SOURCE3; /*!< SCT IPU abort source register: Status register indicating which
1438 input source caused abort output 0. */
1439 } LPC_SCTIPU_Type;
1440
1441
1442 /* ================================================================================ */
1443 /* ================ FLASHCTRL ================ */
1444 /* ================================================================================ */
1445
1446
1447 /**
1448 * @brief Flash controller (FLASHCTRL)
1449 */
1450
1451 typedef struct { /*!< FLASHCTRL Structure */
1452 __I uint32_t RESERVED0[8];
1453 __IO uint32_t FMSSTART; /*!< Signature start address register */
1454 __IO uint32_t FMSSTOP; /*!< Signature stop-address register */
1455 __I uint32_t RESERVED1;
1456 __I uint32_t FMSW0; /*!< Signature word */
1457 } LPC_FLASHCTRL_Type;
1458
1459
1460 /* ================================================================================ */
1461 /* ================ C_CAN0 ================ */
1462 /* ================================================================================ */
1463
1464
1465 /**
1466 * @brief Controller Area Network C_CAN0 (C_CAN0)
1467 */
1468
1469 typedef struct { /*!< C_CAN0 Structure */
1470 __IO uint32_t CANCNTL; /*!< CAN control */
1471 __IO uint32_t CANSTAT; /*!< Status register */
1472 __I uint32_t CANEC; /*!< Error counter */
1473 __IO uint32_t CANBT; /*!< Bit timing register */
1474 __I uint32_t CANINT; /*!< Interrupt register */
1475 __IO uint32_t CANTEST; /*!< Test register */
1476 __IO uint32_t CANBRPE; /*!< Baud rate prescaler extension register */
1477 __I uint32_t RESERVED0;
1478 __IO uint32_t CANIF1_CMDREQ; /*!< Message interface 1 command request */
1479
1480 union {
1481 __IO uint32_t CANIF1_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
1482 __IO uint32_t CANIF1_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
1483 };
1484 __IO uint32_t CANIF1_MSK1; /*!< Message interface 1 mask 1 */
1485 __IO uint32_t CANIF1_MSK2; /*!< Message interface 1 mask 2 */
1486 __IO uint32_t CANIF1_ARB1; /*!< Message interface 1 arbitration 1 */
1487 __IO uint32_t CANIF1_ARB2; /*!< Message interface 1 arbitration 2 */
1488 __IO uint32_t CANIF1_MCTRL; /*!< Message interface 1 message control */
1489 __IO uint32_t CANIF1_DA1; /*!< Message interface 1 data A1 */
1490 __IO uint32_t CANIF1_DA2; /*!< Message interface 1 data A2 */
1491 __IO uint32_t CANIF1_DB1; /*!< Message interface 1 data B1 */
1492 __IO uint32_t CANIF1_DB2; /*!< Message interface 1 data B2 */
1493 __I uint32_t RESERVED1[13];
1494 __IO uint32_t CANIF2_CMDREQ; /*!< Message interface 1 command request */
1495
1496 union {
1497 __IO uint32_t CANIF2_CMDMSK_W; /*!< Message interface 1 command mask (write direction) */
1498 __IO uint32_t CANIF2_CMDMSK_R; /*!< Message interface 1 command mask (read direction) */
1499 };
1500 __IO uint32_t CANIF2_MSK1; /*!< Message interface 1 mask 1 */
1501 __IO uint32_t CANIF2_MSK2; /*!< Message interface 1 mask 2 */
1502 __IO uint32_t CANIF2_ARB1; /*!< Message interface 1 arbitration 1 */
1503 __IO uint32_t CANIF2_ARB2; /*!< Message interface 1 arbitration 2 */
1504 __IO uint32_t CANIF2_MCTRL; /*!< Message interface 1 message control */
1505 __IO uint32_t CANIF2_DA1; /*!< Message interface 2 data A1 */
1506 __IO uint32_t CANIF2_DA2; /*!< Message interface 2 data A2 */
1507 __IO uint32_t CANIF2_DB1; /*!< Message interface 2 data B1 */
1508 __IO uint32_t CANIF2_DB2; /*!< Message interface 2 data B2 */
1509 __I uint32_t RESERVED2[21];
1510 __I uint32_t CANTXREQ1; /*!< Transmission request 1 */
1511 __I uint32_t CANTXREQ2; /*!< Transmission request 2 */
1512 __I uint32_t RESERVED3[6];
1513 __I uint32_t CANND1; /*!< New data 1 */
1514 __I uint32_t CANND2; /*!< New data 2 */
1515 __I uint32_t RESERVED4[6];
1516 __I uint32_t CANIR1; /*!< Interrupt pending 1 */
1517 __I uint32_t CANIR2; /*!< Interrupt pending 2 */
1518 __I uint32_t RESERVED5[6];
1519 __I uint32_t CANMSGV1; /*!< Message valid 1 */
1520 __I uint32_t CANMSGV2; /*!< Message valid 2 */
1521 __I uint32_t RESERVED6[6];
1522 __IO uint32_t CANCLKDIV; /*!< Can clock divider register */
1523 } LPC_C_CAN0_Type;
1524
1525
1526 /* ================================================================================ */
1527 /* ================ IOCON ================ */
1528 /* ================================================================================ */
1529
1530
1531 /**
1532 * @brief I/O pin configuration (IOCON) (IOCON)
1533 */
1534
1535 typedef struct { /*!< IOCON Structure */
1536 __IO uint32_t PIO0_0; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1537 __IO uint32_t PIO0_1; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1538 __IO uint32_t PIO0_2; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1539 __IO uint32_t PIO0_3; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1540 __IO uint32_t PIO0_4; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1541 __IO uint32_t PIO0_5; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1542 __IO uint32_t PIO0_6; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1543 __IO uint32_t PIO0_7; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1544 __IO uint32_t PIO0_8; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1545 __IO uint32_t PIO0_9; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1546 __IO uint32_t PIO0_10; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1547 __IO uint32_t PIO0_11; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1548 __IO uint32_t PIO0_12; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1549 __IO uint32_t PIO0_13; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1550 __IO uint32_t PIO0_14; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1551 __IO uint32_t PIO0_15; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1552 __IO uint32_t PIO0_16; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1553 __IO uint32_t PIO0_17; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1554 __IO uint32_t PIO0_18; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1555 __IO uint32_t PIO0_19; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1556 __IO uint32_t PIO0_20; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1557 __IO uint32_t PIO0_21; /*!< Digital I/O control for port 0 pins PIO0_0 to PIO0_21. */
1558 __IO uint32_t PIO0_22; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
1559 the I2C-bus SCL function. */
1560 __IO uint32_t PIO0_23; /*!< I/O control for open-drain pin PIO0_22. This pin is used for
1561 the I2C-bus SCL function. */
1562 __IO uint32_t PIO0_24; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1563 __IO uint32_t PIO0_25; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1564 __IO uint32_t PIO0_26; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1565 __IO uint32_t PIO0_27; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1566 __IO uint32_t PIO0_28; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1567 __IO uint32_t PIO0_29; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1568 __IO uint32_t PIO0_30; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1569 __IO uint32_t PIO0_31; /*!< Digital I/O control for port 0 pins PIO0_24 to PIO0_31. */
1570 __IO uint32_t PIO1_0; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1571 __IO uint32_t PIO1_1; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1572 __IO uint32_t PIO1_2; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1573 __IO uint32_t PIO1_3; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1574 __IO uint32_t PIO1_4; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1575 __IO uint32_t PIO1_5; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1576 __IO uint32_t PIO1_6; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1577 __IO uint32_t PIO1_7; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1578 __IO uint32_t PIO1_8; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1579 __IO uint32_t PIO1_9; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1580 __IO uint32_t PIO1_10; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1581 __IO uint32_t PIO1_11; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1582 __IO uint32_t PIO1_12; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1583 __IO uint32_t PIO1_13; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1584 __IO uint32_t PIO1_14; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1585 __IO uint32_t PIO1_15; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1586 __IO uint32_t PIO1_16; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1587 __IO uint32_t PIO1_17; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1588 __IO uint32_t PIO1_18; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1589 __IO uint32_t PIO1_19; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1590 __IO uint32_t PIO1_20; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1591 __IO uint32_t PIO1_21; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1592 __IO uint32_t PIO1_22; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1593 __IO uint32_t PIO1_23; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1594 __IO uint32_t PIO1_24; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1595 __IO uint32_t PIO1_25; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1596 __IO uint32_t PIO1_26; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1597 __IO uint32_t PIO1_27; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1598 __IO uint32_t PIO1_28; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1599 __IO uint32_t PIO1_29; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1600 __IO uint32_t PIO1_30; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1601 __IO uint32_t PIO1_31; /*!< Digital I/O control for port 1 pins PIO1_24 to PIO1_31. */
1602 __IO uint32_t PIO2_0; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1603 __IO uint32_t PIO2_1; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1604 __IO uint32_t PIO2_2; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1605 __IO uint32_t PIO2_3; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1606 __IO uint32_t PIO2_4; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1607 __IO uint32_t PIO2_5; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1608 __IO uint32_t PIO2_6; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1609 __IO uint32_t PIO2_7; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1610 __IO uint32_t PIO2_8; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1611 __IO uint32_t PIO2_9; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1612 __IO uint32_t PIO2_10; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1613 __IO uint32_t PIO2_11; /*!< Digital I/O control for port 2 pins PIO2_0 to PIO2_11. */
1614 } LPC_IOCON_Type;
1615
1616
1617 /* -------------------- End of section using anonymous unions ------------------- */
1618 #if defined(__CC_ARM)
1619 #pragma pop
1620 #elif defined(__ICCARM__)
1621 /* leave anonymous unions enabled */
1622 #elif defined(__GNUC__)
1623 /* anonymous unions are enabled by default */
1624 #elif defined(__TMS470__)
1625 /* anonymous unions are enabled by default */
1626 #elif defined(__TASKING__)
1627 #pragma warning restore
1628 #else
1629 #warning Not supported compiler type
1630 #endif
1631
1632
1633
1634
1635 /* ================================================================================ */
1636 /* ================ Peripheral memory map ================ */
1637 /* ================================================================================ */
1638
1639 #define LPC_GPIO_PORT_BASE 0x1C000000UL
1640 #define LPC_DMA_BASE 0x1C004000UL
1641 #define LPC_USB_BASE 0x1C00C000UL
1642 #define LPC_CRC_BASE 0x1C010000UL
1643 #define LPC_SCT0_BASE 0x1C018000UL
1644 #define LPC_SCT1_BASE 0x1C01C000UL
1645 #define LPC_SCT2_BASE 0x1C020000UL
1646 #define LPC_SCT3_BASE 0x1C024000UL
1647 #define LPC_ADC0_BASE 0x40000000UL
1648 #define LPC_DAC_BASE 0x40004000UL
1649 #define LPC_ACMP_BASE 0x40008000UL
1650 #define LPC_INMUX_BASE 0x40014000UL
1651 #define LPC_RTC_BASE 0x40028000UL
1652 #define LPC_WWDT_BASE 0x4002C000UL
1653 #define LPC_SWM_BASE 0x40038000UL
1654 #define LPC_PMU_BASE 0x4003C000UL
1655 #define LPC_USART0_BASE 0x40040000UL
1656 #define LPC_USART1_BASE 0x40044000UL
1657 #define LPC_SPI0_BASE 0x40048000UL
1658 #define LPC_SPI1_BASE 0x4004C000UL
1659 #define LPC_I2C0_BASE 0x40050000UL
1660 #define LPC_QEI_BASE 0x40058000UL
1661 #define LPC_SYSCON_BASE 0x40074000UL
1662 #define LPC_ADC1_BASE 0x40080000UL
1663 #define LPC_MRT_BASE 0x400A0000UL
1664 #define LPC_PINT_BASE 0x400A4000UL
1665 #define LPC_GINT0_BASE 0x400A8000UL
1666 #define LPC_GINT1_BASE 0x400AC000UL
1667 #define LPC_RIT_BASE 0x400B4000UL
1668 #define LPC_SCTIPU_BASE 0x400B8000UL
1669 #define LPC_FLASHCTRL_BASE 0x400BC000UL
1670 #define LPC_USART2_BASE 0x400C0000UL
1671 #define LPC_C_CAN0_BASE 0x400F0000UL
1672 #define LPC_IOCON_BASE 0x400F8000UL
1673
1674
1675 /* ================================================================================ */
1676 /* ================ Peripheral declaration ================ */
1677 /* ================================================================================ */
1678
1679 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
1680 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
1681 #define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
1682 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
1683 #define LPC_SCT0 ((LPC_SCT0_Type *) LPC_SCT0_BASE)
1684 #define LPC_SCT1 ((LPC_SCT0_Type *) LPC_SCT1_BASE)
1685 #define LPC_SCT2 ((LPC_SCT2_Type *) LPC_SCT2_BASE)
1686 #define LPC_SCT3 ((LPC_SCT2_Type *) LPC_SCT3_BASE)
1687 #define LPC_ADC0 ((LPC_ADC0_Type *) LPC_ADC0_BASE)
1688 #define LPC_DAC ((LPC_DAC_Type *) LPC_DAC_BASE)
1689 #define LPC_ACMP ((LPC_ACMP_Type *) LPC_ACMP_BASE)
1690 #define LPC_INMUX ((LPC_INMUX_Type *) LPC_INMUX_BASE)
1691 #define LPC_RTC ((LPC_RTC_Type *) LPC_RTC_BASE)
1692 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
1693 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
1694 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
1695 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
1696 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
1697 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
1698 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
1699 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
1700 #define LPC_QEI ((LPC_QEI_Type *) LPC_QEI_BASE)
1701 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
1702 #define LPC_ADC1 ((LPC_ADC0_Type *) LPC_ADC1_BASE)
1703 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
1704 #define LPC_PINT ((LPC_PINT_Type *) LPC_PINT_BASE)
1705 #define LPC_GINT0 ((LPC_GINT0_Type *) LPC_GINT0_BASE)
1706 #define LPC_GINT1 ((LPC_GINT0_Type *) LPC_GINT1_BASE)
1707 #define LPC_RIT ((LPC_RIT_Type *) LPC_RIT_BASE)
1708 #define LPC_SCTIPU ((LPC_SCTIPU_Type *) LPC_SCTIPU_BASE)
1709 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
1710 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
1711 #define LPC_C_CAN0 ((LPC_C_CAN0_Type *) LPC_C_CAN0_BASE)
1712 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
1713
1714
1715 /** @} */ /* End of group Device_Peripheral_Registers */
1716 /** @} */ /* End of group LPC15xx */
1717 /** @} */ /* End of group (null) */
1718
1719 #ifdef __cplusplus
1720 }
1721 #endif
1722
1723
1724 #endif /* LPC15XX_H */
1725
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