tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_ARM_MICRO/startup_LPC15xx.s

   1 ;/**************************************************************************//**
   2 ; * @file     startup_LPC15xx.s
   3 ; * @brief    CMSIS Cortex-M3 Core Device Startup File for
   4 ; *           NXP LPC15xx Device Series
   5 ; * @version  V1.00
   6 ; * @date     17. July 2013
   7 ; *
   8 ; * @note
   9 ; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
  10 ; *
  11 ; * @par
  12 ; * ARM Limited (ARM) is supplying this software for use with Cortex-M
  13 ; * processor based microcontrollers.  This file can be freely distributed
  14 ; * within development tools that are supporting such ARM based processors.
  15 ; *
  16 ; * @par
  17 ; * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  18 ; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  19 ; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  20 ; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  21 ; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  22 ; *
  23 ; ******************************************************************************/
  24
  25 ; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------
  26
  27 ; <h> Stack Configuration
  28 ;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  29 ; </h>
  30
  31 Stack_Size      EQU     0x00000200
  32
  33                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  34                 EXPORT  __initial_sp
  35
  36 __initial_sp        EQU     0x02009000  ; Top of RAM from LPC1549
  37
  38
  39 ; <h> Heap Configuration
  40 ;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  41 ; </h>
  42
  43 Heap_Size       EQU     0x00000000
  44
  45                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  46 __heap_base
  47 Heap_Mem        SPACE   Heap_Size
  48 __heap_limit
  49
  50
  51                 PRESERVE8
  52                 THUMB
  53
  54
  55 ; Vector Table Mapped to Address 0 at Reset
  56
  57                 AREA    RESET, DATA, READONLY
  58                 EXPORT  __Vectors
  59
  60 __Vectors       DCD     __initial_sp              ; Top of Stack
  61                 DCD     Reset_Handler             ; Reset Handler
  62                 DCD     NMI_Handler               ; NMI Handler
  63                 DCD     HardFault_Handler         ; Hard Fault Handler
  64                 DCD     MemManage_Handler         ; MPU Fault Handler
  65                 DCD     BusFault_Handler          ; Bus Fault Handler
  66                 DCD     UsageFault_Handler        ; Usage Fault Handler
  67                 DCD     0                         ; Reserved
  68                 DCD     0                         ; Reserved
  69                 DCD     0                         ; Reserved
  70                 DCD     0                         ; Reserved
  71                 DCD     SVC_Handler               ; SVCall Handler
  72                 DCD     DebugMon_Handler          ; Debug Monitor Handler
  73                 DCD     0                         ; Reserved
  74                 DCD     PendSV_Handler            ; PendSV Handler
  75                 DCD     SysTick_Handler           ; SysTick Handler
  76
  77                 ; External Interrupts
  78                 DCD     WDT_IRQHandler            ; 16+ 0 Windowed watchdog timer interrupt
  79                 DCD     BOD_IRQHandler            ; 16+ 1 BOD interrupt
  80                 DCD     FLASH_IRQHandler          ; 16+ 2 Flash controller interrupt
  81                 DCD     EE_IRQHandler             ; 16+ 3 EEPROM controller interrupt
  82                 DCD     DMA_IRQHandler            ; 16+ 4 DMA interrupt
  83                 DCD     GINT0_IRQHandler          ; 16+ 5 GPIO group0 interrupt
  84                 DCD     GINT1_IRQHandler          ; 16+ 6 GPIO group1 interrupt
  85                 DCD     PIN_INT0_IRQHandler       ; 16+ 7 Pin interrupt 0 or pattern match engine slice 0 interrupt
  86                 DCD     PIN_INT1_IRQHandler       ; 16+ 8 Pin interrupt 1 or pattern match engine slice 1 interrupt
  87                 DCD     PIN_INT2_IRQHandler       ; 16+ 9 Pin interrupt 2 or pattern match engine slice 2 interrupt
  88                 DCD     PIN_INT3_IRQHandler       ; 16+10 Pin interrupt 3 or pattern match engine slice 3 interrupt
  89                 DCD     PIN_INT4_IRQHandler       ; 16+11 Pin interrupt 4 or pattern match engine slice 4 interrupt
  90                 DCD     PIN_INT5_IRQHandler       ; 16+12 Pin interrupt 5 or pattern match engine slice 5 interrupt
  91                 DCD     PIN_INT6_IRQHandler       ; 16+13 Pin interrupt 6 or pattern match engine slice 6 interrupt
  92                 DCD     PIN_INT7_IRQHandler       ; 16+14 Pin interrupt 7 or pattern match engine slice 7 interrupt
  93                 DCD     RIT_IRQHandler            ; 16+15 RIT interrupt
  94                 DCD     SCT0_IRQHandler           ; 16+16 State configurable timer interrupt
  95                 DCD     SCT1_IRQHandler           ; 16+17 State configurable timer interrupt
  96                 DCD     SCT2_IRQHandler           ; 16+18 State configurable timer interrupt
  97                 DCD     SCT3_IRQHandler           ; 16+19 State configurable timer interrupt
  98                 DCD     MRT_IRQHandler            ; 16+20 Multi-rate timer interrupt
  99                 DCD     UART0_IRQHandler          ; 16+21 USART0 interrupt
 100                 DCD     UART1_IRQHandler          ; 16+22 USART1 interrupt
 101                 DCD     UART2_IRQHandler          ; 16+23 USART2 interrupt
 102                 DCD     I2C0_IRQHandler           ; 16+24 I2C0 interrupt
 103                 DCD     SPI0_IRQHandler           ; 16+25 SPI0 interrupt
 104                 DCD     SPI1_IRQHandler           ; 16+26 SPI1 interrupt
 105                 DCD     C_CAN0_IRQHandler         ; 16+27 C_CAN0 interrupt
 106                 DCD     USB_IRQ_IRQHandler        ; 16+28 USB interrupt
 107                 DCD     USB_FIQ_IRQHandler        ; 16+29 USB interrupt
 108                 DCD     USBWAKEUP_IRQHandler      ; 16+30 USB wake-up interrupt
 109                 DCD     ADC0_SEQA_IRQHandler      ; 16+31 ADC0 sequence A completion.
 110                 DCD     ADC0_SEQB_IRQHandler      ; 16+32 ADC0 sequence B completion.
 111                 DCD     ADC0_THCMP_IRQHandler     ; 16+33 ADC0 threshold compare
 112                 DCD     ADC0_OVR_IRQHandler       ; 16+34 ADC0 overrun
 113                 DCD     ADC1_SEQA_IRQHandler      ; 16+35 ADC1 sequence A completion.
 114                 DCD     ADC1_SEQB_IRQHandler      ; 16+36 ADC1 sequence B completion.
 115                 DCD     ADC1_THCMP_IRQHandler     ; 16+37 ADC1 threshold compare
 116                 DCD     ADC1_OVR_IRQHandler       ; 16+38 ADC1 overrun
 117                 DCD     DAC_IRQHandler            ; 16+39 DAC interrupt
 118                 DCD     CMP0_IRQHandler           ; 16+40 Analog comparator 0 interrupt (ACMP0)
 119                 DCD     CMP1_IRQHandler           ; 16+41 Analog comparator 1 interrupt (ACMP1)
 120                 DCD     CMP2_IRQHandler           ; 16+42 Analog comparator 2 interrupt (ACMP2)
 121                 DCD     CMP3_IRQHandler           ; 16+43 Analog comparator 3 interrupt (ACMP3)
 122                 DCD     QEI_IRQHandler            ; 16+44 QEI interrupt
 123                 DCD     RTC_ALARM_IRQHandler      ; 16+45 RTC alarm interrupt
 124                 DCD     RTC_WAKE_IRQHandler       ; 16+46 RTC wake-up interrut
 125
 126 ; <h> Code Read Protection
 127 ;   <o> Code Read Protection  <0xFFFFFFFF=>CRP Disabled
 128 ;                             <0x12345678=>CRP Level 1
 129 ;                             <0x87654321=>CRP Level 2
 130 ;                             <0x43218765=>CRP Level 3 (ARE YOU SURE?)
 131 ;                             <0x4E697370=>NO ISP (ARE YOU SURE?)
 132 ; </h>
 133                 IF      :LNOT::DEF:NO_CRP
 134                 AREA    |.ARM.__at_0x02FC|, CODE, READONLY
 135                 DCD     0xFFFFFFFF
 136                 ENDIF
 137
 138                 AREA    |.text|, CODE, READONLY
 139
 140
 141 ; Reset Handler
 142
 143 Reset_Handler   PROC
 144                 EXPORT  Reset_Handler             [WEAK]
 145                 IMPORT  SystemInit
 146                 IMPORT  __main
 147
 148 ;--- enable SRAM1 and SRAM2 memory
 149                 LDR     R0, =0x400740C4   ; SYSAHBCLKCTRL0 register addr
 150                 LDR     R2, [R0]          ; read SYSAHBCLKCTRL0
 151                 ORR     R2, R2, #0x18     ; enable SRAM1, SRAM2
 152                 STR     R2, [R0]          ; store SYSAHBCLKCTRL0
 153 ;---
 154                 LDR     R0, =SystemInit
 155                 BLX     R0
 156                 LDR     R0, =__main
 157                 BX      R0
 158                 ENDP
 159
 160
 161 ; Dummy Exception Handlers (infinite loops which can be modified)
 162
 163 NMI_Handler     PROC
 164                 EXPORT  NMI_Handler               [WEAK]
 165                 B       .
 166                 ENDP
 167 HardFault_Handler\
 168                 PROC
 169                 EXPORT  HardFault_Handler         [WEAK]
 170                 B       .
 171                 ENDP
 172 MemManage_Handler\
 173                 PROC
 174                 EXPORT  MemManage_Handler         [WEAK]
 175                 B       .
 176                 ENDP
 177 BusFault_Handler\
 178                 PROC
 179                 EXPORT  BusFault_Handler          [WEAK]
 180                 B       .
 181                 ENDP
 182 UsageFault_Handler\
 183                 PROC
 184                 EXPORT  UsageFault_Handler        [WEAK]
 185                 B       .
 186                 ENDP
 187 SVC_Handler     PROC
 188                 EXPORT  SVC_Handler               [WEAK]
 189                 B       .
 190                 ENDP
 191 DebugMon_Handler\
 192                 PROC
 193                 EXPORT  DebugMon_Handler          [WEAK]
 194                 B       .
 195                 ENDP
 196 PendSV_Handler  PROC
 197                 EXPORT  PendSV_Handler            [WEAK]
 198                 B       .
 199                 ENDP
 200 SysTick_Handler PROC
 201                 EXPORT  SysTick_Handler           [WEAK]
 202                 B       .
 203                 ENDP
 204
 205 Default_Handler PROC
 206
 207                 EXPORT  WDT_IRQHandler            [WEAK]
 208                 EXPORT  BOD_IRQHandler            [WEAK]
 209                 EXPORT  FLASH_IRQHandler          [WEAK]
 210                 EXPORT  EE_IRQHandler             [WEAK]
 211                 EXPORT  DMA_IRQHandler            [WEAK]
 212                 EXPORT  GINT0_IRQHandler          [WEAK]
 213                 EXPORT  GINT1_IRQHandler          [WEAK]
 214                 EXPORT  PIN_INT0_IRQHandler       [WEAK]
 215                 EXPORT  PIN_INT1_IRQHandler       [WEAK]
 216                 EXPORT  PIN_INT2_IRQHandler       [WEAK]
 217                 EXPORT  PIN_INT3_IRQHandler       [WEAK]
 218                 EXPORT  PIN_INT4_IRQHandler       [WEAK]
 219                 EXPORT  PIN_INT5_IRQHandler       [WEAK]
 220                 EXPORT  PIN_INT6_IRQHandler       [WEAK]
 221                 EXPORT  PIN_INT7_IRQHandler       [WEAK]
 222                 EXPORT  RIT_IRQHandler            [WEAK]
 223                 EXPORT  SCT0_IRQHandler           [WEAK]
 224                 EXPORT  SCT1_IRQHandler           [WEAK]
 225                 EXPORT  SCT2_IRQHandler           [WEAK]
 226                 EXPORT  SCT3_IRQHandler           [WEAK]
 227                 EXPORT  MRT_IRQHandler            [WEAK]
 228                 EXPORT  UART0_IRQHandler          [WEAK]
 229                 EXPORT  UART1_IRQHandler          [WEAK]
 230                 EXPORT  UART2_IRQHandler          [WEAK]
 231                 EXPORT  I2C0_IRQHandler           [WEAK]
 232                 EXPORT  SPI0_IRQHandler           [WEAK]
 233                 EXPORT  SPI1_IRQHandler           [WEAK]
 234                 EXPORT  C_CAN0_IRQHandler         [WEAK]
 235                 EXPORT  USB_IRQ_IRQHandler        [WEAK]
 236                 EXPORT  USB_FIQ_IRQHandler        [WEAK]
 237                 EXPORT  USBWAKEUP_IRQHandler      [WEAK]
 238                 EXPORT  ADC0_SEQA_IRQHandler      [WEAK]
 239                 EXPORT  ADC0_SEQB_IRQHandler      [WEAK]
 240                 EXPORT  ADC0_THCMP_IRQHandler     [WEAK]
 241                 EXPORT  ADC0_OVR_IRQHandler       [WEAK]
 242                 EXPORT  ADC1_SEQA_IRQHandler      [WEAK]
 243                 EXPORT  ADC1_SEQB_IRQHandler      [WEAK]
 244                 EXPORT  ADC1_THCMP_IRQHandler     [WEAK]
 245                 EXPORT  ADC1_OVR_IRQHandler       [WEAK]
 246                 EXPORT  DAC_IRQHandler            [WEAK]
 247                 EXPORT  CMP0_IRQHandler           [WEAK]
 248                 EXPORT  CMP1_IRQHandler           [WEAK]
 249                 EXPORT  CMP2_IRQHandler           [WEAK]
 250                 EXPORT  CMP3_IRQHandler           [WEAK]
 251                 EXPORT  QEI_IRQHandler            [WEAK]
 252                 EXPORT  RTC_ALARM_IRQHandler      [WEAK]
 253                 EXPORT  RTC_WAKE_IRQHandler       [WEAK]
 254
 255 WDT_IRQHandler
 256 BOD_IRQHandler
 257 FLASH_IRQHandler
 258 EE_IRQHandler
 259 DMA_IRQHandler
 260 GINT0_IRQHandler
 261 GINT1_IRQHandler
 262 PIN_INT0_IRQHandler
 263 PIN_INT1_IRQHandler
 264 PIN_INT2_IRQHandler
 265 PIN_INT3_IRQHandler
 266 PIN_INT4_IRQHandler
 267 PIN_INT5_IRQHandler
 268 PIN_INT6_IRQHandler
 269 PIN_INT7_IRQHandler
 270 RIT_IRQHandler
 271 SCT0_IRQHandler
 272 SCT1_IRQHandler
 273 SCT2_IRQHandler
 274 SCT3_IRQHandler
 275 MRT_IRQHandler
 276 UART0_IRQHandler
 277 UART1_IRQHandler
 278 UART2_IRQHandler
 279 I2C0_IRQHandler
 280 SPI0_IRQHandler
 281 SPI1_IRQHandler
 282 C_CAN0_IRQHandler
 283 USB_IRQ_IRQHandler
 284 USB_FIQ_IRQHandler
 285 USBWAKEUP_IRQHandler
 286 ADC0_SEQA_IRQHandler
 287 ADC0_SEQB_IRQHandler
 288 ADC0_THCMP_IRQHandler
 289 ADC0_OVR_IRQHandler
 290 ADC1_SEQA_IRQHandler
 291 ADC1_SEQB_IRQHandler
 292 ADC1_THCMP_IRQHandler
 293 ADC1_OVR_IRQHandler
 294 DAC_IRQHandler
 295 CMP0_IRQHandler
 296 CMP1_IRQHandler
 297 CMP2_IRQHandler
 298 CMP3_IRQHandler
 299 QEI_IRQHandler
 300 RTC_ALARM_IRQHandler
 301 RTC_WAKE_IRQHandler
 302
 303                 B       .
 304
 305                 ENDP
 306
 307
 308                 ALIGN
 309
 310
 311 ; User Initial Stack & Heap
 312
 313                 EXPORT  __initial_sp
 314                 EXPORT  __heap_base
 315                 EXPORT  __heap_limit
 316
 317                 END