tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC15XX/TOOLCHAIN_GCC_ARM/startup_LPC15xx.s

   1 /* File: startup_ARMCM3.s
   2  * Purpose: startup file for Cortex-M3/M4 devices. Should use with
   3  *   GNU Tools for ARM Embedded Processors
   4  * Version: V1.1
   5  * Date: 17 June 2011
   6  *
   7  * Copyright (C) 2011 ARM Limited. All rights reserved.
   8  * ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
   9  * processor based microcontrollers.  This file can be freely distributed
  10  * within development tools that are supporting such ARM based processors.
  11  *
  12  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  13  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  15  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  16  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  17  */
  18     .syntax unified
  19     .arch armv7-m
  20
  21 /* Memory Model
  22    The HEAP starts at the end of the DATA section and grows upward.
  23
  24    The STACK starts at the end of the RAM and grows downward.
  25
  26    The HEAP and stack STACK are only checked at compile time:
  27    (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE
  28
  29    This is just a check for the bare minimum for the Heap+Stack area before
  30    aborting compilation, it is not the run time limit:
  31    Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100
  32  */
  33     .section .stack
  34     .align 3
  35 #ifdef __STACK_SIZE
  36     .equ    Stack_Size, __STACK_SIZE
  37 #else
  38     .equ    Stack_Size, 0xc00
  39 #endif
  40     .globl    __StackTop
  41     .globl    __StackLimit
  42 __StackLimit:
  43     .space    Stack_Size
  44     .size __StackLimit, . - __StackLimit
  45 __StackTop:
  46     .size __StackTop, . - __StackTop
  47
  48     .section .heap
  49     .align 3
  50 #ifdef __HEAP_SIZE
  51     .equ    Heap_Size, __HEAP_SIZE
  52 #else
  53     .equ    Heap_Size, 0x800
  54 #endif
  55     .globl    __HeapBase
  56     .globl    __HeapLimit
  57 __HeapBase:
  58     .space    Heap_Size
  59     .size __HeapBase, . - __HeapBase
  60 __HeapLimit:
  61     .size __HeapLimit, . - __HeapLimit
  62
  63     .section .isr_vector
  64     .align 2
  65     .globl __isr_vector
  66 __isr_vector:
  67     .long    __StackTop            /* Top of Stack */
  68     .long    Reset_Handler         /* Reset Handler */
  69     .long    NMI_Handler           /* NMI Handler */
  70     .long    HardFault_Handler     /* Hard Fault Handler */
  71     .long    MemManage_Handler     /* MPU Fault Handler */
  72     .long    BusFault_Handler      /* Bus Fault Handler */
  73     .long    UsageFault_Handler    /* Usage Fault Handler */
  74     .long    0                     /* Reserved */
  75     .long    0                     /* Reserved */
  76     .long    0                     /* Reserved */
  77     .long    0                     /* Reserved */
  78     .long    SVC_Handler           /* SVCall Handler */
  79     .long    DebugMon_Handler      /* Debug Monitor Handler */
  80     .long    0                     /* Reserved */
  81     .long    PendSV_Handler        /* PendSV Handler */
  82     .long    SysTick_Handler       /* SysTick Handler */
  83
  84     /* External interrupts */
  85     .long   WDT_IRQHandler              /*  0: Windowed watchdog timer      */
  86     .long   BOD_IRQHandler              /*  1: Brown-Out Detect             */
  87     .long   FMC_IRQHandler              /*  2: Flash controller             */
  88     .long   EEPROM_IRQHandler           /*  3: EEPROM controller            */
  89     .long   DMA_IRQHandler              /*  4: DMA                          */
  90     .long   GINT0_IRQHandler            /*  5: GPIO group 0                 */
  91     .long   GINT1_IRQHandler            /*  6: GPIO group 1                 */
  92     .long   PIN_INT0_IRQHandler         /*  7: PIO INT0                     */
  93     .long   PIN_INT1_IRQHandler         /*  8: PIO INT1                     */
  94     .long   PIN_INT2_IRQHandler         /*  9: PIO INT2                     */
  95     .long   PIN_INT3_IRQHandler         /* 10: PIO INT3                     */
  96     .long   PIN_INT4_IRQHandler         /* 11: PIO INT4                     */
  97     .long   PIN_INT5_IRQHandler         /* 12: PIO INT5                     */
  98     .long   PIN_INT6_IRQHandler         /* 13: PIO INT6                     */
  99     .long   PIN_INT7_IRQHandler         /* 14: PIO INT7                     */
 100     .long   RIT_IRQHandler              /* 15: Repetitive Interrupt Timer   */
 101     .long   SCT0_IRQHandler             /* 16: State configurable timer     */
 102     .long   SCT1_IRQHandler             /* 17: State configurable timer     */
 103     .long   SCT2_IRQHandler             /* 18: State configurable timer     */
 104     .long   SCT3_IRQHandler             /* 19: State configurable timer     */
 105     .long   MRT_IRQHandler              /* 20: Multi-Rate Timer             */
 106     .long   UART0_IRQHandler            /* 21: UART0                        */
 107     .long   UART1_IRQHandler            /* 22: UART1                        */
 108     .long   UART2_IRQHandler            /* 23: UART2                        */
 109     .long   I2C0_IRQHandler             /* 24: I2C0 controller              */
 110     .long   SPI0_IRQHandler             /* 25: SPI0 controller              */
 111     .long   SPI1_IRQHandler             /* 26: SPI1 controller              */
 112     .long   CAN_IRQHandler              /* 27: C_CAN0                       */
 113     .long   USB_IRQHandler              /* 28: USB IRQ                      */
 114     .long   USB_FIQHandler              /* 29: USB FIQ                      */
 115     .long   USBWakeup_IRQHandler        /* 30: USB wake-up                  */
 116     .long   ADC0A_IRQHandler            /* 31: ADC0 sequence A completion   */
 117     .long   ADC0B_IRQHandler            /* 32: ADC0 sequence B completion   */
 118     .long   ADC0_THCMP_IRQHandler       /* 33: ADC0 threshold compare       */
 119     .long   ADC0_OVR_IRQHandler         /* 34: ADC0 overrun                 */
 120     .long   ADC1A_IRQHandler            /* 35: ADC1 sequence A completion   */
 121     .long   ADC1B_IRQHandler            /* 36: ADC1 sequence B completion   */
 122     .long   ADC1_THCMP_IRQHandler       /* 37: ADC1 threshold compare       */
 123     .long   ADC1_OVR_IRQHandler         /* 38: ADC1 overrun                 */
 124     .long   DAC_IRQHandler              /* 39: DAC                          */
 125     .long   ACMP0_IRQHandler            /* 40: Analog Comparator 0          */
 126     .long   ACMP1_IRQHandler            /* 41: Analog Comparator 1          */
 127     .long   ACMP2_IRQHandler            /* 42: Analog Comparator 2          */
 128     .long   ACMP3_IRQHandler            /* 43: Analog Comparator 3          */
 129     .long   QEI_IRQHandler              /* 44: Quadrature Encoder Interface */
 130     .long   RTC_ALARM_IRQHandler        /* 45: RTC alarm                    */
 131     .long   RTC_WAKE_IRQHandler         /* 46: RTC wake-up                  */
 132
 133     .size    __isr_vector, . - __isr_vector
 134
 135     .text
 136     .thumb
 137     .thumb_func
 138     .align 2
 139     .globl    Reset_Handler
 140     .type    Reset_Handler, %function
 141 Reset_Handler:
 142 /*     Loop to copy data from read only memory to RAM. The ranges
 143  *      of copy from/to are specified by following symbols evaluated in
 144  *      linker script.
 145  *      _etext: End of code section, i.e., begin of data sections to copy from.
 146  *      __data_start__/__data_end__: RAM address range that data should be
 147  *      copied to. Both must be aligned to 4 bytes boundary.  */
 148
 149     ldr    r1, =__etext
 150     ldr    r2, =__data_start__
 151     ldr    r3, =__data_end__
 152
 153 .Lflash_to_ram_loop:
 154     cmp     r2, r3
 155     ittt    lt
 156     ldrlt   r0, [r1], #4
 157     strlt   r0, [r2], #4
 158     blt    .Lflash_to_ram_loop
 159
 160     ldr    r0, =SystemInit
 161     blx    r0
 162     ldr    r0, =_start
 163     bx    r0
 164     .pool
 165     .size Reset_Handler, . - Reset_Handler
 166
 167     .text
 168 /*    Macro to define default handlers. Default handler
 169  *    will be weak symbol and just dead loops. They can be
 170  *    overwritten by other handlers */
 171     .macro    def_default_handler    handler_name
 172     .align 1
 173     .thumb_func
 174     .weak    \handler_name
 175     .type    \handler_name, %function
 176 \handler_name :
 177     b    .
 178     .size    \handler_name, . - \handler_name
 179     .endm
 180
 181     def_default_handler    NMI_Handler
 182     def_default_handler    HardFault_Handler
 183     def_default_handler    MemManage_Handler
 184     def_default_handler    BusFault_Handler
 185     def_default_handler    UsageFault_Handler
 186     def_default_handler    SVC_Handler
 187     def_default_handler    DebugMon_Handler
 188     def_default_handler    PendSV_Handler
 189     def_default_handler    SysTick_Handler
 190     def_default_handler    Default_Handler
 191
 192     .macro    def_irq_default_handler    handler_name
 193     .weak     \handler_name
 194     .set      \handler_name, Default_Handler
 195     .endm
 196
 197     def_irq_default_handler     WDT_IRQHandler
 198     def_irq_default_handler     BOD_IRQHandler
 199     def_irq_default_handler     FMC_IRQHandler
 200     def_irq_default_handler     EEPROM_IRQHandler
 201     def_irq_default_handler     DMA_IRQHandler
 202     def_irq_default_handler     GINT0_IRQHandler
 203     def_irq_default_handler     GINT1_IRQHandler
 204     def_irq_default_handler     PIN_INT0_IRQHandler
 205     def_irq_default_handler     PIN_INT1_IRQHandler
 206     def_irq_default_handler     PIN_INT2_IRQHandler
 207     def_irq_default_handler     PIN_INT3_IRQHandler
 208     def_irq_default_handler     PIN_INT4_IRQHandler
 209     def_irq_default_handler     PIN_INT5_IRQHandler
 210     def_irq_default_handler     PIN_INT6_IRQHandler
 211     def_irq_default_handler     PIN_INT7_IRQHandler
 212     def_irq_default_handler     RIT_IRQHandler
 213     def_irq_default_handler     SCT0_IRQHandler
 214     def_irq_default_handler     SCT1_IRQHandler
 215     def_irq_default_handler     SCT2_IRQHandler
 216     def_irq_default_handler     SCT3_IRQHandler
 217     def_irq_default_handler     MRT_IRQHandler
 218     def_irq_default_handler     UART0_IRQHandler
 219     def_irq_default_handler     UART1_IRQHandler
 220     def_irq_default_handler     UART2_IRQHandler
 221     def_irq_default_handler     I2C0_IRQHandler
 222     def_irq_default_handler     SPI0_IRQHandler
 223     def_irq_default_handler     SPI1_IRQHandler
 224     def_irq_default_handler     CAN_IRQHandler
 225     def_irq_default_handler     USB_IRQHandler
 226     def_irq_default_handler     USB_FIQHandler
 227     def_irq_default_handler     USBWakeup_IRQHandler
 228     def_irq_default_handler     ADC0A_IRQHandler
 229     def_irq_default_handler     ADC0B_IRQHandler
 230     def_irq_default_handler     ADC0_THCMP_IRQHandler
 231     def_irq_default_handler     ADC0_OVR_IRQHandler
 232     def_irq_default_handler     ADC1A_IRQHandler
 233     def_irq_default_handler     ADC1B_IRQHandler
 234     def_irq_default_handler     ADC1_THCMP_IRQHandler
 235     def_irq_default_handler     ADC1_OVR_IRQHandler
 236     def_irq_default_handler     DAC_IRQHandler
 237     def_irq_default_handler     ACMP0_IRQHandler
 238     def_irq_default_handler     ACMP1_IRQHandler
 239     def_irq_default_handler     ACMP2_IRQHandler
 240     def_irq_default_handler     ACMP3_IRQHandler
 241     def_irq_default_handler     QEI_IRQHandler
 242     def_irq_default_handler     RTC_ALARM_IRQHandler
 243     def_irq_default_handler     RTC_WAKE_IRQHandler
 244     def_irq_default_handler     DEF_IRQHandler
 245
 246     .end
 247