tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/LPC17xx.h

   1 /**************************************************************************//**
   2  * @file     LPC17xx.h
   3  * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
   4  *           NXP LPC17xx Device Series
   5  * @version: V1.09
   6  * @date:    17. March 2010
   7
   8  *
   9  * @note
  10  * Copyright (C) 2009 ARM Limited. All rights reserved.
  11  *
  12  * @par
  13  * ARM Limited (ARM) is supplying this software for use with Cortex-M
  14  * processor based microcontrollers.  This file can be freely distributed
  15  * within development tools that are supporting such ARM based processors.
  16  *
  17  * @par
  18  * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
  19  * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
  20  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
  21  * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
  22  * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
  23  *
  24  ******************************************************************************/
  25
  26
  27 #ifndef __LPC17xx_H__
  28 #define __LPC17xx_H__
  29
  30 /*
  31  * ==========================================================================
  32  * ---------- Interrupt Number Definition -----------------------------------
  33  * ==========================================================================
  34  */
  35
  36 typedef enum IRQn
  37 {
  38 /******  Cortex-M3 Processor Exceptions Numbers ***************************************************/
  39   NonMaskableInt_IRQn           = -14,      /*!< 2 Non Maskable Interrupt                         */
  40   MemoryManagement_IRQn         = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt          */
  41   BusFault_IRQn                 = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                  */
  42   UsageFault_IRQn               = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                */
  43   SVCall_IRQn                   = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                   */
  44   DebugMonitor_IRQn             = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt             */
  45   PendSV_IRQn                   = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                   */
  46   SysTick_IRQn                  = -1,       /*!< 15 Cortex-M3 System Tick Interrupt               */
  47
  48 /******  LPC17xx Specific Interrupt Numbers *******************************************************/
  49   WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
  50   TIMER0_IRQn                   = 1,        /*!< Timer0 Interrupt                                 */
  51   TIMER1_IRQn                   = 2,        /*!< Timer1 Interrupt                                 */
  52   TIMER2_IRQn                   = 3,        /*!< Timer2 Interrupt                                 */
  53   TIMER3_IRQn                   = 4,        /*!< Timer3 Interrupt                                 */
  54   UART0_IRQn                    = 5,        /*!< UART0 Interrupt                                  */
  55   UART1_IRQn                    = 6,        /*!< UART1 Interrupt                                  */
  56   UART2_IRQn                    = 7,        /*!< UART2 Interrupt                                  */
  57   UART3_IRQn                    = 8,        /*!< UART3 Interrupt                                  */
  58   PWM1_IRQn                     = 9,        /*!< PWM1 Interrupt                                   */
  59   I2C0_IRQn                     = 10,       /*!< I2C0 Interrupt                                   */
  60   I2C1_IRQn                     = 11,       /*!< I2C1 Interrupt                                   */
  61   I2C2_IRQn                     = 12,       /*!< I2C2 Interrupt                                   */
  62   SPI_IRQn                      = 13,       /*!< SPI Interrupt                                    */
  63   SSP0_IRQn                     = 14,       /*!< SSP0 Interrupt                                   */
  64   SSP1_IRQn                     = 15,       /*!< SSP1 Interrupt                                   */
  65   PLL0_IRQn                     = 16,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
  66   RTC_IRQn                      = 17,       /*!< Real Time Clock Interrupt                        */
  67   EINT0_IRQn                    = 18,       /*!< External Interrupt 0 Interrupt                   */
  68   EINT1_IRQn                    = 19,       /*!< External Interrupt 1 Interrupt                   */
  69   EINT2_IRQn                    = 20,       /*!< External Interrupt 2 Interrupt                   */
  70   EINT3_IRQn                    = 21,       /*!< External Interrupt 3 Interrupt                   */
  71   ADC_IRQn                      = 22,       /*!< A/D Converter Interrupt                          */
  72   BOD_IRQn                      = 23,       /*!< Brown-Out Detect Interrupt                       */
  73   USB_IRQn                      = 24,       /*!< USB Interrupt                                    */
  74   CAN_IRQn                      = 25,       /*!< CAN Interrupt                                    */
  75   DMA_IRQn                      = 26,       /*!< General Purpose DMA Interrupt                    */
  76   I2S_IRQn                      = 27,       /*!< I2S Interrupt                                    */
  77   ENET_IRQn                     = 28,       /*!< Ethernet Interrupt                               */
  78   RIT_IRQn                      = 29,       /*!< Repetitive Interrupt Timer Interrupt             */
  79   MCPWM_IRQn                    = 30,       /*!< Motor Control PWM Interrupt                      */
  80   QEI_IRQn                      = 31,       /*!< Quadrature Encoder Interface Interrupt           */
  81   PLL1_IRQn                     = 32,       /*!< PLL1 Lock (USB PLL) Interrupt                    */
  82   USBActivity_IRQn              = 33,       /* USB Activity interrupt                             */
  83   CANActivity_IRQn              = 34,       /* CAN Activity interrupt                             */
  84 } IRQn_Type;
  85
  86
  87 /*
  88  * ==========================================================================
  89  * ----------- Processor and Core Peripheral Section ------------------------
  90  * ==========================================================================
  91  */
  92
  93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
  94 #define __MPU_PRESENT             1         /*!< MPU present or not                               */
  95 #define __NVIC_PRIO_BITS          5         /*!< Number of Bits used for Priority Levels          */
  96 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
  97
  98
  99 #include "core_cm3.h"                       /* Cortex-M3 processor and core peripherals           */
 100 #include "system_LPC17xx.h"                 /* System Header                                      */
 101
 102
 103 /******************************************************************************/
 104 /*                Device Specific Peripheral registers structures             */
 105 /******************************************************************************/
 106
 107 #if defined ( __CC_ARM   )
 108 #pragma anon_unions
 109 #endif
 110
 111 /*------------- System Control (SC) ------------------------------------------*/
 112 typedef struct
 113 {
 114   __IO uint32_t FLASHCFG;               /* Flash Accelerator Module           */
 115        uint32_t RESERVED0[31];
 116   __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
 117   __IO uint32_t PLL0CFG;
 118   __I  uint32_t PLL0STAT;
 119   __O  uint32_t PLL0FEED;
 120        uint32_t RESERVED1[4];
 121   __IO uint32_t PLL1CON;
 122   __IO uint32_t PLL1CFG;
 123   __I  uint32_t PLL1STAT;
 124   __O  uint32_t PLL1FEED;
 125        uint32_t RESERVED2[4];
 126   __IO uint32_t PCON;
 127   __IO uint32_t PCONP;
 128        uint32_t RESERVED3[15];
 129   __IO uint32_t CCLKCFG;
 130   __IO uint32_t USBCLKCFG;
 131   __IO uint32_t CLKSRCSEL;
 132   __IO uint32_t CANSLEEPCLR;
 133   __IO uint32_t CANWAKEFLAGS;
 134        uint32_t RESERVED4[10];
 135   __IO uint32_t EXTINT;                 /* External Interrupts                */
 136        uint32_t RESERVED5;
 137   __IO uint32_t EXTMODE;
 138   __IO uint32_t EXTPOLAR;
 139        uint32_t RESERVED6[12];
 140   __IO uint32_t RSID;                   /* Reset                              */
 141        uint32_t RESERVED7[7];
 142   __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
 143   __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
 144   __IO uint32_t PCLKSEL0;
 145   __IO uint32_t PCLKSEL1;
 146        uint32_t RESERVED8[4];
 147   __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
 148   __IO uint32_t DMAREQSEL;
 149   __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
 150  } LPC_SC_TypeDef;
 151
 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
 153 typedef struct
 154 {
 155   __IO uint32_t PINSEL0;
 156   __IO uint32_t PINSEL1;
 157   __IO uint32_t PINSEL2;
 158   __IO uint32_t PINSEL3;
 159   __IO uint32_t PINSEL4;
 160   __IO uint32_t PINSEL5;
 161   __IO uint32_t PINSEL6;
 162   __IO uint32_t PINSEL7;
 163   __IO uint32_t PINSEL8;
 164   __IO uint32_t PINSEL9;
 165   __IO uint32_t PINSEL10;
 166        uint32_t RESERVED0[5];
 167   __IO uint32_t PINMODE0;
 168   __IO uint32_t PINMODE1;
 169   __IO uint32_t PINMODE2;
 170   __IO uint32_t PINMODE3;
 171   __IO uint32_t PINMODE4;
 172   __IO uint32_t PINMODE5;
 173   __IO uint32_t PINMODE6;
 174   __IO uint32_t PINMODE7;
 175   __IO uint32_t PINMODE8;
 176   __IO uint32_t PINMODE9;
 177   __IO uint32_t PINMODE_OD0;
 178   __IO uint32_t PINMODE_OD1;
 179   __IO uint32_t PINMODE_OD2;
 180   __IO uint32_t PINMODE_OD3;
 181   __IO uint32_t PINMODE_OD4;
 182   __IO uint32_t I2CPADCFG;
 183 } LPC_PINCON_TypeDef;
 184
 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
 186 typedef struct
 187 {
 188   union {
 189     __IO uint32_t FIODIR;
 190     struct {
 191       __IO uint16_t FIODIRL;
 192       __IO uint16_t FIODIRH;
 193     };
 194     struct {
 195       __IO uint8_t  FIODIR0;
 196       __IO uint8_t  FIODIR1;
 197       __IO uint8_t  FIODIR2;
 198       __IO uint8_t  FIODIR3;
 199     };
 200   };
 201   uint32_t RESERVED0[3];
 202   union {
 203     __IO uint32_t FIOMASK;
 204     struct {
 205       __IO uint16_t FIOMASKL;
 206       __IO uint16_t FIOMASKH;
 207     };
 208     struct {
 209       __IO uint8_t  FIOMASK0;
 210       __IO uint8_t  FIOMASK1;
 211       __IO uint8_t  FIOMASK2;
 212       __IO uint8_t  FIOMASK3;
 213     };
 214   };
 215   union {
 216     __IO uint32_t FIOPIN;
 217     struct {
 218       __IO uint16_t FIOPINL;
 219       __IO uint16_t FIOPINH;
 220     };
 221     struct {
 222       __IO uint8_t  FIOPIN0;
 223       __IO uint8_t  FIOPIN1;
 224       __IO uint8_t  FIOPIN2;
 225       __IO uint8_t  FIOPIN3;
 226     };
 227   };
 228   union {
 229     __IO uint32_t FIOSET;
 230     struct {
 231       __IO uint16_t FIOSETL;
 232       __IO uint16_t FIOSETH;
 233     };
 234     struct {
 235       __IO uint8_t  FIOSET0;
 236       __IO uint8_t  FIOSET1;
 237       __IO uint8_t  FIOSET2;
 238       __IO uint8_t  FIOSET3;
 239     };
 240   };
 241   union {
 242     __O  uint32_t FIOCLR;
 243     struct {
 244       __O  uint16_t FIOCLRL;
 245       __O  uint16_t FIOCLRH;
 246     };
 247     struct {
 248       __O  uint8_t  FIOCLR0;
 249       __O  uint8_t  FIOCLR1;
 250       __O  uint8_t  FIOCLR2;
 251       __O  uint8_t  FIOCLR3;
 252     };
 253   };
 254 } LPC_GPIO_TypeDef;
 255
 256 typedef struct
 257 {
 258   __I  uint32_t IntStatus;
 259   __I  uint32_t IO0IntStatR;
 260   __I  uint32_t IO0IntStatF;
 261   __O  uint32_t IO0IntClr;
 262   __IO uint32_t IO0IntEnR;
 263   __IO uint32_t IO0IntEnF;
 264        uint32_t RESERVED0[3];
 265   __I  uint32_t IO2IntStatR;
 266   __I  uint32_t IO2IntStatF;
 267   __O  uint32_t IO2IntClr;
 268   __IO uint32_t IO2IntEnR;
 269   __IO uint32_t IO2IntEnF;
 270 } LPC_GPIOINT_TypeDef;
 271
 272 /*------------- Timer (TIM) --------------------------------------------------*/
 273 typedef struct
 274 {
 275   __IO uint32_t IR;
 276   __IO uint32_t TCR;
 277   __IO uint32_t TC;
 278   __IO uint32_t PR;
 279   __IO uint32_t PC;
 280   __IO uint32_t MCR;
 281   __IO uint32_t MR0;
 282   __IO uint32_t MR1;
 283   __IO uint32_t MR2;
 284   __IO uint32_t MR3;
 285   __IO uint32_t CCR;
 286   __I  uint32_t CR0;
 287   __I  uint32_t CR1;
 288        uint32_t RESERVED0[2];
 289   __IO uint32_t EMR;
 290        uint32_t RESERVED1[12];
 291   __IO uint32_t CTCR;
 292 } LPC_TIM_TypeDef;
 293
 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
 295 typedef struct
 296 {
 297   __IO uint32_t IR;
 298   __IO uint32_t TCR;
 299   __IO uint32_t TC;
 300   __IO uint32_t PR;
 301   __IO uint32_t PC;
 302   __IO uint32_t MCR;
 303   __IO uint32_t MR0;
 304   __IO uint32_t MR1;
 305   __IO uint32_t MR2;
 306   __IO uint32_t MR3;
 307   __IO uint32_t CCR;
 308   __I  uint32_t CR0;
 309   __I  uint32_t CR1;
 310   __I  uint32_t CR2;
 311   __I  uint32_t CR3;
 312        uint32_t RESERVED0;
 313   __IO uint32_t MR4;
 314   __IO uint32_t MR5;
 315   __IO uint32_t MR6;
 316   __IO uint32_t PCR;
 317   __IO uint32_t LER;
 318        uint32_t RESERVED1[7];
 319   __IO uint32_t CTCR;
 320 } LPC_PWM_TypeDef;
 321
 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
 323 typedef struct
 324 {
 325   union {
 326   __I  uint8_t  RBR;
 327   __O  uint8_t  THR;
 328   __IO uint8_t  DLL;
 329        uint32_t RESERVED0;
 330   };
 331   union {
 332   __IO uint8_t  DLM;
 333   __IO uint32_t IER;
 334   };
 335   union {
 336   __I  uint32_t IIR;
 337   __O  uint8_t  FCR;
 338   };
 339   __IO uint8_t  LCR;
 340        uint8_t  RESERVED1[7];
 341   __I  uint8_t  LSR;
 342        uint8_t  RESERVED2[7];
 343   __IO uint8_t  SCR;
 344        uint8_t  RESERVED3[3];
 345   __IO uint32_t ACR;
 346   __IO uint8_t  ICR;
 347        uint8_t  RESERVED4[3];
 348   __IO uint8_t  FDR;
 349        uint8_t  RESERVED5[7];
 350   __IO uint8_t  TER;
 351        uint8_t  RESERVED6[39];
 352   __IO uint32_t FIFOLVL;
 353 } LPC_UART_TypeDef;
 354
 355 typedef struct
 356 {
 357   union {
 358   __I  uint8_t  RBR;
 359   __O  uint8_t  THR;
 360   __IO uint8_t  DLL;
 361        uint32_t RESERVED0;
 362   };
 363   union {
 364   __IO uint8_t  DLM;
 365   __IO uint32_t IER;
 366   };
 367   union {
 368   __I  uint32_t IIR;
 369   __O  uint8_t  FCR;
 370   };
 371   __IO uint8_t  LCR;
 372        uint8_t  RESERVED1[7];
 373   __I  uint8_t  LSR;
 374        uint8_t  RESERVED2[7];
 375   __IO uint8_t  SCR;
 376        uint8_t  RESERVED3[3];
 377   __IO uint32_t ACR;
 378   __IO uint8_t  ICR;
 379        uint8_t  RESERVED4[3];
 380   __IO uint8_t  FDR;
 381        uint8_t  RESERVED5[7];
 382   __IO uint8_t  TER;
 383        uint8_t  RESERVED6[39];
 384   __IO uint32_t FIFOLVL;
 385 } LPC_UART0_TypeDef;
 386
 387 typedef struct
 388 {
 389   union {
 390   __I  uint8_t  RBR;
 391   __O  uint8_t  THR;
 392   __IO uint8_t  DLL;
 393        uint32_t RESERVED0;
 394   };
 395   union {
 396   __IO uint8_t  DLM;
 397   __IO uint32_t IER;
 398   };
 399   union {
 400   __I  uint32_t IIR;
 401   __O  uint8_t  FCR;
 402   };
 403   __IO uint8_t  LCR;
 404        uint8_t  RESERVED1[3];
 405   __IO uint8_t  MCR;
 406        uint8_t  RESERVED2[3];
 407   __I  uint8_t  LSR;
 408        uint8_t  RESERVED3[3];
 409   __I  uint8_t  MSR;
 410        uint8_t  RESERVED4[3];
 411   __IO uint8_t  SCR;
 412        uint8_t  RESERVED5[3];
 413   __IO uint32_t ACR;
 414        uint32_t RESERVED6;
 415   __IO uint32_t FDR;
 416        uint32_t RESERVED7;
 417   __IO uint8_t  TER;
 418        uint8_t  RESERVED8[27];
 419   __IO uint8_t  RS485CTRL;
 420        uint8_t  RESERVED9[3];
 421   __IO uint8_t  ADRMATCH;
 422        uint8_t  RESERVED10[3];
 423   __IO uint8_t  RS485DLY;
 424        uint8_t  RESERVED11[3];
 425   __IO uint32_t FIFOLVL;
 426 } LPC_UART1_TypeDef;
 427
 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
 429 typedef struct
 430 {
 431   __IO uint32_t SPCR;
 432   __I  uint32_t SPSR;
 433   __IO uint32_t SPDR;
 434   __IO uint32_t SPCCR;
 435        uint32_t RESERVED0[3];
 436   __IO uint32_t SPINT;
 437 } LPC_SPI_TypeDef;
 438
 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
 440 typedef struct
 441 {
 442   __IO uint32_t CR0;
 443   __IO uint32_t CR1;
 444   __IO uint32_t DR;
 445   __I  uint32_t SR;
 446   __IO uint32_t CPSR;
 447   __IO uint32_t IMSC;
 448   __IO uint32_t RIS;
 449   __IO uint32_t MIS;
 450   __IO uint32_t ICR;
 451   __IO uint32_t DMACR;
 452 } LPC_SSP_TypeDef;
 453
 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
 455 typedef struct
 456 {
 457   __IO uint32_t I2CONSET;
 458   __I  uint32_t I2STAT;
 459   __IO uint32_t I2DAT;
 460   __IO uint32_t I2ADR0;
 461   __IO uint32_t I2SCLH;
 462   __IO uint32_t I2SCLL;
 463   __O  uint32_t I2CONCLR;
 464   __IO uint32_t MMCTRL;
 465   __IO uint32_t I2ADR1;
 466   __IO uint32_t I2ADR2;
 467   __IO uint32_t I2ADR3;
 468   __I  uint32_t I2DATA_BUFFER;
 469   __IO uint32_t I2MASK0;
 470   __IO uint32_t I2MASK1;
 471   __IO uint32_t I2MASK2;
 472   __IO uint32_t I2MASK3;
 473 } LPC_I2C_TypeDef;
 474
 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
 476 typedef struct
 477 {
 478   __IO uint32_t I2SDAO;
 479   __IO uint32_t I2SDAI;
 480   __O  uint32_t I2STXFIFO;
 481   __I  uint32_t I2SRXFIFO;
 482   __I  uint32_t I2SSTATE;
 483   __IO uint32_t I2SDMA1;
 484   __IO uint32_t I2SDMA2;
 485   __IO uint32_t I2SIRQ;
 486   __IO uint32_t I2STXRATE;
 487   __IO uint32_t I2SRXRATE;
 488   __IO uint32_t I2STXBITRATE;
 489   __IO uint32_t I2SRXBITRATE;
 490   __IO uint32_t I2STXMODE;
 491   __IO uint32_t I2SRXMODE;
 492 } LPC_I2S_TypeDef;
 493
 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
 495 typedef struct
 496 {
 497   __IO uint32_t RICOMPVAL;
 498   __IO uint32_t RIMASK;
 499   __IO uint8_t  RICTRL;
 500        uint8_t  RESERVED0[3];
 501   __IO uint32_t RICOUNTER;
 502 } LPC_RIT_TypeDef;
 503
 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
 505 typedef struct
 506 {
 507   __IO uint8_t  ILR;
 508        uint8_t  RESERVED0[7];
 509   __IO uint8_t  CCR;
 510        uint8_t  RESERVED1[3];
 511   __IO uint8_t  CIIR;
 512        uint8_t  RESERVED2[3];
 513   __IO uint8_t  AMR;
 514        uint8_t  RESERVED3[3];
 515   __I  uint32_t CTIME0;
 516   __I  uint32_t CTIME1;
 517   __I  uint32_t CTIME2;
 518   __IO uint8_t  SEC;
 519        uint8_t  RESERVED4[3];
 520   __IO uint8_t  MIN;
 521        uint8_t  RESERVED5[3];
 522   __IO uint8_t  HOUR;
 523        uint8_t  RESERVED6[3];
 524   __IO uint8_t  DOM;
 525        uint8_t  RESERVED7[3];
 526   __IO uint8_t  DOW;
 527        uint8_t  RESERVED8[3];
 528   __IO uint16_t DOY;
 529        uint16_t RESERVED9;
 530   __IO uint8_t  MONTH;
 531        uint8_t  RESERVED10[3];
 532   __IO uint16_t YEAR;
 533        uint16_t RESERVED11;
 534   __IO uint32_t CALIBRATION;
 535   __IO uint32_t GPREG0;
 536   __IO uint32_t GPREG1;
 537   __IO uint32_t GPREG2;
 538   __IO uint32_t GPREG3;
 539   __IO uint32_t GPREG4;
 540   __IO uint8_t  RTC_AUXEN;
 541        uint8_t  RESERVED12[3];
 542   __IO uint8_t  RTC_AUX;
 543        uint8_t  RESERVED13[3];
 544   __IO uint8_t  ALSEC;
 545        uint8_t  RESERVED14[3];
 546   __IO uint8_t  ALMIN;
 547        uint8_t  RESERVED15[3];
 548   __IO uint8_t  ALHOUR;
 549        uint8_t  RESERVED16[3];
 550   __IO uint8_t  ALDOM;
 551        uint8_t  RESERVED17[3];
 552   __IO uint8_t  ALDOW;
 553        uint8_t  RESERVED18[3];
 554   __IO uint16_t ALDOY;
 555        uint16_t RESERVED19;
 556   __IO uint8_t  ALMON;
 557        uint8_t  RESERVED20[3];
 558   __IO uint16_t ALYEAR;
 559        uint16_t RESERVED21;
 560 } LPC_RTC_TypeDef;
 561
 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
 563 typedef struct
 564 {
 565   __IO uint8_t  WDMOD;
 566        uint8_t  RESERVED0[3];
 567   __IO uint32_t WDTC;
 568   __O  uint8_t  WDFEED;
 569        uint8_t  RESERVED1[3];
 570   __I  uint32_t WDTV;
 571   __IO uint32_t WDCLKSEL;
 572 } LPC_WDT_TypeDef;
 573
 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
 575 typedef struct
 576 {
 577   __IO uint32_t ADCR;
 578   __IO uint32_t ADGDR;
 579        uint32_t RESERVED0;
 580   __IO uint32_t ADINTEN;
 581   __I  uint32_t ADDR0;
 582   __I  uint32_t ADDR1;
 583   __I  uint32_t ADDR2;
 584   __I  uint32_t ADDR3;
 585   __I  uint32_t ADDR4;
 586   __I  uint32_t ADDR5;
 587   __I  uint32_t ADDR6;
 588   __I  uint32_t ADDR7;
 589   __I  uint32_t ADSTAT;
 590   __IO uint32_t ADTRM;
 591 } LPC_ADC_TypeDef;
 592
 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
 594 typedef struct
 595 {
 596   __IO uint32_t DACR;
 597   __IO uint32_t DACCTRL;
 598   __IO uint16_t DACCNTVAL;
 599 } LPC_DAC_TypeDef;
 600
 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
 602 typedef struct
 603 {
 604   __I  uint32_t MCCON;
 605   __O  uint32_t MCCON_SET;
 606   __O  uint32_t MCCON_CLR;
 607   __I  uint32_t MCCAPCON;
 608   __O  uint32_t MCCAPCON_SET;
 609   __O  uint32_t MCCAPCON_CLR;
 610   __IO uint32_t MCTIM0;
 611   __IO uint32_t MCTIM1;
 612   __IO uint32_t MCTIM2;
 613   __IO uint32_t MCPER0;
 614   __IO uint32_t MCPER1;
 615   __IO uint32_t MCPER2;
 616   __IO uint32_t MCPW0;
 617   __IO uint32_t MCPW1;
 618   __IO uint32_t MCPW2;
 619   __IO uint32_t MCDEADTIME;
 620   __IO uint32_t MCCCP;
 621   __IO uint32_t MCCR0;
 622   __IO uint32_t MCCR1;
 623   __IO uint32_t MCCR2;
 624   __I  uint32_t MCINTEN;
 625   __O  uint32_t MCINTEN_SET;
 626   __O  uint32_t MCINTEN_CLR;
 627   __I  uint32_t MCCNTCON;
 628   __O  uint32_t MCCNTCON_SET;
 629   __O  uint32_t MCCNTCON_CLR;
 630   __I  uint32_t MCINTFLAG;
 631   __O  uint32_t MCINTFLAG_SET;
 632   __O  uint32_t MCINTFLAG_CLR;
 633   __O  uint32_t MCCAP_CLR;
 634 } LPC_MCPWM_TypeDef;
 635
 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
 637 typedef struct
 638 {
 639   __O  uint32_t QEICON;
 640   __I  uint32_t QEISTAT;
 641   __IO uint32_t QEICONF;
 642   __I  uint32_t QEIPOS;
 643   __IO uint32_t QEIMAXPOS;
 644   __IO uint32_t CMPOS0;
 645   __IO uint32_t CMPOS1;
 646   __IO uint32_t CMPOS2;
 647   __I  uint32_t INXCNT;
 648   __IO uint32_t INXCMP;
 649   __IO uint32_t QEILOAD;
 650   __I  uint32_t QEITIME;
 651   __I  uint32_t QEIVEL;
 652   __I  uint32_t QEICAP;
 653   __IO uint32_t VELCOMP;
 654   __IO uint32_t FILTER;
 655        uint32_t RESERVED0[998];
 656   __O  uint32_t QEIIEC;
 657   __O  uint32_t QEIIES;
 658   __I  uint32_t QEIINTSTAT;
 659   __I  uint32_t QEIIE;
 660   __O  uint32_t QEICLR;
 661   __O  uint32_t QEISET;
 662 } LPC_QEI_TypeDef;
 663
 664 /*------------- Controller Area Network (CAN) --------------------------------*/
 665 typedef struct
 666 {
 667   __IO uint32_t mask[512];              /* ID Masks                           */
 668 } LPC_CANAF_RAM_TypeDef;
 669
 670 typedef struct                          /* Acceptance Filter Registers        */
 671 {
 672   __IO uint32_t AFMR;
 673   __IO uint32_t SFF_sa;
 674   __IO uint32_t SFF_GRP_sa;
 675   __IO uint32_t EFF_sa;
 676   __IO uint32_t EFF_GRP_sa;
 677   __IO uint32_t ENDofTable;
 678   __I  uint32_t LUTerrAd;
 679   __I  uint32_t LUTerr;
 680   __IO uint32_t FCANIE;
 681   __IO uint32_t FCANIC0;
 682   __IO uint32_t FCANIC1;
 683 } LPC_CANAF_TypeDef;
 684
 685 typedef struct                          /* Central Registers                  */
 686 {
 687   __I  uint32_t CANTxSR;
 688   __I  uint32_t CANRxSR;
 689   __I  uint32_t CANMSR;
 690 } LPC_CANCR_TypeDef;
 691
 692 typedef struct                          /* Controller Registers               */
 693 {
 694   __IO uint32_t MOD;
 695   __O  uint32_t CMR;
 696   __IO uint32_t GSR;
 697   __I  uint32_t ICR;
 698   __IO uint32_t IER;
 699   __IO uint32_t BTR;
 700   __IO uint32_t EWL;
 701   __I  uint32_t SR;
 702   __IO uint32_t RFS;
 703   __IO uint32_t RID;
 704   __IO uint32_t RDA;
 705   __IO uint32_t RDB;
 706   __IO uint32_t TFI1;
 707   __IO uint32_t TID1;
 708   __IO uint32_t TDA1;
 709   __IO uint32_t TDB1;
 710   __IO uint32_t TFI2;
 711   __IO uint32_t TID2;
 712   __IO uint32_t TDA2;
 713   __IO uint32_t TDB2;
 714   __IO uint32_t TFI3;
 715   __IO uint32_t TID3;
 716   __IO uint32_t TDA3;
 717   __IO uint32_t TDB3;
 718 } LPC_CAN_TypeDef;
 719
 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
 721 typedef struct                          /* Common Registers                   */
 722 {
 723   __I  uint32_t DMACIntStat;
 724   __I  uint32_t DMACIntTCStat;
 725   __O  uint32_t DMACIntTCClear;
 726   __I  uint32_t DMACIntErrStat;
 727   __O  uint32_t DMACIntErrClr;
 728   __I  uint32_t DMACRawIntTCStat;
 729   __I  uint32_t DMACRawIntErrStat;
 730   __I  uint32_t DMACEnbldChns;
 731   __IO uint32_t DMACSoftBReq;
 732   __IO uint32_t DMACSoftSReq;
 733   __IO uint32_t DMACSoftLBReq;
 734   __IO uint32_t DMACSoftLSReq;
 735   __IO uint32_t DMACConfig;
 736   __IO uint32_t DMACSync;
 737 } LPC_GPDMA_TypeDef;
 738
 739 typedef struct                          /* Channel Registers                  */
 740 {
 741   __IO uint32_t DMACCSrcAddr;
 742   __IO uint32_t DMACCDestAddr;
 743   __IO uint32_t DMACCLLI;
 744   __IO uint32_t DMACCControl;
 745   __IO uint32_t DMACCConfig;
 746 } LPC_GPDMACH_TypeDef;
 747
 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
 749 typedef struct
 750 {
 751   __I  uint32_t HcRevision;             /* USB Host Registers                 */
 752   __IO uint32_t HcControl;
 753   __IO uint32_t HcCommandStatus;
 754   __IO uint32_t HcInterruptStatus;
 755   __IO uint32_t HcInterruptEnable;
 756   __IO uint32_t HcInterruptDisable;
 757   __IO uint32_t HcHCCA;
 758   __I  uint32_t HcPeriodCurrentED;
 759   __IO uint32_t HcControlHeadED;
 760   __IO uint32_t HcControlCurrentED;
 761   __IO uint32_t HcBulkHeadED;
 762   __IO uint32_t HcBulkCurrentED;
 763   __I  uint32_t HcDoneHead;
 764   __IO uint32_t HcFmInterval;
 765   __I  uint32_t HcFmRemaining;
 766   __I  uint32_t HcFmNumber;
 767   __IO uint32_t HcPeriodicStart;
 768   __IO uint32_t HcLSTreshold;
 769   __IO uint32_t HcRhDescriptorA;
 770   __IO uint32_t HcRhDescriptorB;
 771   __IO uint32_t HcRhStatus;
 772   __IO uint32_t HcRhPortStatus1;
 773   __IO uint32_t HcRhPortStatus2;
 774        uint32_t RESERVED0[40];
 775   __I  uint32_t Module_ID;
 776
 777   __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
 778   __IO uint32_t OTGIntEn;
 779   __O  uint32_t OTGIntSet;
 780   __O  uint32_t OTGIntClr;
 781   __IO uint32_t OTGStCtrl;
 782   __IO uint32_t OTGTmr;
 783        uint32_t RESERVED1[58];
 784
 785   __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
 786   __IO uint32_t USBDevIntEn;
 787   __O  uint32_t USBDevIntClr;
 788   __O  uint32_t USBDevIntSet;
 789
 790   __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
 791   __I  uint32_t USBCmdData;
 792
 793   __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
 794   __O  uint32_t USBTxData;
 795   __I  uint32_t USBRxPLen;
 796   __O  uint32_t USBTxPLen;
 797   __IO uint32_t USBCtrl;
 798   __O  uint32_t USBDevIntPri;
 799
 800   __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
 801   __IO uint32_t USBEpIntEn;
 802   __O  uint32_t USBEpIntClr;
 803   __O  uint32_t USBEpIntSet;
 804   __O  uint32_t USBEpIntPri;
 805
 806   __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
 807   __O  uint32_t USBEpInd;
 808   __IO uint32_t USBMaxPSize;
 809
 810   __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
 811   __O  uint32_t USBDMARClr;
 812   __O  uint32_t USBDMARSet;
 813        uint32_t RESERVED2[9];
 814   __IO uint32_t USBUDCAH;
 815   __I  uint32_t USBEpDMASt;
 816   __O  uint32_t USBEpDMAEn;
 817   __O  uint32_t USBEpDMADis;
 818   __I  uint32_t USBDMAIntSt;
 819   __IO uint32_t USBDMAIntEn;
 820        uint32_t RESERVED3[2];
 821   __I  uint32_t USBEoTIntSt;
 822   __O  uint32_t USBEoTIntClr;
 823   __O  uint32_t USBEoTIntSet;
 824   __I  uint32_t USBNDDRIntSt;
 825   __O  uint32_t USBNDDRIntClr;
 826   __O  uint32_t USBNDDRIntSet;
 827   __I  uint32_t USBSysErrIntSt;
 828   __O  uint32_t USBSysErrIntClr;
 829   __O  uint32_t USBSysErrIntSet;
 830        uint32_t RESERVED4[15];
 831
 832   union {
 833   __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
 834   __O  uint32_t I2C_TX;
 835   };
 836   __I  uint32_t I2C_STS;
 837   __IO uint32_t I2C_CTL;
 838   __IO uint32_t I2C_CLKHI;
 839   __O  uint32_t I2C_CLKLO;
 840        uint32_t RESERVED5[824];
 841
 842   union {
 843   __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
 844   __IO uint32_t OTGClkCtrl;
 845   };
 846   union {
 847   __I  uint32_t USBClkSt;
 848   __I  uint32_t OTGClkSt;
 849   };
 850 } LPC_USB_TypeDef;
 851
 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
 853 typedef struct
 854 {
 855   __IO uint32_t MAC1;                   /* MAC Registers                      */
 856   __IO uint32_t MAC2;
 857   __IO uint32_t IPGT;
 858   __IO uint32_t IPGR;
 859   __IO uint32_t CLRT;
 860   __IO uint32_t MAXF;
 861   __IO uint32_t SUPP;
 862   __IO uint32_t TEST;
 863   __IO uint32_t MCFG;
 864   __IO uint32_t MCMD;
 865   __IO uint32_t MADR;
 866   __O  uint32_t MWTD;
 867   __I  uint32_t MRDD;
 868   __I  uint32_t MIND;
 869        uint32_t RESERVED0[2];
 870   __IO uint32_t SA0;
 871   __IO uint32_t SA1;
 872   __IO uint32_t SA2;
 873        uint32_t RESERVED1[45];
 874   __IO uint32_t Command;                /* Control Registers                  */
 875   __I  uint32_t Status;
 876   __IO uint32_t RxDescriptor;
 877   __IO uint32_t RxStatus;
 878   __IO uint32_t RxDescriptorNumber;
 879   __I  uint32_t RxProduceIndex;
 880   __IO uint32_t RxConsumeIndex;
 881   __IO uint32_t TxDescriptor;
 882   __IO uint32_t TxStatus;
 883   __IO uint32_t TxDescriptorNumber;
 884   __IO uint32_t TxProduceIndex;
 885   __I  uint32_t TxConsumeIndex;
 886        uint32_t RESERVED2[10];
 887   __I  uint32_t TSV0;
 888   __I  uint32_t TSV1;
 889   __I  uint32_t RSV;
 890        uint32_t RESERVED3[3];
 891   __IO uint32_t FlowControlCounter;
 892   __I  uint32_t FlowControlStatus;
 893        uint32_t RESERVED4[34];
 894   __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
 895   __IO uint32_t RxFilterWoLStatus;
 896   __IO uint32_t RxFilterWoLClear;
 897        uint32_t RESERVED5;
 898   __IO uint32_t HashFilterL;
 899   __IO uint32_t HashFilterH;
 900        uint32_t RESERVED6[882];
 901   __I  uint32_t IntStatus;              /* Module Control Registers           */
 902   __IO uint32_t IntEnable;
 903   __O  uint32_t IntClear;
 904   __O  uint32_t IntSet;
 905        uint32_t RESERVED7;
 906   __IO uint32_t PowerDown;
 907        uint32_t RESERVED8;
 908   __IO uint32_t Module_ID;
 909 } LPC_EMAC_TypeDef;
 910
 911 #if defined ( __CC_ARM   )
 912 #pragma no_anon_unions
 913 #endif
 914
 915
 916 /******************************************************************************/
 917 /*                         Peripheral memory map                              */
 918 /******************************************************************************/
 919 /* Base addresses                                                             */
 920 #define LPC_FLASH_BASE        (0x00000000UL)
 921 #define LPC_RAM_BASE          (0x10000000UL)
 922 #define LPC_GPIO_BASE         (0x2009C000UL)
 923 #define LPC_APB0_BASE         (0x40000000UL)
 924 #define LPC_APB1_BASE         (0x40080000UL)
 925 #define LPC_AHB_BASE          (0x50000000UL)
 926 #define LPC_CM3_BASE          (0xE0000000UL)
 927
 928 /* APB0 peripherals                                                           */
 929 #define LPC_WDT_BASE          (LPC_APB0_BASE + 0x00000)
 930 #define LPC_TIM0_BASE         (LPC_APB0_BASE + 0x04000)
 931 #define LPC_TIM1_BASE         (LPC_APB0_BASE + 0x08000)
 932 #define LPC_UART0_BASE        (LPC_APB0_BASE + 0x0C000)
 933 #define LPC_UART1_BASE        (LPC_APB0_BASE + 0x10000)
 934 #define LPC_PWM1_BASE         (LPC_APB0_BASE + 0x18000)
 935 #define LPC_I2C0_BASE         (LPC_APB0_BASE + 0x1C000)
 936 #define LPC_SPI_BASE          (LPC_APB0_BASE + 0x20000)
 937 #define LPC_RTC_BASE          (LPC_APB0_BASE + 0x24000)
 938 #define LPC_GPIOINT_BASE      (LPC_APB0_BASE + 0x28080)
 939 #define LPC_PINCON_BASE       (LPC_APB0_BASE + 0x2C000)
 940 #define LPC_SSP1_BASE         (LPC_APB0_BASE + 0x30000)
 941 #define LPC_ADC_BASE          (LPC_APB0_BASE + 0x34000)
 942 #define LPC_CANAF_RAM_BASE    (LPC_APB0_BASE + 0x38000)
 943 #define LPC_CANAF_BASE        (LPC_APB0_BASE + 0x3C000)
 944 #define LPC_CANCR_BASE        (LPC_APB0_BASE + 0x40000)
 945 #define LPC_CAN1_BASE         (LPC_APB0_BASE + 0x44000)
 946 #define LPC_CAN2_BASE         (LPC_APB0_BASE + 0x48000)
 947 #define LPC_I2C1_BASE         (LPC_APB0_BASE + 0x5C000)
 948
 949 /* APB1 peripherals                                                           */
 950 #define LPC_SSP0_BASE         (LPC_APB1_BASE + 0x08000)
 951 #define LPC_DAC_BASE          (LPC_APB1_BASE + 0x0C000)
 952 #define LPC_TIM2_BASE         (LPC_APB1_BASE + 0x10000)
 953 #define LPC_TIM3_BASE         (LPC_APB1_BASE + 0x14000)
 954 #define LPC_UART2_BASE        (LPC_APB1_BASE + 0x18000)
 955 #define LPC_UART3_BASE        (LPC_APB1_BASE + 0x1C000)
 956 #define LPC_I2C2_BASE         (LPC_APB1_BASE + 0x20000)
 957 #define LPC_I2S_BASE          (LPC_APB1_BASE + 0x28000)
 958 #define LPC_RIT_BASE          (LPC_APB1_BASE + 0x30000)
 959 #define LPC_MCPWM_BASE        (LPC_APB1_BASE + 0x38000)
 960 #define LPC_QEI_BASE          (LPC_APB1_BASE + 0x3C000)
 961 #define LPC_SC_BASE           (LPC_APB1_BASE + 0x7C000)
 962
 963 /* AHB peripherals                                                            */
 964 #define LPC_EMAC_BASE         (LPC_AHB_BASE  + 0x00000)
 965 #define LPC_GPDMA_BASE        (LPC_AHB_BASE  + 0x04000)
 966 #define LPC_GPDMACH0_BASE     (LPC_AHB_BASE  + 0x04100)
 967 #define LPC_GPDMACH1_BASE     (LPC_AHB_BASE  + 0x04120)
 968 #define LPC_GPDMACH2_BASE     (LPC_AHB_BASE  + 0x04140)
 969 #define LPC_GPDMACH3_BASE     (LPC_AHB_BASE  + 0x04160)
 970 #define LPC_GPDMACH4_BASE     (LPC_AHB_BASE  + 0x04180)
 971 #define LPC_GPDMACH5_BASE     (LPC_AHB_BASE  + 0x041A0)
 972 #define LPC_GPDMACH6_BASE     (LPC_AHB_BASE  + 0x041C0)
 973 #define LPC_GPDMACH7_BASE     (LPC_AHB_BASE  + 0x041E0)
 974 #define LPC_USB_BASE          (LPC_AHB_BASE  + 0x0C000)
 975
 976 /* GPIOs                                                                      */
 977 #define LPC_GPIO0_BASE        (LPC_GPIO_BASE + 0x00000)
 978 #define LPC_GPIO1_BASE        (LPC_GPIO_BASE + 0x00020)
 979 #define LPC_GPIO2_BASE        (LPC_GPIO_BASE + 0x00040)
 980 #define LPC_GPIO3_BASE        (LPC_GPIO_BASE + 0x00060)
 981 #define LPC_GPIO4_BASE        (LPC_GPIO_BASE + 0x00080)
 982
 983
 984 /******************************************************************************/
 985 /*                         Peripheral declaration                             */
 986 /******************************************************************************/
 987 #define LPC_SC                ((LPC_SC_TypeDef        *) LPC_SC_BASE       )
 988 #define LPC_GPIO0             ((LPC_GPIO_TypeDef      *) LPC_GPIO0_BASE    )
 989 #define LPC_GPIO1             ((LPC_GPIO_TypeDef      *) LPC_GPIO1_BASE    )
 990 #define LPC_GPIO2             ((LPC_GPIO_TypeDef      *) LPC_GPIO2_BASE    )
 991 #define LPC_GPIO3             ((LPC_GPIO_TypeDef      *) LPC_GPIO3_BASE    )
 992 #define LPC_GPIO4             ((LPC_GPIO_TypeDef      *) LPC_GPIO4_BASE    )
 993 #define LPC_WDT               ((LPC_WDT_TypeDef       *) LPC_WDT_BASE      )
 994 #define LPC_TIM0              ((LPC_TIM_TypeDef       *) LPC_TIM0_BASE     )
 995 #define LPC_TIM1              ((LPC_TIM_TypeDef       *) LPC_TIM1_BASE     )
 996 #define LPC_TIM2              ((LPC_TIM_TypeDef       *) LPC_TIM2_BASE     )
 997 #define LPC_TIM3              ((LPC_TIM_TypeDef       *) LPC_TIM3_BASE     )
 998 #define LPC_RIT               ((LPC_RIT_TypeDef       *) LPC_RIT_BASE      )
 999 #define LPC_UART0             ((LPC_UART0_TypeDef     *) LPC_UART0_BASE    )
1000 #define LPC_UART1             ((LPC_UART1_TypeDef     *) LPC_UART1_BASE    )
1001 #define LPC_UART2             ((LPC_UART_TypeDef      *) LPC_UART2_BASE    )
1002 #define LPC_UART3             ((LPC_UART_TypeDef      *) LPC_UART3_BASE    )
1003 #define LPC_PWM1              ((LPC_PWM_TypeDef       *) LPC_PWM1_BASE     )
1004 #define LPC_I2C0              ((LPC_I2C_TypeDef       *) LPC_I2C0_BASE     )
1005 #define LPC_I2C1              ((LPC_I2C_TypeDef       *) LPC_I2C1_BASE     )
1006 #define LPC_I2C2              ((LPC_I2C_TypeDef       *) LPC_I2C2_BASE     )
1007 #define LPC_I2S               ((LPC_I2S_TypeDef       *) LPC_I2S_BASE      )
1008 #define LPC_SPI               ((LPC_SPI_TypeDef       *) LPC_SPI_BASE      )
1009 #define LPC_RTC               ((LPC_RTC_TypeDef       *) LPC_RTC_BASE      )
1010 #define LPC_GPIOINT           ((LPC_GPIOINT_TypeDef   *) LPC_GPIOINT_BASE  )
1011 #define LPC_PINCON            ((LPC_PINCON_TypeDef    *) LPC_PINCON_BASE   )
1012 #define LPC_SSP0              ((LPC_SSP_TypeDef       *) LPC_SSP0_BASE     )
1013 #define LPC_SSP1              ((LPC_SSP_TypeDef       *) LPC_SSP1_BASE     )
1014 #define LPC_ADC               ((LPC_ADC_TypeDef       *) LPC_ADC_BASE      )
1015 #define LPC_DAC               ((LPC_DAC_TypeDef       *) LPC_DAC_BASE      )
1016 #define LPC_CANAF_RAM         ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
1017 #define LPC_CANAF             ((LPC_CANAF_TypeDef     *) LPC_CANAF_BASE    )
1018 #define LPC_CANCR             ((LPC_CANCR_TypeDef     *) LPC_CANCR_BASE    )
1019 #define LPC_CAN1              ((LPC_CAN_TypeDef       *) LPC_CAN1_BASE     )
1020 #define LPC_CAN2              ((LPC_CAN_TypeDef       *) LPC_CAN2_BASE     )
1021 #define LPC_MCPWM             ((LPC_MCPWM_TypeDef     *) LPC_MCPWM_BASE    )
1022 #define LPC_QEI               ((LPC_QEI_TypeDef       *) LPC_QEI_BASE      )
1023 #define LPC_EMAC              ((LPC_EMAC_TypeDef      *) LPC_EMAC_BASE     )
1024 #define LPC_GPDMA             ((LPC_GPDMA_TypeDef     *) LPC_GPDMA_BASE    )
1025 #define LPC_GPDMACH0          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH0_BASE )
1026 #define LPC_GPDMACH1          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH1_BASE )
1027 #define LPC_GPDMACH2          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH2_BASE )
1028 #define LPC_GPDMACH3          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH3_BASE )
1029 #define LPC_GPDMACH4          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH4_BASE )
1030 #define LPC_GPDMACH5          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH5_BASE )
1031 #define LPC_GPDMACH6          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH6_BASE )
1032 #define LPC_GPDMACH7          ((LPC_GPDMACH_TypeDef   *) LPC_GPDMACH7_BASE )
1033 #define LPC_USB               ((LPC_USB_TypeDef       *) LPC_USB_BASE      )
1034
1035 #endif  // __LPC17xx_H__