tmk_core/tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/LPC23xx.h

   1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
   2  * Copyright (C) 2009 ARM Limited. All rights reserved.
   3  *
   4  * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
   5  */
   6
   7 #ifndef __LPC23xx_H
   8 #define __LPC23xx_H
   9
  10 #ifdef __cplusplus
  11  extern "C" {
  12 #endif
  13
  14 /*
  15  * ==========================================================================
  16  * ---------- Interrupt Number Definition -----------------------------------
  17  * ==========================================================================
  18  */
  19
  20 typedef enum IRQn
  21 {
  22 /******  LPC23xx Specific Interrupt Numbers *******************************************************/
  23   WDT_IRQn                      = 0,        /*!< Watchdog Timer Interrupt                         */
  24
  25   TIMER0_IRQn                   = 4,        /*!< Timer0 Interrupt                                 */
  26   TIMER1_IRQn                   = 5,        /*!< Timer1 Interrupt                                 */
  27   UART0_IRQn                    = 6,        /*!< UART0 Interrupt                                  */
  28   UART1_IRQn                    = 7,        /*!< UART1 Interrupt                                  */
  29   PWM1_IRQn                     = 8,        /*!< PWM1 Interrupt                                   */
  30   I2C0_IRQn                     = 9,        /*!< I2C0 Interrupt                                   */
  31   SPI_IRQn                      = 10,       /*!< SPI Interrupt                                    */
  32   SSP0_IRQn                     = 10,       /*!< SSP0 Interrupt                                   */
  33   SSP1_IRQn                     = 11,       /*!< SSP1 Interrupt                                   */
  34   PLL0_IRQn                     = 12,       /*!< PLL0 Lock (Main PLL) Interrupt                   */
  35   RTC_IRQn                      = 13,       /*!< Real Time Clock Interrupt                        */
  36   EINT0_IRQn                    = 14,       /*!< External Interrupt 0 Interrupt                   */
  37   EINT1_IRQn                    = 15,       /*!< External Interrupt 1 Interrupt                   */
  38   EINT2_IRQn                    = 16,       /*!< External Interrupt 2 Interrupt                   */
  39   EINT3_IRQn                    = 17,       /*!< External Interrupt 3 Interrupt                   */
  40   ADC_IRQn                      = 18,       /*!< A/D Converter Interrupt                          */
  41   I2C1_IRQn                     = 19,       /*!< I2C1 Interrupt                                   */
  42   BOD_IRQn                      = 20,       /*!< Brown-Out Detect Interrupt                       */
  43   ENET_IRQn                     = 21,       /*!< Ethernet Interrupt                               */
  44   USB_IRQn                      = 22,       /*!< USB Interrupt                                    */
  45   CAN_IRQn                      = 23,       /*!< CAN Interrupt                                    */
  46   MIC_IRQn                      = 24,       /*!< Multimedia Interface Controler                   */
  47   DMA_IRQn                      = 25,       /*!< General Purpose DMA Interrupt                    */
  48   TIMER2_IRQn                   = 26,       /*!< Timer2 Interrupt                                 */
  49   TIMER3_IRQn                   = 27,       /*!< Timer3 Interrupt                                 */
  50   UART2_IRQn                    = 28,       /*!< UART2 Interrupt                                  */
  51   UART3_IRQn                    = 29,       /*!< UART3 Interrupt                                  */
  52   I2C2_IRQn                     = 30,       /*!< I2C2 Interrupt                                   */
  53   I2S_IRQn                      = 31,       /*!< I2S Interrupt                                    */
  54 } IRQn_Type;
  55
  56 /*
  57  * ==========================================================================
  58  * ----------- Processor and Core Peripheral Section ------------------------
  59  * ==========================================================================
  60  */
  61
  62 /* Configuration of the ARM7 Processor and Core Peripherals */
  63 #define __MPU_PRESENT             0         /*!< MPU present or not                               */
  64 #define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels          */
  65 #define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used     */
  66
  67
  68 #include <core_arm7.h>
  69 #include "system_LPC23xx.h"                 /* System Header                                      */
  70
  71
  72 /******************************************************************************/
  73 /*                Device Specific Peripheral registers structures             */
  74 /******************************************************************************/
  75 #if defined ( __CC_ARM   )
  76   #pragma anon_unions
  77 #endif
  78
  79 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
  80 typedef struct
  81 {
  82   __I  uint32_t IRQStatus;
  83   __I  uint32_t FIQStatus;
  84   __I  uint32_t RawIntr;
  85   __IO uint32_t IntSelect;
  86   __IO uint32_t IntEnable;
  87   __O  uint32_t IntEnClr;
  88   __IO uint32_t SoftInt;
  89   __O  uint32_t SoftIntClr;
  90   __IO uint32_t Protection;
  91   __IO uint32_t SWPriorityMask;
  92   __IO uint32_t RESERVED0[54];
  93   __IO uint32_t VectAddr[32];
  94   __IO uint32_t RESERVED1[32];
  95   __IO uint32_t VectPriority[32];
  96   __IO uint32_t RESERVED2[800];
  97   __IO uint32_t Address;
  98 } LPC_VIC_TypeDef;
  99
 100 /*------------- System Control (SC) ------------------------------------------*/
 101 typedef struct
 102 {
 103   __IO uint32_t MAMCR;
 104   __IO uint32_t MAMTIM;
 105        uint32_t RESERVED0[14];
 106   __IO uint32_t MEMMAP;
 107        uint32_t RESERVED1[15];
 108   __IO uint32_t PLL0CON;                /* Clocking and Power Control         */
 109   __IO uint32_t PLL0CFG;
 110   __I  uint32_t PLL0STAT;
 111   __O  uint32_t PLL0FEED;
 112        uint32_t RESERVED2[12];
 113   __IO uint32_t PCON;
 114   __IO uint32_t PCONP;
 115        uint32_t RESERVED3[15];
 116   __IO uint32_t CCLKCFG;
 117   __IO uint32_t USBCLKCFG;
 118   __IO uint32_t CLKSRCSEL;
 119        uint32_t RESERVED4[12];
 120   __IO uint32_t EXTINT;                 /* External Interrupts                */
 121   __IO uint32_t INTWAKE;
 122   __IO uint32_t EXTMODE;
 123   __IO uint32_t EXTPOLAR;
 124        uint32_t RESERVED6[12];
 125   __IO uint32_t RSID;                   /* Reset                              */
 126   __IO uint32_t CSPR;
 127   __IO uint32_t AHBCFG1;
 128   __IO uint32_t AHBCFG2;
 129        uint32_t RESERVED7[4];
 130   __IO uint32_t SCS;                    /* Syscon Miscellaneous Registers     */
 131   __IO uint32_t IRCTRIM;                /* Clock Dividers                     */
 132   __IO uint32_t PCLKSEL0;
 133   __IO uint32_t PCLKSEL1;
 134        uint32_t RESERVED8[4];
 135   __IO uint32_t USBIntSt;               /* USB Device/OTG Interrupt Register  */
 136        uint32_t RESERVED9;
 137 //  __IO uint32_t CLKOUTCFG;              /* Clock Output Configuration         */
 138  } LPC_SC_TypeDef;
 139
 140 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
 141 typedef struct
 142 {
 143   __IO uint32_t PINSEL0;
 144   __IO uint32_t PINSEL1;
 145   __IO uint32_t PINSEL2;
 146   __IO uint32_t PINSEL3;
 147   __IO uint32_t PINSEL4;
 148   __IO uint32_t PINSEL5;
 149   __IO uint32_t PINSEL6;
 150   __IO uint32_t PINSEL7;
 151   __IO uint32_t PINSEL8;
 152   __IO uint32_t PINSEL9;
 153   __IO uint32_t PINSEL10;
 154        uint32_t RESERVED0[5];
 155   __IO uint32_t PINMODE0;
 156   __IO uint32_t PINMODE1;
 157   __IO uint32_t PINMODE2;
 158   __IO uint32_t PINMODE3;
 159   __IO uint32_t PINMODE4;
 160   __IO uint32_t PINMODE5;
 161   __IO uint32_t PINMODE6;
 162   __IO uint32_t PINMODE7;
 163   __IO uint32_t PINMODE8;
 164   __IO uint32_t PINMODE9;
 165   __IO uint32_t PINMODE_OD0;
 166   __IO uint32_t PINMODE_OD1;
 167   __IO uint32_t PINMODE_OD2;
 168   __IO uint32_t PINMODE_OD3;
 169   __IO uint32_t PINMODE_OD4;
 170 } LPC_PINCON_TypeDef;
 171
 172 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
 173 typedef struct
 174 {
 175   __IO uint32_t FIODIR;
 176        uint32_t RESERVED0[3];
 177   __IO uint32_t FIOMASK;
 178   __IO uint32_t FIOPIN;
 179   __IO uint32_t FIOSET;
 180   __O  uint32_t FIOCLR;
 181 } LPC_GPIO_TypeDef;
 182
 183 typedef struct
 184 {
 185   __I  uint32_t IntStatus;
 186   __I  uint32_t IO0IntStatR;
 187   __I  uint32_t IO0IntStatF;
 188   __O  uint32_t IO0IntClr;
 189   __IO uint32_t IO0IntEnR;
 190   __IO uint32_t IO0IntEnF;
 191        uint32_t RESERVED0[3];
 192   __I  uint32_t IO2IntStatR;
 193   __I  uint32_t IO2IntStatF;
 194   __O  uint32_t IO2IntClr;
 195   __IO uint32_t IO2IntEnR;
 196   __IO uint32_t IO2IntEnF;
 197 } LPC_GPIOINT_TypeDef;
 198
 199 /*------------- Timer (TIM) --------------------------------------------------*/
 200 typedef struct
 201 {
 202   __IO uint32_t IR;
 203   __IO uint32_t TCR;
 204   __IO uint32_t TC;
 205   __IO uint32_t PR;
 206   __IO uint32_t PC;
 207   __IO uint32_t MCR;
 208   __IO uint32_t MR0;
 209   __IO uint32_t MR1;
 210   __IO uint32_t MR2;
 211   __IO uint32_t MR3;
 212   __IO uint32_t CCR;
 213   __I  uint32_t CR0;
 214   __I  uint32_t CR1;
 215        uint32_t RESERVED0[2];
 216   __IO uint32_t EMR;
 217        uint32_t RESERVED1[12];
 218   __IO uint32_t CTCR;
 219 } LPC_TIM_TypeDef;
 220
 221 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
 222 typedef struct
 223 {
 224   __IO uint32_t IR;
 225   __IO uint32_t TCR;
 226   __IO uint32_t TC;
 227   __IO uint32_t PR;
 228   __IO uint32_t PC;
 229   __IO uint32_t MCR;
 230   __IO uint32_t MR0;
 231   __IO uint32_t MR1;
 232   __IO uint32_t MR2;
 233   __IO uint32_t MR3;
 234   __IO uint32_t CCR;
 235   __I  uint32_t CR0;
 236   __I  uint32_t CR1;
 237   __I  uint32_t CR2;
 238   __I  uint32_t CR3;
 239        uint32_t RESERVED0;
 240   __IO uint32_t MR4;
 241   __IO uint32_t MR5;
 242   __IO uint32_t MR6;
 243   __IO uint32_t PCR;
 244   __IO uint32_t LER;
 245        uint32_t RESERVED1[7];
 246   __IO uint32_t CTCR;
 247 } LPC_PWM_TypeDef;
 248
 249 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
 250 typedef struct
 251 {
 252   union {
 253   __I  uint8_t  RBR;
 254   __O  uint8_t  THR;
 255   __IO uint8_t  DLL;
 256        uint32_t RESERVED0;
 257   };
 258   union {
 259   __IO uint8_t  DLM;
 260   __IO uint32_t IER;
 261   };
 262   union {
 263   __I  uint32_t IIR;
 264   __O  uint8_t  FCR;
 265   };
 266   __IO uint8_t  LCR;
 267        uint8_t  RESERVED1[7];
 268   __IO uint8_t  LSR;
 269        uint8_t  RESERVED2[7];
 270   __IO uint8_t  SCR;
 271        uint8_t  RESERVED3[3];
 272   __IO uint32_t ACR;
 273   __IO uint8_t  ICR;
 274        uint8_t  RESERVED4[3];
 275   __IO uint8_t  FDR;
 276        uint8_t  RESERVED5[7];
 277   __IO uint8_t  TER;
 278        uint8_t  RESERVED6[27];
 279   __IO uint8_t  RS485CTRL;
 280        uint8_t  RESERVED7[3];
 281   __IO uint8_t  ADRMATCH;
 282 } LPC_UART_TypeDef;
 283
 284 typedef struct
 285 {
 286   union {
 287   __I  uint8_t  RBR;
 288   __O  uint8_t  THR;
 289   __IO uint8_t  DLL;
 290        uint32_t RESERVED0;
 291   };
 292   union {
 293   __IO uint8_t  DLM;
 294   __IO uint32_t IER;
 295   };
 296   union {
 297   __I  uint32_t IIR;
 298   __O  uint8_t  FCR;
 299   };
 300   __IO uint8_t  LCR;
 301        uint8_t  RESERVED1[3];
 302   __IO uint8_t  MCR;
 303        uint8_t  RESERVED2[3];
 304   __IO uint8_t  LSR;
 305        uint8_t  RESERVED3[3];
 306   __IO uint8_t  MSR;
 307        uint8_t  RESERVED4[3];
 308   __IO uint8_t  SCR;
 309        uint8_t  RESERVED5[3];
 310   __IO uint32_t ACR;
 311        uint32_t RESERVED6;
 312   __IO uint32_t FDR;
 313        uint32_t RESERVED7;
 314   __IO uint8_t  TER;
 315        uint8_t  RESERVED8[27];
 316   __IO uint8_t  RS485CTRL;
 317        uint8_t  RESERVED9[3];
 318   __IO uint8_t  ADRMATCH;
 319        uint8_t  RESERVED10[3];
 320   __IO uint8_t  RS485DLY;
 321 } LPC_UART1_TypeDef;
 322
 323 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
 324 typedef struct
 325 {
 326   __IO uint32_t SPCR;
 327   __I  uint32_t SPSR;
 328   __IO uint32_t SPDR;
 329   __IO uint32_t SPCCR;
 330        uint32_t RESERVED0[3];
 331   __IO uint32_t SPINT;
 332 } LPC_SPI_TypeDef;
 333
 334 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
 335 typedef struct
 336 {
 337   __IO uint32_t CR0;
 338   __IO uint32_t CR1;
 339   __IO uint32_t DR;
 340   __I  uint32_t SR;
 341   __IO uint32_t CPSR;
 342   __IO uint32_t IMSC;
 343   __IO uint32_t RIS;
 344   __IO uint32_t MIS;
 345   __IO uint32_t ICR;
 346   __IO uint32_t DMACR;
 347 } LPC_SSP_TypeDef;
 348
 349 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
 350 typedef struct
 351 {
 352   __IO uint32_t I2CONSET;
 353   __I  uint32_t I2STAT;
 354   __IO uint32_t I2DAT;
 355   __IO uint32_t I2ADR0;
 356   __IO uint32_t I2SCLH;
 357   __IO uint32_t I2SCLL;
 358   __O  uint32_t I2CONCLR;
 359   __IO uint32_t MMCTRL;
 360   __IO uint32_t I2ADR1;
 361   __IO uint32_t I2ADR2;
 362   __IO uint32_t I2ADR3;
 363   __I  uint32_t I2DATA_BUFFER;
 364   __IO uint32_t I2MASK0;
 365   __IO uint32_t I2MASK1;
 366   __IO uint32_t I2MASK2;
 367   __IO uint32_t I2MASK3;
 368 } LPC_I2C_TypeDef;
 369
 370 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
 371 typedef struct
 372 {
 373   __IO uint32_t I2SDAO;
 374   __I  uint32_t I2SDAI;
 375   __O  uint32_t I2STXFIFO;
 376   __I  uint32_t I2SRXFIFO;
 377   __I  uint32_t I2SSTATE;
 378   __IO uint32_t I2SDMA1;
 379   __IO uint32_t I2SDMA2;
 380   __IO uint32_t I2SIRQ;
 381   __IO uint32_t I2STXRATE;
 382   __IO uint32_t I2SRXRATE;
 383   __IO uint32_t I2STXBITRATE;
 384   __IO uint32_t I2SRXBITRATE;
 385   __IO uint32_t I2STXMODE;
 386   __IO uint32_t I2SRXMODE;
 387 } LPC_I2S_TypeDef;
 388
 389 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
 390 typedef struct
 391 {
 392   __IO uint8_t  ILR;
 393        uint8_t  RESERVED0[3];
 394   __IO uint8_t  CTC;
 395        uint8_t  RESERVED1[3];
 396   __IO uint8_t  CCR;
 397        uint8_t  RESERVED2[3];
 398   __IO uint8_t  CIIR;
 399        uint8_t  RESERVED3[3];
 400   __IO uint8_t  AMR;
 401        uint8_t  RESERVED4[3];
 402   __I  uint32_t CTIME0;
 403   __I  uint32_t CTIME1;
 404   __I  uint32_t CTIME2;
 405   __IO uint8_t  SEC;
 406        uint8_t  RESERVED5[3];
 407   __IO uint8_t  MIN;
 408        uint8_t  RESERVED6[3];
 409   __IO uint8_t  HOUR;
 410        uint8_t  RESERVED7[3];
 411   __IO uint8_t  DOM;
 412        uint8_t  RESERVED8[3];
 413   __IO uint8_t  DOW;
 414        uint8_t  RESERVED9[3];
 415   __IO uint16_t DOY;
 416        uint16_t RESERVED10;
 417   __IO uint8_t  MONTH;
 418        uint8_t  RESERVED11[3];
 419   __IO uint16_t YEAR;
 420        uint16_t RESERVED12;
 421   __IO uint32_t CALIBRATION;
 422   __IO uint32_t GPREG0;
 423   __IO uint32_t GPREG1;
 424   __IO uint32_t GPREG2;
 425   __IO uint32_t GPREG3;
 426   __IO uint32_t GPREG4;
 427   __IO uint8_t  WAKEUPDIS;
 428        uint8_t  RESERVED13[3];
 429   __IO uint8_t  PWRCTRL;
 430        uint8_t  RESERVED14[3];
 431   __IO uint8_t  ALSEC;
 432        uint8_t  RESERVED15[3];
 433   __IO uint8_t  ALMIN;
 434        uint8_t  RESERVED16[3];
 435   __IO uint8_t  ALHOUR;
 436        uint8_t  RESERVED17[3];
 437   __IO uint8_t  ALDOM;
 438        uint8_t  RESERVED18[3];
 439   __IO uint8_t  ALDOW;
 440        uint8_t  RESERVED19[3];
 441   __IO uint16_t ALDOY;
 442        uint16_t RESERVED20;
 443   __IO uint8_t  ALMON;
 444        uint8_t  RESERVED21[3];
 445   __IO uint16_t ALYEAR;
 446        uint16_t RESERVED22;
 447 } LPC_RTC_TypeDef;
 448
 449 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
 450 typedef struct
 451 {
 452   __IO uint8_t  WDMOD;
 453        uint8_t  RESERVED0[3];
 454   __IO uint32_t WDTC;
 455   __O  uint8_t  WDFEED;
 456        uint8_t  RESERVED1[3];
 457   __I  uint32_t WDTV;
 458   __IO uint32_t WDCLKSEL;
 459 } LPC_WDT_TypeDef;
 460
 461 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
 462 typedef struct
 463 {
 464   __IO uint32_t ADCR;
 465   __IO uint32_t ADGDR;
 466        uint32_t RESERVED0;
 467   __IO uint32_t ADINTEN;
 468   __I  uint32_t ADDR0;
 469   __I  uint32_t ADDR1;
 470   __I  uint32_t ADDR2;
 471   __I  uint32_t ADDR3;
 472   __I  uint32_t ADDR4;
 473   __I  uint32_t ADDR5;
 474   __I  uint32_t ADDR6;
 475   __I  uint32_t ADDR7;
 476   __I  uint32_t ADSTAT;
 477   __IO uint32_t ADTRM;
 478 } LPC_ADC_TypeDef;
 479
 480 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
 481 typedef struct
 482 {
 483   __IO uint32_t DACR;
 484   __IO uint32_t DACCTRL;
 485   __IO uint16_t DACCNTVAL;
 486 } LPC_DAC_TypeDef;
 487
 488 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
 489 typedef struct
 490 {
 491   __IO uint32_t MCIPower;               /* Power control                      */
 492   __IO uint32_t MCIClock;               /* Clock control                      */
 493   __IO uint32_t MCIArgument;
 494   __IO uint32_t MMCCommand;
 495   __I  uint32_t MCIRespCmd;
 496   __I  uint32_t MCIResponse0;
 497   __I  uint32_t MCIResponse1;
 498   __I  uint32_t MCIResponse2;
 499   __I  uint32_t MCIResponse3;
 500   __IO uint32_t MCIDataTimer;
 501   __IO uint32_t MCIDataLength;
 502   __IO uint32_t MCIDataCtrl;
 503   __I  uint32_t MCIDataCnt;
 504 } LPC_MCI_TypeDef;
 505
 506 /*------------- Controller Area Network (CAN) --------------------------------*/
 507 typedef struct
 508 {
 509   __IO uint32_t mask[512];              /* ID Masks                           */
 510 } LPC_CANAF_RAM_TypeDef;
 511
 512 typedef struct                          /* Acceptance Filter Registers        */
 513 {
 514   __IO uint32_t AFMR;
 515   __IO uint32_t SFF_sa;
 516   __IO uint32_t SFF_GRP_sa;
 517   __IO uint32_t EFF_sa;
 518   __IO uint32_t EFF_GRP_sa;
 519   __IO uint32_t ENDofTable;
 520   __I  uint32_t LUTerrAd;
 521   __I  uint32_t LUTerr;
 522 } LPC_CANAF_TypeDef;
 523
 524 typedef struct                          /* Central Registers                  */
 525 {
 526   __I  uint32_t CANTxSR;
 527   __I  uint32_t CANRxSR;
 528   __I  uint32_t CANMSR;
 529 } LPC_CANCR_TypeDef;
 530
 531 typedef struct                          /* Controller Registers               */
 532 {
 533   __IO uint32_t MOD;
 534   __O  uint32_t CMR;
 535   __IO uint32_t GSR;
 536   __I  uint32_t ICR;
 537   __IO uint32_t IER;
 538   __IO uint32_t BTR;
 539   __IO uint32_t EWL;
 540   __I  uint32_t SR;
 541   __IO uint32_t RFS;
 542   __IO uint32_t RID;
 543   __IO uint32_t RDA;
 544   __IO uint32_t RDB;
 545   __IO uint32_t TFI1;
 546   __IO uint32_t TID1;
 547   __IO uint32_t TDA1;
 548   __IO uint32_t TDB1;
 549   __IO uint32_t TFI2;
 550   __IO uint32_t TID2;
 551   __IO uint32_t TDA2;
 552   __IO uint32_t TDB2;
 553   __IO uint32_t TFI3;
 554   __IO uint32_t TID3;
 555   __IO uint32_t TDA3;
 556   __IO uint32_t TDB3;
 557 } LPC_CAN_TypeDef;
 558
 559 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
 560 typedef struct                          /* Common Registers                   */
 561 {
 562   __I  uint32_t DMACIntStat;
 563   __I  uint32_t DMACIntTCStat;
 564   __O  uint32_t DMACIntTCClear;
 565   __I  uint32_t DMACIntErrStat;
 566   __O  uint32_t DMACIntErrClr;
 567   __I  uint32_t DMACRawIntTCStat;
 568   __I  uint32_t DMACRawIntErrStat;
 569   __I  uint32_t DMACEnbldChns;
 570   __IO uint32_t DMACSoftBReq;
 571   __IO uint32_t DMACSoftSReq;
 572   __IO uint32_t DMACSoftLBReq;
 573   __IO uint32_t DMACSoftLSReq;
 574   __IO uint32_t DMACConfig;
 575   __IO uint32_t DMACSync;
 576 } LPC_GPDMA_TypeDef;
 577
 578 typedef struct                          /* Channel Registers                  */
 579 {
 580   __IO uint32_t DMACCSrcAddr;
 581   __IO uint32_t DMACCDestAddr;
 582   __IO uint32_t DMACCLLI;
 583   __IO uint32_t DMACCControl;
 584   __IO uint32_t DMACCConfig;
 585 } LPC_GPDMACH_TypeDef;
 586
 587 /*------------- Universal Serial Bus (USB) -----------------------------------*/
 588 typedef struct
 589 {
 590   __I  uint32_t HcRevision;             /* USB Host Registers                 */
 591   __IO uint32_t HcControl;
 592   __IO uint32_t HcCommandStatus;
 593   __IO uint32_t HcInterruptStatus;
 594   __IO uint32_t HcInterruptEnable;
 595   __IO uint32_t HcInterruptDisable;
 596   __IO uint32_t HcHCCA;
 597   __I  uint32_t HcPeriodCurrentED;
 598   __IO uint32_t HcControlHeadED;
 599   __IO uint32_t HcControlCurrentED;
 600   __IO uint32_t HcBulkHeadED;
 601   __IO uint32_t HcBulkCurrentED;
 602   __I  uint32_t HcDoneHead;
 603   __IO uint32_t HcFmInterval;
 604   __I  uint32_t HcFmRemaining;
 605   __I  uint32_t HcFmNumber;
 606   __IO uint32_t HcPeriodicStart;
 607   __IO uint32_t HcLSTreshold;
 608   __IO uint32_t HcRhDescriptorA;
 609   __IO uint32_t HcRhDescriptorB;
 610   __IO uint32_t HcRhStatus;
 611   __IO uint32_t HcRhPortStatus1;
 612   __IO uint32_t HcRhPortStatus2;
 613        uint32_t RESERVED0[40];
 614   __I  uint32_t Module_ID;
 615
 616   __I  uint32_t OTGIntSt;               /* USB On-The-Go Registers            */
 617   __IO uint32_t OTGIntEn;
 618   __O  uint32_t OTGIntSet;
 619   __O  uint32_t OTGIntClr;
 620   __IO uint32_t OTGStCtrl;
 621   __IO uint32_t OTGTmr;
 622        uint32_t RESERVED1[58];
 623
 624   __I  uint32_t USBDevIntSt;            /* USB Device Interrupt Registers     */
 625   __IO uint32_t USBDevIntEn;
 626   __O  uint32_t USBDevIntClr;
 627   __O  uint32_t USBDevIntSet;
 628
 629   __O  uint32_t USBCmdCode;             /* USB Device SIE Command Registers   */
 630   __I  uint32_t USBCmdData;
 631
 632   __I  uint32_t USBRxData;              /* USB Device Transfer Registers      */
 633   __O  uint32_t USBTxData;
 634   __I  uint32_t USBRxPLen;
 635   __O  uint32_t USBTxPLen;
 636   __IO uint32_t USBCtrl;
 637   __O  uint32_t USBDevIntPri;
 638
 639   __I  uint32_t USBEpIntSt;             /* USB Device Endpoint Interrupt Regs */
 640   __IO uint32_t USBEpIntEn;
 641   __O  uint32_t USBEpIntClr;
 642   __O  uint32_t USBEpIntSet;
 643   __O  uint32_t USBEpIntPri;
 644
 645   __IO uint32_t USBReEp;                /* USB Device Endpoint Realization Reg*/
 646   __O  uint32_t USBEpInd;
 647   __IO uint32_t USBMaxPSize;
 648
 649   __I  uint32_t USBDMARSt;              /* USB Device DMA Registers           */
 650   __O  uint32_t USBDMARClr;
 651   __O  uint32_t USBDMARSet;
 652        uint32_t RESERVED2[9];
 653   __IO uint32_t USBUDCAH;
 654   __I  uint32_t USBEpDMASt;
 655   __O  uint32_t USBEpDMAEn;
 656   __O  uint32_t USBEpDMADis;
 657   __I  uint32_t USBDMAIntSt;
 658   __IO uint32_t USBDMAIntEn;
 659        uint32_t RESERVED3[2];
 660   __I  uint32_t USBEoTIntSt;
 661   __O  uint32_t USBEoTIntClr;
 662   __O  uint32_t USBEoTIntSet;
 663   __I  uint32_t USBNDDRIntSt;
 664   __O  uint32_t USBNDDRIntClr;
 665   __O  uint32_t USBNDDRIntSet;
 666   __I  uint32_t USBSysErrIntSt;
 667   __O  uint32_t USBSysErrIntClr;
 668   __O  uint32_t USBSysErrIntSet;
 669        uint32_t RESERVED4[15];
 670
 671   __I  uint32_t I2C_RX;                 /* USB OTG I2C Registers              */
 672   __O  uint32_t I2C_WO;
 673   __I  uint32_t I2C_STS;
 674   __IO uint32_t I2C_CTL;
 675   __IO uint32_t I2C_CLKHI;
 676   __O  uint32_t I2C_CLKLO;
 677        uint32_t RESERVED5[823];
 678
 679   union {
 680   __IO uint32_t USBClkCtrl;             /* USB Clock Control Registers        */
 681   __IO uint32_t OTGClkCtrl;
 682   };
 683   union {
 684   __I  uint32_t USBClkSt;
 685   __I  uint32_t OTGClkSt;
 686   };
 687 } LPC_USB_TypeDef;
 688
 689 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
 690 typedef struct
 691 {
 692   __IO uint32_t MAC1;                   /* MAC Registers                      */
 693   __IO uint32_t MAC2;
 694   __IO uint32_t IPGT;
 695   __IO uint32_t IPGR;
 696   __IO uint32_t CLRT;
 697   __IO uint32_t MAXF;
 698   __IO uint32_t SUPP;
 699   __IO uint32_t TEST;
 700   __IO uint32_t MCFG;
 701   __IO uint32_t MCMD;
 702   __IO uint32_t MADR;
 703   __O  uint32_t MWTD;
 704   __I  uint32_t MRDD;
 705   __I  uint32_t MIND;
 706        uint32_t RESERVED0[2];
 707   __IO uint32_t SA0;
 708   __IO uint32_t SA1;
 709   __IO uint32_t SA2;
 710        uint32_t RESERVED1[45];
 711   __IO uint32_t Command;                /* Control Registers                  */
 712   __I  uint32_t Status;
 713   __IO uint32_t RxDescriptor;
 714   __IO uint32_t RxStatus;
 715   __IO uint32_t RxDescriptorNumber;
 716   __I  uint32_t RxProduceIndex;
 717   __IO uint32_t RxConsumeIndex;
 718   __IO uint32_t TxDescriptor;
 719   __IO uint32_t TxStatus;
 720   __IO uint32_t TxDescriptorNumber;
 721   __IO uint32_t TxProduceIndex;
 722   __I  uint32_t TxConsumeIndex;
 723        uint32_t RESERVED2[10];
 724   __I  uint32_t TSV0;
 725   __I  uint32_t TSV1;
 726   __I  uint32_t RSV;
 727        uint32_t RESERVED3[3];
 728   __IO uint32_t FlowControlCounter;
 729   __I  uint32_t FlowControlStatus;
 730        uint32_t RESERVED4[34];
 731   __IO uint32_t RxFilterCtrl;           /* Rx Filter Registers                */
 732   __IO uint32_t RxFilterWoLStatus;
 733   __IO uint32_t RxFilterWoLClear;
 734        uint32_t RESERVED5;
 735   __IO uint32_t HashFilterL;
 736   __IO uint32_t HashFilterH;
 737        uint32_t RESERVED6[882];
 738   __I  uint32_t IntStatus;              /* Module Control Registers           */
 739   __IO uint32_t IntEnable;
 740   __O  uint32_t IntClear;
 741   __O  uint32_t IntSet;
 742        uint32_t RESERVED7;
 743   __IO uint32_t PowerDown;
 744        uint32_t RESERVED8;
 745   __IO uint32_t Module_ID;
 746 } LPC_EMAC_TypeDef;
 747
 748 #if defined ( __CC_ARM   )
 749   #pragma no_anon_unions
 750 #endif
 751
 752 /******************************************************************************/
 753 /*                         Peripheral memory map                              */
 754 /******************************************************************************/
 755 /* Base addresses                                                             */
 756
 757 /* AHB Peripheral # 0 */
 758
 759 /*
 760 #define FLASH_BASE            (0x00000000UL)
 761 #define RAM_BASE              (0x10000000UL)
 762 #define GPIO_BASE             (0x2009C000UL)
 763 #define APB0_BASE             (0x40000000UL)
 764 #define APB1_BASE             (0x40080000UL)
 765 #define AHB_BASE              (0x50000000UL)
 766 #define CM3_BASE              (0xE0000000UL)
 767 */
 768
 769 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
 770
 771 #define LPC_WDT_BASE              (0xE0000000)
 772 #define LPC_TIM0_BASE             (0xE0004000)
 773 #define LPC_TIM1_BASE             (0xE0008000)
 774 #define LPC_UART0_BASE            (0xE000C000)
 775 #define LPC_UART1_BASE            (0xE0010000)
 776 #define LPC_PWM1_BASE             (0xE0018000)
 777 #define LPC_I2C0_BASE             (0xE001C000)
 778 #define LPC_SPI_BASE              (0xE0020000)
 779 #define LPC_RTC_BASE              (0xE0024000)
 780 #define LPC_GPIOINT_BASE          (0xE0028080)
 781 #define LPC_PINCON_BASE           (0xE002C000)
 782 #define LPC_SSP1_BASE             (0xE0030000)
 783 #define LPC_ADC_BASE              (0xE0034000)
 784 #define LPC_CANAF_RAM_BASE        (0xE0038000)
 785 #define LPC_CANAF_BASE            (0xE003C000)
 786 #define LPC_CANCR_BASE            (0xE0040000)
 787 #define LPC_CAN1_BASE             (0xE0044000)
 788 #define LPC_CAN2_BASE             (0xE0048000)
 789 #define LPC_I2C1_BASE             (0xE005C000)
 790 #define LPC_SSP0_BASE             (0xE0068000)
 791 #define LPC_DAC_BASE              (0xE006C000)
 792 #define LPC_TIM2_BASE             (0xE0070000)
 793 #define LPC_TIM3_BASE             (0xE0074000)
 794 #define LPC_UART2_BASE            (0xE0078000)
 795 #define LPC_UART3_BASE            (0xE007C000)
 796 #define LPC_I2C2_BASE             (0xE0080000)
 797 #define LPC_I2S_BASE              (0xE0088000)
 798 #define LPC_MCI_BASE              (0xE008C000)
 799 #define LPC_SC_BASE               (0xE01FC000)
 800 #define LPC_EMAC_BASE             (0xFFE00000)
 801 #define LPC_GPDMA_BASE            (0xFFE04000)
 802 #define LPC_GPDMACH0_BASE         (0xFFE04100)
 803 #define LPC_GPDMACH1_BASE         (0xFFE04120)
 804 #define LPC_USB_BASE              (0xFFE0C000)
 805 #define LPC_VIC_BASE              (0xFFFFF000)
 806
 807 /* GPIOs                                                                      */
 808 #define LPC_GPIO0_BASE            (0x3FFFC000)
 809 #define LPC_GPIO1_BASE            (0x3FFFC020)
 810 #define LPC_GPIO2_BASE            (0x3FFFC040)
 811 #define LPC_GPIO3_BASE            (0x3FFFC060)
 812 #define LPC_GPIO4_BASE            (0x3FFFC080)
 813
 814
 815 /******************************************************************************/
 816 /*                         Peripheral declaration                             */
 817 /******************************************************************************/
 818 #define LPC_SC                    ((       LPC_SC_TypeDef *)        LPC_SC_BASE)
 819 #define LPC_GPIO0                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO0_BASE)
 820 #define LPC_GPIO1                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO1_BASE)
 821 #define LPC_GPIO2                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO2_BASE)
 822 #define LPC_GPIO3                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO3_BASE)
 823 #define LPC_GPIO4                 ((     LPC_GPIO_TypeDef *)     LPC_GPIO4_BASE)
 824 #define LPC_WDT                   ((      LPC_WDT_TypeDef *)       LPC_WDT_BASE)
 825 #define LPC_TIM0                  ((      LPC_TIM_TypeDef *)      LPC_TIM0_BASE)
 826 #define LPC_TIM1                  ((      LPC_TIM_TypeDef *)      LPC_TIM1_BASE)
 827 #define LPC_TIM2                  ((      LPC_TIM_TypeDef *)      LPC_TIM2_BASE)
 828 #define LPC_TIM3                  ((      LPC_TIM_TypeDef *)      LPC_TIM3_BASE)
 829 #define LPC_UART0                 ((     LPC_UART_TypeDef *)     LPC_UART0_BASE)
 830 #define LPC_UART1                 ((    LPC_UART1_TypeDef *)     LPC_UART1_BASE)
 831 #define LPC_UART2                 ((     LPC_UART_TypeDef *)     LPC_UART2_BASE)
 832 #define LPC_UART3                 ((     LPC_UART_TypeDef *)     LPC_UART3_BASE)
 833 #define LPC_PWM1                  ((      LPC_PWM_TypeDef *)      LPC_PWM1_BASE)
 834 #define LPC_I2C0                  ((      LPC_I2C_TypeDef *)      LPC_I2C0_BASE)
 835 #define LPC_I2C1                  ((      LPC_I2C_TypeDef *)      LPC_I2C1_BASE)
 836 #define LPC_I2C2                  ((      LPC_I2C_TypeDef *)      LPC_I2C2_BASE)
 837 #define LPC_I2S                   ((      LPC_I2S_TypeDef *)       LPC_I2S_BASE)
 838 #define LPC_SPI                   ((      LPC_SPI_TypeDef *)       LPC_SPI_BASE)
 839 #define LPC_RTC                   ((      LPC_RTC_TypeDef *)       LPC_RTC_BASE)
 840 #define LPC_GPIOINT               ((  LPC_GPIOINT_TypeDef *)   LPC_GPIOINT_BASE)
 841 #define LPC_PINCON                ((   LPC_PINCON_TypeDef *)    LPC_PINCON_BASE)
 842 #define LPC_SSP0                  ((      LPC_SSP_TypeDef *)      LPC_SSP0_BASE)
 843 #define LPC_SSP1                  ((      LPC_SSP_TypeDef *)      LPC_SSP1_BASE)
 844 #define LPC_ADC                   ((      LPC_ADC_TypeDef *)       LPC_ADC_BASE)
 845 #define LPC_DAC                   ((      LPC_DAC_TypeDef *)       LPC_DAC_BASE)
 846 #define LPC_CANAF_RAM             ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
 847 #define LPC_CANAF                 ((    LPC_CANAF_TypeDef *)     LPC_CANAF_BASE)
 848 #define LPC_CANCR                 ((    LPC_CANCR_TypeDef *)     LPC_CANCR_BASE)
 849 #define LPC_CAN1                  ((      LPC_CAN_TypeDef *)      LPC_CAN1_BASE)
 850 #define LPC_CAN2                  ((      LPC_CAN_TypeDef *)      LPC_CAN2_BASE)
 851 #define LPC_MCI                   ((      LPC_MCI_TypeDef *)       LPC_MCI_BASE)
 852 #define LPC_EMAC                  ((     LPC_EMAC_TypeDef *)      LPC_EMAC_BASE)
 853 #define LPC_GPDMA                 ((    LPC_GPDMA_TypeDef *)     LPC_GPDMA_BASE)
 854 #define LPC_GPDMACH0              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH0_BASE)
 855 #define LPC_GPDMACH1              ((  LPC_GPDMACH_TypeDef *)  LPC_GPDMACH1_BASE)
 856 #define LPC_USB                   ((      LPC_USB_TypeDef *)       LPC_USB_BASE)
 857 #define LPC_VIC                   ((      LPC_VIC_TypeDef *)       LPC_VIC_BASE)
 858
 859 #ifdef __cplusplus
 860  }
 861 #endif
 862
 863 #endif  // __LPC23xx_H
 864