Delete MOUSEKEY_DELAY_TIME in config.h
[tmk_keyboard.git] / converter / ps2_usb / config.h
1 /*
2 Copyright 2012 Jun Wako <wakojun@gmail.com>
3
4 This program is free software: you can redistribute it and/or modify
5 it under the terms of the GNU General Public License as published by
6 the Free Software Foundation, either version 2 of the License, or
7 (at your option) any later version.
8
9 This program is distributed in the hope that it will be useful,
10 but WITHOUT ANY WARRANTY; without even the implied warranty of
11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 GNU General Public License for more details.
13
14 You should have received a copy of the GNU General Public License
15 along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef CONFIG_H
19 #define CONFIG_H
20
21 #include <avr/interrupt.h>
22
23 #define VENDOR_ID 0xFEED
24 #define PRODUCT_ID 0x6512
25 #define MANUFACTURER t.m.k.
26 #define PRODUCT PS/2 keyboard converter
27 #define DESCRIPTION convert PS/2 keyboard to USB
28
29
30 /* matrix size */
31 #define MATRIX_ROWS 32 // keycode bit: 3-0
32 #define MATRIX_COLS 8 // keycode bit: 6-4
33
34
35 /* key combination for command */
36 #define IS_COMMAND() ( \
37 keyboard_report->mods == (MOD_BIT(KC_LSHIFT) | MOD_BIT(KC_RSHIFT)) || \
38 keyboard_report->mods == (MOD_BIT(KC_LCTRL) | MOD_BIT(KC_RSHIFT)) \
39 )
40
41
42 #ifdef PS2_USE_USART
43 #if defined(__AVR_ATmega16U4__) || defined(__AVR_ATmega32U4__)
44 /* XCK for clock line and RXD for data line */
45 #define PS2_CLOCK_PORT PORTD
46 #define PS2_CLOCK_PIN PIND
47 #define PS2_CLOCK_DDR DDRD
48 #define PS2_CLOCK_BIT 5
49 #define PS2_DATA_PORT PORTD
50 #define PS2_DATA_PIN PIND
51 #define PS2_DATA_DDR DDRD
52 #define PS2_DATA_BIT 2
53
54 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
55 /* set DDR of CLOCK as input to be slave */
56 #define PS2_USART_INIT() do { \
57 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
58 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
59 UCSR1C = ((1 << UMSEL10) | \
60 (3 << UPM10) | \
61 (0 << USBS1) | \
62 (3 << UCSZ10) | \
63 (0 << UCPOL1)); \
64 UCSR1A = 0; \
65 UBRR1H = 0; \
66 UBRR1L = 0; \
67 } while (0)
68 #define PS2_USART_RX_INT_ON() do { \
69 UCSR1B = ((1 << RXCIE1) | \
70 (1 << RXEN1)); \
71 } while (0)
72 #define PS2_USART_RX_POLL_ON() do { \
73 UCSR1B = (1 << RXEN1); \
74 } while (0)
75 #define PS2_USART_OFF() do { \
76 UCSR1C = 0; \
77 UCSR1B &= ~((1 << RXEN1) | \
78 (1 << TXEN1)); \
79 } while (0)
80 #define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
81 #define PS2_USART_RX_DATA UDR1
82 #define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
83 #define PS2_USART_RX_VECT USART1_RX_vect
84
85 #elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega168P__) || defined(__AVR_ATmega328P__)
86 /* XCK for clock line and RXD for data line */
87 #define PS2_CLOCK_PORT PORTD
88 #define PS2_CLOCK_PIN PIND
89 #define PS2_CLOCK_DDR DDRD
90 #define PS2_CLOCK_BIT 4
91 #define PS2_DATA_PORT PORTD
92 #define PS2_DATA_PIN PIND
93 #define PS2_DATA_DDR DDRD
94 #define PS2_DATA_BIT 0
95
96 /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
97 /* set DDR of CLOCK as input to be slave */
98 #define PS2_USART_INIT() do { \
99 PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
100 PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
101 UCSR0C = ((1 << UMSEL00) | \
102 (3 << UPM00) | \
103 (0 << USBS0) | \
104 (3 << UCSZ00) | \
105 (0 << UCPOL0)); \
106 UCSR0A = 0; \
107 UBRR0H = 0; \
108 UBRR0L = 0; \
109 } while (0)
110 #define PS2_USART_RX_INT_ON() do { \
111 UCSR0B = ((1 << RXCIE0) | \
112 (1 << RXEN0)); \
113 } while (0)
114 #define PS2_USART_RX_POLL_ON() do { \
115 UCSR0B = (1 << RXEN0); \
116 } while (0)
117 #define PS2_USART_OFF() do { \
118 UCSR0C = 0; \
119 UCSR0B &= ~((1 << RXEN0) | \
120 (1 << TXEN0)); \
121 } while (0)
122 #define PS2_USART_RX_READY (UCSR0A & (1<<RXC0))
123 #define PS2_USART_RX_DATA UDR0
124 #define PS2_USART_ERROR (UCSR0A & ((1<<FE0) | (1<<DOR0) | (1<<UPE0)))
125 #define PS2_USART_RX_VECT USART_RX_vect
126 #endif
127 #endif
128
129
130 #ifdef PS2_USE_INT
131 /* uses INT1 for clock line(ATMega32U4) */
132 #define PS2_CLOCK_PORT PORTD
133 #define PS2_CLOCK_PIN PIND
134 #define PS2_CLOCK_DDR DDRD
135 #define PS2_CLOCK_BIT 1
136 #define PS2_DATA_PORT PORTD
137 #define PS2_DATA_PIN PIND
138 #define PS2_DATA_DDR DDRD
139 #define PS2_DATA_BIT 2
140
141 #define PS2_INT_INIT() do { \
142 EICRA |= ((1<<ISC11) | \
143 (0<<ISC10)); \
144 } while (0)
145 #define PS2_INT_ON() do { \
146 EIMSK |= (1<<INT1); \
147 } while (0)
148 #define PS2_INT_OFF() do { \
149 EIMSK &= ~(1<<INT1); \
150 } while (0)
151 #define PS2_INT_VECT INT1_vect
152 #endif
153
154
155 #ifdef PS2_USE_BUSYWAIT
156 #define PS2_CLOCK_PORT PORTF
157 #define PS2_CLOCK_PIN PINF
158 #define PS2_CLOCK_DDR DDRF
159 #define PS2_CLOCK_BIT 0
160 #define PS2_DATA_PORT PORTF
161 #define PS2_DATA_PIN PINF
162 #define PS2_DATA_DDR DDRF
163 #define PS2_DATA_BIT 1
164 #endif
165
166 #endif
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