/** ****************************************************************************** * @file stm32f091xc.h * @author MCD Application Team * @version V2.2.0 * @date 05-December-2014 * @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - Peripheral's registers declarations and bits definition * - Macros to access peripheral’s registers hardware * ****************************************************************************** * @attention * *

© COPYRIGHT(c) 2014 STMicroelectronics

* * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * 3. Neither the name of STMicroelectronics nor the names of its contributors * may be used to endorse or promote products derived from this software * without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup stm32f091xc * @{ */ #ifndef __STM32F091xC_H #define __STM32F091xC_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M0 Processor and Core Peripherals */ #define __CM0_REV 0 /*!< Core Revision r0p0 */ #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */ #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief STM32F091xC device Interrupt Number Definition */ typedef enum { /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ /****** STM32F091xC specific Interrupt Numbers **************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_VDDIO2_IRQn = 1, /*!< PVD & VDDIO2 Interrupts through EXTI Lines 16 and 31 */ RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */ FLASH_IRQn = 3, /*!< FLASH global Interrupt */ RCC_CRS_IRQn = 4, /*!< RCC & CRS global Interrupts */ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ TSC_IRQn = 8, /*!< Touch Sensing Controller Interrupts */ DMA1_Ch1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ DMA1_Ch2_3_DMA2_Ch1_2_IRQn = 10, /*!< DMA1 Channel 2 and 3 & DMA2 Channel 1 and 2 Interrupts */ DMA1_Ch4_7_DMA2_Ch3_5_IRQn = 11, /*!< DMA1 Channel 4 to 7 & DMA2 Channel 3 to 5 Interrupts */ ADC1_COMP_IRQn = 12, /*!< ADC, COMP1 and COMP2 Interrupts (EXTI Lines 21 and 22) */ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ TIM6_DAC_IRQn = 17, /*!< TIM6 global and DAC channel underrun error Interrupts */ TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */ I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */ SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ USART1_IRQn = 27, /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */ USART2_IRQn = 28, /*!< USART2 global Interrupt & EXTI Line26 Interrupt (USART2 wakeup) */ USART3_8_IRQn = 29, /*!< USART3 to USART8 global Interrupts */ CEC_CAN_IRQn = 30 /*!< CEC and CAN global Interrupts & EXTI Line27 Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */ #include "system_stm32f0xx.h" /* STM32F0xx System Header */ #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */ __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */ __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */ __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */ __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */ __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */ uint32_t RESERVED1; /*!< Reserved, 0x18 */ uint32_t RESERVED2; /*!< Reserved, 0x1C */ __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */ uint32_t RESERVED3; /*!< Reserved, 0x24 */ __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */ uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */ }ADC_TypeDef; typedef struct { __IO uint32_t CCR; }ADC_Common_TypeDef; /** * @brief Controller Area Network TxMailBox */ typedef struct { __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */ __IO uint32_t TDLR; /*!< CAN mailbox data low register */ __IO uint32_t TDHR; /*!< CAN mailbox data high register */ }CAN_TxMailBox_TypeDef; /** * @brief Controller Area Network FIFOMailBox */ typedef struct { __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */ }CAN_FIFOMailBox_TypeDef; /** * @brief Controller Area Network FilterRegister */ typedef struct { __IO uint32_t FR1; /*!< CAN Filter bank register 1 */ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */ }CAN_FilterRegister_TypeDef; /** * @brief Controller Area Network */ typedef struct { __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */ uint32_t RESERVED2; /*!< Reserved, 0x208 */ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */ uint32_t RESERVED3; /*!< Reserved, 0x210 */ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */ uint32_t RESERVED4; /*!< Reserved, 0x218 */ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */ }CAN_TypeDef; /** * @brief HDMI-CEC */ typedef struct { __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */ __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */ __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */ __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */ __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */ __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */ }CEC_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< Comparator 1 & 2 control Status register, Address offset: 0x00 */ }COMP1_2_TypeDef; typedef struct { __IO uint16_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */ }COMP_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ uint8_t RESERVED0; /*!< Reserved, 0x05 */ uint16_t RESERVED1; /*!< Reserved, 0x06 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ uint32_t RESERVED2; /*!< Reserved, 0x0C */ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ }CRC_TypeDef; /** * @brief Clock Recovery System */ typedef struct { __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ }CRS_TypeDef; /** * @brief Digital to Analog Converter */ typedef struct { __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ }DAC_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */ }DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ }DMA_Channel_TypeDef; typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ uint32_t RESERVED0[40];/*!< Reserved as declared by channel typedef 0x08 - 0xA4 */ __IO uint32_t CSELR; /*!< Channel selection register, Address offset: 0xA8 */ }DMA_TypeDef; /** * @brief External Interrupt/Event Controller */ typedef struct { __IO uint32_t IMR; /*! exti[31] Interrupt */ #define SYSCFG_ITLINE1_SR_VDDIO2 ((uint32_t)0x00000002) /*!< VDDIO2 -> exti[16] Interrupt */ #define SYSCFG_ITLINE2_SR_RTC_WAKEUP ((uint32_t)0x00000001) /*!< RTC WAKEUP -> exti[20] Interrupt */ #define SYSCFG_ITLINE2_SR_RTC_TSTAMP ((uint32_t)0x00000002) /*!< RTC Time Stamp -> exti[19] interrupt */ #define SYSCFG_ITLINE2_SR_RTC_ALRA ((uint32_t)0x00000003) /*!< RTC Alarm -> exti[17] interrupt .... */ #define SYSCFG_ITLINE3_SR_FLASH_ITF ((uint32_t)0x00000001) /*!< Flash ITF Interrupt */ #define SYSCFG_ITLINE4_SR_CRS ((uint32_t)0x00000001) /*!< CRS interrupt */ #define SYSCFG_ITLINE4_SR_CLK_CTRL ((uint32_t)0x00000002) /*!< CLK CTRL interrupt */ #define SYSCFG_ITLINE5_SR_EXTI0 ((uint32_t)0x00000001) /*!< External Interrupt 0 */ #define SYSCFG_ITLINE5_SR_EXTI1 ((uint32_t)0x00000002) /*!< External Interrupt 1 */ #define SYSCFG_ITLINE6_SR_EXTI2 ((uint32_t)0x00000001) /*!< External Interrupt 2 */ #define SYSCFG_ITLINE6_SR_EXTI3 ((uint32_t)0x00000002) /*!< External Interrupt 3 */ #define SYSCFG_ITLINE7_SR_EXTI4 ((uint32_t)0x00000001) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI5 ((uint32_t)0x00000002) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI6 ((uint32_t)0x00000004) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI7 ((uint32_t)0x00000008) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI8 ((uint32_t)0x00000010) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI9 ((uint32_t)0x00000020) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI10 ((uint32_t)0x00000040) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI11 ((uint32_t)0x00000080) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI12 ((uint32_t)0x00000100) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI13 ((uint32_t)0x00000200) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI14 ((uint32_t)0x00000400) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE7_SR_EXTI15 ((uint32_t)0x00000800) /*!< External Interrupt 15 to 4 */ #define SYSCFG_ITLINE8_SR_TSC_EOA ((uint32_t)0x00000001) /*!< Touch control EOA Interrupt */ #define SYSCFG_ITLINE8_SR_TSC_MCE ((uint32_t)0x00000002) /*!< Touch control MCE Interrupt */ #define SYSCFG_ITLINE9_SR_DMA1_CH1 ((uint32_t)0x00000001) /*!< DMA1 Channel 1 Interrupt */ #define SYSCFG_ITLINE10_SR_DMA1_CH2 ((uint32_t)0x00000001) /*!< DMA1 Channel 2 Interrupt */ #define SYSCFG_ITLINE10_SR_DMA1_CH3 ((uint32_t)0x00000002) /*!< DMA2 Channel 3 Interrupt */ #define SYSCFG_ITLINE10_SR_DMA2_CH1 ((uint32_t)0x00000004) /*!< DMA2 Channel 1 Interrupt */ #define SYSCFG_ITLINE10_SR_DMA2_CH2 ((uint32_t)0x00000008) /*!< DMA2 Channel 2 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH4 ((uint32_t)0x00000001) /*!< DMA1 Channel 4 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH5 ((uint32_t)0x00000002) /*!< DMA1 Channel 5 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH6 ((uint32_t)0x00000004) /*!< DMA1 Channel 6 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA1_CH7 ((uint32_t)0x00000008) /*!< DMA1 Channel 7 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA2_CH3 ((uint32_t)0x00000010) /*!< DMA2 Channel 3 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA2_CH4 ((uint32_t)0x00000020) /*!< DMA2 Channel 4 Interrupt */ #define SYSCFG_ITLINE11_SR_DMA2_CH5 ((uint32_t)0x00000040) /*!< DMA2 Channel 5 Interrupt */ #define SYSCFG_ITLINE12_SR_ADC ((uint32_t)0x00000001) /*!< ADC Interrupt */ #define SYSCFG_ITLINE12_SR_COMP1 ((uint32_t)0x00000002) /*!< COMP1 Interrupt -> exti[21] */ #define SYSCFG_ITLINE12_SR_COMP2 ((uint32_t)0x00000004) /*!< COMP2 Interrupt -> exti[22] */ #define SYSCFG_ITLINE13_SR_TIM1_BRK ((uint32_t)0x00000001) /*!< TIM1 BRK Interrupt */ #define SYSCFG_ITLINE13_SR_TIM1_UPD ((uint32_t)0x00000002) /*!< TIM1 UPD Interrupt */ #define SYSCFG_ITLINE13_SR_TIM1_TRG ((uint32_t)0x00000004) /*!< TIM1 TRG Interrupt */ #define SYSCFG_ITLINE13_SR_TIM1_CCU ((uint32_t)0x00000008) /*!< TIM1 CCU Interrupt */ #define SYSCFG_ITLINE14_SR_TIM1_CC ((uint32_t)0x00000001) /*!< TIM1 CC Interrupt */ #define SYSCFG_ITLINE15_SR_TIM2_GLB ((uint32_t)0x00000001) /*!< TIM2 GLB Interrupt */ #define SYSCFG_ITLINE16_SR_TIM3_GLB ((uint32_t)0x00000001) /*!< TIM3 GLB Interrupt */ #define SYSCFG_ITLINE17_SR_DAC ((uint32_t)0x00000001) /*!< DAC Interrupt */ #define SYSCFG_ITLINE17_SR_TIM6_GLB ((uint32_t)0x00000002) /*!< TIM6 GLB Interrupt */ #define SYSCFG_ITLINE18_SR_TIM7_GLB ((uint32_t)0x00000001) /*!< TIM7 GLB Interrupt */ #define SYSCFG_ITLINE19_SR_TIM14_GLB ((uint32_t)0x00000001) /*!< TIM14 GLB Interrupt */ #define SYSCFG_ITLINE20_SR_TIM15_GLB ((uint32_t)0x00000001) /*!< TIM15 GLB Interrupt */ #define SYSCFG_ITLINE21_SR_TIM16_GLB ((uint32_t)0x00000001) /*!< TIM16 GLB Interrupt */ #define SYSCFG_ITLINE22_SR_TIM17_GLB ((uint32_t)0x00000001) /*!< TIM17 GLB Interrupt */ #define SYSCFG_ITLINE23_SR_I2C1_GLB ((uint32_t)0x00000001) /*!< I2C1 GLB Interrupt -> exti[23] */ #define SYSCFG_ITLINE24_SR_I2C2_GLB ((uint32_t)0x00000001) /*!< I2C2 GLB Interrupt */ #define SYSCFG_ITLINE25_SR_SPI1 ((uint32_t)0x00000001) /*!< SPI1 Interrupt */ #define SYSCFG_ITLINE26_SR_SPI2 ((uint32_t)0x00000001) /*!< SPI2 Interrupt */ #define SYSCFG_ITLINE27_SR_USART1_GLB ((uint32_t)0x00000001) /*!< USART1 GLB Interrupt -> exti[25] */ #define SYSCFG_ITLINE28_SR_USART2_GLB ((uint32_t)0x00000001) /*!< USART2 GLB Interrupt -> exti[26] */ #define SYSCFG_ITLINE29_SR_USART3_GLB ((uint32_t)0x00000001) /*!< USART3 GLB Interrupt -> exti[28] */ #define SYSCFG_ITLINE29_SR_USART4_GLB ((uint32_t)0x00000002) /*!< USART4 GLB Interrupt */ #define SYSCFG_ITLINE29_SR_USART5_GLB ((uint32_t)0x00000004) /*!< USART5 GLB Interrupt */ #define SYSCFG_ITLINE29_SR_USART6_GLB ((uint32_t)0x00000008) /*!< USART6 GLB Interrupt */ #define SYSCFG_ITLINE29_SR_USART7_GLB ((uint32_t)0x00000010) /*!< USART7 GLB Interrupt */ #define SYSCFG_ITLINE29_SR_USART8_GLB ((uint32_t)0x00000020) /*!< USART8 GLB Interrupt */ #define SYSCFG_ITLINE30_SR_CAN ((uint32_t)0x00000001) /*!< CAN Interrupt */ #define SYSCFG_ITLINE30_SR_CEC ((uint32_t)0x00000002) /*!< CEC Interrupt */ /*****************************************************************************/ /* */ /* Timers (TIM) */ /* */ /*****************************************************************************/ /******************* Bit definition for TIM_CR1 register *******************/ #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!