/*---------------------------------------------------------------------------- * RL-ARM - RTX *---------------------------------------------------------------------------- * Name: RTX_Conf_CM.C * Purpose: Configuration of CMSIS RTX Kernel * Rev.: V4.60 *---------------------------------------------------------------------------- * * Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH * All rights reserved. * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * - Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * - Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. * - Neither the name of ARM nor the names of its contributors may be used * to endorse or promote products derived from this software without * specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. *---------------------------------------------------------------------------*/ #include "cmsis_os.h" /*---------------------------------------------------------------------------- * RTX User configuration part BEGIN *---------------------------------------------------------------------------*/ //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- // // Thread Configuration // ======================= // // Number of concurrent running threads <0-250> // Defines max. number of threads that will run at the same time. // Default: 6 #ifndef OS_TASKCNT #define OS_TASKCNT 25 #endif // Default Thread stack size [bytes] <64-4096:8><#/4> // Defines default stack size for threads with osThreadDef stacksz = 0 // Default: 200 #ifndef OS_STKSIZE #define OS_STKSIZE 200 #endif // Main Thread stack size [bytes] <64-4096:8><#/4> // Defines stack size for main thread. // Default: 200 #ifndef OS_MAINSTKSIZE #define OS_MAINSTKSIZE 2048 #endif // Number of threads with user-provided stack size <0-250> // Defines the number of threads with user-provided stack size. // Default: 0 #ifndef OS_PRIVCNT #define OS_PRIVCNT 10 #endif // Total stack size [bytes] for threads with user-provided stack size <0-4096:8><#/4> // Defines the combined stack size for threads with user-provided stack size. // Default: 0 #ifndef OS_PRIVSTKSIZE #define OS_PRIVSTKSIZE 8192 #endif // Check for stack overflow // Includes the stack checking code for stack overflow. // Note that additional code reduces the Kernel performance. #ifndef OS_STKCHECK #define OS_STKCHECK 1 #endif // Processor mode for thread execution // <0=> Unprivileged mode // <1=> Privileged mode // Default: Privileged mode #ifndef OS_RUNPRIV #define OS_RUNPRIV 1 #endif // // RTX Kernel Timer Tick Configuration // ====================================== // Use Cortex-M SysTick timer as RTX Kernel Timer // Use the Cortex-M SysTick timer as a time-base for RTX. #ifndef OS_SYSTICK #define OS_SYSTICK 0 #endif // // Timer clock value [Hz] <1-1000000000> // Defines the timer clock value. // Default: 12000000 (12MHz) #ifndef OS_CLOCK # if defined(TARGET_RZ_A1H) #define OS_CLOCK 12000000 # else # error "no target defined" # endif #endif // Timer tick value [us] <1-1000000> // Defines the timer tick value. // Default: 1000 (1ms) #ifndef OS_TICK #define OS_TICK 1000 #endif // // System Configuration // ======================= // // Round-Robin Thread switching // =============================== // // Enables Round-Robin Thread switching. #ifndef OS_ROBIN #define OS_ROBIN 1 #endif // Round-Robin Timeout [ticks] <1-1000> // Defines how long a thread will execute before a thread switch. // Default: 5 #ifndef OS_ROBINTOUT #define OS_ROBINTOUT 5 #endif // // User Timers // ============== // Enables user Timers #ifndef OS_TIMERS #define OS_TIMERS 1 #endif // Timer Thread Priority // <1=> Low // <2=> Below Normal <3=> Normal <4=> Above Normal // <5=> High // <6=> Realtime (highest) // Defines priority for Timer Thread // Default: High #ifndef OS_TIMERPRIO #define OS_TIMERPRIO 5 #endif // Timer Thread stack size [bytes] <64-4096:8><#/4> // Defines stack size for Timer thread. // Default: 200 #ifndef OS_TIMERSTKSZ #define OS_TIMERSTKSZ WORDS_STACK_SIZE #endif // Timer Callback Queue size <1-32> // Number of concurrent active timer callback functions. // Default: 4 #ifndef OS_TIMERCBQS #define OS_TIMERCBQS 4 #endif // // ISR FIFO Queue size<4=> 4 entries <8=> 8 entries // <12=> 12 entries <16=> 16 entries // <24=> 24 entries <32=> 32 entries // <48=> 48 entries <64=> 64 entries // <96=> 96 entries // ISR functions store requests to this buffer, // when they are called from the interrupt handler. // Default: 16 entries #ifndef OS_FIFOSZ #define OS_FIFOSZ 16 #endif // //------------- <<< end of configuration section >>> ----------------------- // Standard library system mutexes // =============================== // Define max. number system mutexes that are used to protect // the arm standard runtime library. For microlib they are not used. #ifndef OS_MUTEXCNT #define OS_MUTEXCNT 12 #endif /*---------------------------------------------------------------------------- * RTX User configuration part END *---------------------------------------------------------------------------*/ #define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1) /*---------------------------------------------------------------------------- * Global Functions *---------------------------------------------------------------------------*/ /*--------------------------- os_idle_demon ---------------------------------*/ void os_idle_demon (void) { /* The idle demon is a system thread, running when no other thread is */ /* ready to run. */ for (;;) { /* HERE: include optional user code to be executed when no thread runs.*/ } } #if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer /*--------------------------- os_tick_init ----------------------------------*/ #ifdef TARGET_RZ_A1H #define OSTM0 (0xFCFEC000uL) /* OSTM0 */ #define OSTM1 (0xFCFEC400uL) /* OSTM1 */ #define CPG (0xFCFE0410uL) /* CPG */ #define CPGSTBCR5 (*((volatile unsigned char*)(CPG + 0x00000018uL))) #define OSTM0CMP (*((volatile unsigned long*)(OSTM0 + 0x00000000uL))) #define OSTM0CNT (*((volatile unsigned long*)(OSTM0 + 0x00000004uL))) #define OSTM0TE (*((volatile unsigned char*)(OSTM0 + 0x00000010uL))) #define OSTM0TS (*((volatile unsigned char*)(OSTM0 + 0x00000014uL))) #define OSTM0TT (*((volatile unsigned char*)(OSTM0 + 0x00000018uL))) #define OSTM0CTL (*((volatile unsigned char*)(OSTM0 + 0x00000020uL))) #define OSTM1CMP (*((volatile unsigned long*)(OSTM1 + 0x00000000uL))) #define OSTM1CNT (*((volatile unsigned long*)(OSTM1 + 0x00000004uL))) #define OSTM1TE (*((volatile unsigned char*)(OSTM1 + 0x00000010uL))) #define OSTM1TS (*((volatile unsigned char*)(OSTM1 + 0x00000014uL))) #define OSTM1TT (*((volatile unsigned char*)(OSTM1 + 0x00000018uL))) #define OSTM1CTL (*((volatile unsigned char*)(OSTM1 + 0x00000020uL))) #define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */ #define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u) #define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u) typedef enum { IRQ_SGI0 = 0, IRQ_OSTMI0TINT = 134 } IRQn_Type; typedef void(*IRQHandler)(); extern void PendSV_Handler(uint32_t); extern void OS_Tick_Handler(uint32_t); extern uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler); #endif // Initialize alternative hardware timer as RTX kernel timer // Return: IRQ number of the alternative hardware timer int os_tick_init (void) { #ifdef TARGET_RZ_A1H CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP51); /* enable OSTM0 clock */ OSTM0TT = 0x1; /* Stop the counter and clears the OSTM0TE bit. */ OSTM0CTL = 0x1; /* Interval timer mode. Interrupt enabled */ OSTM0CMP = (uint32_t)(((double)CM0_RENESAS_RZ_A1_P0_CLK*(double)OS_TICK)/1E6); OSTM0TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */ InterruptHandlerRegister(IRQ_SGI0 , (IRQHandler)PendSV_Handler); InterruptHandlerRegister(IRQ_OSTMI0TINT, (IRQHandler)OS_Tick_Handler); return IRQ_OSTMI0TINT; /* Return IRQ number of timer (0..239) */ /* RTX will set and configure the interrupt */ #endif } /*--------------------------- os_tick_irqack --------------------------------*/ // Acknowledge alternative hardware timer interrupt void os_tick_irqack (void) { /* ... */ } #endif // (OS_SYSTICK == 0) /*--------------------------- os_error --------------------------------------*/ extern void mbed_die(void); void os_error (uint32_t err_code) { /* This function is called when a runtime error is detected. Parameter */ /* 'err_code' holds the runtime error code (defined in RTL.H). */ mbed_die(); /* HERE: include optional code to be executed on runtime error. */ for (;;); } /*---------------------------------------------------------------------------- * RTX Configuration Functions *---------------------------------------------------------------------------*/ #include "RTX_CM_lib.h" /*---------------------------------------------------------------------------- * end of file *---------------------------------------------------------------------------*/