/* ** ################################################################### ** Processors: MK64FN1M0VDC12 ** MK64FN1M0VLL12 ** MK64FN1M0VLQ12 ** MK64FN1M0VMD12 ** ** Compilers: Keil ARM C/C++ Compiler ** Freescale C/C++ for Embedded ARM ** GNU C Compiler ** GNU C Compiler - CodeSourcery Sourcery G++ ** IAR ANSI C/C++ Compiler for ARM ** ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 ** Version: rev. 2.5, 2014-02-10 ** Build: b140604 ** ** Abstract: ** CMSIS Peripheral Access Layer for MK64F12 ** ** Copyright (c) 1997 - 2014 Freescale Semiconductor, Inc. ** All rights reserved. ** ** Redistribution and use in source and binary forms, with or without modification, ** are permitted provided that the following conditions are met: ** ** o Redistributions of source code must retain the above copyright notice, this list ** of conditions and the following disclaimer. ** ** o Redistributions in binary form must reproduce the above copyright notice, this ** list of conditions and the following disclaimer in the documentation and/or ** other materials provided with the distribution. ** ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its ** contributors may be used to endorse or promote products derived from this ** software without specific prior written permission. ** ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ** ** http: www.freescale.com ** mail: support@freescale.com ** ** Revisions: ** - rev. 1.0 (2013-08-12) ** Initial version. ** - rev. 2.0 (2013-10-29) ** Register accessor macros added to the memory map. ** Symbols for Processor Expert memory map compatibility added to the memory map. ** Startup file for gcc has been updated according to CMSIS 3.2. ** System initialization updated. ** MCG - registers updated. ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. ** - rev. 2.1 (2013-10-30) ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. ** - rev. 2.2 (2013-12-09) ** DMA - EARS register removed. ** AIPS0, AIPS1 - MPRA register updated. ** - rev. 2.3 (2014-01-24) ** Update according to reference manual rev. 2 ** ENET, MCG, MCM, SIM, USB - registers updated ** - rev. 2.4 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** - rev. 2.5 (2014-02-10) ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h ** Update of SystemInit() and SystemCoreClockUpdate() functions. ** Module access macro module_BASES replaced by module_BASE_PTRS. ** ** ################################################################### */ /*! * @file MK64F12.h * @version 2.5 * @date 2014-02-10 * @brief CMSIS Peripheral Access Layer for MK64F12 * * CMSIS Peripheral Access Layer for MK64F12 */ /* ---------------------------------------------------------------------------- -- MCU activation ---------------------------------------------------------------------------- */ /* Prevention from multiple including the same memory map */ #if !defined(MK64F12_H_) /* Check if memory map has not been already included */ #define MK64F12_H_ #define MCU_MK64F12 /* Check if another memory map has not been also included */ #if (defined(MCU_ACTIVE)) #error MK64F12 memory map: There is already included another memory map. Only one memory map can be included. #endif /* (defined(MCU_ACTIVE)) */ #define MCU_ACTIVE #include /** Memory map major version (memory maps with equal major version number are * compatible) */ #define MCU_MEM_MAP_VERSION 0x0200u /** Memory map minor version */ #define MCU_MEM_MAP_VERSION_MINOR 0x0005u /** * @brief Macro to calculate address of an aliased word in the peripheral * bitband area for a peripheral register and bit (bit band region 0x40000000 to * 0x400FFFFF). * @param Reg Register to access. * @param Bit Bit number to access. * @return Address of the aliased word in the peripheral bitband area. */ #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit)))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 32bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) #define BITBAND_REG(Reg,Bit) (BITBAND_REG32(Reg,Bit)) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 16bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) /** * @brief Macro to access a single bit of a peripheral register (bit band region * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can * be used for peripherals with 8bit access allowed. * @param Reg Register to access. * @param Bit Bit number to access. * @return Value of the targeted bit in the bit band region. */ #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR(Reg,Bit)))) /* ---------------------------------------------------------------------------- -- Interrupt vector numbers ---------------------------------------------------------------------------- */ /*! * @addtogroup Interrupt_vector_numbers Interrupt vector numbers * @{ */ /** Interrupt Number Definitions */ #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */ typedef enum IRQn { /* Core interrupts */ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ /* Device specific interrupts */ DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */ DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */ DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */ DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */ DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */ DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */ DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */ DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */ DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */ DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */ DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */ DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */ DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */ DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */ DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */ DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */ DMA_Error_IRQn = 16, /**< DMA Error Interrupt */ MCM_IRQn = 17, /**< Normal Interrupt */ FTFE_IRQn = 18, /**< FTFE Command complete interrupt */ Read_Collision_IRQn = 19, /**< Read Collision Interrupt */ LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */ LLW_IRQn = 21, /**< Low Leakage Wakeup */ Watchdog_IRQn = 22, /**< WDOG Interrupt */ RNG_IRQn = 23, /**< RNG Interrupt */ I2C0_IRQn = 24, /**< I2C0 interrupt */ I2C1_IRQn = 25, /**< I2C1 interrupt */ SPI0_IRQn = 26, /**< SPI0 Interrupt */ SPI1_IRQn = 27, /**< SPI1 Interrupt */ I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */ I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */ UART0_LON_IRQn = 30, /**< UART0 LON interrupt */ UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */ UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */ UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */ UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */ UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */ UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */ UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */ UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */ ADC0_IRQn = 39, /**< ADC0 interrupt */ CMP0_IRQn = 40, /**< CMP0 interrupt */ CMP1_IRQn = 41, /**< CMP1 interrupt */ FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */ FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */ FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */ CMT_IRQn = 45, /**< CMT interrupt */ RTC_IRQn = 46, /**< RTC interrupt */ RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */ PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */ PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */ PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */ PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */ PDB0_IRQn = 52, /**< PDB0 Interrupt */ USB0_IRQn = 53, /**< USB0 interrupt */ USBDCD_IRQn = 54, /**< USBDCD Interrupt */ Reserved71_IRQn = 55, /**< Reserved interrupt 71 */ DAC0_IRQn = 56, /**< DAC0 interrupt */ MCG_IRQn = 57, /**< MCG Interrupt */ LPTimer_IRQn = 58, /**< LPTimer interrupt */ PORTA_IRQn = 59, /**< Port A interrupt */ PORTB_IRQn = 60, /**< Port B interrupt */ PORTC_IRQn = 61, /**< Port C interrupt */ PORTD_IRQn = 62, /**< Port D interrupt */ PORTE_IRQn = 63, /**< Port E interrupt */ SWI_IRQn = 64, /**< Software interrupt */ SPI2_IRQn = 65, /**< SPI2 Interrupt */ UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */ UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */ UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */ UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */ CMP2_IRQn = 70, /**< CMP2 interrupt */ FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */ DAC1_IRQn = 72, /**< DAC1 interrupt */ ADC1_IRQn = 73, /**< ADC1 interrupt */ I2C2_IRQn = 74, /**< I2C2 interrupt */ CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */ CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */ CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */ CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */ CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */ CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */ SDHC_IRQn = 81, /**< SDHC interrupt */ ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */ ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */ ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */ ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */ } IRQn_Type; /*! * @} */ /* end of group Interrupt_vector_numbers */ /* ---------------------------------------------------------------------------- -- Cortex M4 Core Configuration ---------------------------------------------------------------------------- */ /*! * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration * @{ */ #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ #include "core_cm4.h" /* Core Peripheral Access Layer */ #include "system_MK64F12.h" /* Device specific configuration file */ /*! * @} */ /* end of group Cortex_Core_Configuration */ /* ---------------------------------------------------------------------------- -- Device Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup Peripheral_access_layer Device Peripheral Access Layer * @{ */ /* ** Start of section using anonymous unions */ #if defined(__ARMCC_VERSION) #pragma push #pragma anon_unions #elif defined(__CWCC__) #pragma push #pragma cpp_extensions on #elif defined(__GNUC__) /* anonymous unions are enabled by default */ #elif defined(__IAR_SYSTEMS_ICC__) #pragma language=extended #else #error Not supported compiler type #endif /* ---------------------------------------------------------------------------- -- ADC Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer * @{ */ /** ADC - Register Layout Typedef */ typedef struct { __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ uint8_t RESERVED_0[4]; __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ } ADC_Type, *ADC_MemMapPtr; /* ---------------------------------------------------------------------------- -- ADC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros * @{ */ /* ADC - Register accessors */ #define ADC_SC1_REG(base,index) ((base)->SC1[index]) #define ADC_CFG1_REG(base) ((base)->CFG1) #define ADC_CFG2_REG(base) ((base)->CFG2) #define ADC_R_REG(base,index) ((base)->R[index]) #define ADC_CV1_REG(base) ((base)->CV1) #define ADC_CV2_REG(base) ((base)->CV2) #define ADC_SC2_REG(base) ((base)->SC2) #define ADC_SC3_REG(base) ((base)->SC3) #define ADC_OFS_REG(base) ((base)->OFS) #define ADC_PG_REG(base) ((base)->PG) #define ADC_MG_REG(base) ((base)->MG) #define ADC_CLPD_REG(base) ((base)->CLPD) #define ADC_CLPS_REG(base) ((base)->CLPS) #define ADC_CLP4_REG(base) ((base)->CLP4) #define ADC_CLP3_REG(base) ((base)->CLP3) #define ADC_CLP2_REG(base) ((base)->CLP2) #define ADC_CLP1_REG(base) ((base)->CLP1) #define ADC_CLP0_REG(base) ((base)->CLP0) #define ADC_CLMD_REG(base) ((base)->CLMD) #define ADC_CLMS_REG(base) ((base)->CLMS) #define ADC_CLM4_REG(base) ((base)->CLM4) #define ADC_CLM3_REG(base) ((base)->CLM3) #define ADC_CLM2_REG(base) ((base)->CLM2) #define ADC_CLM1_REG(base) ((base)->CLM1) #define ADC_CLM0_REG(base) ((base)->CLM0) /*! * @} */ /* end of group ADC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ADC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ADC_Register_Masks ADC Register Masks * @{ */ /* SC1 Bit Fields */ #define ADC_SC1_ADCH_MASK 0x1Fu #define ADC_SC1_ADCH_SHIFT 0 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<MPRA) #define AIPS_PACRA_REG(base) ((base)->PACRA) #define AIPS_PACRB_REG(base) ((base)->PACRB) #define AIPS_PACRC_REG(base) ((base)->PACRC) #define AIPS_PACRD_REG(base) ((base)->PACRD) #define AIPS_PACRE_REG(base) ((base)->PACRE) #define AIPS_PACRF_REG(base) ((base)->PACRF) #define AIPS_PACRG_REG(base) ((base)->PACRG) #define AIPS_PACRH_REG(base) ((base)->PACRH) #define AIPS_PACRI_REG(base) ((base)->PACRI) #define AIPS_PACRJ_REG(base) ((base)->PACRJ) #define AIPS_PACRK_REG(base) ((base)->PACRK) #define AIPS_PACRL_REG(base) ((base)->PACRL) #define AIPS_PACRM_REG(base) ((base)->PACRM) #define AIPS_PACRN_REG(base) ((base)->PACRN) #define AIPS_PACRO_REG(base) ((base)->PACRO) #define AIPS_PACRP_REG(base) ((base)->PACRP) #define AIPS_PACRU_REG(base) ((base)->PACRU) /*! * @} */ /* end of group AIPS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AIPS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPS_Register_Masks AIPS Register Masks * @{ */ /* MPRA Bit Fields */ #define AIPS_MPRA_MPL5_MASK 0x100u #define AIPS_MPRA_MPL5_SHIFT 8 #define AIPS_MPRA_MTW5_MASK 0x200u #define AIPS_MPRA_MTW5_SHIFT 9 #define AIPS_MPRA_MTR5_MASK 0x400u #define AIPS_MPRA_MTR5_SHIFT 10 #define AIPS_MPRA_MPL4_MASK 0x1000u #define AIPS_MPRA_MPL4_SHIFT 12 #define AIPS_MPRA_MTW4_MASK 0x2000u #define AIPS_MPRA_MTW4_SHIFT 13 #define AIPS_MPRA_MTR4_MASK 0x4000u #define AIPS_MPRA_MTR4_SHIFT 14 #define AIPS_MPRA_MPL3_MASK 0x10000u #define AIPS_MPRA_MPL3_SHIFT 16 #define AIPS_MPRA_MTW3_MASK 0x20000u #define AIPS_MPRA_MTW3_SHIFT 17 #define AIPS_MPRA_MTR3_MASK 0x40000u #define AIPS_MPRA_MTR3_SHIFT 18 #define AIPS_MPRA_MPL2_MASK 0x100000u #define AIPS_MPRA_MPL2_SHIFT 20 #define AIPS_MPRA_MTW2_MASK 0x200000u #define AIPS_MPRA_MTW2_SHIFT 21 #define AIPS_MPRA_MTR2_MASK 0x400000u #define AIPS_MPRA_MTR2_SHIFT 22 #define AIPS_MPRA_MPL1_MASK 0x1000000u #define AIPS_MPRA_MPL1_SHIFT 24 #define AIPS_MPRA_MTW1_MASK 0x2000000u #define AIPS_MPRA_MTW1_SHIFT 25 #define AIPS_MPRA_MTR1_MASK 0x4000000u #define AIPS_MPRA_MTR1_SHIFT 26 #define AIPS_MPRA_MPL0_MASK 0x10000000u #define AIPS_MPRA_MPL0_SHIFT 28 #define AIPS_MPRA_MTW0_MASK 0x20000000u #define AIPS_MPRA_MTW0_SHIFT 29 #define AIPS_MPRA_MTR0_MASK 0x40000000u #define AIPS_MPRA_MTR0_SHIFT 30 /* PACRA Bit Fields */ #define AIPS_PACRA_TP7_MASK 0x1u #define AIPS_PACRA_TP7_SHIFT 0 #define AIPS_PACRA_WP7_MASK 0x2u #define AIPS_PACRA_WP7_SHIFT 1 #define AIPS_PACRA_SP7_MASK 0x4u #define AIPS_PACRA_SP7_SHIFT 2 #define AIPS_PACRA_TP6_MASK 0x10u #define AIPS_PACRA_TP6_SHIFT 4 #define AIPS_PACRA_WP6_MASK 0x20u #define AIPS_PACRA_WP6_SHIFT 5 #define AIPS_PACRA_SP6_MASK 0x40u #define AIPS_PACRA_SP6_SHIFT 6 #define AIPS_PACRA_TP5_MASK 0x100u #define AIPS_PACRA_TP5_SHIFT 8 #define AIPS_PACRA_WP5_MASK 0x200u #define AIPS_PACRA_WP5_SHIFT 9 #define AIPS_PACRA_SP5_MASK 0x400u #define AIPS_PACRA_SP5_SHIFT 10 #define AIPS_PACRA_TP4_MASK 0x1000u #define AIPS_PACRA_TP4_SHIFT 12 #define AIPS_PACRA_WP4_MASK 0x2000u #define AIPS_PACRA_WP4_SHIFT 13 #define AIPS_PACRA_SP4_MASK 0x4000u #define AIPS_PACRA_SP4_SHIFT 14 #define AIPS_PACRA_TP3_MASK 0x10000u #define AIPS_PACRA_TP3_SHIFT 16 #define AIPS_PACRA_WP3_MASK 0x20000u #define AIPS_PACRA_WP3_SHIFT 17 #define AIPS_PACRA_SP3_MASK 0x40000u #define AIPS_PACRA_SP3_SHIFT 18 #define AIPS_PACRA_TP2_MASK 0x100000u #define AIPS_PACRA_TP2_SHIFT 20 #define AIPS_PACRA_WP2_MASK 0x200000u #define AIPS_PACRA_WP2_SHIFT 21 #define AIPS_PACRA_SP2_MASK 0x400000u #define AIPS_PACRA_SP2_SHIFT 22 #define AIPS_PACRA_TP1_MASK 0x1000000u #define AIPS_PACRA_TP1_SHIFT 24 #define AIPS_PACRA_WP1_MASK 0x2000000u #define AIPS_PACRA_WP1_SHIFT 25 #define AIPS_PACRA_SP1_MASK 0x4000000u #define AIPS_PACRA_SP1_SHIFT 26 #define AIPS_PACRA_TP0_MASK 0x10000000u #define AIPS_PACRA_TP0_SHIFT 28 #define AIPS_PACRA_WP0_MASK 0x20000000u #define AIPS_PACRA_WP0_SHIFT 29 #define AIPS_PACRA_SP0_MASK 0x40000000u #define AIPS_PACRA_SP0_SHIFT 30 /* PACRB Bit Fields */ #define AIPS_PACRB_TP7_MASK 0x1u #define AIPS_PACRB_TP7_SHIFT 0 #define AIPS_PACRB_WP7_MASK 0x2u #define AIPS_PACRB_WP7_SHIFT 1 #define AIPS_PACRB_SP7_MASK 0x4u #define AIPS_PACRB_SP7_SHIFT 2 #define AIPS_PACRB_TP6_MASK 0x10u #define AIPS_PACRB_TP6_SHIFT 4 #define AIPS_PACRB_WP6_MASK 0x20u #define AIPS_PACRB_WP6_SHIFT 5 #define AIPS_PACRB_SP6_MASK 0x40u #define AIPS_PACRB_SP6_SHIFT 6 #define AIPS_PACRB_TP5_MASK 0x100u #define AIPS_PACRB_TP5_SHIFT 8 #define AIPS_PACRB_WP5_MASK 0x200u #define AIPS_PACRB_WP5_SHIFT 9 #define AIPS_PACRB_SP5_MASK 0x400u #define AIPS_PACRB_SP5_SHIFT 10 #define AIPS_PACRB_TP4_MASK 0x1000u #define AIPS_PACRB_TP4_SHIFT 12 #define AIPS_PACRB_WP4_MASK 0x2000u #define AIPS_PACRB_WP4_SHIFT 13 #define AIPS_PACRB_SP4_MASK 0x4000u #define AIPS_PACRB_SP4_SHIFT 14 #define AIPS_PACRB_TP3_MASK 0x10000u #define AIPS_PACRB_TP3_SHIFT 16 #define AIPS_PACRB_WP3_MASK 0x20000u #define AIPS_PACRB_WP3_SHIFT 17 #define AIPS_PACRB_SP3_MASK 0x40000u #define AIPS_PACRB_SP3_SHIFT 18 #define AIPS_PACRB_TP2_MASK 0x100000u #define AIPS_PACRB_TP2_SHIFT 20 #define AIPS_PACRB_WP2_MASK 0x200000u #define AIPS_PACRB_WP2_SHIFT 21 #define AIPS_PACRB_SP2_MASK 0x400000u #define AIPS_PACRB_SP2_SHIFT 22 #define AIPS_PACRB_TP1_MASK 0x1000000u #define AIPS_PACRB_TP1_SHIFT 24 #define AIPS_PACRB_WP1_MASK 0x2000000u #define AIPS_PACRB_WP1_SHIFT 25 #define AIPS_PACRB_SP1_MASK 0x4000000u #define AIPS_PACRB_SP1_SHIFT 26 #define AIPS_PACRB_TP0_MASK 0x10000000u #define AIPS_PACRB_TP0_SHIFT 28 #define AIPS_PACRB_WP0_MASK 0x20000000u #define AIPS_PACRB_WP0_SHIFT 29 #define AIPS_PACRB_SP0_MASK 0x40000000u #define AIPS_PACRB_SP0_SHIFT 30 /* PACRC Bit Fields */ #define AIPS_PACRC_TP7_MASK 0x1u #define AIPS_PACRC_TP7_SHIFT 0 #define AIPS_PACRC_WP7_MASK 0x2u #define AIPS_PACRC_WP7_SHIFT 1 #define AIPS_PACRC_SP7_MASK 0x4u #define AIPS_PACRC_SP7_SHIFT 2 #define AIPS_PACRC_TP6_MASK 0x10u #define AIPS_PACRC_TP6_SHIFT 4 #define AIPS_PACRC_WP6_MASK 0x20u #define AIPS_PACRC_WP6_SHIFT 5 #define AIPS_PACRC_SP6_MASK 0x40u #define AIPS_PACRC_SP6_SHIFT 6 #define AIPS_PACRC_TP5_MASK 0x100u #define AIPS_PACRC_TP5_SHIFT 8 #define AIPS_PACRC_WP5_MASK 0x200u #define AIPS_PACRC_WP5_SHIFT 9 #define AIPS_PACRC_SP5_MASK 0x400u #define AIPS_PACRC_SP5_SHIFT 10 #define AIPS_PACRC_TP4_MASK 0x1000u #define AIPS_PACRC_TP4_SHIFT 12 #define AIPS_PACRC_WP4_MASK 0x2000u #define AIPS_PACRC_WP4_SHIFT 13 #define AIPS_PACRC_SP4_MASK 0x4000u #define AIPS_PACRC_SP4_SHIFT 14 #define AIPS_PACRC_TP3_MASK 0x10000u #define AIPS_PACRC_TP3_SHIFT 16 #define AIPS_PACRC_WP3_MASK 0x20000u #define AIPS_PACRC_WP3_SHIFT 17 #define AIPS_PACRC_SP3_MASK 0x40000u #define AIPS_PACRC_SP3_SHIFT 18 #define AIPS_PACRC_TP2_MASK 0x100000u #define AIPS_PACRC_TP2_SHIFT 20 #define AIPS_PACRC_WP2_MASK 0x200000u #define AIPS_PACRC_WP2_SHIFT 21 #define AIPS_PACRC_SP2_MASK 0x400000u #define AIPS_PACRC_SP2_SHIFT 22 #define AIPS_PACRC_TP1_MASK 0x1000000u #define AIPS_PACRC_TP1_SHIFT 24 #define AIPS_PACRC_WP1_MASK 0x2000000u #define AIPS_PACRC_WP1_SHIFT 25 #define AIPS_PACRC_SP1_MASK 0x4000000u #define AIPS_PACRC_SP1_SHIFT 26 #define AIPS_PACRC_TP0_MASK 0x10000000u #define AIPS_PACRC_TP0_SHIFT 28 #define AIPS_PACRC_WP0_MASK 0x20000000u #define AIPS_PACRC_WP0_SHIFT 29 #define AIPS_PACRC_SP0_MASK 0x40000000u #define AIPS_PACRC_SP0_SHIFT 30 /* PACRD Bit Fields */ #define AIPS_PACRD_TP7_MASK 0x1u #define AIPS_PACRD_TP7_SHIFT 0 #define AIPS_PACRD_WP7_MASK 0x2u #define AIPS_PACRD_WP7_SHIFT 1 #define AIPS_PACRD_SP7_MASK 0x4u #define AIPS_PACRD_SP7_SHIFT 2 #define AIPS_PACRD_TP6_MASK 0x10u #define AIPS_PACRD_TP6_SHIFT 4 #define AIPS_PACRD_WP6_MASK 0x20u #define AIPS_PACRD_WP6_SHIFT 5 #define AIPS_PACRD_SP6_MASK 0x40u #define AIPS_PACRD_SP6_SHIFT 6 #define AIPS_PACRD_TP5_MASK 0x100u #define AIPS_PACRD_TP5_SHIFT 8 #define AIPS_PACRD_WP5_MASK 0x200u #define AIPS_PACRD_WP5_SHIFT 9 #define AIPS_PACRD_SP5_MASK 0x400u #define AIPS_PACRD_SP5_SHIFT 10 #define AIPS_PACRD_TP4_MASK 0x1000u #define AIPS_PACRD_TP4_SHIFT 12 #define AIPS_PACRD_WP4_MASK 0x2000u #define AIPS_PACRD_WP4_SHIFT 13 #define AIPS_PACRD_SP4_MASK 0x4000u #define AIPS_PACRD_SP4_SHIFT 14 #define AIPS_PACRD_TP3_MASK 0x10000u #define AIPS_PACRD_TP3_SHIFT 16 #define AIPS_PACRD_WP3_MASK 0x20000u #define AIPS_PACRD_WP3_SHIFT 17 #define AIPS_PACRD_SP3_MASK 0x40000u #define AIPS_PACRD_SP3_SHIFT 18 #define AIPS_PACRD_TP2_MASK 0x100000u #define AIPS_PACRD_TP2_SHIFT 20 #define AIPS_PACRD_WP2_MASK 0x200000u #define AIPS_PACRD_WP2_SHIFT 21 #define AIPS_PACRD_SP2_MASK 0x400000u #define AIPS_PACRD_SP2_SHIFT 22 #define AIPS_PACRD_TP1_MASK 0x1000000u #define AIPS_PACRD_TP1_SHIFT 24 #define AIPS_PACRD_WP1_MASK 0x2000000u #define AIPS_PACRD_WP1_SHIFT 25 #define AIPS_PACRD_SP1_MASK 0x4000000u #define AIPS_PACRD_SP1_SHIFT 26 #define AIPS_PACRD_TP0_MASK 0x10000000u #define AIPS_PACRD_TP0_SHIFT 28 #define AIPS_PACRD_WP0_MASK 0x20000000u #define AIPS_PACRD_WP0_SHIFT 29 #define AIPS_PACRD_SP0_MASK 0x40000000u #define AIPS_PACRD_SP0_SHIFT 30 /* PACRE Bit Fields */ #define AIPS_PACRE_TP7_MASK 0x1u #define AIPS_PACRE_TP7_SHIFT 0 #define AIPS_PACRE_WP7_MASK 0x2u #define AIPS_PACRE_WP7_SHIFT 1 #define AIPS_PACRE_SP7_MASK 0x4u #define AIPS_PACRE_SP7_SHIFT 2 #define AIPS_PACRE_TP6_MASK 0x10u #define AIPS_PACRE_TP6_SHIFT 4 #define AIPS_PACRE_WP6_MASK 0x20u #define AIPS_PACRE_WP6_SHIFT 5 #define AIPS_PACRE_SP6_MASK 0x40u #define AIPS_PACRE_SP6_SHIFT 6 #define AIPS_PACRE_TP5_MASK 0x100u #define AIPS_PACRE_TP5_SHIFT 8 #define AIPS_PACRE_WP5_MASK 0x200u #define AIPS_PACRE_WP5_SHIFT 9 #define AIPS_PACRE_SP5_MASK 0x400u #define AIPS_PACRE_SP5_SHIFT 10 #define AIPS_PACRE_TP4_MASK 0x1000u #define AIPS_PACRE_TP4_SHIFT 12 #define AIPS_PACRE_WP4_MASK 0x2000u #define AIPS_PACRE_WP4_SHIFT 13 #define AIPS_PACRE_SP4_MASK 0x4000u #define AIPS_PACRE_SP4_SHIFT 14 #define AIPS_PACRE_TP3_MASK 0x10000u #define AIPS_PACRE_TP3_SHIFT 16 #define AIPS_PACRE_WP3_MASK 0x20000u #define AIPS_PACRE_WP3_SHIFT 17 #define AIPS_PACRE_SP3_MASK 0x40000u #define AIPS_PACRE_SP3_SHIFT 18 #define AIPS_PACRE_TP2_MASK 0x100000u #define AIPS_PACRE_TP2_SHIFT 20 #define AIPS_PACRE_WP2_MASK 0x200000u #define AIPS_PACRE_WP2_SHIFT 21 #define AIPS_PACRE_SP2_MASK 0x400000u #define AIPS_PACRE_SP2_SHIFT 22 #define AIPS_PACRE_TP1_MASK 0x1000000u #define AIPS_PACRE_TP1_SHIFT 24 #define AIPS_PACRE_WP1_MASK 0x2000000u #define AIPS_PACRE_WP1_SHIFT 25 #define AIPS_PACRE_SP1_MASK 0x4000000u #define AIPS_PACRE_SP1_SHIFT 26 #define AIPS_PACRE_TP0_MASK 0x10000000u #define AIPS_PACRE_TP0_SHIFT 28 #define AIPS_PACRE_WP0_MASK 0x20000000u #define AIPS_PACRE_WP0_SHIFT 29 #define AIPS_PACRE_SP0_MASK 0x40000000u #define AIPS_PACRE_SP0_SHIFT 30 /* PACRF Bit Fields */ #define AIPS_PACRF_TP7_MASK 0x1u #define AIPS_PACRF_TP7_SHIFT 0 #define AIPS_PACRF_WP7_MASK 0x2u #define AIPS_PACRF_WP7_SHIFT 1 #define AIPS_PACRF_SP7_MASK 0x4u #define AIPS_PACRF_SP7_SHIFT 2 #define AIPS_PACRF_TP6_MASK 0x10u #define AIPS_PACRF_TP6_SHIFT 4 #define AIPS_PACRF_WP6_MASK 0x20u #define AIPS_PACRF_WP6_SHIFT 5 #define AIPS_PACRF_SP6_MASK 0x40u #define AIPS_PACRF_SP6_SHIFT 6 #define AIPS_PACRF_TP5_MASK 0x100u #define AIPS_PACRF_TP5_SHIFT 8 #define AIPS_PACRF_WP5_MASK 0x200u #define AIPS_PACRF_WP5_SHIFT 9 #define AIPS_PACRF_SP5_MASK 0x400u #define AIPS_PACRF_SP5_SHIFT 10 #define AIPS_PACRF_TP4_MASK 0x1000u #define AIPS_PACRF_TP4_SHIFT 12 #define AIPS_PACRF_WP4_MASK 0x2000u #define AIPS_PACRF_WP4_SHIFT 13 #define AIPS_PACRF_SP4_MASK 0x4000u #define AIPS_PACRF_SP4_SHIFT 14 #define AIPS_PACRF_TP3_MASK 0x10000u #define AIPS_PACRF_TP3_SHIFT 16 #define AIPS_PACRF_WP3_MASK 0x20000u #define AIPS_PACRF_WP3_SHIFT 17 #define AIPS_PACRF_SP3_MASK 0x40000u #define AIPS_PACRF_SP3_SHIFT 18 #define AIPS_PACRF_TP2_MASK 0x100000u #define AIPS_PACRF_TP2_SHIFT 20 #define AIPS_PACRF_WP2_MASK 0x200000u #define AIPS_PACRF_WP2_SHIFT 21 #define AIPS_PACRF_SP2_MASK 0x400000u #define AIPS_PACRF_SP2_SHIFT 22 #define AIPS_PACRF_TP1_MASK 0x1000000u #define AIPS_PACRF_TP1_SHIFT 24 #define AIPS_PACRF_WP1_MASK 0x2000000u #define AIPS_PACRF_WP1_SHIFT 25 #define AIPS_PACRF_SP1_MASK 0x4000000u #define AIPS_PACRF_SP1_SHIFT 26 #define AIPS_PACRF_TP0_MASK 0x10000000u #define AIPS_PACRF_TP0_SHIFT 28 #define AIPS_PACRF_WP0_MASK 0x20000000u #define AIPS_PACRF_WP0_SHIFT 29 #define AIPS_PACRF_SP0_MASK 0x40000000u #define AIPS_PACRF_SP0_SHIFT 30 /* PACRG Bit Fields */ #define AIPS_PACRG_TP7_MASK 0x1u #define AIPS_PACRG_TP7_SHIFT 0 #define AIPS_PACRG_WP7_MASK 0x2u #define AIPS_PACRG_WP7_SHIFT 1 #define AIPS_PACRG_SP7_MASK 0x4u #define AIPS_PACRG_SP7_SHIFT 2 #define AIPS_PACRG_TP6_MASK 0x10u #define AIPS_PACRG_TP6_SHIFT 4 #define AIPS_PACRG_WP6_MASK 0x20u #define AIPS_PACRG_WP6_SHIFT 5 #define AIPS_PACRG_SP6_MASK 0x40u #define AIPS_PACRG_SP6_SHIFT 6 #define AIPS_PACRG_TP5_MASK 0x100u #define AIPS_PACRG_TP5_SHIFT 8 #define AIPS_PACRG_WP5_MASK 0x200u #define AIPS_PACRG_WP5_SHIFT 9 #define AIPS_PACRG_SP5_MASK 0x400u #define AIPS_PACRG_SP5_SHIFT 10 #define AIPS_PACRG_TP4_MASK 0x1000u #define AIPS_PACRG_TP4_SHIFT 12 #define AIPS_PACRG_WP4_MASK 0x2000u #define AIPS_PACRG_WP4_SHIFT 13 #define AIPS_PACRG_SP4_MASK 0x4000u #define AIPS_PACRG_SP4_SHIFT 14 #define AIPS_PACRG_TP3_MASK 0x10000u #define AIPS_PACRG_TP3_SHIFT 16 #define AIPS_PACRG_WP3_MASK 0x20000u #define AIPS_PACRG_WP3_SHIFT 17 #define AIPS_PACRG_SP3_MASK 0x40000u #define AIPS_PACRG_SP3_SHIFT 18 #define AIPS_PACRG_TP2_MASK 0x100000u #define AIPS_PACRG_TP2_SHIFT 20 #define AIPS_PACRG_WP2_MASK 0x200000u #define AIPS_PACRG_WP2_SHIFT 21 #define AIPS_PACRG_SP2_MASK 0x400000u #define AIPS_PACRG_SP2_SHIFT 22 #define AIPS_PACRG_TP1_MASK 0x1000000u #define AIPS_PACRG_TP1_SHIFT 24 #define AIPS_PACRG_WP1_MASK 0x2000000u #define AIPS_PACRG_WP1_SHIFT 25 #define AIPS_PACRG_SP1_MASK 0x4000000u #define AIPS_PACRG_SP1_SHIFT 26 #define AIPS_PACRG_TP0_MASK 0x10000000u #define AIPS_PACRG_TP0_SHIFT 28 #define AIPS_PACRG_WP0_MASK 0x20000000u #define AIPS_PACRG_WP0_SHIFT 29 #define AIPS_PACRG_SP0_MASK 0x40000000u #define AIPS_PACRG_SP0_SHIFT 30 /* PACRH Bit Fields */ #define AIPS_PACRH_TP7_MASK 0x1u #define AIPS_PACRH_TP7_SHIFT 0 #define AIPS_PACRH_WP7_MASK 0x2u #define AIPS_PACRH_WP7_SHIFT 1 #define AIPS_PACRH_SP7_MASK 0x4u #define AIPS_PACRH_SP7_SHIFT 2 #define AIPS_PACRH_TP6_MASK 0x10u #define AIPS_PACRH_TP6_SHIFT 4 #define AIPS_PACRH_WP6_MASK 0x20u #define AIPS_PACRH_WP6_SHIFT 5 #define AIPS_PACRH_SP6_MASK 0x40u #define AIPS_PACRH_SP6_SHIFT 6 #define AIPS_PACRH_TP5_MASK 0x100u #define AIPS_PACRH_TP5_SHIFT 8 #define AIPS_PACRH_WP5_MASK 0x200u #define AIPS_PACRH_WP5_SHIFT 9 #define AIPS_PACRH_SP5_MASK 0x400u #define AIPS_PACRH_SP5_SHIFT 10 #define AIPS_PACRH_TP4_MASK 0x1000u #define AIPS_PACRH_TP4_SHIFT 12 #define AIPS_PACRH_WP4_MASK 0x2000u #define AIPS_PACRH_WP4_SHIFT 13 #define AIPS_PACRH_SP4_MASK 0x4000u #define AIPS_PACRH_SP4_SHIFT 14 #define AIPS_PACRH_TP3_MASK 0x10000u #define AIPS_PACRH_TP3_SHIFT 16 #define AIPS_PACRH_WP3_MASK 0x20000u #define AIPS_PACRH_WP3_SHIFT 17 #define AIPS_PACRH_SP3_MASK 0x40000u #define AIPS_PACRH_SP3_SHIFT 18 #define AIPS_PACRH_TP2_MASK 0x100000u #define AIPS_PACRH_TP2_SHIFT 20 #define AIPS_PACRH_WP2_MASK 0x200000u #define AIPS_PACRH_WP2_SHIFT 21 #define AIPS_PACRH_SP2_MASK 0x400000u #define AIPS_PACRH_SP2_SHIFT 22 #define AIPS_PACRH_TP1_MASK 0x1000000u #define AIPS_PACRH_TP1_SHIFT 24 #define AIPS_PACRH_WP1_MASK 0x2000000u #define AIPS_PACRH_WP1_SHIFT 25 #define AIPS_PACRH_SP1_MASK 0x4000000u #define AIPS_PACRH_SP1_SHIFT 26 #define AIPS_PACRH_TP0_MASK 0x10000000u #define AIPS_PACRH_TP0_SHIFT 28 #define AIPS_PACRH_WP0_MASK 0x20000000u #define AIPS_PACRH_WP0_SHIFT 29 #define AIPS_PACRH_SP0_MASK 0x40000000u #define AIPS_PACRH_SP0_SHIFT 30 /* PACRI Bit Fields */ #define AIPS_PACRI_TP7_MASK 0x1u #define AIPS_PACRI_TP7_SHIFT 0 #define AIPS_PACRI_WP7_MASK 0x2u #define AIPS_PACRI_WP7_SHIFT 1 #define AIPS_PACRI_SP7_MASK 0x4u #define AIPS_PACRI_SP7_SHIFT 2 #define AIPS_PACRI_TP6_MASK 0x10u #define AIPS_PACRI_TP6_SHIFT 4 #define AIPS_PACRI_WP6_MASK 0x20u #define AIPS_PACRI_WP6_SHIFT 5 #define AIPS_PACRI_SP6_MASK 0x40u #define AIPS_PACRI_SP6_SHIFT 6 #define AIPS_PACRI_TP5_MASK 0x100u #define AIPS_PACRI_TP5_SHIFT 8 #define AIPS_PACRI_WP5_MASK 0x200u #define AIPS_PACRI_WP5_SHIFT 9 #define AIPS_PACRI_SP5_MASK 0x400u #define AIPS_PACRI_SP5_SHIFT 10 #define AIPS_PACRI_TP4_MASK 0x1000u #define AIPS_PACRI_TP4_SHIFT 12 #define AIPS_PACRI_WP4_MASK 0x2000u #define AIPS_PACRI_WP4_SHIFT 13 #define AIPS_PACRI_SP4_MASK 0x4000u #define AIPS_PACRI_SP4_SHIFT 14 #define AIPS_PACRI_TP3_MASK 0x10000u #define AIPS_PACRI_TP3_SHIFT 16 #define AIPS_PACRI_WP3_MASK 0x20000u #define AIPS_PACRI_WP3_SHIFT 17 #define AIPS_PACRI_SP3_MASK 0x40000u #define AIPS_PACRI_SP3_SHIFT 18 #define AIPS_PACRI_TP2_MASK 0x100000u #define AIPS_PACRI_TP2_SHIFT 20 #define AIPS_PACRI_WP2_MASK 0x200000u #define AIPS_PACRI_WP2_SHIFT 21 #define AIPS_PACRI_SP2_MASK 0x400000u #define AIPS_PACRI_SP2_SHIFT 22 #define AIPS_PACRI_TP1_MASK 0x1000000u #define AIPS_PACRI_TP1_SHIFT 24 #define AIPS_PACRI_WP1_MASK 0x2000000u #define AIPS_PACRI_WP1_SHIFT 25 #define AIPS_PACRI_SP1_MASK 0x4000000u #define AIPS_PACRI_SP1_SHIFT 26 #define AIPS_PACRI_TP0_MASK 0x10000000u #define AIPS_PACRI_TP0_SHIFT 28 #define AIPS_PACRI_WP0_MASK 0x20000000u #define AIPS_PACRI_WP0_SHIFT 29 #define AIPS_PACRI_SP0_MASK 0x40000000u #define AIPS_PACRI_SP0_SHIFT 30 /* PACRJ Bit Fields */ #define AIPS_PACRJ_TP7_MASK 0x1u #define AIPS_PACRJ_TP7_SHIFT 0 #define AIPS_PACRJ_WP7_MASK 0x2u #define AIPS_PACRJ_WP7_SHIFT 1 #define AIPS_PACRJ_SP7_MASK 0x4u #define AIPS_PACRJ_SP7_SHIFT 2 #define AIPS_PACRJ_TP6_MASK 0x10u #define AIPS_PACRJ_TP6_SHIFT 4 #define AIPS_PACRJ_WP6_MASK 0x20u #define AIPS_PACRJ_WP6_SHIFT 5 #define AIPS_PACRJ_SP6_MASK 0x40u #define AIPS_PACRJ_SP6_SHIFT 6 #define AIPS_PACRJ_TP5_MASK 0x100u #define AIPS_PACRJ_TP5_SHIFT 8 #define AIPS_PACRJ_WP5_MASK 0x200u #define AIPS_PACRJ_WP5_SHIFT 9 #define AIPS_PACRJ_SP5_MASK 0x400u #define AIPS_PACRJ_SP5_SHIFT 10 #define AIPS_PACRJ_TP4_MASK 0x1000u #define AIPS_PACRJ_TP4_SHIFT 12 #define AIPS_PACRJ_WP4_MASK 0x2000u #define AIPS_PACRJ_WP4_SHIFT 13 #define AIPS_PACRJ_SP4_MASK 0x4000u #define AIPS_PACRJ_SP4_SHIFT 14 #define AIPS_PACRJ_TP3_MASK 0x10000u #define AIPS_PACRJ_TP3_SHIFT 16 #define AIPS_PACRJ_WP3_MASK 0x20000u #define AIPS_PACRJ_WP3_SHIFT 17 #define AIPS_PACRJ_SP3_MASK 0x40000u #define AIPS_PACRJ_SP3_SHIFT 18 #define AIPS_PACRJ_TP2_MASK 0x100000u #define AIPS_PACRJ_TP2_SHIFT 20 #define AIPS_PACRJ_WP2_MASK 0x200000u #define AIPS_PACRJ_WP2_SHIFT 21 #define AIPS_PACRJ_SP2_MASK 0x400000u #define AIPS_PACRJ_SP2_SHIFT 22 #define AIPS_PACRJ_TP1_MASK 0x1000000u #define AIPS_PACRJ_TP1_SHIFT 24 #define AIPS_PACRJ_WP1_MASK 0x2000000u #define AIPS_PACRJ_WP1_SHIFT 25 #define AIPS_PACRJ_SP1_MASK 0x4000000u #define AIPS_PACRJ_SP1_SHIFT 26 #define AIPS_PACRJ_TP0_MASK 0x10000000u #define AIPS_PACRJ_TP0_SHIFT 28 #define AIPS_PACRJ_WP0_MASK 0x20000000u #define AIPS_PACRJ_WP0_SHIFT 29 #define AIPS_PACRJ_SP0_MASK 0x40000000u #define AIPS_PACRJ_SP0_SHIFT 30 /* PACRK Bit Fields */ #define AIPS_PACRK_TP7_MASK 0x1u #define AIPS_PACRK_TP7_SHIFT 0 #define AIPS_PACRK_WP7_MASK 0x2u #define AIPS_PACRK_WP7_SHIFT 1 #define AIPS_PACRK_SP7_MASK 0x4u #define AIPS_PACRK_SP7_SHIFT 2 #define AIPS_PACRK_TP6_MASK 0x10u #define AIPS_PACRK_TP6_SHIFT 4 #define AIPS_PACRK_WP6_MASK 0x20u #define AIPS_PACRK_WP6_SHIFT 5 #define AIPS_PACRK_SP6_MASK 0x40u #define AIPS_PACRK_SP6_SHIFT 6 #define AIPS_PACRK_TP5_MASK 0x100u #define AIPS_PACRK_TP5_SHIFT 8 #define AIPS_PACRK_WP5_MASK 0x200u #define AIPS_PACRK_WP5_SHIFT 9 #define AIPS_PACRK_SP5_MASK 0x400u #define AIPS_PACRK_SP5_SHIFT 10 #define AIPS_PACRK_TP4_MASK 0x1000u #define AIPS_PACRK_TP4_SHIFT 12 #define AIPS_PACRK_WP4_MASK 0x2000u #define AIPS_PACRK_WP4_SHIFT 13 #define AIPS_PACRK_SP4_MASK 0x4000u #define AIPS_PACRK_SP4_SHIFT 14 #define AIPS_PACRK_TP3_MASK 0x10000u #define AIPS_PACRK_TP3_SHIFT 16 #define AIPS_PACRK_WP3_MASK 0x20000u #define AIPS_PACRK_WP3_SHIFT 17 #define AIPS_PACRK_SP3_MASK 0x40000u #define AIPS_PACRK_SP3_SHIFT 18 #define AIPS_PACRK_TP2_MASK 0x100000u #define AIPS_PACRK_TP2_SHIFT 20 #define AIPS_PACRK_WP2_MASK 0x200000u #define AIPS_PACRK_WP2_SHIFT 21 #define AIPS_PACRK_SP2_MASK 0x400000u #define AIPS_PACRK_SP2_SHIFT 22 #define AIPS_PACRK_TP1_MASK 0x1000000u #define AIPS_PACRK_TP1_SHIFT 24 #define AIPS_PACRK_WP1_MASK 0x2000000u #define AIPS_PACRK_WP1_SHIFT 25 #define AIPS_PACRK_SP1_MASK 0x4000000u #define AIPS_PACRK_SP1_SHIFT 26 #define AIPS_PACRK_TP0_MASK 0x10000000u #define AIPS_PACRK_TP0_SHIFT 28 #define AIPS_PACRK_WP0_MASK 0x20000000u #define AIPS_PACRK_WP0_SHIFT 29 #define AIPS_PACRK_SP0_MASK 0x40000000u #define AIPS_PACRK_SP0_SHIFT 30 /* PACRL Bit Fields */ #define AIPS_PACRL_TP7_MASK 0x1u #define AIPS_PACRL_TP7_SHIFT 0 #define AIPS_PACRL_WP7_MASK 0x2u #define AIPS_PACRL_WP7_SHIFT 1 #define AIPS_PACRL_SP7_MASK 0x4u #define AIPS_PACRL_SP7_SHIFT 2 #define AIPS_PACRL_TP6_MASK 0x10u #define AIPS_PACRL_TP6_SHIFT 4 #define AIPS_PACRL_WP6_MASK 0x20u #define AIPS_PACRL_WP6_SHIFT 5 #define AIPS_PACRL_SP6_MASK 0x40u #define AIPS_PACRL_SP6_SHIFT 6 #define AIPS_PACRL_TP5_MASK 0x100u #define AIPS_PACRL_TP5_SHIFT 8 #define AIPS_PACRL_WP5_MASK 0x200u #define AIPS_PACRL_WP5_SHIFT 9 #define AIPS_PACRL_SP5_MASK 0x400u #define AIPS_PACRL_SP5_SHIFT 10 #define AIPS_PACRL_TP4_MASK 0x1000u #define AIPS_PACRL_TP4_SHIFT 12 #define AIPS_PACRL_WP4_MASK 0x2000u #define AIPS_PACRL_WP4_SHIFT 13 #define AIPS_PACRL_SP4_MASK 0x4000u #define AIPS_PACRL_SP4_SHIFT 14 #define AIPS_PACRL_TP3_MASK 0x10000u #define AIPS_PACRL_TP3_SHIFT 16 #define AIPS_PACRL_WP3_MASK 0x20000u #define AIPS_PACRL_WP3_SHIFT 17 #define AIPS_PACRL_SP3_MASK 0x40000u #define AIPS_PACRL_SP3_SHIFT 18 #define AIPS_PACRL_TP2_MASK 0x100000u #define AIPS_PACRL_TP2_SHIFT 20 #define AIPS_PACRL_WP2_MASK 0x200000u #define AIPS_PACRL_WP2_SHIFT 21 #define AIPS_PACRL_SP2_MASK 0x400000u #define AIPS_PACRL_SP2_SHIFT 22 #define AIPS_PACRL_TP1_MASK 0x1000000u #define AIPS_PACRL_TP1_SHIFT 24 #define AIPS_PACRL_WP1_MASK 0x2000000u #define AIPS_PACRL_WP1_SHIFT 25 #define AIPS_PACRL_SP1_MASK 0x4000000u #define AIPS_PACRL_SP1_SHIFT 26 #define AIPS_PACRL_TP0_MASK 0x10000000u #define AIPS_PACRL_TP0_SHIFT 28 #define AIPS_PACRL_WP0_MASK 0x20000000u #define AIPS_PACRL_WP0_SHIFT 29 #define AIPS_PACRL_SP0_MASK 0x40000000u #define AIPS_PACRL_SP0_SHIFT 30 /* PACRM Bit Fields */ #define AIPS_PACRM_TP7_MASK 0x1u #define AIPS_PACRM_TP7_SHIFT 0 #define AIPS_PACRM_WP7_MASK 0x2u #define AIPS_PACRM_WP7_SHIFT 1 #define AIPS_PACRM_SP7_MASK 0x4u #define AIPS_PACRM_SP7_SHIFT 2 #define AIPS_PACRM_TP6_MASK 0x10u #define AIPS_PACRM_TP6_SHIFT 4 #define AIPS_PACRM_WP6_MASK 0x20u #define AIPS_PACRM_WP6_SHIFT 5 #define AIPS_PACRM_SP6_MASK 0x40u #define AIPS_PACRM_SP6_SHIFT 6 #define AIPS_PACRM_TP5_MASK 0x100u #define AIPS_PACRM_TP5_SHIFT 8 #define AIPS_PACRM_WP5_MASK 0x200u #define AIPS_PACRM_WP5_SHIFT 9 #define AIPS_PACRM_SP5_MASK 0x400u #define AIPS_PACRM_SP5_SHIFT 10 #define AIPS_PACRM_TP4_MASK 0x1000u #define AIPS_PACRM_TP4_SHIFT 12 #define AIPS_PACRM_WP4_MASK 0x2000u #define AIPS_PACRM_WP4_SHIFT 13 #define AIPS_PACRM_SP4_MASK 0x4000u #define AIPS_PACRM_SP4_SHIFT 14 #define AIPS_PACRM_TP3_MASK 0x10000u #define AIPS_PACRM_TP3_SHIFT 16 #define AIPS_PACRM_WP3_MASK 0x20000u #define AIPS_PACRM_WP3_SHIFT 17 #define AIPS_PACRM_SP3_MASK 0x40000u #define AIPS_PACRM_SP3_SHIFT 18 #define AIPS_PACRM_TP2_MASK 0x100000u #define AIPS_PACRM_TP2_SHIFT 20 #define AIPS_PACRM_WP2_MASK 0x200000u #define AIPS_PACRM_WP2_SHIFT 21 #define AIPS_PACRM_SP2_MASK 0x400000u #define AIPS_PACRM_SP2_SHIFT 22 #define AIPS_PACRM_TP1_MASK 0x1000000u #define AIPS_PACRM_TP1_SHIFT 24 #define AIPS_PACRM_WP1_MASK 0x2000000u #define AIPS_PACRM_WP1_SHIFT 25 #define AIPS_PACRM_SP1_MASK 0x4000000u #define AIPS_PACRM_SP1_SHIFT 26 #define AIPS_PACRM_TP0_MASK 0x10000000u #define AIPS_PACRM_TP0_SHIFT 28 #define AIPS_PACRM_WP0_MASK 0x20000000u #define AIPS_PACRM_WP0_SHIFT 29 #define AIPS_PACRM_SP0_MASK 0x40000000u #define AIPS_PACRM_SP0_SHIFT 30 /* PACRN Bit Fields */ #define AIPS_PACRN_TP7_MASK 0x1u #define AIPS_PACRN_TP7_SHIFT 0 #define AIPS_PACRN_WP7_MASK 0x2u #define AIPS_PACRN_WP7_SHIFT 1 #define AIPS_PACRN_SP7_MASK 0x4u #define AIPS_PACRN_SP7_SHIFT 2 #define AIPS_PACRN_TP6_MASK 0x10u #define AIPS_PACRN_TP6_SHIFT 4 #define AIPS_PACRN_WP6_MASK 0x20u #define AIPS_PACRN_WP6_SHIFT 5 #define AIPS_PACRN_SP6_MASK 0x40u #define AIPS_PACRN_SP6_SHIFT 6 #define AIPS_PACRN_TP5_MASK 0x100u #define AIPS_PACRN_TP5_SHIFT 8 #define AIPS_PACRN_WP5_MASK 0x200u #define AIPS_PACRN_WP5_SHIFT 9 #define AIPS_PACRN_SP5_MASK 0x400u #define AIPS_PACRN_SP5_SHIFT 10 #define AIPS_PACRN_TP4_MASK 0x1000u #define AIPS_PACRN_TP4_SHIFT 12 #define AIPS_PACRN_WP4_MASK 0x2000u #define AIPS_PACRN_WP4_SHIFT 13 #define AIPS_PACRN_SP4_MASK 0x4000u #define AIPS_PACRN_SP4_SHIFT 14 #define AIPS_PACRN_TP3_MASK 0x10000u #define AIPS_PACRN_TP3_SHIFT 16 #define AIPS_PACRN_WP3_MASK 0x20000u #define AIPS_PACRN_WP3_SHIFT 17 #define AIPS_PACRN_SP3_MASK 0x40000u #define AIPS_PACRN_SP3_SHIFT 18 #define AIPS_PACRN_TP2_MASK 0x100000u #define AIPS_PACRN_TP2_SHIFT 20 #define AIPS_PACRN_WP2_MASK 0x200000u #define AIPS_PACRN_WP2_SHIFT 21 #define AIPS_PACRN_SP2_MASK 0x400000u #define AIPS_PACRN_SP2_SHIFT 22 #define AIPS_PACRN_TP1_MASK 0x1000000u #define AIPS_PACRN_TP1_SHIFT 24 #define AIPS_PACRN_WP1_MASK 0x2000000u #define AIPS_PACRN_WP1_SHIFT 25 #define AIPS_PACRN_SP1_MASK 0x4000000u #define AIPS_PACRN_SP1_SHIFT 26 #define AIPS_PACRN_TP0_MASK 0x10000000u #define AIPS_PACRN_TP0_SHIFT 28 #define AIPS_PACRN_WP0_MASK 0x20000000u #define AIPS_PACRN_WP0_SHIFT 29 #define AIPS_PACRN_SP0_MASK 0x40000000u #define AIPS_PACRN_SP0_SHIFT 30 /* PACRO Bit Fields */ #define AIPS_PACRO_TP7_MASK 0x1u #define AIPS_PACRO_TP7_SHIFT 0 #define AIPS_PACRO_WP7_MASK 0x2u #define AIPS_PACRO_WP7_SHIFT 1 #define AIPS_PACRO_SP7_MASK 0x4u #define AIPS_PACRO_SP7_SHIFT 2 #define AIPS_PACRO_TP6_MASK 0x10u #define AIPS_PACRO_TP6_SHIFT 4 #define AIPS_PACRO_WP6_MASK 0x20u #define AIPS_PACRO_WP6_SHIFT 5 #define AIPS_PACRO_SP6_MASK 0x40u #define AIPS_PACRO_SP6_SHIFT 6 #define AIPS_PACRO_TP5_MASK 0x100u #define AIPS_PACRO_TP5_SHIFT 8 #define AIPS_PACRO_WP5_MASK 0x200u #define AIPS_PACRO_WP5_SHIFT 9 #define AIPS_PACRO_SP5_MASK 0x400u #define AIPS_PACRO_SP5_SHIFT 10 #define AIPS_PACRO_TP4_MASK 0x1000u #define AIPS_PACRO_TP4_SHIFT 12 #define AIPS_PACRO_WP4_MASK 0x2000u #define AIPS_PACRO_WP4_SHIFT 13 #define AIPS_PACRO_SP4_MASK 0x4000u #define AIPS_PACRO_SP4_SHIFT 14 #define AIPS_PACRO_TP3_MASK 0x10000u #define AIPS_PACRO_TP3_SHIFT 16 #define AIPS_PACRO_WP3_MASK 0x20000u #define AIPS_PACRO_WP3_SHIFT 17 #define AIPS_PACRO_SP3_MASK 0x40000u #define AIPS_PACRO_SP3_SHIFT 18 #define AIPS_PACRO_TP2_MASK 0x100000u #define AIPS_PACRO_TP2_SHIFT 20 #define AIPS_PACRO_WP2_MASK 0x200000u #define AIPS_PACRO_WP2_SHIFT 21 #define AIPS_PACRO_SP2_MASK 0x400000u #define AIPS_PACRO_SP2_SHIFT 22 #define AIPS_PACRO_TP1_MASK 0x1000000u #define AIPS_PACRO_TP1_SHIFT 24 #define AIPS_PACRO_WP1_MASK 0x2000000u #define AIPS_PACRO_WP1_SHIFT 25 #define AIPS_PACRO_SP1_MASK 0x4000000u #define AIPS_PACRO_SP1_SHIFT 26 #define AIPS_PACRO_TP0_MASK 0x10000000u #define AIPS_PACRO_TP0_SHIFT 28 #define AIPS_PACRO_WP0_MASK 0x20000000u #define AIPS_PACRO_WP0_SHIFT 29 #define AIPS_PACRO_SP0_MASK 0x40000000u #define AIPS_PACRO_SP0_SHIFT 30 /* PACRP Bit Fields */ #define AIPS_PACRP_TP7_MASK 0x1u #define AIPS_PACRP_TP7_SHIFT 0 #define AIPS_PACRP_WP7_MASK 0x2u #define AIPS_PACRP_WP7_SHIFT 1 #define AIPS_PACRP_SP7_MASK 0x4u #define AIPS_PACRP_SP7_SHIFT 2 #define AIPS_PACRP_TP6_MASK 0x10u #define AIPS_PACRP_TP6_SHIFT 4 #define AIPS_PACRP_WP6_MASK 0x20u #define AIPS_PACRP_WP6_SHIFT 5 #define AIPS_PACRP_SP6_MASK 0x40u #define AIPS_PACRP_SP6_SHIFT 6 #define AIPS_PACRP_TP5_MASK 0x100u #define AIPS_PACRP_TP5_SHIFT 8 #define AIPS_PACRP_WP5_MASK 0x200u #define AIPS_PACRP_WP5_SHIFT 9 #define AIPS_PACRP_SP5_MASK 0x400u #define AIPS_PACRP_SP5_SHIFT 10 #define AIPS_PACRP_TP4_MASK 0x1000u #define AIPS_PACRP_TP4_SHIFT 12 #define AIPS_PACRP_WP4_MASK 0x2000u #define AIPS_PACRP_WP4_SHIFT 13 #define AIPS_PACRP_SP4_MASK 0x4000u #define AIPS_PACRP_SP4_SHIFT 14 #define AIPS_PACRP_TP3_MASK 0x10000u #define AIPS_PACRP_TP3_SHIFT 16 #define AIPS_PACRP_WP3_MASK 0x20000u #define AIPS_PACRP_WP3_SHIFT 17 #define AIPS_PACRP_SP3_MASK 0x40000u #define AIPS_PACRP_SP3_SHIFT 18 #define AIPS_PACRP_TP2_MASK 0x100000u #define AIPS_PACRP_TP2_SHIFT 20 #define AIPS_PACRP_WP2_MASK 0x200000u #define AIPS_PACRP_WP2_SHIFT 21 #define AIPS_PACRP_SP2_MASK 0x400000u #define AIPS_PACRP_SP2_SHIFT 22 #define AIPS_PACRP_TP1_MASK 0x1000000u #define AIPS_PACRP_TP1_SHIFT 24 #define AIPS_PACRP_WP1_MASK 0x2000000u #define AIPS_PACRP_WP1_SHIFT 25 #define AIPS_PACRP_SP1_MASK 0x4000000u #define AIPS_PACRP_SP1_SHIFT 26 #define AIPS_PACRP_TP0_MASK 0x10000000u #define AIPS_PACRP_TP0_SHIFT 28 #define AIPS_PACRP_WP0_MASK 0x20000000u #define AIPS_PACRP_WP0_SHIFT 29 #define AIPS_PACRP_SP0_MASK 0x40000000u #define AIPS_PACRP_SP0_SHIFT 30 /* PACRU Bit Fields */ #define AIPS_PACRU_TP1_MASK 0x1000000u #define AIPS_PACRU_TP1_SHIFT 24 #define AIPS_PACRU_WP1_MASK 0x2000000u #define AIPS_PACRU_WP1_SHIFT 25 #define AIPS_PACRU_SP1_MASK 0x4000000u #define AIPS_PACRU_SP1_SHIFT 26 #define AIPS_PACRU_TP0_MASK 0x10000000u #define AIPS_PACRU_TP0_SHIFT 28 #define AIPS_PACRU_WP0_MASK 0x20000000u #define AIPS_PACRU_WP0_SHIFT 29 #define AIPS_PACRU_SP0_MASK 0x40000000u #define AIPS_PACRU_SP0_SHIFT 30 /*! * @} */ /* end of group AIPS_Register_Masks */ /* AIPS - Peripheral instance base addresses */ /** Peripheral AIPS0 base address */ #define AIPS0_BASE (0x40000000u) /** Peripheral AIPS0 base pointer */ #define AIPS0 ((AIPS_Type *)AIPS0_BASE) #define AIPS0_BASE_PTR (AIPS0) /** Peripheral AIPS1 base address */ #define AIPS1_BASE (0x40080000u) /** Peripheral AIPS1 base pointer */ #define AIPS1 ((AIPS_Type *)AIPS1_BASE) #define AIPS1_BASE_PTR (AIPS1) /** Array initializer of AIPS peripheral base addresses */ #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE } /** Array initializer of AIPS peripheral base pointers */ #define AIPS_BASE_PTRS { AIPS0, AIPS1 } /* ---------------------------------------------------------------------------- -- AIPS - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup AIPS_Register_Accessor_Macros AIPS - Register accessor macros * @{ */ /* AIPS - Register instance definitions */ /* AIPS0 */ #define AIPS0_MPRA AIPS_MPRA_REG(AIPS0) #define AIPS0_PACRA AIPS_PACRA_REG(AIPS0) #define AIPS0_PACRB AIPS_PACRB_REG(AIPS0) #define AIPS0_PACRC AIPS_PACRC_REG(AIPS0) #define AIPS0_PACRD AIPS_PACRD_REG(AIPS0) #define AIPS0_PACRE AIPS_PACRE_REG(AIPS0) #define AIPS0_PACRF AIPS_PACRF_REG(AIPS0) #define AIPS0_PACRG AIPS_PACRG_REG(AIPS0) #define AIPS0_PACRH AIPS_PACRH_REG(AIPS0) #define AIPS0_PACRI AIPS_PACRI_REG(AIPS0) #define AIPS0_PACRJ AIPS_PACRJ_REG(AIPS0) #define AIPS0_PACRK AIPS_PACRK_REG(AIPS0) #define AIPS0_PACRL AIPS_PACRL_REG(AIPS0) #define AIPS0_PACRM AIPS_PACRM_REG(AIPS0) #define AIPS0_PACRN AIPS_PACRN_REG(AIPS0) #define AIPS0_PACRO AIPS_PACRO_REG(AIPS0) #define AIPS0_PACRP AIPS_PACRP_REG(AIPS0) #define AIPS0_PACRU AIPS_PACRU_REG(AIPS0) /* AIPS1 */ #define AIPS1_MPRA AIPS_MPRA_REG(AIPS1) #define AIPS1_PACRA AIPS_PACRA_REG(AIPS1) #define AIPS1_PACRB AIPS_PACRB_REG(AIPS1) #define AIPS1_PACRC AIPS_PACRC_REG(AIPS1) #define AIPS1_PACRD AIPS_PACRD_REG(AIPS1) #define AIPS1_PACRE AIPS_PACRE_REG(AIPS1) #define AIPS1_PACRF AIPS_PACRF_REG(AIPS1) #define AIPS1_PACRG AIPS_PACRG_REG(AIPS1) #define AIPS1_PACRH AIPS_PACRH_REG(AIPS1) #define AIPS1_PACRI AIPS_PACRI_REG(AIPS1) #define AIPS1_PACRJ AIPS_PACRJ_REG(AIPS1) #define AIPS1_PACRK AIPS_PACRK_REG(AIPS1) #define AIPS1_PACRL AIPS_PACRL_REG(AIPS1) #define AIPS1_PACRM AIPS_PACRM_REG(AIPS1) #define AIPS1_PACRN AIPS_PACRN_REG(AIPS1) #define AIPS1_PACRO AIPS_PACRO_REG(AIPS1) #define AIPS1_PACRP AIPS_PACRP_REG(AIPS1) #define AIPS1_PACRU AIPS_PACRU_REG(AIPS1) /*! * @} */ /* end of group AIPS_Register_Accessor_Macros */ /*! * @} */ /* end of group AIPS_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- AXBS Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer * @{ */ /** AXBS - Register Layout Typedef */ typedef struct { struct { /* offset: 0x0, array step: 0x100 */ __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */ uint8_t RESERVED_0[12]; __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ uint8_t RESERVED_1[236]; } SLAVE[5]; uint8_t RESERVED_0[768]; __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ uint8_t RESERVED_1[252]; __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ uint8_t RESERVED_2[252]; __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ uint8_t RESERVED_3[252]; __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ uint8_t RESERVED_4[252]; __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ uint8_t RESERVED_5[252]; __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ } AXBS_Type, *AXBS_MemMapPtr; /* ---------------------------------------------------------------------------- -- AXBS - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup AXBS_Register_Accessor_Macros AXBS - Register accessor macros * @{ */ /* AXBS - Register accessors */ #define AXBS_PRS_REG(base,index) ((base)->SLAVE[index].PRS) #define AXBS_CRS_REG(base,index) ((base)->SLAVE[index].CRS) #define AXBS_MGPCR0_REG(base) ((base)->MGPCR0) #define AXBS_MGPCR1_REG(base) ((base)->MGPCR1) #define AXBS_MGPCR2_REG(base) ((base)->MGPCR2) #define AXBS_MGPCR3_REG(base) ((base)->MGPCR3) #define AXBS_MGPCR4_REG(base) ((base)->MGPCR4) #define AXBS_MGPCR5_REG(base) ((base)->MGPCR5) /*! * @} */ /* end of group AXBS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- AXBS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup AXBS_Register_Masks AXBS Register Masks * @{ */ /* PRS Bit Fields */ #define AXBS_PRS_M0_MASK 0x7u #define AXBS_PRS_M0_SHIFT 0 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x))<MCR) #define CAN_CTRL1_REG(base) ((base)->CTRL1) #define CAN_TIMER_REG(base) ((base)->TIMER) #define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) #define CAN_RX14MASK_REG(base) ((base)->RX14MASK) #define CAN_RX15MASK_REG(base) ((base)->RX15MASK) #define CAN_ECR_REG(base) ((base)->ECR) #define CAN_ESR1_REG(base) ((base)->ESR1) #define CAN_IMASK1_REG(base) ((base)->IMASK1) #define CAN_IFLAG1_REG(base) ((base)->IFLAG1) #define CAN_CTRL2_REG(base) ((base)->CTRL2) #define CAN_ESR2_REG(base) ((base)->ESR2) #define CAN_CRCR_REG(base) ((base)->CRCR) #define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) #define CAN_RXFIR_REG(base) ((base)->RXFIR) #define CAN_CS_REG(base,index) ((base)->MB[index].CS) #define CAN_ID_REG(base,index) ((base)->MB[index].ID) #define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) #define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) #define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) /*! * @} */ /* end of group CAN_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAN Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAN_Register_Masks CAN Register Masks * @{ */ /* MCR Bit Fields */ #define CAN_MCR_MAXMB_MASK 0x7Fu #define CAN_MCR_MAXMB_SHIFT 0 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<DIRECT[index]) #define CAU_LDR_CASR_REG(base) ((base)->LDR_CASR) #define CAU_LDR_CAA_REG(base) ((base)->LDR_CAA) #define CAU_LDR_CA_REG(base,index) ((base)->LDR_CA[index]) #define CAU_STR_CASR_REG(base) ((base)->STR_CASR) #define CAU_STR_CAA_REG(base) ((base)->STR_CAA) #define CAU_STR_CA_REG(base,index) ((base)->STR_CA[index]) #define CAU_ADR_CASR_REG(base) ((base)->ADR_CASR) #define CAU_ADR_CAA_REG(base) ((base)->ADR_CAA) #define CAU_ADR_CA_REG(base,index) ((base)->ADR_CA[index]) #define CAU_RADR_CASR_REG(base) ((base)->RADR_CASR) #define CAU_RADR_CAA_REG(base) ((base)->RADR_CAA) #define CAU_RADR_CA_REG(base,index) ((base)->RADR_CA[index]) #define CAU_XOR_CASR_REG(base) ((base)->XOR_CASR) #define CAU_XOR_CAA_REG(base) ((base)->XOR_CAA) #define CAU_XOR_CA_REG(base,index) ((base)->XOR_CA[index]) #define CAU_ROTL_CASR_REG(base) ((base)->ROTL_CASR) #define CAU_ROTL_CAA_REG(base) ((base)->ROTL_CAA) #define CAU_ROTL_CA_REG(base,index) ((base)->ROTL_CA[index]) #define CAU_AESC_CASR_REG(base) ((base)->AESC_CASR) #define CAU_AESC_CAA_REG(base) ((base)->AESC_CAA) #define CAU_AESC_CA_REG(base,index) ((base)->AESC_CA[index]) #define CAU_AESIC_CASR_REG(base) ((base)->AESIC_CASR) #define CAU_AESIC_CAA_REG(base) ((base)->AESIC_CAA) #define CAU_AESIC_CA_REG(base,index) ((base)->AESIC_CA[index]) /*! * @} */ /* end of group CAU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CAU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CAU_Register_Masks CAU Register Masks * @{ */ /* DIRECT Bit Fields */ #define CAU_DIRECT_CAU_DIRECT0_MASK 0xFFFFFFFFu #define CAU_DIRECT_CAU_DIRECT0_SHIFT 0 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x))<CR0) #define CMP_CR1_REG(base) ((base)->CR1) #define CMP_FPR_REG(base) ((base)->FPR) #define CMP_SCR_REG(base) ((base)->SCR) #define CMP_DACCR_REG(base) ((base)->DACCR) #define CMP_MUXCR_REG(base) ((base)->MUXCR) /*! * @} */ /* end of group CMP_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CMP Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMP_Register_Masks CMP Register Masks * @{ */ /* CR0 Bit Fields */ #define CMP_CR0_HYSTCTR_MASK 0x3u #define CMP_CR0_HYSTCTR_SHIFT 0 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<CGH1) #define CMT_CGL1_REG(base) ((base)->CGL1) #define CMT_CGH2_REG(base) ((base)->CGH2) #define CMT_CGL2_REG(base) ((base)->CGL2) #define CMT_OC_REG(base) ((base)->OC) #define CMT_MSC_REG(base) ((base)->MSC) #define CMT_CMD1_REG(base) ((base)->CMD1) #define CMT_CMD2_REG(base) ((base)->CMD2) #define CMT_CMD3_REG(base) ((base)->CMD3) #define CMT_CMD4_REG(base) ((base)->CMD4) #define CMT_PPS_REG(base) ((base)->PPS) #define CMT_DMA_REG(base) ((base)->DMA) /*! * @} */ /* end of group CMT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CMT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CMT_Register_Masks CMT Register Masks * @{ */ /* CGH1 Bit Fields */ #define CMT_CGH1_PH_MASK 0xFFu #define CMT_CGH1_PH_SHIFT 0 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x))<ACCESS16BIT.DATAL) #define CRC_DATAH_REG(base) ((base)->ACCESS16BIT.DATAH) #define CRC_DATA_REG(base) ((base)->DATA) #define CRC_DATALL_REG(base) ((base)->ACCESS8BIT.DATALL) #define CRC_DATALU_REG(base) ((base)->ACCESS8BIT.DATALU) #define CRC_DATAHL_REG(base) ((base)->ACCESS8BIT.DATAHL) #define CRC_DATAHU_REG(base) ((base)->ACCESS8BIT.DATAHU) #define CRC_GPOLYL_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYL) #define CRC_GPOLYH_REG(base) ((base)->GPOLY_ACCESS16BIT.GPOLYH) #define CRC_GPOLY_REG(base) ((base)->GPOLY) #define CRC_GPOLYLL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLL) #define CRC_GPOLYLU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYLU) #define CRC_GPOLYHL_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHL) #define CRC_GPOLYHU_REG(base) ((base)->GPOLY_ACCESS8BIT.GPOLYHU) #define CRC_CTRL_REG(base) ((base)->CTRL) #define CRC_CTRLHU_REG(base) ((base)->CTRL_ACCESS8BIT.CTRLHU) /*! * @} */ /* end of group CRC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- CRC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup CRC_Register_Masks CRC Register Masks * @{ */ /* DATAL Bit Fields */ #define CRC_DATAL_DATAL_MASK 0xFFFFu #define CRC_DATAL_DATAL_SHIFT 0 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x))<DAT[index].DATL) #define DAC_DATH_REG(base,index) ((base)->DAT[index].DATH) #define DAC_SR_REG(base) ((base)->SR) #define DAC_C0_REG(base) ((base)->C0) #define DAC_C1_REG(base) ((base)->C1) #define DAC_C2_REG(base) ((base)->C2) /*! * @} */ /* end of group DAC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DAC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DAC_Register_Masks DAC Register Masks * @{ */ /* DATL Bit Fields */ #define DAC_DATL_DATA0_MASK 0xFFu #define DAC_DATL_DATA0_SHIFT 0 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<CR) #define DMA_ES_REG(base) ((base)->ES) #define DMA_ERQ_REG(base) ((base)->ERQ) #define DMA_EEI_REG(base) ((base)->EEI) #define DMA_CEEI_REG(base) ((base)->CEEI) #define DMA_SEEI_REG(base) ((base)->SEEI) #define DMA_CERQ_REG(base) ((base)->CERQ) #define DMA_SERQ_REG(base) ((base)->SERQ) #define DMA_CDNE_REG(base) ((base)->CDNE) #define DMA_SSRT_REG(base) ((base)->SSRT) #define DMA_CERR_REG(base) ((base)->CERR) #define DMA_CINT_REG(base) ((base)->CINT) #define DMA_INT_REG(base) ((base)->INT) #define DMA_ERR_REG(base) ((base)->ERR) #define DMA_HRS_REG(base) ((base)->HRS) #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) #define DMA_DCHPRI7_REG(base) ((base)->DCHPRI7) #define DMA_DCHPRI6_REG(base) ((base)->DCHPRI6) #define DMA_DCHPRI5_REG(base) ((base)->DCHPRI5) #define DMA_DCHPRI4_REG(base) ((base)->DCHPRI4) #define DMA_DCHPRI11_REG(base) ((base)->DCHPRI11) #define DMA_DCHPRI10_REG(base) ((base)->DCHPRI10) #define DMA_DCHPRI9_REG(base) ((base)->DCHPRI9) #define DMA_DCHPRI8_REG(base) ((base)->DCHPRI8) #define DMA_DCHPRI15_REG(base) ((base)->DCHPRI15) #define DMA_DCHPRI14_REG(base) ((base)->DCHPRI14) #define DMA_DCHPRI13_REG(base) ((base)->DCHPRI13) #define DMA_DCHPRI12_REG(base) ((base)->DCHPRI12) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) /*! * @} */ /* end of group DMA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /* CR Bit Fields */ #define DMA_CR_EDBG_MASK 0x2u #define DMA_CR_EDBG_SHIFT 1 #define DMA_CR_ERCA_MASK 0x4u #define DMA_CR_ERCA_SHIFT 2 #define DMA_CR_HOE_MASK 0x10u #define DMA_CR_HOE_SHIFT 4 #define DMA_CR_HALT_MASK 0x20u #define DMA_CR_HALT_SHIFT 5 #define DMA_CR_CLM_MASK 0x40u #define DMA_CR_CLM_SHIFT 6 #define DMA_CR_EMLM_MASK 0x80u #define DMA_CR_EMLM_SHIFT 7 #define DMA_CR_ECX_MASK 0x10000u #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 #define DMA_ES_SBE_MASK 0x2u #define DMA_ES_SBE_SHIFT 1 #define DMA_ES_SGE_MASK 0x4u #define DMA_ES_SGE_SHIFT 2 #define DMA_ES_NCE_MASK 0x8u #define DMA_ES_NCE_SHIFT 3 #define DMA_ES_DOE_MASK 0x10u #define DMA_ES_DOE_SHIFT 4 #define DMA_ES_DAE_MASK 0x20u #define DMA_ES_DAE_SHIFT 5 #define DMA_ES_SOE_MASK 0x40u #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 #define DMA_ES_ERRCHN_MASK 0xF00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<CHCFG[index]) /*! * @} */ /* end of group DMAMUX_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMAMUX Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks * @{ */ /* CHCFG Bit Fields */ #define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu #define DMAMUX_CHCFG_SOURCE_SHIFT 0 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<EIR) #define ENET_EIMR_REG(base) ((base)->EIMR) #define ENET_RDAR_REG(base) ((base)->RDAR) #define ENET_TDAR_REG(base) ((base)->TDAR) #define ENET_ECR_REG(base) ((base)->ECR) #define ENET_MMFR_REG(base) ((base)->MMFR) #define ENET_MSCR_REG(base) ((base)->MSCR) #define ENET_MIBC_REG(base) ((base)->MIBC) #define ENET_RCR_REG(base) ((base)->RCR) #define ENET_TCR_REG(base) ((base)->TCR) #define ENET_PALR_REG(base) ((base)->PALR) #define ENET_PAUR_REG(base) ((base)->PAUR) #define ENET_OPD_REG(base) ((base)->OPD) #define ENET_IAUR_REG(base) ((base)->IAUR) #define ENET_IALR_REG(base) ((base)->IALR) #define ENET_GAUR_REG(base) ((base)->GAUR) #define ENET_GALR_REG(base) ((base)->GALR) #define ENET_TFWR_REG(base) ((base)->TFWR) #define ENET_RDSR_REG(base) ((base)->RDSR) #define ENET_TDSR_REG(base) ((base)->TDSR) #define ENET_MRBR_REG(base) ((base)->MRBR) #define ENET_RSFL_REG(base) ((base)->RSFL) #define ENET_RSEM_REG(base) ((base)->RSEM) #define ENET_RAEM_REG(base) ((base)->RAEM) #define ENET_RAFL_REG(base) ((base)->RAFL) #define ENET_TSEM_REG(base) ((base)->TSEM) #define ENET_TAEM_REG(base) ((base)->TAEM) #define ENET_TAFL_REG(base) ((base)->TAFL) #define ENET_TIPG_REG(base) ((base)->TIPG) #define ENET_FTRL_REG(base) ((base)->FTRL) #define ENET_TACC_REG(base) ((base)->TACC) #define ENET_RACC_REG(base) ((base)->RACC) #define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) #define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) #define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) #define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) #define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) #define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) #define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) #define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) #define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) #define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) #define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) #define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) #define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) #define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) #define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) #define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) #define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) #define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) #define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) #define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) #define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) #define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) #define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) #define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) #define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) #define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) #define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) #define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) #define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) #define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) #define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) #define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) #define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) #define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) #define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) #define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) #define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) #define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) #define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) #define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) #define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) #define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) #define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) #define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) #define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) #define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) #define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) #define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) #define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) #define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) #define ENET_ATCR_REG(base) ((base)->ATCR) #define ENET_ATVR_REG(base) ((base)->ATVR) #define ENET_ATOFF_REG(base) ((base)->ATOFF) #define ENET_ATPER_REG(base) ((base)->ATPER) #define ENET_ATCOR_REG(base) ((base)->ATCOR) #define ENET_ATINC_REG(base) ((base)->ATINC) #define ENET_ATSTMP_REG(base) ((base)->ATSTMP) #define ENET_TGSR_REG(base) ((base)->TGSR) #define ENET_TCSR_REG(base,index) ((base)->CHANNEL[index].TCSR) #define ENET_TCCR_REG(base,index) ((base)->CHANNEL[index].TCCR) /*! * @} */ /* end of group ENET_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- ENET Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup ENET_Register_Masks ENET Register Masks * @{ */ /* EIR Bit Fields */ #define ENET_EIR_TS_TIMER_MASK 0x8000u #define ENET_EIR_TS_TIMER_SHIFT 15 #define ENET_EIR_TS_AVAIL_MASK 0x10000u #define ENET_EIR_TS_AVAIL_SHIFT 16 #define ENET_EIR_WAKEUP_MASK 0x20000u #define ENET_EIR_WAKEUP_SHIFT 17 #define ENET_EIR_PLR_MASK 0x40000u #define ENET_EIR_PLR_SHIFT 18 #define ENET_EIR_UN_MASK 0x80000u #define ENET_EIR_UN_SHIFT 19 #define ENET_EIR_RL_MASK 0x100000u #define ENET_EIR_RL_SHIFT 20 #define ENET_EIR_LC_MASK 0x200000u #define ENET_EIR_LC_SHIFT 21 #define ENET_EIR_EBERR_MASK 0x400000u #define ENET_EIR_EBERR_SHIFT 22 #define ENET_EIR_MII_MASK 0x800000u #define ENET_EIR_MII_SHIFT 23 #define ENET_EIR_RXB_MASK 0x1000000u #define ENET_EIR_RXB_SHIFT 24 #define ENET_EIR_RXF_MASK 0x2000000u #define ENET_EIR_RXF_SHIFT 25 #define ENET_EIR_TXB_MASK 0x4000000u #define ENET_EIR_TXB_SHIFT 26 #define ENET_EIR_TXF_MASK 0x8000000u #define ENET_EIR_TXF_SHIFT 27 #define ENET_EIR_GRA_MASK 0x10000000u #define ENET_EIR_GRA_SHIFT 28 #define ENET_EIR_BABT_MASK 0x20000000u #define ENET_EIR_BABT_SHIFT 29 #define ENET_EIR_BABR_MASK 0x40000000u #define ENET_EIR_BABR_SHIFT 30 /* EIMR Bit Fields */ #define ENET_EIMR_TS_TIMER_MASK 0x8000u #define ENET_EIMR_TS_TIMER_SHIFT 15 #define ENET_EIMR_TS_AVAIL_MASK 0x10000u #define ENET_EIMR_TS_AVAIL_SHIFT 16 #define ENET_EIMR_WAKEUP_MASK 0x20000u #define ENET_EIMR_WAKEUP_SHIFT 17 #define ENET_EIMR_PLR_MASK 0x40000u #define ENET_EIMR_PLR_SHIFT 18 #define ENET_EIMR_UN_MASK 0x80000u #define ENET_EIMR_UN_SHIFT 19 #define ENET_EIMR_RL_MASK 0x100000u #define ENET_EIMR_RL_SHIFT 20 #define ENET_EIMR_LC_MASK 0x200000u #define ENET_EIMR_LC_SHIFT 21 #define ENET_EIMR_EBERR_MASK 0x400000u #define ENET_EIMR_EBERR_SHIFT 22 #define ENET_EIMR_MII_MASK 0x800000u #define ENET_EIMR_MII_SHIFT 23 #define ENET_EIMR_RXB_MASK 0x1000000u #define ENET_EIMR_RXB_SHIFT 24 #define ENET_EIMR_RXF_MASK 0x2000000u #define ENET_EIMR_RXF_SHIFT 25 #define ENET_EIMR_TXB_MASK 0x4000000u #define ENET_EIMR_TXB_SHIFT 26 #define ENET_EIMR_TXF_MASK 0x8000000u #define ENET_EIMR_TXF_SHIFT 27 #define ENET_EIMR_GRA_MASK 0x10000000u #define ENET_EIMR_GRA_SHIFT 28 #define ENET_EIMR_BABT_MASK 0x20000000u #define ENET_EIMR_BABT_SHIFT 29 #define ENET_EIMR_BABR_MASK 0x40000000u #define ENET_EIMR_BABR_SHIFT 30 /* RDAR Bit Fields */ #define ENET_RDAR_RDAR_MASK 0x1000000u #define ENET_RDAR_RDAR_SHIFT 24 /* TDAR Bit Fields */ #define ENET_TDAR_TDAR_MASK 0x1000000u #define ENET_TDAR_TDAR_SHIFT 24 /* ECR Bit Fields */ #define ENET_ECR_RESET_MASK 0x1u #define ENET_ECR_RESET_SHIFT 0 #define ENET_ECR_ETHEREN_MASK 0x2u #define ENET_ECR_ETHEREN_SHIFT 1 #define ENET_ECR_MAGICEN_MASK 0x4u #define ENET_ECR_MAGICEN_SHIFT 2 #define ENET_ECR_SLEEP_MASK 0x8u #define ENET_ECR_SLEEP_SHIFT 3 #define ENET_ECR_EN1588_MASK 0x10u #define ENET_ECR_EN1588_SHIFT 4 #define ENET_ECR_DBGEN_MASK 0x40u #define ENET_ECR_DBGEN_SHIFT 6 #define ENET_ECR_STOPEN_MASK 0x80u #define ENET_ECR_STOPEN_SHIFT 7 #define ENET_ECR_DBSWP_MASK 0x100u #define ENET_ECR_DBSWP_SHIFT 8 /* MMFR Bit Fields */ #define ENET_MMFR_DATA_MASK 0xFFFFu #define ENET_MMFR_DATA_SHIFT 0 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) #define EWM_SERV_REG(base) ((base)->SERV) #define EWM_CMPL_REG(base) ((base)->CMPL) #define EWM_CMPH_REG(base) ((base)->CMPH) /*! * @} */ /* end of group EWM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- EWM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup EWM_Register_Masks EWM Register Masks * @{ */ /* CTRL Bit Fields */ #define EWM_CTRL_EWMEN_MASK 0x1u #define EWM_CTRL_EWMEN_SHIFT 0 #define EWM_CTRL_ASSIN_MASK 0x2u #define EWM_CTRL_ASSIN_SHIFT 1 #define EWM_CTRL_INEN_MASK 0x4u #define EWM_CTRL_INEN_SHIFT 2 #define EWM_CTRL_INTEN_MASK 0x8u #define EWM_CTRL_INTEN_SHIFT 3 /* SERV Bit Fields */ #define EWM_SERV_SERVICE_MASK 0xFFu #define EWM_SERV_SERVICE_SHIFT 0 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x))<CS[index].CSAR) #define FB_CSMR_REG(base,index) ((base)->CS[index].CSMR) #define FB_CSCR_REG(base,index) ((base)->CS[index].CSCR) #define FB_CSPMCR_REG(base) ((base)->CSPMCR) /*! * @} */ /* end of group FB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FB_Register_Masks FB Register Masks * @{ */ /* CSAR Bit Fields */ #define FB_CSAR_BA_MASK 0xFFFF0000u #define FB_CSAR_BA_SHIFT 16 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x))<PFAPR) #define FMC_PFB0CR_REG(base) ((base)->PFB0CR) #define FMC_PFB1CR_REG(base) ((base)->PFB1CR) #define FMC_TAGVDW0S_REG(base,index) ((base)->TAGVDW0S[index]) #define FMC_TAGVDW1S_REG(base,index) ((base)->TAGVDW1S[index]) #define FMC_TAGVDW2S_REG(base,index) ((base)->TAGVDW2S[index]) #define FMC_TAGVDW3S_REG(base,index) ((base)->TAGVDW3S[index]) #define FMC_DATA_U_REG(base,index,index2) ((base)->SET[index][index2].DATA_U) #define FMC_DATA_L_REG(base,index,index2) ((base)->SET[index][index2].DATA_L) /*! * @} */ /* end of group FMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FMC_Register_Masks FMC Register Masks * @{ */ /* PFAPR Bit Fields */ #define FMC_PFAPR_M0AP_MASK 0x3u #define FMC_PFAPR_M0AP_SHIFT 0 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x))<FSTAT) #define FTFE_FCNFG_REG(base) ((base)->FCNFG) #define FTFE_FSEC_REG(base) ((base)->FSEC) #define FTFE_FOPT_REG(base) ((base)->FOPT) #define FTFE_FCCOB3_REG(base) ((base)->FCCOB3) #define FTFE_FCCOB2_REG(base) ((base)->FCCOB2) #define FTFE_FCCOB1_REG(base) ((base)->FCCOB1) #define FTFE_FCCOB0_REG(base) ((base)->FCCOB0) #define FTFE_FCCOB7_REG(base) ((base)->FCCOB7) #define FTFE_FCCOB6_REG(base) ((base)->FCCOB6) #define FTFE_FCCOB5_REG(base) ((base)->FCCOB5) #define FTFE_FCCOB4_REG(base) ((base)->FCCOB4) #define FTFE_FCCOBB_REG(base) ((base)->FCCOBB) #define FTFE_FCCOBA_REG(base) ((base)->FCCOBA) #define FTFE_FCCOB9_REG(base) ((base)->FCCOB9) #define FTFE_FCCOB8_REG(base) ((base)->FCCOB8) #define FTFE_FPROT3_REG(base) ((base)->FPROT3) #define FTFE_FPROT2_REG(base) ((base)->FPROT2) #define FTFE_FPROT1_REG(base) ((base)->FPROT1) #define FTFE_FPROT0_REG(base) ((base)->FPROT0) #define FTFE_FEPROT_REG(base) ((base)->FEPROT) #define FTFE_FDPROT_REG(base) ((base)->FDPROT) /*! * @} */ /* end of group FTFE_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTFE Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTFE_Register_Masks FTFE Register Masks * @{ */ /* FSTAT Bit Fields */ #define FTFE_FSTAT_MGSTAT0_MASK 0x1u #define FTFE_FSTAT_MGSTAT0_SHIFT 0 #define FTFE_FSTAT_FPVIOL_MASK 0x10u #define FTFE_FSTAT_FPVIOL_SHIFT 4 #define FTFE_FSTAT_ACCERR_MASK 0x20u #define FTFE_FSTAT_ACCERR_SHIFT 5 #define FTFE_FSTAT_RDCOLERR_MASK 0x40u #define FTFE_FSTAT_RDCOLERR_SHIFT 6 #define FTFE_FSTAT_CCIF_MASK 0x80u #define FTFE_FSTAT_CCIF_SHIFT 7 /* FCNFG Bit Fields */ #define FTFE_FCNFG_EEERDY_MASK 0x1u #define FTFE_FCNFG_EEERDY_SHIFT 0 #define FTFE_FCNFG_RAMRDY_MASK 0x2u #define FTFE_FCNFG_RAMRDY_SHIFT 1 #define FTFE_FCNFG_PFLSH_MASK 0x4u #define FTFE_FCNFG_PFLSH_SHIFT 2 #define FTFE_FCNFG_SWAP_MASK 0x8u #define FTFE_FCNFG_SWAP_SHIFT 3 #define FTFE_FCNFG_ERSSUSP_MASK 0x10u #define FTFE_FCNFG_ERSSUSP_SHIFT 4 #define FTFE_FCNFG_ERSAREQ_MASK 0x20u #define FTFE_FCNFG_ERSAREQ_SHIFT 5 #define FTFE_FCNFG_RDCOLLIE_MASK 0x40u #define FTFE_FCNFG_RDCOLLIE_SHIFT 6 #define FTFE_FCNFG_CCIE_MASK 0x80u #define FTFE_FCNFG_CCIE_SHIFT 7 /* FSEC Bit Fields */ #define FTFE_FSEC_SEC_MASK 0x3u #define FTFE_FSEC_SEC_SHIFT 0 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<SC) #define FTM_CNT_REG(base) ((base)->CNT) #define FTM_MOD_REG(base) ((base)->MOD) #define FTM_CnSC_REG(base,index) ((base)->CONTROLS[index].CnSC) #define FTM_CnV_REG(base,index) ((base)->CONTROLS[index].CnV) #define FTM_CNTIN_REG(base) ((base)->CNTIN) #define FTM_STATUS_REG(base) ((base)->STATUS) #define FTM_MODE_REG(base) ((base)->MODE) #define FTM_SYNC_REG(base) ((base)->SYNC) #define FTM_OUTINIT_REG(base) ((base)->OUTINIT) #define FTM_OUTMASK_REG(base) ((base)->OUTMASK) #define FTM_COMBINE_REG(base) ((base)->COMBINE) #define FTM_DEADTIME_REG(base) ((base)->DEADTIME) #define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) #define FTM_POL_REG(base) ((base)->POL) #define FTM_FMS_REG(base) ((base)->FMS) #define FTM_FILTER_REG(base) ((base)->FILTER) #define FTM_FLTCTRL_REG(base) ((base)->FLTCTRL) #define FTM_QDCTRL_REG(base) ((base)->QDCTRL) #define FTM_CONF_REG(base) ((base)->CONF) #define FTM_FLTPOL_REG(base) ((base)->FLTPOL) #define FTM_SYNCONF_REG(base) ((base)->SYNCONF) #define FTM_INVCTRL_REG(base) ((base)->INVCTRL) #define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) #define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) /*! * @} */ /* end of group FTM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- FTM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup FTM_Register_Masks FTM Register Masks * @{ */ /* SC Bit Fields */ #define FTM_SC_PS_MASK 0x7u #define FTM_SC_PS_SHIFT 0 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<PDOR) #define GPIO_PSOR_REG(base) ((base)->PSOR) #define GPIO_PCOR_REG(base) ((base)->PCOR) #define GPIO_PTOR_REG(base) ((base)->PTOR) #define GPIO_PDIR_REG(base) ((base)->PDIR) #define GPIO_PDDR_REG(base) ((base)->PDDR) /*! * @} */ /* end of group GPIO_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- GPIO Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup GPIO_Register_Masks GPIO Register Masks * @{ */ /* PDOR Bit Fields */ #define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu #define GPIO_PDOR_PDO_SHIFT 0 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<A1) #define I2C_F_REG(base) ((base)->F) #define I2C_C1_REG(base) ((base)->C1) #define I2C_S_REG(base) ((base)->S) #define I2C_D_REG(base) ((base)->D) #define I2C_C2_REG(base) ((base)->C2) #define I2C_FLT_REG(base) ((base)->FLT) #define I2C_RA_REG(base) ((base)->RA) #define I2C_SMB_REG(base) ((base)->SMB) #define I2C_A2_REG(base) ((base)->A2) #define I2C_SLTH_REG(base) ((base)->SLTH) #define I2C_SLTL_REG(base) ((base)->SLTL) /*! * @} */ /* end of group I2C_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2C Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2C_Register_Masks I2C Register Masks * @{ */ /* A1 Bit Fields */ #define I2C_A1_AD_MASK 0xFEu #define I2C_A1_AD_SHIFT 1 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<TCSR) #define I2S_TCR1_REG(base) ((base)->TCR1) #define I2S_TCR2_REG(base) ((base)->TCR2) #define I2S_TCR3_REG(base) ((base)->TCR3) #define I2S_TCR4_REG(base) ((base)->TCR4) #define I2S_TCR5_REG(base) ((base)->TCR5) #define I2S_TDR_REG(base,index) ((base)->TDR[index]) #define I2S_TFR_REG(base,index) ((base)->TFR[index]) #define I2S_TMR_REG(base) ((base)->TMR) #define I2S_RCSR_REG(base) ((base)->RCSR) #define I2S_RCR1_REG(base) ((base)->RCR1) #define I2S_RCR2_REG(base) ((base)->RCR2) #define I2S_RCR3_REG(base) ((base)->RCR3) #define I2S_RCR4_REG(base) ((base)->RCR4) #define I2S_RCR5_REG(base) ((base)->RCR5) #define I2S_RDR_REG(base,index) ((base)->RDR[index]) #define I2S_RFR_REG(base,index) ((base)->RFR[index]) #define I2S_RMR_REG(base) ((base)->RMR) #define I2S_MCR_REG(base) ((base)->MCR) #define I2S_MDR_REG(base) ((base)->MDR) /*! * @} */ /* end of group I2S_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- I2S Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup I2S_Register_Masks I2S Register Masks * @{ */ /* TCSR Bit Fields */ #define I2S_TCSR_FRDE_MASK 0x1u #define I2S_TCSR_FRDE_SHIFT 0 #define I2S_TCSR_FWDE_MASK 0x2u #define I2S_TCSR_FWDE_SHIFT 1 #define I2S_TCSR_FRIE_MASK 0x100u #define I2S_TCSR_FRIE_SHIFT 8 #define I2S_TCSR_FWIE_MASK 0x200u #define I2S_TCSR_FWIE_SHIFT 9 #define I2S_TCSR_FEIE_MASK 0x400u #define I2S_TCSR_FEIE_SHIFT 10 #define I2S_TCSR_SEIE_MASK 0x800u #define I2S_TCSR_SEIE_SHIFT 11 #define I2S_TCSR_WSIE_MASK 0x1000u #define I2S_TCSR_WSIE_SHIFT 12 #define I2S_TCSR_FRF_MASK 0x10000u #define I2S_TCSR_FRF_SHIFT 16 #define I2S_TCSR_FWF_MASK 0x20000u #define I2S_TCSR_FWF_SHIFT 17 #define I2S_TCSR_FEF_MASK 0x40000u #define I2S_TCSR_FEF_SHIFT 18 #define I2S_TCSR_SEF_MASK 0x80000u #define I2S_TCSR_SEF_SHIFT 19 #define I2S_TCSR_WSF_MASK 0x100000u #define I2S_TCSR_WSF_SHIFT 20 #define I2S_TCSR_SR_MASK 0x1000000u #define I2S_TCSR_SR_SHIFT 24 #define I2S_TCSR_FR_MASK 0x2000000u #define I2S_TCSR_FR_SHIFT 25 #define I2S_TCSR_BCE_MASK 0x10000000u #define I2S_TCSR_BCE_SHIFT 28 #define I2S_TCSR_DBGE_MASK 0x20000000u #define I2S_TCSR_DBGE_SHIFT 29 #define I2S_TCSR_STOPE_MASK 0x40000000u #define I2S_TCSR_STOPE_SHIFT 30 #define I2S_TCSR_TE_MASK 0x80000000u #define I2S_TCSR_TE_SHIFT 31 /* TCR1 Bit Fields */ #define I2S_TCR1_TFW_MASK 0x7u #define I2S_TCR1_TFW_SHIFT 0 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<PE1) #define LLWU_PE2_REG(base) ((base)->PE2) #define LLWU_PE3_REG(base) ((base)->PE3) #define LLWU_PE4_REG(base) ((base)->PE4) #define LLWU_ME_REG(base) ((base)->ME) #define LLWU_F1_REG(base) ((base)->F1) #define LLWU_F2_REG(base) ((base)->F2) #define LLWU_F3_REG(base) ((base)->F3) #define LLWU_FILT1_REG(base) ((base)->FILT1) #define LLWU_FILT2_REG(base) ((base)->FILT2) #define LLWU_RST_REG(base) ((base)->RST) /*! * @} */ /* end of group LLWU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LLWU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LLWU_Register_Masks LLWU Register Masks * @{ */ /* PE1 Bit Fields */ #define LLWU_PE1_WUPE0_MASK 0x3u #define LLWU_PE1_WUPE0_SHIFT 0 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<CSR) #define LPTMR_PSR_REG(base) ((base)->PSR) #define LPTMR_CMR_REG(base) ((base)->CMR) #define LPTMR_CNR_REG(base) ((base)->CNR) /*! * @} */ /* end of group LPTMR_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- LPTMR Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup LPTMR_Register_Masks LPTMR Register Masks * @{ */ /* CSR Bit Fields */ #define LPTMR_CSR_TEN_MASK 0x1u #define LPTMR_CSR_TEN_SHIFT 0 #define LPTMR_CSR_TMS_MASK 0x2u #define LPTMR_CSR_TMS_SHIFT 1 #define LPTMR_CSR_TFC_MASK 0x4u #define LPTMR_CSR_TFC_SHIFT 2 #define LPTMR_CSR_TPP_MASK 0x8u #define LPTMR_CSR_TPP_SHIFT 3 #define LPTMR_CSR_TPS_MASK 0x30u #define LPTMR_CSR_TPS_SHIFT 4 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<C1) #define MCG_C2_REG(base) ((base)->C2) #define MCG_C3_REG(base) ((base)->C3) #define MCG_C4_REG(base) ((base)->C4) #define MCG_C5_REG(base) ((base)->C5) #define MCG_C6_REG(base) ((base)->C6) #define MCG_S_REG(base) ((base)->S) #define MCG_SC_REG(base) ((base)->SC) #define MCG_ATCVH_REG(base) ((base)->ATCVH) #define MCG_ATCVL_REG(base) ((base)->ATCVL) #define MCG_C7_REG(base) ((base)->C7) #define MCG_C8_REG(base) ((base)->C8) /*! * @} */ /* end of group MCG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCG_Register_Masks MCG Register Masks * @{ */ /* C1 Bit Fields */ #define MCG_C1_IREFSTEN_MASK 0x1u #define MCG_C1_IREFSTEN_SHIFT 0 #define MCG_C1_IRCLKEN_MASK 0x2u #define MCG_C1_IRCLKEN_SHIFT 1 #define MCG_C1_IREFS_MASK 0x4u #define MCG_C1_IREFS_SHIFT 2 #define MCG_C1_FRDIV_MASK 0x38u #define MCG_C1_FRDIV_SHIFT 3 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<PLASC) #define MCM_PLAMC_REG(base) ((base)->PLAMC) #define MCM_CR_REG(base) ((base)->CR) #define MCM_ISCR_REG(base) ((base)->ISCR) #define MCM_ETBCC_REG(base) ((base)->ETBCC) #define MCM_ETBRL_REG(base) ((base)->ETBRL) #define MCM_ETBCNT_REG(base) ((base)->ETBCNT) #define MCM_PID_REG(base) ((base)->PID) /*! * @} */ /* end of group MCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MCM_Register_Masks MCM Register Masks * @{ */ /* PLASC Bit Fields */ #define MCM_PLASC_ASC_MASK 0xFFu #define MCM_PLASC_ASC_SHIFT 0 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CESR) #define MPU_EAR_REG(base,index) ((base)->SP[index].EAR) #define MPU_EDR_REG(base,index) ((base)->SP[index].EDR) #define MPU_WORD_REG(base,index,index2) ((base)->WORD[index][index2]) #define MPU_RGDAAC_REG(base,index) ((base)->RGDAAC[index]) /*! * @} */ /* end of group MPU_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- MPU Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup MPU_Register_Masks MPU Register Masks * @{ */ /* CESR Bit Fields */ #define MPU_CESR_VLD_MASK 0x1u #define MPU_CESR_VLD_SHIFT 0 #define MPU_CESR_NRGD_MASK 0xF00u #define MPU_CESR_NRGD_SHIFT 8 #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x))<BACKKEY3) #define NV_BACKKEY2_REG(base) ((base)->BACKKEY2) #define NV_BACKKEY1_REG(base) ((base)->BACKKEY1) #define NV_BACKKEY0_REG(base) ((base)->BACKKEY0) #define NV_BACKKEY7_REG(base) ((base)->BACKKEY7) #define NV_BACKKEY6_REG(base) ((base)->BACKKEY6) #define NV_BACKKEY5_REG(base) ((base)->BACKKEY5) #define NV_BACKKEY4_REG(base) ((base)->BACKKEY4) #define NV_FPROT3_REG(base) ((base)->FPROT3) #define NV_FPROT2_REG(base) ((base)->FPROT2) #define NV_FPROT1_REG(base) ((base)->FPROT1) #define NV_FPROT0_REG(base) ((base)->FPROT0) #define NV_FSEC_REG(base) ((base)->FSEC) #define NV_FOPT_REG(base) ((base)->FOPT) #define NV_FEPROT_REG(base) ((base)->FEPROT) #define NV_FDPROT_REG(base) ((base)->FDPROT) /*! * @} */ /* end of group NV_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- NV Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup NV_Register_Masks NV Register Masks * @{ */ /* BACKKEY3 Bit Fields */ #define NV_BACKKEY3_KEY_MASK 0xFFu #define NV_BACKKEY3_KEY_SHIFT 0 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<CR) /*! * @} */ /* end of group OSC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- OSC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Masks OSC Register Masks * @{ */ /* CR Bit Fields */ #define OSC_CR_SC16P_MASK 0x1u #define OSC_CR_SC16P_SHIFT 0 #define OSC_CR_SC8P_MASK 0x2u #define OSC_CR_SC8P_SHIFT 1 #define OSC_CR_SC4P_MASK 0x4u #define OSC_CR_SC4P_SHIFT 2 #define OSC_CR_SC2P_MASK 0x8u #define OSC_CR_SC2P_SHIFT 3 #define OSC_CR_EREFSTEN_MASK 0x20u #define OSC_CR_EREFSTEN_SHIFT 5 #define OSC_CR_ERCLKEN_MASK 0x80u #define OSC_CR_ERCLKEN_SHIFT 7 /*! * @} */ /* end of group OSC_Register_Masks */ /* OSC - Peripheral instance base addresses */ /** Peripheral OSC base address */ #define OSC_BASE (0x40065000u) /** Peripheral OSC base pointer */ #define OSC ((OSC_Type *)OSC_BASE) #define OSC_BASE_PTR (OSC) /** Array initializer of OSC peripheral base addresses */ #define OSC_BASE_ADDRS { OSC_BASE } /** Array initializer of OSC peripheral base pointers */ #define OSC_BASE_PTRS { OSC } /* ---------------------------------------------------------------------------- -- OSC - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup OSC_Register_Accessor_Macros OSC - Register accessor macros * @{ */ /* OSC - Register instance definitions */ /* OSC */ #define OSC_CR OSC_CR_REG(OSC) /*! * @} */ /* end of group OSC_Register_Accessor_Macros */ /*! * @} */ /* end of group OSC_Peripheral_Access_Layer */ /* ---------------------------------------------------------------------------- -- PDB Peripheral Access Layer ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer * @{ */ /** PDB - Register Layout Typedef */ typedef struct { __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */ __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */ __I uint32_t CNT; /**< Counter register, offset: 0x8 */ __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */ struct { /* offset: 0x10, array step: 0x28 */ __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */ __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */ __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */ uint8_t RESERVED_0[24]; } CH[2]; uint8_t RESERVED_0[240]; struct { /* offset: 0x150, array step: 0x8 */ __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */ __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */ } DAC[2]; uint8_t RESERVED_1[48]; __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */ __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */ } PDB_Type, *PDB_MemMapPtr; /* ---------------------------------------------------------------------------- -- PDB - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Register_Accessor_Macros PDB - Register accessor macros * @{ */ /* PDB - Register accessors */ #define PDB_SC_REG(base) ((base)->SC) #define PDB_MOD_REG(base) ((base)->MOD) #define PDB_CNT_REG(base) ((base)->CNT) #define PDB_IDLY_REG(base) ((base)->IDLY) #define PDB_C1_REG(base,index) ((base)->CH[index].C1) #define PDB_S_REG(base,index) ((base)->CH[index].S) #define PDB_DLY_REG(base,index,index2) ((base)->CH[index].DLY[index2]) #define PDB_INTC_REG(base,index) ((base)->DAC[index].INTC) #define PDB_INT_REG(base,index) ((base)->DAC[index].INT) #define PDB_POEN_REG(base) ((base)->POEN) #define PDB_PODLY_REG(base,index) ((base)->PODLY[index]) /*! * @} */ /* end of group PDB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PDB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PDB_Register_Masks PDB Register Masks * @{ */ /* SC Bit Fields */ #define PDB_SC_LDOK_MASK 0x1u #define PDB_SC_LDOK_SHIFT 0 #define PDB_SC_CONT_MASK 0x2u #define PDB_SC_CONT_SHIFT 1 #define PDB_SC_MULT_MASK 0xCu #define PDB_SC_MULT_SHIFT 2 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x))<MCR) #define PIT_LDVAL_REG(base,index) ((base)->CHANNEL[index].LDVAL) #define PIT_CVAL_REG(base,index) ((base)->CHANNEL[index].CVAL) #define PIT_TCTRL_REG(base,index) ((base)->CHANNEL[index].TCTRL) #define PIT_TFLG_REG(base,index) ((base)->CHANNEL[index].TFLG) /*! * @} */ /* end of group PIT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PIT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PIT_Register_Masks PIT Register Masks * @{ */ /* MCR Bit Fields */ #define PIT_MCR_FRZ_MASK 0x1u #define PIT_MCR_FRZ_SHIFT 0 #define PIT_MCR_MDIS_MASK 0x2u #define PIT_MCR_MDIS_SHIFT 1 /* LDVAL Bit Fields */ #define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu #define PIT_LDVAL_TSV_SHIFT 0 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<LVDSC1) #define PMC_LVDSC2_REG(base) ((base)->LVDSC2) #define PMC_REGSC_REG(base) ((base)->REGSC) /*! * @} */ /* end of group PMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PMC_Register_Masks PMC Register Masks * @{ */ /* LVDSC1 Bit Fields */ #define PMC_LVDSC1_LVDV_MASK 0x3u #define PMC_LVDSC1_LVDV_SHIFT 0 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<PCR[index]) #define PORT_GPCLR_REG(base) ((base)->GPCLR) #define PORT_GPCHR_REG(base) ((base)->GPCHR) #define PORT_ISFR_REG(base) ((base)->ISFR) #define PORT_DFER_REG(base) ((base)->DFER) #define PORT_DFCR_REG(base) ((base)->DFCR) #define PORT_DFWR_REG(base) ((base)->DFWR) /*! * @} */ /* end of group PORT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- PORT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup PORT_Register_Masks PORT Register Masks * @{ */ /* PCR Bit Fields */ #define PORT_PCR_PS_MASK 0x1u #define PORT_PCR_PS_SHIFT 0 #define PORT_PCR_PE_MASK 0x2u #define PORT_PCR_PE_SHIFT 1 #define PORT_PCR_SRE_MASK 0x4u #define PORT_PCR_SRE_SHIFT 2 #define PORT_PCR_PFE_MASK 0x10u #define PORT_PCR_PFE_SHIFT 4 #define PORT_PCR_ODE_MASK 0x20u #define PORT_PCR_ODE_SHIFT 5 #define PORT_PCR_DSE_MASK 0x40u #define PORT_PCR_DSE_SHIFT 6 #define PORT_PCR_MUX_MASK 0x700u #define PORT_PCR_MUX_SHIFT 8 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<SRS0) #define RCM_SRS1_REG(base) ((base)->SRS1) #define RCM_RPFC_REG(base) ((base)->RPFC) #define RCM_RPFW_REG(base) ((base)->RPFW) #define RCM_MR_REG(base) ((base)->MR) /*! * @} */ /* end of group RCM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RCM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RCM_Register_Masks RCM Register Masks * @{ */ /* SRS0 Bit Fields */ #define RCM_SRS0_WAKEUP_MASK 0x1u #define RCM_SRS0_WAKEUP_SHIFT 0 #define RCM_SRS0_LVD_MASK 0x2u #define RCM_SRS0_LVD_SHIFT 1 #define RCM_SRS0_LOC_MASK 0x4u #define RCM_SRS0_LOC_SHIFT 2 #define RCM_SRS0_LOL_MASK 0x8u #define RCM_SRS0_LOL_SHIFT 3 #define RCM_SRS0_WDOG_MASK 0x20u #define RCM_SRS0_WDOG_SHIFT 5 #define RCM_SRS0_PIN_MASK 0x40u #define RCM_SRS0_PIN_SHIFT 6 #define RCM_SRS0_POR_MASK 0x80u #define RCM_SRS0_POR_SHIFT 7 /* SRS1 Bit Fields */ #define RCM_SRS1_JTAG_MASK 0x1u #define RCM_SRS1_JTAG_SHIFT 0 #define RCM_SRS1_LOCKUP_MASK 0x2u #define RCM_SRS1_LOCKUP_SHIFT 1 #define RCM_SRS1_SW_MASK 0x4u #define RCM_SRS1_SW_SHIFT 2 #define RCM_SRS1_MDM_AP_MASK 0x8u #define RCM_SRS1_MDM_AP_SHIFT 3 #define RCM_SRS1_EZPT_MASK 0x10u #define RCM_SRS1_EZPT_SHIFT 4 #define RCM_SRS1_SACKERR_MASK 0x20u #define RCM_SRS1_SACKERR_SHIFT 5 /* RPFC Bit Fields */ #define RCM_RPFC_RSTFLTSRW_MASK 0x3u #define RCM_RPFC_RSTFLTSRW_SHIFT 0 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<REG[index]) /*! * @} */ /* end of group RFSYS_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RFSYS Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RFSYS_Register_Masks RFSYS Register Masks * @{ */ /* REG Bit Fields */ #define RFSYS_REG_LL_MASK 0xFFu #define RFSYS_REG_LL_SHIFT 0 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x))<REG[index]) /*! * @} */ /* end of group RFVBAT_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RFVBAT Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks * @{ */ /* REG Bit Fields */ #define RFVBAT_REG_LL_MASK 0xFFu #define RFVBAT_REG_LL_SHIFT 0 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x))<CR) #define RNG_SR_REG(base) ((base)->SR) #define RNG_ER_REG(base) ((base)->ER) #define RNG_OR_REG(base) ((base)->OR) /*! * @} */ /* end of group RNG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RNG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RNG_Register_Masks RNG Register Masks * @{ */ /* CR Bit Fields */ #define RNG_CR_GO_MASK 0x1u #define RNG_CR_GO_SHIFT 0 #define RNG_CR_HA_MASK 0x2u #define RNG_CR_HA_SHIFT 1 #define RNG_CR_INTM_MASK 0x4u #define RNG_CR_INTM_SHIFT 2 #define RNG_CR_CLRI_MASK 0x8u #define RNG_CR_CLRI_SHIFT 3 #define RNG_CR_SLP_MASK 0x10u #define RNG_CR_SLP_SHIFT 4 /* SR Bit Fields */ #define RNG_SR_SECV_MASK 0x1u #define RNG_SR_SECV_SHIFT 0 #define RNG_SR_LRS_MASK 0x2u #define RNG_SR_LRS_SHIFT 1 #define RNG_SR_ORU_MASK 0x4u #define RNG_SR_ORU_SHIFT 2 #define RNG_SR_ERRI_MASK 0x8u #define RNG_SR_ERRI_SHIFT 3 #define RNG_SR_SLP_MASK 0x10u #define RNG_SR_SLP_SHIFT 4 #define RNG_SR_OREG_LVL_MASK 0xFF00u #define RNG_SR_OREG_LVL_SHIFT 8 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x))<TSR) #define RTC_TPR_REG(base) ((base)->TPR) #define RTC_TAR_REG(base) ((base)->TAR) #define RTC_TCR_REG(base) ((base)->TCR) #define RTC_CR_REG(base) ((base)->CR) #define RTC_SR_REG(base) ((base)->SR) #define RTC_LR_REG(base) ((base)->LR) #define RTC_IER_REG(base) ((base)->IER) #define RTC_WAR_REG(base) ((base)->WAR) #define RTC_RAR_REG(base) ((base)->RAR) /*! * @} */ /* end of group RTC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- RTC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup RTC_Register_Masks RTC Register Masks * @{ */ /* TSR Bit Fields */ #define RTC_TSR_TSR_MASK 0xFFFFFFFFu #define RTC_TSR_TSR_SHIFT 0 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<DSADDR) #define SDHC_BLKATTR_REG(base) ((base)->BLKATTR) #define SDHC_CMDARG_REG(base) ((base)->CMDARG) #define SDHC_XFERTYP_REG(base) ((base)->XFERTYP) #define SDHC_CMDRSP_REG(base,index) ((base)->CMDRSP[index]) #define SDHC_DATPORT_REG(base) ((base)->DATPORT) #define SDHC_PRSSTAT_REG(base) ((base)->PRSSTAT) #define SDHC_PROCTL_REG(base) ((base)->PROCTL) #define SDHC_SYSCTL_REG(base) ((base)->SYSCTL) #define SDHC_IRQSTAT_REG(base) ((base)->IRQSTAT) #define SDHC_IRQSTATEN_REG(base) ((base)->IRQSTATEN) #define SDHC_IRQSIGEN_REG(base) ((base)->IRQSIGEN) #define SDHC_AC12ERR_REG(base) ((base)->AC12ERR) #define SDHC_HTCAPBLT_REG(base) ((base)->HTCAPBLT) #define SDHC_WML_REG(base) ((base)->WML) #define SDHC_FEVT_REG(base) ((base)->FEVT) #define SDHC_ADMAES_REG(base) ((base)->ADMAES) #define SDHC_ADSADDR_REG(base) ((base)->ADSADDR) #define SDHC_VENDOR_REG(base) ((base)->VENDOR) #define SDHC_MMCBOOT_REG(base) ((base)->MMCBOOT) #define SDHC_HOSTVER_REG(base) ((base)->HOSTVER) /*! * @} */ /* end of group SDHC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SDHC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SDHC_Register_Masks SDHC Register Masks * @{ */ /* DSADDR Bit Fields */ #define SDHC_DSADDR_DSADDR_MASK 0xFFFFFFFCu #define SDHC_DSADDR_DSADDR_SHIFT 2 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x))<SOPT1) #define SIM_SOPT1CFG_REG(base) ((base)->SOPT1CFG) #define SIM_SOPT2_REG(base) ((base)->SOPT2) #define SIM_SOPT4_REG(base) ((base)->SOPT4) #define SIM_SOPT5_REG(base) ((base)->SOPT5) #define SIM_SOPT7_REG(base) ((base)->SOPT7) #define SIM_SDID_REG(base) ((base)->SDID) #define SIM_SCGC1_REG(base) ((base)->SCGC1) #define SIM_SCGC2_REG(base) ((base)->SCGC2) #define SIM_SCGC3_REG(base) ((base)->SCGC3) #define SIM_SCGC4_REG(base) ((base)->SCGC4) #define SIM_SCGC5_REG(base) ((base)->SCGC5) #define SIM_SCGC6_REG(base) ((base)->SCGC6) #define SIM_SCGC7_REG(base) ((base)->SCGC7) #define SIM_CLKDIV1_REG(base) ((base)->CLKDIV1) #define SIM_CLKDIV2_REG(base) ((base)->CLKDIV2) #define SIM_FCFG1_REG(base) ((base)->FCFG1) #define SIM_FCFG2_REG(base) ((base)->FCFG2) #define SIM_UIDH_REG(base) ((base)->UIDH) #define SIM_UIDMH_REG(base) ((base)->UIDMH) #define SIM_UIDML_REG(base) ((base)->UIDML) #define SIM_UIDL_REG(base) ((base)->UIDL) /*! * @} */ /* end of group SIM_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SIM Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SIM_Register_Masks SIM Register Masks * @{ */ /* SOPT1 Bit Fields */ #define SIM_SOPT1_RAMSIZE_MASK 0xF000u #define SIM_SOPT1_RAMSIZE_SHIFT 12 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x))<PMPROT) #define SMC_PMCTRL_REG(base) ((base)->PMCTRL) #define SMC_VLLSCTRL_REG(base) ((base)->VLLSCTRL) #define SMC_PMSTAT_REG(base) ((base)->PMSTAT) /*! * @} */ /* end of group SMC_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SMC Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SMC_Register_Masks SMC Register Masks * @{ */ /* PMPROT Bit Fields */ #define SMC_PMPROT_AVLLS_MASK 0x2u #define SMC_PMPROT_AVLLS_SHIFT 1 #define SMC_PMPROT_ALLS_MASK 0x8u #define SMC_PMPROT_ALLS_SHIFT 3 #define SMC_PMPROT_AVLP_MASK 0x20u #define SMC_PMPROT_AVLP_SHIFT 5 /* PMCTRL Bit Fields */ #define SMC_PMCTRL_STOPM_MASK 0x7u #define SMC_PMCTRL_STOPM_SHIFT 0 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<MCR) #define SPI_TCR_REG(base) ((base)->TCR) #define SPI_CTAR_REG(base,index2) ((base)->CTAR[index2]) #define SPI_CTAR_SLAVE_REG(base,index2) ((base)->CTAR_SLAVE[index2]) #define SPI_SR_REG(base) ((base)->SR) #define SPI_RSER_REG(base) ((base)->RSER) #define SPI_PUSHR_REG(base) ((base)->PUSHR) #define SPI_PUSHR_SLAVE_REG(base) ((base)->PUSHR_SLAVE) #define SPI_POPR_REG(base) ((base)->POPR) #define SPI_TXFR0_REG(base) ((base)->TXFR0) #define SPI_TXFR1_REG(base) ((base)->TXFR1) #define SPI_TXFR2_REG(base) ((base)->TXFR2) #define SPI_TXFR3_REG(base) ((base)->TXFR3) #define SPI_RXFR0_REG(base) ((base)->RXFR0) #define SPI_RXFR1_REG(base) ((base)->RXFR1) #define SPI_RXFR2_REG(base) ((base)->RXFR2) #define SPI_RXFR3_REG(base) ((base)->RXFR3) /*! * @} */ /* end of group SPI_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- SPI Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup SPI_Register_Masks SPI Register Masks * @{ */ /* MCR Bit Fields */ #define SPI_MCR_HALT_MASK 0x1u #define SPI_MCR_HALT_SHIFT 0 #define SPI_MCR_SMPL_PT_MASK 0x300u #define SPI_MCR_SMPL_PT_SHIFT 8 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x))<BDH) #define UART_BDL_REG(base) ((base)->BDL) #define UART_C1_REG(base) ((base)->C1) #define UART_C2_REG(base) ((base)->C2) #define UART_S1_REG(base) ((base)->S1) #define UART_S2_REG(base) ((base)->S2) #define UART_C3_REG(base) ((base)->C3) #define UART_D_REG(base) ((base)->D) #define UART_MA1_REG(base) ((base)->MA1) #define UART_MA2_REG(base) ((base)->MA2) #define UART_C4_REG(base) ((base)->C4) #define UART_C5_REG(base) ((base)->C5) #define UART_ED_REG(base) ((base)->ED) #define UART_MODEM_REG(base) ((base)->MODEM) #define UART_IR_REG(base) ((base)->IR) #define UART_PFIFO_REG(base) ((base)->PFIFO) #define UART_CFIFO_REG(base) ((base)->CFIFO) #define UART_SFIFO_REG(base) ((base)->SFIFO) #define UART_TWFIFO_REG(base) ((base)->TWFIFO) #define UART_TCFIFO_REG(base) ((base)->TCFIFO) #define UART_RWFIFO_REG(base) ((base)->RWFIFO) #define UART_RCFIFO_REG(base) ((base)->RCFIFO) #define UART_C7816_REG(base) ((base)->C7816) #define UART_IE7816_REG(base) ((base)->IE7816) #define UART_IS7816_REG(base) ((base)->IS7816) #define UART_WP7816T0_REG(base) ((base)->WP7816T0) #define UART_WP7816T1_REG(base) ((base)->WP7816T1) #define UART_WN7816_REG(base) ((base)->WN7816) #define UART_WF7816_REG(base) ((base)->WF7816) #define UART_ET7816_REG(base) ((base)->ET7816) #define UART_TL7816_REG(base) ((base)->TL7816) /*! * @} */ /* end of group UART_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- UART Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup UART_Register_Masks UART Register Masks * @{ */ /* BDH Bit Fields */ #define UART_BDH_SBR_MASK 0x1Fu #define UART_BDH_SBR_SHIFT 0 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<PERID) #define USB_IDCOMP_REG(base) ((base)->IDCOMP) #define USB_REV_REG(base) ((base)->REV) #define USB_ADDINFO_REG(base) ((base)->ADDINFO) #define USB_OTGISTAT_REG(base) ((base)->OTGISTAT) #define USB_OTGICR_REG(base) ((base)->OTGICR) #define USB_OTGSTAT_REG(base) ((base)->OTGSTAT) #define USB_OTGCTL_REG(base) ((base)->OTGCTL) #define USB_ISTAT_REG(base) ((base)->ISTAT) #define USB_INTEN_REG(base) ((base)->INTEN) #define USB_ERRSTAT_REG(base) ((base)->ERRSTAT) #define USB_ERREN_REG(base) ((base)->ERREN) #define USB_STAT_REG(base) ((base)->STAT) #define USB_CTL_REG(base) ((base)->CTL) #define USB_ADDR_REG(base) ((base)->ADDR) #define USB_BDTPAGE1_REG(base) ((base)->BDTPAGE1) #define USB_FRMNUML_REG(base) ((base)->FRMNUML) #define USB_FRMNUMH_REG(base) ((base)->FRMNUMH) #define USB_TOKEN_REG(base) ((base)->TOKEN) #define USB_SOFTHLD_REG(base) ((base)->SOFTHLD) #define USB_BDTPAGE2_REG(base) ((base)->BDTPAGE2) #define USB_BDTPAGE3_REG(base) ((base)->BDTPAGE3) #define USB_ENDPT_REG(base,index) ((base)->ENDPOINT[index].ENDPT) #define USB_USBCTRL_REG(base) ((base)->USBCTRL) #define USB_OBSERVE_REG(base) ((base)->OBSERVE) #define USB_CONTROL_REG(base) ((base)->CONTROL) #define USB_USBTRC0_REG(base) ((base)->USBTRC0) #define USB_USBFRMADJUST_REG(base) ((base)->USBFRMADJUST) #define USB_CLK_RECOVER_CTRL_REG(base) ((base)->CLK_RECOVER_CTRL) #define USB_CLK_RECOVER_IRC_EN_REG(base) ((base)->CLK_RECOVER_IRC_EN) #define USB_CLK_RECOVER_INT_STATUS_REG(base) ((base)->CLK_RECOVER_INT_STATUS) /*! * @} */ /* end of group USB_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USB Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USB_Register_Masks USB Register Masks * @{ */ /* PERID Bit Fields */ #define USB_PERID_ID_MASK 0x3Fu #define USB_PERID_ID_SHIFT 0 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<CONTROL) #define USBDCD_CLOCK_REG(base) ((base)->CLOCK) #define USBDCD_STATUS_REG(base) ((base)->STATUS) #define USBDCD_TIMER0_REG(base) ((base)->TIMER0) #define USBDCD_TIMER1_REG(base) ((base)->TIMER1) #define USBDCD_TIMER2_BC11_REG(base) ((base)->TIMER2_BC11) #define USBDCD_TIMER2_BC12_REG(base) ((base)->TIMER2_BC12) /*! * @} */ /* end of group USBDCD_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- USBDCD Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup USBDCD_Register_Masks USBDCD Register Masks * @{ */ /* CONTROL Bit Fields */ #define USBDCD_CONTROL_IACK_MASK 0x1u #define USBDCD_CONTROL_IACK_SHIFT 0 #define USBDCD_CONTROL_IF_MASK 0x100u #define USBDCD_CONTROL_IF_SHIFT 8 #define USBDCD_CONTROL_IE_MASK 0x10000u #define USBDCD_CONTROL_IE_SHIFT 16 #define USBDCD_CONTROL_BC12_MASK 0x20000u #define USBDCD_CONTROL_BC12_SHIFT 17 #define USBDCD_CONTROL_START_MASK 0x1000000u #define USBDCD_CONTROL_START_SHIFT 24 #define USBDCD_CONTROL_SR_MASK 0x2000000u #define USBDCD_CONTROL_SR_SHIFT 25 /* CLOCK Bit Fields */ #define USBDCD_CLOCK_CLOCK_UNIT_MASK 0x1u #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT 0 #define USBDCD_CLOCK_CLOCK_SPEED_MASK 0xFFCu #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT 2 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x))<TRM) #define VREF_SC_REG(base) ((base)->SC) /*! * @} */ /* end of group VREF_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- VREF Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup VREF_Register_Masks VREF Register Masks * @{ */ /* TRM Bit Fields */ #define VREF_TRM_TRIM_MASK 0x3Fu #define VREF_TRM_TRIM_SHIFT 0 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x))<STCTRLH) #define WDOG_STCTRLL_REG(base) ((base)->STCTRLL) #define WDOG_TOVALH_REG(base) ((base)->TOVALH) #define WDOG_TOVALL_REG(base) ((base)->TOVALL) #define WDOG_WINH_REG(base) ((base)->WINH) #define WDOG_WINL_REG(base) ((base)->WINL) #define WDOG_REFRESH_REG(base) ((base)->REFRESH) #define WDOG_UNLOCK_REG(base) ((base)->UNLOCK) #define WDOG_TMROUTH_REG(base) ((base)->TMROUTH) #define WDOG_TMROUTL_REG(base) ((base)->TMROUTL) #define WDOG_RSTCNT_REG(base) ((base)->RSTCNT) #define WDOG_PRESC_REG(base) ((base)->PRESC) /*! * @} */ /* end of group WDOG_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- WDOG Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup WDOG_Register_Masks WDOG Register Masks * @{ */ /* STCTRLH Bit Fields */ #define WDOG_STCTRLH_WDOGEN_MASK 0x1u #define WDOG_STCTRLH_WDOGEN_SHIFT 0 #define WDOG_STCTRLH_CLKSRC_MASK 0x2u #define WDOG_STCTRLH_CLKSRC_SHIFT 1 #define WDOG_STCTRLH_IRQRSTEN_MASK 0x4u #define WDOG_STCTRLH_IRQRSTEN_SHIFT 2 #define WDOG_STCTRLH_WINEN_MASK 0x8u #define WDOG_STCTRLH_WINEN_SHIFT 3 #define WDOG_STCTRLH_ALLOWUPDATE_MASK 0x10u #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT 4 #define WDOG_STCTRLH_DBGEN_MASK 0x20u #define WDOG_STCTRLH_DBGEN_SHIFT 5 #define WDOG_STCTRLH_STOPEN_MASK 0x40u #define WDOG_STCTRLH_STOPEN_SHIFT 6 #define WDOG_STCTRLH_WAITEN_MASK 0x80u #define WDOG_STCTRLH_WAITEN_SHIFT 7 #define WDOG_STCTRLH_TESTWDOG_MASK 0x400u #define WDOG_STCTRLH_TESTWDOG_SHIFT 10 #define WDOG_STCTRLH_TESTSEL_MASK 0x800u #define WDOG_STCTRLH_TESTSEL_SHIFT 11 #define WDOG_STCTRLH_BYTESEL_MASK 0x3000u #define WDOG_STCTRLH_BYTESEL_SHIFT 12 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x))<