3 .word ( 0x0260 | 1<<0 | 5<<2 | 1<<7 | 3<<10 )
4 ; reserved_bits | security_off | lvr_1v8 | io_drv_norm | boot_fast
7 notes: .ds 16 ; 0x00 .. 0x0f
12 .even ; make next two bytes word-aligned
19 .even ; SP must be aligned
24 ; aliases for memory locations:
49 ; Calibration Parameters:
50 ; Bitshift Variations calls for an 8kHz sample rate; with an interrupt every
51 ; 512 cycles (the next power of two above the 495 cycles the program needs for
52 ; execution), this gives us a clock speed of 512 * 8khz = 4.096MHz. The MCU
53 ; will be powered by a 3V lithium coin cell.
54 calib_freq = 4096000 ; Hz
58 ; during playback: IHRC/4, WDT off, keep ILRC on
59 active_clock = (( 0<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 ))
60 ; during deep-sleep: ILRC/1, WDT off
61 sleep_clock = (( 7<<5 | 1<<4 | 0<<3 | 1<<2 | 0<<1 | 0<<0 ))
62 ; for extra power saving, consider: 6<<5|0<<3 for ilrc/6, 2<<5|1<<3 for ilrc/16
64 ; cycle count (worst-case)
67 ; sample: 115 + 4*g + 2*mod3 = 495
69 ; TOTAL: sample + overhead = 507
84 ADD mod3lo, a ; mod3lo = hi+lo
92 AND a, #0xf ; (mod3lo>>4)
93 XCH mod3lo ; a=mod3lo, mod3lo=mod3lo>>4
94 AND a, #0xF ; a=mod3lo&0xf, mod3lo=mod3lo>>4
95 ADD a, mod3lo ; (mod3lo & 0xF)
99 AND a, #0x3 ; a = (mod3lo & 0x3)
101 SR mod3lo ; (mod3lo >> 2)
105 AND a, #0x3 ; a = (mod3lo & 0x3)
107 SR mod3lo ; (mod3lo >> 2)
116 ; notes_ix_hi = always 0
129 ; note: LSB of result (mul0) is not needed for our purposes
204 SET1 clkmd, #4 ; enable IHRC
206 MOV clkmd, a ; switch to IHRC
208 ;; .org 0xe8 ; comment out on 2nd iteration
209 ;; ; calibration placeholder:
213 ;; AND a, #( calib_freq )
214 ;; AND a, #( calib_freq>>8 )
215 ;; AND a, #( calib_freq>>16 )
216 ;; AND a, #( calib_freq>>24 )
217 ;; AND a, #( calib_vdd )
218 ;; AND a, #( calib_vdd>>8 )
227 MOV a, #0x50 ; data direction: PWM & debug output, rest input
228 MOV pac, a ; (conserves power, apparently)
230 MOV padier, a ; disable pin wakeup, except on audio pin
231 MOV pa, a ; PortA data = 0
232 MOV paph, a ; disable all pull-ups
235 ; Since (unlike in the ATTiny4 version) the interrupt timer is not tied
236 ; to the PWM frequency, we can use a much faster clock for PWM. The
237 ; highest "carrier frequency" for the PCM samples we can generate is by
238 ; setting Timer2 to 6 bit, (IHRC/1)/1 mode, giving a frequency of
239 ; (4*4.096MHz)/2^6 = 256kHz.
242 MOV a, #(( 2<<4 | 3<<2 | 1<<1 | 0<<0 ))
243 MOV tm2c, a ; timer2: IHRC, PA4, PWM, not inverted
244 MOV a, #(( 0<<7 | 1<<5 | 0<<0 ))
245 MOV tm2s, a ; 8bit, /4 prescaler, divide by (0+1)
246 ;XXX: increase pwm base frequency (/1) -> (4*4.096mhz)/(2^8) = 64khz
249 ;mov a, #(( 0<<0 | 1<<3 | 4<<5 )) ; ovf@bit8 (512cy; §9.2.5), clk/4, ihrc
250 MOV a, #(( 1<<0 | 1<<3 | 4<<5 )) ; ovf@bit9 (???cy; §9.2.5), clk/4, ihrc
251 ;XXX: datasheet §5.10.1 says bit8 = 256cycles, 9.2.5 says bit8=512cy
252 ; note: ovf@bit9 causes 4khz isr => we need ovf@bit8.
254 MOV a, #(1<<2) ; enable timer16 int, disable all others
258 SET1 eoscr, #0 ; disable bandgap and lvr
259 SET0 gpcc, #7 ; disable comparator
266 ;rom is not mmapped; must load notes into ram first
295 CEQSN a, #0x78 ; compare, skip next if equal
296 ; Note: usually, this is the place where the MCU is put into some
297 ; sort of low power/sleep mode. But the Padauk's stopexe instruction
298 ; causes the ISR to a) run at greatly reduced frequency (100hz vs
299 ; 1khz for timer16@bit11; probably due to slow wakeup), b)
300 ; double-fire some (20-30%) of the time, c) jitter -50% to +10%. so
301 ; we don't sleep at all between samples (which is only a short time
305 ; at this point, i2==0x78, i.e. the music is finished.
306 ; => goto halt (fallthrough)
309 CLEAR i2 ; clear halting signal
311 ; Note: disabling the timers isn't strictly necessary (as stopsys halts
312 ; all timers anyways), but I'm hoping it may reduce power consumption.
313 ; We're lucky that we only need to toggle a single bit to switch
314 ; between the required clock source and 'off' (0010xxxx->0000xxxx for
315 ; timer2, 100xxxxx->000xxxxx for timer16), so we can hack our way out
316 ; of loading an immediate each time.
320 SET1 pa, #4 ; assert a high level on the audio pin for good measure
321 SET0 pac, #4 ; ... before setting it to input mode (optional)
323 ;switch to ilrc clock
326 SET0 clkmd, #4 ; disable ihrc
329 ; (at this point, we wait for an i/o-toggle wake up event to resume execution)
332 MOV clkmd, a ; switch to IHRC again
334 SET1 pac, #4 ; restore output mode for audio pin
336 ;reenable timer16, timer2
345 T1SN intrq, #2 ; if intrq.t16 is triggered, skip next
353 ; send pwm data to timer2:
358 ; generate new sample:
359 MOV a, i2; "mov mem,mem"
360 MOV n, a; does not exist
380 MOV tmp_1, a ; fresh tmp_1:
385 OR a, tmp_1 ; tmp_1 done.
413 MOV tmp_1, a ; a saved in tmp_1; fresh a
415 ; shift-divide by six
416 ; note: i2 is max 0x78; so a will <= 20. (breaks vor values >=128)
429 AND a, tmp_1 ; a restored from tmp_1
452 MOV tmp_1, a ; a saved in tmp_1; fresh a
454 ; shift-divide by ten
455 ; note: i2 is max 0x78; so a will <= 12.
468 AND a, tmp_1 ; a restored from tmp_1
474 ; next sample is now ready.