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1 | #include <stdio.h> | |
2 | #include "fakeasm.h" | |
3 | typedef unsigned char u8; | |
4 | ||
5 | u8 data[] = { | |
6 | 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58, | |
7 | 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58 | |
8 | }; | |
9 | u8 zero; //r16 | |
10 | u8 acc; //r17 | |
11 | u8 i0; //r18 | |
12 | u8 i1; //r19 | |
13 | u8 i2; //r20 | |
14 | u8 i3; //r21 | |
15 | u8 n; //r22 | |
16 | u8 s; //r23 | |
17 | u8 _; //r24 | |
18 | u8 loop; //r25 | |
19 | u8 t;/*==Ml*/ //r26 (Xlo) | |
20 | u8 x;/*==Mh*/ //r27 (Xhi) | |
21 | //r28 | |
22 | //r29 | |
23 | /*fakestack_l*/ //r30 (Zlo) | |
24 | /*fakestack_h*/ //r31 (Zhi) | |
25 | #define Mh x //mod3 vars | |
26 | #define Ml t // -"- | |
27 | //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml | |
28 | void mod3(void) { | |
29 | // mod3(Mh.Ml) -> t | |
30 | #define tmp _ | |
31 | ADD (Ml, Mh) | |
32 | CLR (Mh) | |
33 | ADC (Mh, zero, carry) //Mh only holds the carry bit | |
34 | MOV (tmp, Ml) | |
35 | SWAP (tmp) | |
36 | ANDI (tmp, 0x0f) | |
37 | SWAP (Mh) | |
38 | OR (tmp, Mh) | |
39 | ANDI (Ml, 0x0f) | |
40 | ADD (Ml, tmp) | |
41 | MOV (tmp, Ml) | |
42 | LSR (tmp) | |
43 | LSR (tmp) | |
44 | ANDI (Ml, 0x03) | |
45 | ADD (Ml, tmp) | |
46 | MOV (tmp, Ml) | |
47 | LSR (tmp) | |
48 | LSR (tmp) | |
49 | ANDI (Ml, 0x03) | |
50 | ADD (Ml, tmp) | |
51 | CPI (Ml, 3) | |
52 | BRPL (skip) | |
53 | SUBI (Ml, 3) | |
54 | skip:; | |
55 | RET | |
56 | #undef tmp | |
57 | } | |
58 | void g(void) { | |
59 | // g(i, t) -> t | |
60 | // tempvars: `x` and `_` | |
61 | #define tmp _ | |
62 | ANDI (t, 0x07) | |
63 | MOV (tmp, i2) | |
64 | ANDI (tmp, 3) | |
65 | TST (tmp) | |
66 | #undef tmp | |
67 | BREQ (skip) | |
68 | SUBI (t, -8) | |
69 | skip: | |
70 | t = data[t]; | |
71 | /*MOV X_hi==x, data_hi | |
72 | MOV X_lo==t, data_lo | |
73 | ADD X_lo, t | |
74 | ADC X_hi, zero | |
75 | LD t, X */ | |
76 | #define a1 x | |
77 | #define a2 _ | |
78 | #define a0 t | |
79 | // start MUL | |
80 | CLR (a2) | |
81 | CLR (a1) | |
82 | ||
83 | //sorted by ocurrence, then longest cycle count first | |
84 | CPI (t, 0x69) | |
85 | BREQ (mul_69) | |
86 | CPI (t, 0x75) | |
87 | BREQ (mul_75) | |
88 | CPI (t, 0x9d) | |
89 | BREQ (mul_9d) | |
90 | CPI (t, 0x58) | |
91 | BREQ (mul_58) | |
92 | CPI (t, 0x8c) | |
93 | BREQ (mul_8c) | |
94 | CPI (t, 0x84) | |
95 | BREQ (mul_84) | |
96 | CPI (t, 0xb0) | |
97 | BREQ (mul_b0) | |
98 | mul_58: // 0101 1000 (24cy) | |
99 | LSR (a2) | |
100 | ROR (a1) | |
101 | LSR (a2) | |
102 | ROR (a1) | |
103 | LSR (a2) | |
104 | ROR (a1) | |
105 | ADD (a1, i0) | |
106 | ADC (a2, i1, carry) | |
107 | LSR (a2) | |
108 | ROR (a1) | |
109 | ||
110 | ADD (a1, i0) | |
111 | ADC (a2, i1, carry) | |
112 | LSR (a2) | |
113 | ROR (a1) | |
114 | LSR (a2) | |
115 | ROR (a1) | |
116 | ADD (a1, i0) | |
117 | ADC (a2, i1, carry) | |
118 | LSR (a2) | |
119 | ROR (a1) | |
120 | LSR (a2) | |
121 | ROR (a1) | |
122 | RJMP (endmul) | |
123 | mul_69: // 0110 1001 (26cy) | |
124 | ADD (a1, i0) | |
125 | ADC (a2, i1, carry) | |
126 | LSR (a2) | |
127 | ROR (a1) | |
128 | LSR (a2) | |
129 | ROR (a1) | |
130 | LSR (a2) | |
131 | ROR (a1) | |
132 | ADD (a1, i0) | |
133 | ADC (a2, i1, carry) | |
134 | LSR (a2) | |
135 | ROR (a1) | |
136 | ||
137 | LSR (a2) | |
138 | ROR (a1) | |
139 | ADD (a1, i0) | |
140 | ADC (a2, i1, carry) | |
141 | LSR (a2) | |
142 | ROR (a1) | |
143 | ADD (a1, i0) | |
144 | ADC (a2, i1, carry) | |
145 | LSR (a2) | |
146 | ROR (a1) | |
147 | LSR (a2) | |
148 | ROR (a1) | |
149 | RJMP (endmul) | |
150 | mul_75: // 0111 0101 (28cy) | |
151 | ADD (a1, i0) | |
152 | ADC (a2, i1, carry) | |
153 | LSR (a2) | |
154 | ROR (a1) | |
155 | LSR (a2) | |
156 | ROR (a1) | |
157 | ADD (a1, i0) | |
158 | ADC (a2, i1, carry) | |
159 | LSR (a2) | |
160 | ROR (a1) | |
161 | LSR (a2) | |
162 | ROR (a1) | |
163 | ||
164 | ADD (a1, i0) | |
165 | ADC (a2, i1, carry) | |
166 | LSR (a2) | |
167 | ROR (a1) | |
168 | ADD (a1, i0) | |
169 | ADC (a2, i1, carry) | |
170 | LSR (a2) | |
171 | ROR (a1) | |
172 | ADD (a1, i0) | |
173 | ADC (a2, i1, carry) | |
174 | LSR (a2) | |
175 | ROR (a1) | |
176 | LSR (a2) | |
177 | ROR (a1) | |
178 | RJMP (endmul) | |
179 | mul_84: // 1000 0100 (22cy) | |
180 | LSR (a2) | |
181 | ROR (a1) | |
182 | LSR (a2) | |
183 | ROR (a1) | |
184 | ADD (a1, i0) | |
185 | ADC (a2, i1, carry) | |
186 | LSR (a2) | |
187 | ROR (a1) | |
188 | LSR (a2) | |
189 | ROR (a1) | |
190 | ||
191 | LSR (a2) | |
192 | ROR (a1) | |
193 | LSR (a2) | |
194 | ROR (a1) | |
195 | LSR (a2) | |
196 | ROR (a1) | |
197 | ADD (a1, i0) | |
198 | ADC (a2, i1, carry) | |
199 | LSR (a2) | |
200 | ROR (a1) | |
201 | RJMP (endmul) | |
202 | mul_8c: // 1000 1100 (24cy) | |
203 | LSR (a2) | |
204 | ROR (a1) | |
205 | LSR (a2) | |
206 | ROR (a1) | |
207 | ADD (a1, i0) | |
208 | ADC (a2, i1, carry) | |
209 | LSR (a2) | |
210 | ROR (a1) | |
211 | ADD (a1, i0) | |
212 | ADC (a2, i1, carry) | |
213 | LSR (a2) | |
214 | ROR (a1) | |
215 | ||
216 | LSR (a2) | |
217 | ROR (a1) | |
218 | LSR (a2) | |
219 | ROR (a1) | |
220 | LSR (a2) | |
221 | ROR (a1) | |
222 | ADD (a1, i0) | |
223 | ADC (a2, i1, carry) | |
224 | LSR (a2) | |
225 | ROR (a1) | |
226 | RJMP (endmul) | |
227 | mul_9d: // 1001 1101 (28cy) | |
228 | ADD (a1, i0) | |
229 | ADC (a2, i1, carry) | |
230 | LSR (a2) | |
231 | ROR (a1) | |
232 | LSR (a2) | |
233 | ROR (a1) | |
234 | ADD (a1, i0) | |
235 | ADC (a2, i1, carry) | |
236 | LSR (a2) | |
237 | ROR (a1) | |
238 | ADD (a1, i0) | |
239 | ADC (a2, i1, carry) | |
240 | LSR (a2) | |
241 | ROR (a1) | |
242 | ||
243 | ADD (a1, i0) | |
244 | ADC (a2, i1, carry) | |
245 | LSR (a2) | |
246 | ROR (a1) | |
247 | LSR (a2) | |
248 | ROR (a1) | |
249 | LSR (a2) | |
250 | ROR (a1) | |
251 | ADD (a1, i0) | |
252 | ADC (a2, i1, carry) | |
253 | LSR (a2) | |
254 | ROR (a1) | |
255 | RJMP (endmul) | |
256 | mul_b0: // 1011 0000 (22cy) | |
257 | LSR (a2) | |
258 | ROR (a1) | |
259 | LSR (a2) | |
260 | ROR (a1) | |
261 | LSR (a2) | |
262 | ROR (a1) | |
263 | LSR (a2) | |
264 | ROR (a1) | |
265 | ||
266 | ADD (a1, i0) | |
267 | ADC (a2, i1, carry) | |
268 | LSR (a2) | |
269 | ROR (a1) | |
270 | ADD (a1, i0) | |
271 | ADC (a2, i1, carry) | |
272 | LSR (a2) | |
273 | ROR (a1) | |
274 | LSR (a2) | |
275 | ROR (a1) | |
276 | ADD (a1, i0) | |
277 | ADC (a2, i1, carry) | |
278 | LSR (a2) | |
279 | ROR (a1) | |
280 | endmul: | |
281 | // end MUL | |
282 | #undef a0 | |
283 | #undef a1 | |
284 | #undef a2 | |
285 | MOV (t, x) | |
286 | RET //TODO: replace CALL/RET with IJMP? | |
287 | }; | |
288 | ||
289 | int main(void) { | |
290 | CLR (zero) | |
291 | CLR (i0) | |
292 | CLR (i1) | |
293 | CLR (i2) | |
294 | CLR (i3) | |
295 | for (;;) { | |
296 | MOV (n, i2) | |
297 | LSL (n) | |
298 | LSL (n) | |
299 | #define tmp _ | |
300 | MOV (tmp, i1) | |
301 | SWAP (tmp) | |
302 | ANDI (tmp, 0x0f) | |
303 | LSR (tmp) | |
304 | LSR (tmp) | |
305 | OR (n, tmp) | |
306 | #undef tmp | |
307 | MOV (s, i3) | |
308 | LSR (s) | |
309 | ROR (s) | |
310 | ANDI (s, 0x80) | |
311 | #define tmp _ | |
312 | MOV (tmp, i2) | |
313 | LSR (tmp) | |
314 | OR (s, tmp) | |
315 | #undef tmp | |
316 | ||
317 | //voice 1: | |
318 | MOV (t, n) | |
319 | RCALL g(); | |
320 | SWAP (t) | |
321 | ANDI (t, 1) | |
322 | MOV (acc, t) | |
323 | ||
324 | //voice 2: | |
325 | #define tmp _ | |
326 | MOV (tmp, i2) | |
327 | LSL (tmp) | |
328 | LSL (tmp) | |
329 | LSL (tmp) | |
330 | MOV (t, i1) | |
331 | SWAP (t) | |
332 | ANDI (t, 0xf) | |
333 | LSR (t) | |
334 | OR (t, tmp) | |
335 | #undef tmp | |
336 | EOR (t, n) | |
337 | RCALL g(); | |
338 | LSR (t) | |
339 | LSR (t) | |
340 | ANDI (t, 3) | |
341 | AND (t, s) | |
342 | ADD (acc, t) | |
343 | ||
344 | //voice 3: | |
345 | MOV (Ml, i2) | |
346 | SWAP (Ml) | |
347 | ANDI (Ml, 0xf0) | |
348 | LSL (Ml) | |
349 | #define tmp _ | |
350 | MOV (tmp, i1) | |
351 | LSR (tmp) | |
352 | LSR (tmp) | |
353 | LSR (tmp) | |
354 | OR (Ml, tmp) | |
355 | #undef tmp | |
356 | MOV (Mh, i3) | |
357 | SWAP (Mh) | |
358 | ANDI (Mh, 0xf0) | |
359 | LSL (Mh) | |
360 | #define tmp _ | |
361 | MOV (tmp, i2) | |
362 | LSR (tmp) | |
363 | LSR (tmp) | |
364 | LSR (tmp) | |
365 | OR (Mh, tmp) | |
366 | #undef tmp | |
367 | RCALL mod3(); | |
368 | ADD (t, n) | |
369 | RCALL g(); | |
370 | LSR (t) | |
371 | LSR (t) | |
372 | ANDI (t, 3) | |
373 | MOV (x, s) | |
374 | INC (x) | |
375 | #define tmp _ | |
376 | MOV (tmp, x) | |
377 | LSR (tmp) | |
378 | LSR (tmp) | |
379 | ADD (tmp, x) | |
380 | ROR (tmp) | |
381 | LSR (tmp) | |
382 | ADD (tmp, x) | |
383 | ROR (tmp) | |
384 | LSR (tmp) | |
385 | ADD (tmp, x) | |
386 | ROR (tmp) | |
387 | LSR (tmp) | |
388 | AND (t, tmp) | |
389 | #undef tmp | |
390 | ADD (acc, t) | |
391 | ||
392 | //voice 4: | |
393 | MOV (Ml, i2) | |
394 | SWAP (Ml) | |
395 | ANDI (Ml, 0xf0) | |
396 | LSL (Ml) | |
397 | LSL (Ml) | |
398 | #define tmp _ | |
399 | MOV (tmp, i1) | |
400 | LSR (tmp) | |
401 | LSR (tmp) | |
402 | OR (Ml, tmp) | |
403 | #undef tmp | |
404 | MOV (Mh, i3) | |
405 | SWAP (Mh) | |
406 | ANDI (Mh, 0xf0) | |
407 | LSL (Mh) | |
408 | LSL (Mh) | |
409 | #define tmp _ | |
410 | MOV (tmp, i2) | |
411 | LSR (tmp) | |
412 | LSR (tmp) | |
413 | OR (Mh, tmp) | |
414 | #undef tmp | |
415 | RCALL mod3(); | |
416 | SUB (t, n) | |
417 | NEG (t) | |
418 | SUBI (t, -8) | |
419 | RCALL g(); | |
420 | LSR (t) | |
421 | ANDI (t, 3) | |
422 | INC (s) | |
423 | #define tmp _ | |
424 | MOV (tmp, s) | |
425 | LSR (tmp) | |
426 | ADD (tmp, s) | |
427 | ROR (tmp) | |
428 | LSR (tmp) | |
429 | LSR (tmp) | |
430 | ADD (tmp, s) | |
431 | ROR (tmp) | |
432 | ADD (tmp, s) | |
433 | ROR (tmp) | |
434 | LSR (tmp) | |
435 | LSR (tmp) | |
436 | AND (t, tmp) | |
437 | #undef tmp | |
438 | ADD (acc, t) | |
439 | ||
440 | putchar(acc<<4); //TODO | |
441 | SUBI (i0, -1) | |
442 | ADC (i1, zero, !i0) | |
443 | ADC (i2, zero, !i0&&!i1) | |
444 | ADC (i3, zero, !i0&&!i1&&!i2) | |
445 | } | |
446 | } |