new version
[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //zero register
10 u8 i0;
11 u8 i1;
12 u8 i2;
13 u8 i3;
14 u8 x;
15 u8 t;
16 u8 o;
17 u8 _;
18 #define Mh o //mod3 vars
19 #define Ml t // -"-
20 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
21 void mod3(void) {
22 // mod3(Mh.Ml) -> t
23 #define tmp _
24 ADD (Ml, Mh)
25 CLR (Mh)
26 ADC (Mh, zero, carry) //Mh only holds the carry bit
27 MOV (tmp, Ml)
28 SWAP (tmp)
29 ANDI (tmp, 0x0f)
30 SWAP (Mh)
31 OR (tmp, Mh)
32 ANDI (Ml, 0x0f)
33 ADD (Ml, tmp)
34 MOV (tmp, Ml)
35 LSR (tmp)
36 LSR (tmp)
37 ANDI (Ml, 0x03)
38 ADD (Ml, tmp)
39 MOV (tmp, Ml)
40 LSR (tmp)
41 LSR (tmp)
42 ANDI (Ml, 0x03)
43 ADD (Ml, tmp)
44 CPI (Ml, 3)
45 BRPL (skip)
46 SUBI (Ml, 3)
47 skip:;
48 #undef tmp
49 }
50 void g(void) {
51 // g(i, x, t, o) -> t
52 #define tmp _
53 ANDI (t, 0x07)
54 MOV (tmp, i2)
55 ANDI (tmp, 3)
56 TST (tmp)
57 #undef tmp
58 BREQ (skip)
59 SUBI (t, -8)
60 skip:
61 t = data[t];
62 /*MOV X_hi==_, data_hi
63 MOV X_lo==t, data_lo
64 ADD X_lo, t
65 ADC X_hi, zero
66 LD t, X */
67 t = (((i1&0x1f)<<8|i0)*t)>>8; //TODO
68 t >>= o; //NOTE: o == {1, 2, 4}
69 AND (t, x)
70 ANDI (t, 3)
71 RET
72 };
73
74 int main(void) {
75 u8 n;
76 u8 s;
77 u8 acc;
78 //TODO: clear all vars/registers
79 for (;;) {
80 MOV (n, i2)
81 LSL (n)
82 LSL (n)
83 #define tmp acc
84 MOV (tmp, i1)
85 SWAP (tmp)
86 ANDI (tmp, 0x0f)
87 LSR (tmp)
88 LSR (tmp)
89 OR (n, tmp)
90 #undef tmp
91 MOV (s, i3)
92 ROR (s)
93 ROR (s)
94 ANDI (s, 0x80)
95 #define tmp acc
96 MOV (tmp, i2)
97 LSR (tmp)
98 OR (s, tmp)
99 #undef tmp
100
101 //voice 1:
102 LDI (x, 1)
103 MOV (t, n)
104 LDI (o, 4)
105 RCALL g();
106 MOV (acc, t)
107
108 //voice 2:
109 MOV (x, s)
110 #define tmp o
111 MOV (tmp, i2)
112 LSL (tmp)
113 LSL (tmp)
114 LSL (tmp)
115 MOV (t, i1)
116 SWAP (t)
117 ANDI (t, 0xf)
118 LSR (t)
119 OR (t, tmp)
120 #undef tmp
121 EOR (t, n)
122 LDI (o, 2)
123 RCALL g();
124 ADD (acc, t)
125
126 //voice 3:
127 MOV (x, s)
128 INC (x)
129 #define tmp o
130 MOV (tmp, x)
131 LSR (tmp)
132 LSR (tmp)
133 ADD (tmp, x)
134 ROR (tmp)
135 LSR (tmp)
136 ADD (tmp, x)
137 ROR (tmp)
138 LSR (tmp)
139 ADD (tmp, x)
140 ROR (tmp)
141 LSR (tmp)
142 MOV (x, tmp)
143 #undef tmp
144 MOV (Ml, i2)
145 SWAP (Ml)
146 ANDI (Ml, 0xf0)
147 LSL (Ml)
148 #define tmp Mh
149 MOV (tmp, i1)
150 LSR (tmp)
151 LSR (tmp)
152 LSR (tmp)
153 OR (Ml, tmp)
154 #undef tmp
155 MOV (Mh, i3)
156 SWAP (Mh)
157 ANDI (Mh, 0xf0)
158 LSL (Mh)
159 #define tmp _
160 MOV (tmp, i2)
161 LSR (tmp)
162 LSR (tmp)
163 LSR (tmp)
164 OR (Mh, tmp)
165 #undef tmp
166 RCALL mod3();
167 ADD (t, n)
168 LDI (o, 2)
169 RCALL g();
170 ADD (acc, t)
171
172 //voice 4:
173 MOV (x, s)
174 INC (x)
175 #define tmp o
176 MOV (tmp, x)
177 LSR (tmp)
178 ADD (tmp, x)
179 ROR (tmp)
180 LSR (tmp)
181 LSR (tmp)
182 ADD (tmp, x)
183 ROR (tmp)
184 ADD (tmp, x)
185 ROR (tmp)
186 LSR (tmp)
187 LSR (tmp)
188 MOV (x, tmp)
189 #undef tmp
190 MOV (Ml, i2)
191 SWAP (Ml)
192 ANDI (Ml, 0xf0)
193 LSL (Ml)
194 LSL (Ml)
195 #define tmp Mh
196 MOV (tmp, i1)
197 LSR (tmp)
198 LSR (tmp)
199 OR (Ml, tmp)
200 #undef tmp
201 MOV (Mh, i3)
202 SWAP (Mh)
203 ANDI (Mh, 0xf0)
204 LSL (Mh)
205 LSL (Mh)
206 #define tmp _
207 MOV (tmp, i2)
208 LSR (tmp)
209 LSR (tmp)
210 OR (Mh, tmp)
211 #undef tmp
212 RCALL mod3();
213 SUB (t, n)
214 NEG (t)
215 SUBI (t, -8)
216 LDI (o, 1)
217 RCALL g();
218 ADD (acc, t)
219
220 putchar(acc<<4); //TODO
221 SUBI (i0, -1)
222 ADC (i1, zero, !i0)
223 ADC (i2, zero, !i0&&!i1)
224 ADC (i3, zero, !i0&&!i1&&!i2)
225 }
226 }
Imprint / Impressum