10 #define x r24 //==a1==Mh
19 #define Ml t //mod3 vars
21 #define a1 x //mul_ vars
44 .org 0x0000 ; RESET interrupt
49 .org 0x0008 ; TIM0_OVF interrupt
53 .byte 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58
54 .byte 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
56 mod3: ; mod3(Mh.Ml) -> t
60 ADC Mh, Mh ; store carry in Mh
85 ; definitions to mul-tree readable:
86 .macro always _bit ; nop; for when a test() is not necessary (see tree)
88 .macro never _bit ; nop; for when a test() is not necessary (see tree)
90 .macro test _bit,_jmpto
94 .macro i_test _bit,_jmpto ; inverted test (for reordered 0x8_)
102 .macro shift8 ; top three bits don't need to be corrrect, so save cycles by not carrying
105 .macro shift0 ; nop; last shift is common
111 .macro add8 ; ditto with carrying
128 ;TODO: check correctness!
130 ADD Xlo, t ; NOTE: can't overflow, since RAMEND == 0x5F
135 /* decision tree multiplication saves cycles and (hopefully) reduces code size
142 _?000 _?100 _?001 _?101
144 _0000 _1000 _0100 _1100 _1001 _0101 _1101
146 ... ... ... ... ... ... ...
148 B0 58 84 8C 69 75 9D */
165 RJMP end_mul ; calc'd 0xb0
167 m_1000: add16 $ shift16
176 RJMP end_mul ; calc'd 0x58
178 m__100: add16 $ shift16
190 RJMP end_mul ; calc'd 0x8c / 0x84
192 m____1: add16 $ shift16
198 m_1001: add16 $ shift16
207 RJMP end_mul ; calc'd 0x69
209 m__101: add16 $ shift16
220 RJMP end_mul ; calc'd 0x75
222 m_1101: add16 $ shift16
234 LSR a1 ;final shift is a common operation for all
236 MOV t, a1 ;;TODO: use a1 in loop: directly
239 main: ; setup routine
240 ; NOTE: clr i0..i2 moved to .ord 0x0
242 CLR acc ; we output a dummy sample before the actual first one
243 LDI Xhi, hi8(FLASHM + notes) ; never changes
244 LDI one, 1 ; mostly for clearing TIM0_OVF bit
248 OUT SPL, x ; init stack ptr
250 OUT PUEB, zero ; disable pullups
252 OUT DDRB, x ; PORTB0:pwm, PORTB2:debug
254 OUT CCP, x ; change protected ioregs
255 OUT CLKPSR, one ; clock prescaler 1/2 (4Mhz)
256 LDI x, 0xa7 ; determined by trial-and-error (->PORTB2)
257 OUT OSCCAL, x ; set oscillator calibration
258 OUT WDTCSR, zero; turn off watchdog
260 ;set timer/counter0 to 8bit fastpwm, non-inverting, no prescaler
265 OUT TIMSK0, one ; enable tim0_ovf
270 SLEEP ; wait for interrupt
274 OUT OCR0AL, acc ; start by outputting a sample, because routine has variable runtime
276 SBI PORTB, 2 ; to measure runtime
423 SWAP acc ; acc<<4, to be passed to OCR0AL
431 CBI PORTB, 2 ; end runtime measurement
433 OUT TIFR0, one ; clear pending interrupt (routine takes two intr.cycles)
434 RETI ; reenables interrupts