6509ba8a220b10ae30fdda173f39df19ac91ada9
[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //r16
10 u8 acc; //r17
11 u8 i0; //r18
12 u8 i1; //r19
13 u8 i2; //r20
14 u8 i3; //r21
15 u8 n; //r22
16 u8 s; //r23
17 u8 _; //r24
18 //r25
19 u8 t;/*==Ml*/ //r26 (Xlo)
20 u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23 /*fakestack_l*/ //r30 (Zlo)
24 /*fakestack_h*/ //r31 (Zhi)
25 #define Mh x //mod3 vars
26 #define Ml t // -"-
27 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
28 void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
31 ADD (Ml, Mh)
32 CLR (Mh)
33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
39 ANDI (Ml, 0x0f)
40 ADD (Ml, tmp)
41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
44 ANDI (Ml, 0x03)
45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
51 CPI (Ml, 3)
52 BRPL (skip)
53 SUBI (Ml, 3)
54 skip:;
55 RET
56 #undef tmp
57 }
58 void g(void) {
59 // g(i, t) -> t
60 // tempvars: `x` and `_`
61 #define tmp _
62 ANDI (t, 0x07)
63 MOV (tmp, i2)
64 ANDI (tmp, 3)
65 TST (tmp)
66 #undef tmp
67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
70 t = data[t];
71 /*MOV X_hi==x, data_hi
72 MOV X_lo==t, data_lo
73 ADD X_lo, t
74 ADC X_hi, zero
75 LD t, X */
76 #define a1 x
77 #define a2 _
78 #define a0 t
79 CLR (a2)
80 CLR (a1)
81 for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
82 SBRS (t, 0)
83 goto skip2;
84 if (t & 1) {
85 ADD (a1, i0)
86 ADC (a2, i1, carry)
87 }
88 skip2:
89 LSR (a2)
90 ROR (a1)
91 ROR (t)
92 }
93 MOV (t, a1) //can't return x or _ as a1, both needed later besides t
94 #undef a0
95 #undef a1
96 #undef a2
97
98 RET //TODO: replace CALL/RET with IJMP?
99 };
100
101 int main(void) {
102 CLR (zero)
103 CLR (i0)
104 CLR (i1)
105 CLR (i2)
106 CLR (i3)
107 for (;;) {
108 MOV (n, i2)
109 LSL (n)
110 LSL (n)
111 #define tmp _
112 MOV (tmp, i1)
113 SWAP (tmp)
114 ANDI (tmp, 0x0f)
115 LSR (tmp)
116 LSR (tmp)
117 OR (n, tmp)
118 #undef tmp
119 MOV (s, i3)
120 LSR (s)
121 ROR (s)
122 ANDI (s, 0x80)
123 #define tmp _
124 MOV (tmp, i2)
125 LSR (tmp)
126 OR (s, tmp)
127 #undef tmp
128
129 //voice 1:
130 MOV (t, n)
131 RCALL g();
132 SWAP (t)
133 ANDI (t, 1)
134 MOV (acc, t)
135
136 //voice 2:
137 #define tmp _
138 MOV (tmp, i2)
139 LSL (tmp)
140 LSL (tmp)
141 LSL (tmp)
142 MOV (t, i1)
143 SWAP (t)
144 ANDI (t, 0xf)
145 LSR (t)
146 OR (t, tmp)
147 #undef tmp
148 EOR (t, n)
149 RCALL g();
150 LSR (t)
151 LSR (t)
152 ANDI (t, 3)
153 AND (t, s)
154 ADD (acc, t)
155
156 //voice 3:
157 MOV (Ml, i2)
158 SWAP (Ml)
159 ANDI (Ml, 0xf0)
160 LSL (Ml)
161 #define tmp _
162 MOV (tmp, i1)
163 LSR (tmp)
164 LSR (tmp)
165 LSR (tmp)
166 OR (Ml, tmp)
167 #undef tmp
168 MOV (Mh, i3)
169 SWAP (Mh)
170 ANDI (Mh, 0xf0)
171 LSL (Mh)
172 #define tmp _
173 MOV (tmp, i2)
174 LSR (tmp)
175 LSR (tmp)
176 LSR (tmp)
177 OR (Mh, tmp)
178 #undef tmp
179 RCALL mod3();
180 ADD (t, n)
181 RCALL g();
182 LSR (t)
183 LSR (t)
184 ANDI (t, 3)
185 MOV (x, s)
186 INC (x)
187 #define tmp _
188 MOV (tmp, x)
189 LSR (tmp)
190 LSR (tmp)
191 ADD (tmp, x)
192 ROR (tmp)
193 LSR (tmp)
194 ADD (tmp, x)
195 ROR (tmp)
196 LSR (tmp)
197 ADD (tmp, x)
198 ROR (tmp)
199 LSR (tmp)
200 AND (t, tmp)
201 #undef tmp
202 ADD (acc, t)
203
204 //voice 4:
205 MOV (Ml, i2)
206 SWAP (Ml)
207 ANDI (Ml, 0xf0)
208 LSL (Ml)
209 LSL (Ml)
210 #define tmp _
211 MOV (tmp, i1)
212 LSR (tmp)
213 LSR (tmp)
214 OR (Ml, tmp)
215 #undef tmp
216 MOV (Mh, i3)
217 SWAP (Mh)
218 ANDI (Mh, 0xf0)
219 LSL (Mh)
220 LSL (Mh)
221 #define tmp _
222 MOV (tmp, i2)
223 LSR (tmp)
224 LSR (tmp)
225 OR (Mh, tmp)
226 #undef tmp
227 RCALL mod3();
228 SUB (t, n)
229 NEG (t)
230 SUBI (t, -8)
231 RCALL g();
232 LSR (t)
233 ANDI (t, 3)
234 INC (s)
235 #define tmp _
236 MOV (tmp, s)
237 LSR (tmp)
238 ADD (tmp, s)
239 ROR (tmp)
240 LSR (tmp)
241 LSR (tmp)
242 ADD (tmp, s)
243 ROR (tmp)
244 ADD (tmp, s)
245 ROR (tmp)
246 LSR (tmp)
247 LSR (tmp)
248 AND (t, tmp)
249 #undef tmp
250 ADD (acc, t)
251
252 putchar(acc<<4); //TODO
253 SUBI (i0, -1)
254 ADC (i1, zero, !i0)
255 ADC (i2, zero, !i0&&!i1)
256 ADC (i3, zero, !i0&&!i1&&!i2)
257 }
258 }
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