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[Chiptunes.git] / foo.c
1 #include <stdio.h>
2 #include "fakeasm.h"
3 typedef unsigned char u8;
4
5 u8 data[] = {
6 0x84, 0x9d, 0xb0, 0x69, 0x9d, 0x84, 0x69, 0x58,
7 0x75, 0x8c, 0xb0, 0x69, 0x8c, 0x75, 0x69, 0x58
8 };
9 u8 zero; //r16
10 u8 acc; //r17
11 u8 i0; //r18
12 u8 i1; //r19
13 u8 i2; //r20
14 u8 i3; //r21
15 u8 n; //r22
16 u8 s; //r23
17 u8 _; //r24
18 //r25
19 u8 t;/*==Ml*/ //r26 (Xlo)
20 u8 x;/*==Mh*/ //r27 (Xhi)
21 //r28
22 //r29
23 /*fakestack_l*/ //r30 (Zlo)
24 /*fakestack_h*/ //r31 (Zhi)
25 #define Mh x //mod3 vars
26 #define Ml t // -"-
27 //http://homepage.divms.uiowa.edu/~jones/bcd/mod.shtml
28 void mod3(void) {
29 // mod3(Mh.Ml) -> t
30 #define tmp _
31 ADD (Ml, Mh)
32 CLR (Mh)
33 ADC (Mh, zero, carry) //Mh only holds the carry bit
34 MOV (tmp, Ml)
35 SWAP (tmp)
36 ANDI (tmp, 0x0f)
37 SWAP (Mh)
38 OR (tmp, Mh)
39 ANDI (Ml, 0x0f)
40 ADD (Ml, tmp)
41 MOV (tmp, Ml)
42 LSR (tmp)
43 LSR (tmp)
44 ANDI (Ml, 0x03)
45 ADD (Ml, tmp)
46 MOV (tmp, Ml)
47 LSR (tmp)
48 LSR (tmp)
49 ANDI (Ml, 0x03)
50 ADD (Ml, tmp)
51 CPI (Ml, 3)
52 BRPL (skip)
53 SUBI (Ml, 3)
54 skip:;
55 RET
56 #undef tmp
57 }
58 void g(void) {
59 // g(i, t) -> t
60 // tempvars: `x` and `_`
61 #define tmp _
62 ANDI (t, 0x07)
63 MOV (tmp, i2)
64 ANDI (tmp, 3)
65 TST (tmp)
66 #undef tmp
67 BREQ (skip)
68 SUBI (t, -8)
69 skip:
70 t = data[t];
71 /*MOV X_hi==x, data_hi
72 MOV X_lo==t, data_lo
73 ADD X_lo, t
74 ADC X_hi, zero
75 LD t, X */
76 #define a1 x
77 #define a2 _
78 #define a0 t
79 CLR (a2)
80 CLR (a1)
81 for (u8 loop = 0; loop < 8; loop++) { //Note: t&2 always zero
82 SBRS (t, 0)
83 goto skip2;
84 ADD (a1, i0)
85 ADC (a2, i1, carry)
86 skip2:
87 LSR (a2)
88 ROR (a1)
89 ROR (t)
90 }
91 MOV (t, a1) //can't return x or _ as a1, both needed later besides t
92 #undef a0
93 #undef a1
94 #undef a2
95
96 RET //TODO: replace CALL/RET with IJMP?
97 };
98
99 int main(void) {
100 CLR (zero)
101 CLR (i0)
102 CLR (i1)
103 CLR (i2)
104 CLR (i3)
105 for (;;) {
106 MOV (n, i2)
107 LSL (n)
108 LSL (n)
109 #define tmp _
110 MOV (tmp, i1)
111 SWAP (tmp)
112 ANDI (tmp, 0x0f)
113 LSR (tmp)
114 LSR (tmp)
115 OR (n, tmp)
116 #undef tmp
117 MOV (s, i3)
118 LSR (s)
119 ROR (s)
120 ANDI (s, 0x80)
121 #define tmp _
122 MOV (tmp, i2)
123 LSR (tmp)
124 OR (s, tmp)
125 #undef tmp
126
127 //voice 1:
128 MOV (t, n)
129 RCALL g();
130 SWAP (t)
131 ANDI (t, 1)
132 MOV (acc, t)
133
134 //voice 2:
135 #define tmp _
136 MOV (tmp, i2)
137 LSL (tmp)
138 LSL (tmp)
139 LSL (tmp)
140 MOV (t, i1)
141 SWAP (t)
142 ANDI (t, 0xf)
143 LSR (t)
144 OR (t, tmp)
145 #undef tmp
146 EOR (t, n)
147 RCALL g();
148 LSR (t)
149 LSR (t)
150 ANDI (t, 3)
151 AND (t, s)
152 ADD (acc, t)
153
154 //voice 3:
155 MOV (Ml, i2)
156 SWAP (Ml)
157 ANDI (Ml, 0xf0)
158 LSL (Ml)
159 #define tmp _
160 MOV (tmp, i1)
161 LSR (tmp)
162 LSR (tmp)
163 LSR (tmp)
164 OR (Ml, tmp)
165 #undef tmp
166 MOV (Mh, i3)
167 SWAP (Mh)
168 ANDI (Mh, 0xf0)
169 LSL (Mh)
170 #define tmp _
171 MOV (tmp, i2)
172 LSR (tmp)
173 LSR (tmp)
174 LSR (tmp)
175 OR (Mh, tmp)
176 #undef tmp
177 RCALL mod3();
178 ADD (t, n)
179 RCALL g();
180 LSR (t)
181 LSR (t)
182 ANDI (t, 3)
183 MOV (x, s)
184 INC (x)
185 #define tmp _
186 MOV (tmp, x)
187 LSR (tmp)
188 LSR (tmp)
189 ADD (tmp, x)
190 ROR (tmp)
191 LSR (tmp)
192 ADD (tmp, x)
193 ROR (tmp)
194 LSR (tmp)
195 ADD (tmp, x)
196 ROR (tmp)
197 LSR (tmp)
198 AND (t, tmp)
199 #undef tmp
200 ADD (acc, t)
201
202 //voice 4:
203 MOV (Ml, i2)
204 SWAP (Ml)
205 ANDI (Ml, 0xf0)
206 LSL (Ml)
207 LSL (Ml)
208 #define tmp _
209 MOV (tmp, i1)
210 LSR (tmp)
211 LSR (tmp)
212 OR (Ml, tmp)
213 #undef tmp
214 MOV (Mh, i3)
215 SWAP (Mh)
216 ANDI (Mh, 0xf0)
217 LSL (Mh)
218 LSL (Mh)
219 #define tmp _
220 MOV (tmp, i2)
221 LSR (tmp)
222 LSR (tmp)
223 OR (Mh, tmp)
224 #undef tmp
225 RCALL mod3();
226 SUB (t, n)
227 NEG (t)
228 SUBI (t, -8)
229 RCALL g();
230 LSR (t)
231 ANDI (t, 3)
232 INC (s)
233 #define tmp _
234 MOV (tmp, s)
235 LSR (tmp)
236 ADD (tmp, s)
237 ROR (tmp)
238 LSR (tmp)
239 LSR (tmp)
240 ADD (tmp, s)
241 ROR (tmp)
242 ADD (tmp, s)
243 ROR (tmp)
244 LSR (tmp)
245 LSR (tmp)
246 AND (t, tmp)
247 #undef tmp
248 ADD (acc, t)
249
250 putchar(acc<<4); //TODO
251 SUBI (i0, -1)
252 ADC (i1, zero, !i0)
253 ADC (i2, zero, !i0&&!i1)
254 ADC (i3, zero, !i0&&!i1&&!i2)
255 }
256 }
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