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git.gir.st - tmk_keyboard.git/blob - tmk_core/protocol/usb_hid/USB_Host_Shield_2.0/usbhost.h
1 /* Copyright (C) 2011 Circuits At Home, LTD. All rights reserved.
3 This software may be distributed and modified under the terms of the GNU
4 General Public License version 2 (GPL2) as published by the Free Software
5 Foundation and appearing in the file GPL2.TXT included in the packaging of
6 this file. Please note that GPL2 Section 2[b] requires that all works based
7 on this software must also be made publicly available under the terms of
14 Web : http://www.circuitsathome.com
15 e-mail : support@circuitsathome.com
17 /* MAX3421E-based USB Host Library header file */
20 #if !defined(_usb_h_) || defined(_USBHOST_H_)
21 #error "Never include usbhost.h directly; include Usb.h instead"
26 #include <spi4teensy3.h>
27 #include <sys/types.h>
30 /* SPI initialization */
31 template< typename SPI_CLK
, typename SPI_MOSI
, typename SPI_MISO
, typename SPI_SS
> class SPi
{
35 // spi4teensy3 inits everything for us, except /SS
36 // CLK, MOSI and MISO are hard coded for now.
37 // spi4teensy3::init(0,0,0); // full speed, cpol 0, cpha 0
38 spi4teensy3::init(); // full speed, cpol 0, cpha 0
39 SPI_SS::SetDirWrite();
42 #elif SPI_HAS_TRANSACTION
44 SPI
.begin(); // The SPI library with transaction will take care of setting up the pins - settings is set in beginTransaction()
48 SPI_SS::SetDirWrite();
51 #if defined(__MIPSEL__)
52 SPI
.setClockDivider(1);
53 #elif defined(__ARDUINO_X86__)
54 #ifdef SPI_CLOCK_1M // Hack used to check if setClockSpeed is available
55 SPI
.setClockSpeed(12000000); // The MAX3421E can handle up to 26MHz, but in practice this was the maximum that I could reliably use
57 SPI
.setClockDivider(SPI_CLOCK_DIV2
); // This will set the SPI frequency to 8MHz - it could be higher, but it is not supported in the old API
60 SPI
.setClockDivider(4); // Set speed to 84MHz/4=21MHz - the MAX3421E can handle up to 26MHz
63 #elif defined(RBL_NRF51822)
65 SPI_SS::SetDirWrite();
68 // SPI.setFrequency(SPI_FREQUENCY_8M);
73 SPI_CLK::SetDirWrite();
74 SPI_MOSI::SetDirWrite();
75 SPI_MISO::SetDirRead();
76 SPI_SS::SetDirWrite();
77 /* mode 00 (CPOL=0, CPHA=0) master, fclk/2. Mode 11 (CPOL=11, CPHA=11) is also supported by MAX3421E */
87 /* SPI pin definitions. see avrpins.h */
88 #if defined(__AVR_ATmega1280__) || (__AVR_ATmega2560__) || defined(__AVR_ATmega32U4__) || defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
89 typedef SPi
< Pb1
, Pb2
, Pb3
, Pb0
> spi
;
90 #elif defined(__AVR_ATmega168__) || defined(__AVR_ATmega328P__)
91 typedef SPi
< Pb5
, Pb3
, Pb4
, Pb2
> spi
;
92 #elif defined(__AVR_ATmega644__) || defined(__AVR_ATmega644P__) || defined(__AVR_ATmega1284__) || defined(__AVR_ATmega1284P__)
93 typedef SPi
< Pb7
, Pb5
, Pb6
, Pb4
> spi
;
94 #elif (defined(CORE_TEENSY) && (defined(__MK20DX128__) || defined(__MK20DX256__))) || defined(__ARDUINO_X86__) || defined(__MIPSEL__)
95 typedef SPi
< P13
, P11
, P12
, P10
> spi
;
96 #elif defined(ARDUINO_SAM_DUE) && defined(__SAM3X8E__)
97 typedef SPi
< P76
, P75
, P74
, P10
> spi
;
98 #elif defined(RBL_NRF51822)
99 typedef SPi
< P16
, P18
, P17
, P10
> spi
;
101 #error "No SPI entry in usbhost.h"
109 template< typename SPI_SS
, typename INTR
> class MAX3421e
/* : public spi */ {
110 static uint8_t vbusState
;
114 void regWr(uint8_t reg
, uint8_t data
);
115 uint8_t* bytesWr(uint8_t reg
, uint8_t nbytes
, uint8_t* data_p
);
116 void gpioWr(uint8_t data
);
117 uint8_t regRd(uint8_t reg
);
118 uint8_t* bytesRd(uint8_t reg
, uint8_t nbytes
, uint8_t* data_p
);
122 int8_t Init(int mseconds
);
124 void vbusPower(VBUS_t state
) {
125 regWr(rPINCTL
, (bmFDUPSPI
| bmINTLEVEL
| state
));
128 uint8_t getVbusState(void) {
132 uint8_t GpxHandler();
133 uint8_t IntHandler();
137 template< typename SPI_SS
, typename INTR
>
138 uint8_t MAX3421e
< SPI_SS
, INTR
>::vbusState
= 0;
141 template< typename SPI_SS
, typename INTR
>
142 MAX3421e
< SPI_SS
, INTR
>::MAX3421e() {
143 // Leaving ADK hardware setup in here, for now. This really belongs with the other parts.
144 #ifdef BOARD_MEGA_ADK
145 // For Mega ADK, which has a Max3421e on-board, set MAX_RESET to output mode, and then set it to HIGH
151 /* write single byte into MAX3421 register */
152 template< typename SPI_SS
, typename INTR
>
153 void MAX3421e
< SPI_SS
, INTR
>::regWr(uint8_t reg
, uint8_t data
) {
155 #if SPI_HAS_TRANSACTION
156 SPI
.beginTransaction(SPISettings(26000000, MSBFIRST
, SPI_MODE0
)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
160 #if USING_SPI4TEENSY3
164 spi4teensy3::send(c
, 2);
165 #elif SPI_HAS_TRANSACTION
171 SPI
.transfer(reg
| 0x02);
175 while(!(SPSR
& (1 << SPIF
)));
177 while(!(SPSR
& (1 << SPIF
)));
181 #if SPI_HAS_TRANSACTION
182 SPI
.endTransaction();
187 /* multiple-byte write */
189 /* returns a pointer to memory position after last written */
190 template< typename SPI_SS
, typename INTR
>
191 uint8_t* MAX3421e
< SPI_SS
, INTR
>::bytesWr(uint8_t reg
, uint8_t nbytes
, uint8_t* data_p
) {
193 #if SPI_HAS_TRANSACTION
194 SPI
.beginTransaction(SPISettings(26000000, MSBFIRST
, SPI_MODE0
)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
198 #if USING_SPI4TEENSY3
199 spi4teensy3::send(reg
| 0x02);
200 spi4teensy3::send(data_p
, nbytes
);
202 #elif SPI_HAS_TRANSACTION
203 SPI
.transfer(reg
| 0x02);
204 SPI
.transfer(data_p
, nbytes
);
206 #elif defined(__ARDUINO_X86__)
207 SPI
.transfer(reg
| 0x02);
208 SPI
.transferBuffer(data_p
, NULL
, nbytes
);
211 SPI
.transfer(reg
| 0x02);
213 SPI
.transfer(*data_p
);
215 data_p
++; // advance data pointer
218 SPDR
= (reg
| 0x02); //set WR bit and send register number
220 while(!(SPSR
& (1 << SPIF
))); //check if previous byte was sent
221 SPDR
= (*data_p
); // send next data byte
223 data_p
++; // advance data pointer
225 while(!(SPSR
& (1 << SPIF
)));
229 #if SPI_HAS_TRANSACTION
230 SPI
.endTransaction();
236 /*GPIO byte is split between 2 registers, so two writes are needed to write one byte */
238 /* GPOUT bits are in the low nibble. 0-3 in IOPINS1, 4-7 in IOPINS2 */
239 template< typename SPI_SS
, typename INTR
>
240 void MAX3421e
< SPI_SS
, INTR
>::gpioWr(uint8_t data
) {
241 regWr(rIOPINS1
, data
);
243 regWr(rIOPINS2
, data
);
247 /* single host register read */
248 template< typename SPI_SS
, typename INTR
>
249 uint8_t MAX3421e
< SPI_SS
, INTR
>::regRd(uint8_t reg
) {
251 #if SPI_HAS_TRANSACTION
252 SPI
.beginTransaction(SPISettings(26000000, MSBFIRST
, SPI_MODE0
)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
256 #if USING_SPI4TEENSY3
257 spi4teensy3::send(reg
);
258 uint8_t rv
= spi4teensy3::receive();
260 #elif !defined(SPDR) || SPI_HAS_TRANSACTION
262 uint8_t rv
= SPI
.transfer(0); // Send empty byte
266 while(!(SPSR
& (1 << SPIF
)));
267 SPDR
= 0; // Send empty byte
268 while(!(SPSR
& (1 << SPIF
)));
273 #if SPI_HAS_TRANSACTION
274 SPI
.endTransaction();
279 /* multiple-byte register read */
281 /* returns a pointer to a memory position after last read */
282 template< typename SPI_SS
, typename INTR
>
283 uint8_t* MAX3421e
< SPI_SS
, INTR
>::bytesRd(uint8_t reg
, uint8_t nbytes
, uint8_t* data_p
) {
285 #if SPI_HAS_TRANSACTION
286 SPI
.beginTransaction(SPISettings(26000000, MSBFIRST
, SPI_MODE0
)); // The MAX3421E can handle up to 26MHz, use MSB First and SPI mode 0
290 #if USING_SPI4TEENSY3
291 spi4teensy3::send(reg
);
292 spi4teensy3::receive(data_p
, nbytes
);
294 #elif SPI_HAS_TRANSACTION
296 memset(data_p
, 0, nbytes
); // Make sure we send out empty bytes
297 SPI
.transfer(data_p
, nbytes
);
299 #elif defined(__ARDUINO_X86__)
301 SPI
.transferBuffer(NULL
, data_p
, nbytes
);
306 *data_p
++ = SPI
.transfer(0);
311 while(!(SPSR
& (1 << SPIF
))); //wait
313 SPDR
= 0; // Send empty byte
315 while(!(SPSR
& (1 << SPIF
)));
319 printf("%2.2x ", *data_p
);
331 #if SPI_HAS_TRANSACTION
332 SPI
.endTransaction();
337 /* GPIO read. See gpioWr for explanation */
339 /* GPIN pins are in high nibbles of IOPINS1, IOPINS2 */
340 template< typename SPI_SS
, typename INTR
>
341 uint8_t MAX3421e
< SPI_SS
, INTR
>::gpioRd() {
343 gpin
= regRd(rIOPINS2
); //pins 4-7
344 gpin
&= 0xf0; //clean lower nibble
345 gpin
|= (regRd(rIOPINS1
) >> 4); //shift low bits and OR with upper from previous operation.
349 /* reset MAX3421E. Returns number of cycles it took for PLL to stabilize after reset
350 or zero if PLL haven't stabilized in 65535 cycles */
351 template< typename SPI_SS
, typename INTR
>
352 uint16_t MAX3421e
< SPI_SS
, INTR
>::reset() {
354 regWr(rUSBCTL
, bmCHIPRES
);
355 regWr(rUSBCTL
, 0x00);
357 if((regRd(rUSBIRQ
) & bmOSCOKIRQ
)) {
364 /* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
365 template< typename SPI_SS
, typename INTR
>
366 int8_t MAX3421e
< SPI_SS
, INTR
>::Init() {
369 // you really should not init hardware in the constructor when it involves locks.
370 // Also avoids the vbus flicker issue confusing some devices.
371 /* pin and peripheral setup */
372 SPI_SS::SetDirWrite();
377 /* MAX3421E - full-duplex SPI, level interrupt */
378 // GPX pin on. Moved here, otherwise we flicker the vbus.
379 regWr(rPINCTL
, (bmFDUPSPI
| bmINTLEVEL
));
381 if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
385 regWr(rMODE
, bmDPPULLDN
| bmDMPULLDN
| bmHOST
); // set pull-downs, Host
387 regWr(rHIEN
, bmCONDETIE
| bmFRAMEIE
); //connection detection
389 /* check if device is connected */
390 regWr(rHCTL
, bmSAMPLEBUS
); // sample USB bus
391 while(!(regRd(rHCTL
) & bmSAMPLEBUS
)); //wait for sample operation to finish
393 busprobe(); //check if anything is connected
395 regWr(rHIRQ
, bmCONDETIRQ
); //clear connection detect interrupt
396 regWr(rCPUCTL
, 0x01); //enable interrupt pin
401 /* initialize MAX3421E. Set Host mode, pullups, and stuff. Returns 0 if success, -1 if not */
402 template< typename SPI_SS
, typename INTR
>
403 int8_t MAX3421e
< SPI_SS
, INTR
>::Init(int mseconds
) {
406 // you really should not init hardware in the constructor when it involves locks.
407 // Also avoids the vbus flicker issue confusing some devices.
408 /* pin and peripheral setup */
409 SPI_SS::SetDirWrite();
414 /* MAX3421E - full-duplex SPI, level interrupt, vbus off */
415 regWr(rPINCTL
, (bmFDUPSPI
| bmINTLEVEL
| GPX_VBDET
));
417 if(reset() == 0) { //OSCOKIRQ hasn't asserted in time
421 // Delay a minimum of 1 second to ensure any capacitors are drained.
422 // 1 second is required to make sure we do not smoke a Microdrive!
423 if(mseconds
< 1000) mseconds
= 1000;
426 regWr(rMODE
, bmDPPULLDN
| bmDMPULLDN
| bmHOST
); // set pull-downs, Host
428 regWr(rHIEN
, bmCONDETIE
| bmFRAMEIE
); //connection detection
430 /* check if device is connected */
431 regWr(rHCTL
, bmSAMPLEBUS
); // sample USB bus
432 while(!(regRd(rHCTL
) & bmSAMPLEBUS
)); //wait for sample operation to finish
434 busprobe(); //check if anything is connected
436 regWr(rHIRQ
, bmCONDETIRQ
); //clear connection detect interrupt
437 regWr(rCPUCTL
, 0x01); //enable interrupt pin
439 // GPX pin on. This is done here so that busprobe will fail if we have a switch connected.
440 regWr(rPINCTL
, (bmFDUPSPI
| bmINTLEVEL
));
445 /* probe bus to determine device presence and speed and switch host to this speed */
446 template< typename SPI_SS
, typename INTR
>
447 void MAX3421e
< SPI_SS
, INTR
>::busprobe() {
449 bus_sample
= regRd(rHRSL
); //Get J,K status
450 bus_sample
&= (bmJSTATUS
| bmKSTATUS
); //zero the rest of the byte
451 switch(bus_sample
) { //start full-speed or low-speed host
453 if((regRd(rMODE
) & bmLOWSPEED
) == 0) {
454 regWr(rMODE
, MODE_FS_HOST
); //start full-speed host
457 regWr(rMODE
, MODE_LS_HOST
); //start low-speed host
462 if((regRd(rMODE
) & bmLOWSPEED
) == 0) {
463 regWr(rMODE
, MODE_LS_HOST
); //start low-speed host
466 regWr(rMODE
, MODE_FS_HOST
); //start full-speed host
470 case( bmSE1
): //illegal state
473 case( bmSE0
): //disconnected state
474 regWr(rMODE
, bmDPPULLDN
| bmDMPULLDN
| bmHOST
| bmSEPIRQ
);
477 }//end switch( bus_sample )
480 /* MAX3421 state change task and interrupt handler */
481 template< typename SPI_SS
, typename INTR
>
482 uint8_t MAX3421e
< SPI_SS
, INTR
>::Task(void) {
485 //USB_HOST_SERIAL.print("Vbus state: ");
486 //USB_HOST_SERIAL.println( vbusState, HEX );
487 pinvalue
= INTR::IsSet(); //Read();
488 //pinvalue = digitalRead( MAX_INT );
490 rcode
= IntHandler();
492 // pinvalue = digitalRead( MAX_GPX );
493 // if( pinvalue == LOW ) {
496 // usbSM(); //USB state machine
500 template< typename SPI_SS
, typename INTR
>
501 uint8_t MAX3421e
< SPI_SS
, INTR
>::IntHandler() {
503 uint8_t HIRQ_sendback
= 0x00;
504 HIRQ
= regRd(rHIRQ
); //determine interrupt source
505 //if( HIRQ & bmFRAMEIRQ ) { //->1ms SOF interrupt handler
506 // HIRQ_sendback |= bmFRAMEIRQ;
507 //}//end FRAMEIRQ handling
508 if(HIRQ
& bmCONDETIRQ
) {
510 HIRQ_sendback
|= bmCONDETIRQ
;
512 /* End HIRQ interrupts handling, clear serviced IRQs */
513 regWr(rHIRQ
, HIRQ_sendback
);
514 return ( HIRQ_sendback
);
516 //template< typename SPI_SS, typename INTR >
517 //uint8_t MAX3421e< SPI_SS, INTR >::GpxHandler()
519 // uint8_t GPINIRQ = regRd( rGPINIRQ ); //read GPIN IRQ register
520 //// if( GPINIRQ & bmGPINIRQ7 ) { //vbus overload
521 //// vbusPwr( OFF ); //attempt powercycle
524 //// regWr( rGPINIRQ, bmGPINIRQ7 );
526 // return( GPINIRQ );
529 #endif // _USBHOST_H_