tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_Maxim/TARGET_MAX32610/pwrseq_regs.h

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   2  * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
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  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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  33
  34 #ifndef _MXC_PWRSEQ_REGS_H
  35 #define _MXC_PWRSEQ_REGS_H
  36
  37 #ifdef __cplusplus
  38 extern "C" {
  39 #endif
  40
  41 #include <stdint.h>
  42
  43 /**
  44  * @file  pwrseq_regs.h
  45  * @addtogroup pwrseq PWRSEQ
  46  * @{
  47  */
  48
  49 /*                                      Offset   Register Description
  50                                         ======   ================================================= */
  51 typedef struct {
  52     __IO uint32_t reg0;             /*  0x0000   Power Sequencer Control Register 0                */
  53     __IO uint32_t reg1;             /*  0x0004   Power Sequencer Control Register 1                */
  54     __IO uint32_t reg2;             /*  0x0008   Power Sequencer Control Register 2                */
  55     __IO uint32_t reg3;             /*  0x000C   Power Sequencer Control Register 3                */
  56     __IO uint32_t reg4;             /*  0x0010   Power Sequencer Control Register 4                */
  57     __IO uint32_t reg5;             /*  0x0014   Power Sequencer Control Register 5 (Trim 0)       */
  58     __IO uint32_t reg6;             /*  0x0018   Power Sequencer Control Register 6 (Trim 1)       */
  59     __I uint32_t rsv001C;           /*  0x001C                                                     */
  60     __IO uint32_t flags;            /*  0x0020   Power Sequencer Flags                             */
  61     __IO uint32_t msk_flags;        /*  0x0024   Power Sequencer Flags Mask Register               */
  62 } mxc_pwrseq_regs_t;
  63
  64
  65 /*
  66    Register offsets for module PWRSEQ.
  67 */
  68 #define MXC_R_PWRSEQ_OFFS_REG0                    ((uint32_t)0x00000000UL)
  69 #define MXC_R_PWRSEQ_OFFS_REG1                    ((uint32_t)0x00000004UL)
  70 #define MXC_R_PWRSEQ_OFFS_REG2                    ((uint32_t)0x00000008UL)
  71 #define MXC_R_PWRSEQ_OFFS_REG3                    ((uint32_t)0x0000000CUL)
  72 #define MXC_R_PWRSEQ_OFFS_REG4                    ((uint32_t)0x00000010UL)
  73 #define MXC_R_PWRSEQ_OFFS_REG5                    ((uint32_t)0x00000014UL)
  74 #define MXC_R_PWRSEQ_OFFS_REG6                    ((uint32_t)0x00000018UL)
  75 #define MXC_R_PWRSEQ_OFFS_FLAGS                   ((uint32_t)0x00000020UL)
  76 #define MXC_R_PWRSEQ_OFFS_MSK_FLAGS               ((uint32_t)0x00000024UL)
  77
  78
  79 /*
  80    Field positions and masks for module PWRSEQ.
  81 */
  82 #define MXC_F_PWRSEQ_REG0_PWR_LP1_POS                       0
  83 #define MXC_F_PWRSEQ_REG0_PWR_LP1                           ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LP1_POS))
  84 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS                1
  85 #define MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_FIRST_BOOT_POS))
  86 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS                2
  87 #define MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SYS_REBOOT_POS))
  88 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS                 3
  89 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_RUN_POS))
  90 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS                 4
  91 #define MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_LDOEN_SLP_POS))
  92 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS                5
  93 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_RUN_POS))
  94 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS                6
  95 #define MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_CHZYEN_SLP_POS))
  96 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS                  7
  97 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_RUN_POS))
  98 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS                  8
  99 #define MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_ROEN_SLP_POS))
 100 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS                  9
 101 #define MXC_F_PWRSEQ_REG0_PWR_NREN_RUN                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_RUN_POS))
 102 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS                  10
 103 #define MXC_F_PWRSEQ_REG0_PWR_NREN_SLP                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_NREN_SLP_POS))
 104 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS                 11
 105 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN_POS))
 106 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS                 12
 107 #define MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP_POS))
 108 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS                13
 109 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_RUN_POS))
 110 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS                14
 111 #define MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM3EN_SLP_POS))
 112 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS                15
 113 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_RUN_POS))
 114 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS                16
 115 #define MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVM1EN_SLP_POS))
 116 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS              17
 117 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_RUN_POS))
 118 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS              18
 119 #define MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMRTCEN_SLP_POS))
 120 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS                19
 121 #define MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG0_PWR_SVMVDDA3EN_POS))
 122
 123 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS                0
 124 #define MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG                    ((uint32_t)(0x000000FFUL << MXC_F_PWRSEQ_REG1_PWR_TRIKL_CHRG_POS))
 125 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS                  8
 126 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDA3_POS))
 127 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS            9
 128 #define MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_TEMP_SENSOR_PD_POS))
 129 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS                  10
 130 #define MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO                      ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_PD_VDDIO_POS))
 131 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS              11
 132 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW_POS))
 133 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS             12
 134 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW2_POS))
 135 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS             13
 136 #define MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_MAN_VDDIO_SW1_POS))
 137 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS               14
 138 #define MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG1_PWR_GPIO_FREEZE_POS))
 139
 140 #define MXC_F_PWRSEQ_REG2_PWR_RST3_POS                      0
 141 #define MXC_F_PWRSEQ_REG2_PWR_RST3                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_RST3_POS))
 142 #define MXC_F_PWRSEQ_REG2_PWR_W3_POS                        5
 143 #define MXC_F_PWRSEQ_REG2_PWR_W3                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W3_POS))
 144 #define MXC_F_PWRSEQ_REG2_PWR_W1_POS                        10
 145 #define MXC_F_PWRSEQ_REG2_PWR_W1                            ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_POS))
 146 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS                    15
 147 #define MXC_F_PWRSEQ_REG2_PWR_W1_LOW                        ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_W1_LOW_POS))
 148 #define MXC_F_PWRSEQ_REG2_PWR_WRTC_POS                      20
 149 #define MXC_F_PWRSEQ_REG2_PWR_WRTC                          ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG2_PWR_WRTC_POS))
 150 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS                    25
 151 #define MXC_F_PWRSEQ_REG2_PWR_WVDDA3                        ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG2_PWR_WVDDA3_POS))
 152
 153 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS                     0
 154 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL                         ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_POS))
 155 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS               3
 156 #define MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_ROSEL_QUICK_POS))
 157 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS                    5
 158 #define MXC_F_PWRSEQ_REG3_PWR_SVMSEL                        ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_SVMSEL_POS))
 159 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS            8
 160 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO                ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRSVMSELO_POS))
 161 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS              10
 162 #define MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL                  ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG3_PWR_PWRFLTRROSEL_POS))
 163 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS               13
 164 #define MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX                   ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_SVM_CLK_MUX_POS))
 165 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS                15
 166 #define MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_RO_CLK_MUX_POS))
 167 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS                 16
 168 #define MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG3_PWR_QUICK_CNT_POS))
 169 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS                     17
 170 #define MXC_F_PWRSEQ_REG3_PWR_BO_TC                         ((uint32_t)(0x00000003UL << MXC_F_PWRSEQ_REG3_PWR_BO_TC_POS))
 171
 172 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS              0
 173 #define MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_PS_2_GPIO_POS))
 174 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS            1
 175 #define MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_TM_FAST_TIMERS_POS))
 176 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS             2
 177 #define MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_PROT_TRIM_POS))
 178 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS              3
 179 #define MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_DIS_COMP_POS))
 180 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS           4
 181 #define MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_TO_VDD_FAST_POS))
 182 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS               5
 183 #define MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_LDO_OFF_POS))
 184 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS               6
 185 #define MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_REG4_PWR_USB_FRC_VDD_POS))
 186
 187 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS               0
 188 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG                   ((uint32_t)(0x0000003FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_SVM_BG_POS))
 189 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS               6
 190 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8                   ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG1P8_POS))
 191 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS               10
 192 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3                   ((uint32_t)(0x0000001FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_REG3P3_POS))
 193 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS             15
 194 #define MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF                 ((uint32_t)(0x0000007FUL << MXC_F_PWRSEQ_REG5_PWR_TRIM_OSC_VREF_POS))
 195
 196 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS             0
 197 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS                 ((uint32_t)(0x00000007UL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_BIAS_POS))
 198 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS           3
 199 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_PM_RES_POS))
 200 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS           7
 201 #define MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES               ((uint32_t)(0x0000000FUL << MXC_F_PWRSEQ_REG6_PWR_TRIM_USB_DM_RES_POS))
 202
 203 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS               0
 204 #define MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_FIRST_BOOT_POS))
 205 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS               1
 206 #define MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_SYS_REBOOT_POS))
 207 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS             2
 208 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_PWR_FAIL_POS))
 209 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS            3
 210 #define MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_PRV_BOOT_FAIL_POS))
 211 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS              4
 212 #define MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP                  ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_COMP_WAKEUP_POS))
 213 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS                5
 214 #define MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_IO_WAKEUP_POS))
 215 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS                 6
 216 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_RST_POS))
 217 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS                7
 218 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD3_WARN_POS))
 219 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS                 8
 220 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_RST_POS))
 221 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS             9
 222 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_LOW_RST_POS))
 223 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS                10
 224 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD1_WARN_POS))
 225 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS                11
 226 #define MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VRTC_WARN_POS))
 227 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS               12
 228 #define MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_POR3Z_FAIL_POS))
 229 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS                    13
 230 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR0                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR0_POS))
 231 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS                    14
 232 #define MXC_F_PWRSEQ_FLAGS_RTC_CMPR1                        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_CMPR1_POS))
 233 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS             15
 234 #define MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_PRESCALE_CMP_POS))
 235 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS                 16
 236 #define MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER                     ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_RTC_ROLLOVER_POS))
 237 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS             17
 238 #define MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_BROWNOUT_DET_POS))
 239 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS          18
 240 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
 241 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS        19
 242 #define MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
 243 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS                20
 244 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD22_RST_POS))
 245 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS               21
 246 #define MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST                   ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_FLAGS_PWR_VDD195_RST_POS))
 247
 248 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS           1
 249 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_SYS_REBOOT_POS))
 250 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS         2
 251 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_PWR_FAIL_POS))
 252 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS        3
 253 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL            ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_PRV_BOOT_FAIL_POS))
 254 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS          4
 255 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP              ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_COMP_WAKEUP_POS))
 256 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS            5
 257 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_IO_WAKEUP_POS))
 258 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS             6
 259 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_RST_POS))
 260 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS            7
 261 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD3_WARN_POS))
 262 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS             8
 263 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_RST_POS))
 264 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS         9
 265 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_LOW_RST_POS))
 266 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS            10
 267 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD1_WARN_POS))
 268 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS            11
 269 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VRTC_WARN_POS))
 270 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS           12
 271 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_POR3Z_FAIL_POS))
 272 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS                13
 273 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0_POS))
 274 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS                14
 275 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1                    ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR1_POS))
 276 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS         15
 277 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_PRESCALE_CMP_POS))
 278 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS             16
 279 #define MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER                 ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER_POS))
 280 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS         17
 281 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET             ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_BROWNOUT_DET_POS))
 282 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS      18
 283 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP          ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_PLUG_WAKEUP_POS))
 284 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS    19
 285 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP        ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_USB_REMOVE_WAKEUP_POS))
 286 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS            20
 287 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST                ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD22_RST_POS))
 288 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS           21
 289 #define MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST               ((uint32_t)(0x00000001UL << MXC_F_PWRSEQ_MSK_FLAGS_PWR_VDD195_RST_POS))
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294
 295 /**
 296 * @}
 297 */
 298
 299 #endif /* _MXC_PWRSEQ_REGS_H */