tool/mbed/mbed-sdk/libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC23XX/core_arm7.h

   1 /* mbed Microcontroller Library
   2  * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
   3  *
   4  * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
   5  * based on core_cm3.h, V1.20
   6  */
   7
   8 #ifndef __ARM7_CORE_H__
   9 #define __ARM7_CORE_H__
  10
  11 #include "vector_defns.h"
  12
  13 #ifdef __cplusplus
  14 extern "C" {
  15 #endif
  16
  17 #define __CM3_CMSIS_VERSION_MAIN  (0x01)                                                       /*!< [31:16] CMSIS HAL main version */
  18 #define __CM3_CMSIS_VERSION_SUB   (0x20)                                                       /*!< [15:0]  CMSIS HAL sub version  */
  19 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
  20
  21 #define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
  22
  23 /**
  24  *  Lint configuration \n
  25  *  ----------------------- \n
  26  *
  27  *  The following Lint messages will be suppressed and not shown: \n
  28  *  \n
  29  *    --- Error 10: --- \n
  30  *    register uint32_t __regBasePri         __asm("basepri"); \n
  31  *    Error 10: Expecting ';' \n
  32  *     \n
  33  *    --- Error 530: --- \n
  34  *    return(__regBasePri); \n
  35  *    Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
  36  *     \n
  37  *    --- Error 550: --- \n
  38  *      __regBasePri = (basePri & 0x1ff); \n
  39  *    } \n
  40  *    Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
  41  *     \n
  42  *    --- Error 754: --- \n
  43  *    uint32_t RESERVED0[24]; \n
  44  *    Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
  45  *     \n
  46  *    --- Error 750: --- \n
  47  *    #define __CM3_CORE_H__ \n
  48  *    Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
  49  *     \n
  50  *    --- Error 528: --- \n
  51  *    static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
  52  *    Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
  53  *     \n
  54  *    --- Error 751: --- \n
  55  *    } InterruptType_Type; \n
  56  *    Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
  57  * \n
  58  * \n
  59  *    Note:  To re-enable a Message, insert a space before 'lint' * \n
  60  *
  61  */
  62
  63 /*lint -save */
  64 /*lint -e10  */
  65 /*lint -e530 */
  66 /*lint -e550 */
  67 /*lint -e754 */
  68 /*lint -e750 */
  69 /*lint -e528 */
  70 /*lint -e751 */
  71
  72 #include <stdint.h>                           /* Include standard types */
  73
  74 #if defined ( __CC_ARM   )
  75 /**
  76  * @brief  Return the Main Stack Pointer (current ARM7 stack)
  77  *
  78  * @param  none
  79  * @return uint32_t Main Stack Pointer
  80  *
  81  * Return the current value of the MSP (main stack pointer)
  82  * Cortex processor register
  83  */
  84 extern uint32_t __get_MSP(void);
  85 #endif
  86
  87
  88 #if defined (__ICCARM__)
  89   #include <intrinsics.h>                     /* IAR Intrinsics   */
  90 #endif
  91
  92
  93 #ifndef __NVIC_PRIO_BITS
  94   #define __NVIC_PRIO_BITS    4               /*!< standard definition for NVIC Priority Bits */
  95 #endif
  96
  97 typedef struct
  98 {
  99   uint32_t IRQStatus;
 100   uint32_t FIQStatus;
 101   uint32_t RawIntr;
 102   uint32_t IntSelect;
 103   uint32_t IntEnable;
 104   uint32_t IntEnClr;
 105   uint32_t SoftInt;
 106   uint32_t SoftIntClr;
 107   uint32_t Protection;
 108   uint32_t SWPriorityMask;
 109   uint32_t RESERVED0[54];
 110   uint32_t VectAddr[32];
 111   uint32_t RESERVED1[32];
 112   uint32_t VectPriority[32];
 113   uint32_t RESERVED2[800];
 114   uint32_t Address;
 115 } NVIC_TypeDef;
 116
 117 #define NVIC_BASE              (0xFFFFF000)
 118 #define NVIC                   ((      NVIC_TypeDef *)       NVIC_BASE)
 119
 120
 121
 122 /**
 123  * IO definitions
 124  *
 125  * define access restrictions to peripheral registers
 126  */
 127
 128 #ifdef __cplusplus
 129 #define     __I     volatile                  /*!< defines 'read only' permissions      */
 130 #else
 131 #define     __I     volatile const            /*!< defines 'read only' permissions      */
 132 #endif
 133 #define     __O     volatile                  /*!< defines 'write only' permissions     */
 134 #define     __IO    volatile                  /*!< defines 'read / write' permissions   */
 135
 136
 137
 138
 139
 140 #if defined ( __CC_ARM   )
 141   #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
 142   #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
 143
 144 #elif defined ( __ICCARM__ )
 145   #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler           */
 146   #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
 147
 148 #elif defined   (  __GNUC__  )
 149   #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
 150   #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
 151
 152 #elif defined   (  __TASKING__  )
 153   #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler          */
 154   #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler       */
 155
 156 #endif
 157
 158
 159 /* ###################  Compiler specific Intrinsics  ########################### */
 160
 161 #if defined ( __CC_ARM   ) /*------------------RealView Compiler -----------------*/
 162 /* ARM armcc specific functions */
 163
 164 #define __enable_fault_irq                __enable_fiq
 165 #define __disable_fault_irq               __disable_fiq
 166
 167 #define __NOP                             __nop
 168 //#define __WFI                             __wfi
 169 //#define __WFE                             __wfe
 170 //#define __SEV                             __sev
 171 //#define __ISB()                           __isb(0)
 172 //#define __DSB()                           __dsb(0)
 173 //#define __DMB()                           __dmb(0)
 174 //#define __REV                             __rev
 175 //#define __RBIT                            __rbit
 176 #define __LDREXB(ptr)                     ((unsigned char ) __ldrex(ptr))
 177 #define __LDREXH(ptr)                     ((unsigned short) __ldrex(ptr))
 178 #define __LDREXW(ptr)                     ((unsigned int  ) __ldrex(ptr))
 179 #define __STREXB(value, ptr)              __strex(value, ptr)
 180 #define __STREXH(value, ptr)              __strex(value, ptr)
 181 #define __STREXW(value, ptr)              __strex(value, ptr)
 182
 183 #define __disable_irq()         unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
 184                                 LPC_VIC->IntEnClr = 0xffffffff
 185
 186 #define __enable_irq()          LPC_VIC->IntEnable = tmp_IntEnable
 187
 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
 189
 190 #define __enable_irq                              __enable_interrupt        /*!< global Interrupt enable */
 191 #define __disable_irq                             __disable_interrupt       /*!< global Interrupt disable */
 192 #define __NOP                                     __no_operation()          /*!< no operation intrinsic in IAR Compiler */
 193
 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
 195
 196 static __INLINE void __enable_irq() {
 197     unsigned long temp;
 198     __asm__ __volatile__("mrs %0, cpsr\n"
 199                          "bic %0, %0, #0x80\n"
 200                          "msr cpsr_c, %0"
 201                          : "=r" (temp)
 202                          :
 203                          : "memory");
 204 }
 205
 206 static __INLINE void __disable_irq() {
 207     unsigned long old,temp;
 208     __asm__ __volatile__("mrs %0, cpsr\n"
 209                          "orr %1, %0, #0xc0\n"
 210                          "msr cpsr_c, %1"
 211                          : "=r" (old), "=r" (temp)
 212                          :
 213                          : "memory");
 214     // return (old & 0x80) == 0;
 215 }
 216
 217 static __INLINE void __NOP()                      { __ASM volatile ("nop"); }
 218
 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
 220 /* TASKING carm specific functions */
 221
 222 /*
 223  * The CMSIS functions have been implemented as intrinsics in the compiler.
 224  * Please use "carm -?i" to get an up to date list of all instrinsics,
 225  * Including the CMSIS ones.
 226  */
 227
 228 #endif
 229
 230
 231 /**
 232  * @brief  Enable Interrupt in NVIC Interrupt Controller
 233  *
 234  * @param  IRQn_Type IRQn specifies the interrupt number
 235  * @return none
 236  *
 237  * Enable a device specific interupt in the NVIC interrupt controller.
 238  * The interrupt number cannot be a negative value.
 239  */
 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 241 {
 242  NVIC->IntEnable = 1 << (uint32_t)IRQn;
 243 }
 244
 245
 246 /**
 247  * @brief  Disable the interrupt line for external interrupt specified
 248  *
 249  * @param  IRQn_Type IRQn is the positive number of the external interrupt
 250  * @return none
 251  *
 252  * Disable a device specific interupt in the NVIC interrupt controller.
 253  * The interrupt number cannot be a negative value.
 254  */
 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 256 {
 257  NVIC->IntEnClr = 1 << (uint32_t)IRQn;
 258 }
 259
 260 static __INLINE uint32_t __get_IPSR(void)
 261 {
 262  unsigned i;
 263
 264  for(i = 0; i < 32; i ++)
 265    if(NVIC->Address == NVIC->VectAddr[i])
 266      return i;
 267  return 1; // 1 is an invalid entry in the interrupt table on LPC2368
 268 }
 269
 270 #ifdef __cplusplus
 271 }
 272 #endif
 273
 274 #endif /* __ARM7_CORE_H__ */
 275
 276 /*lint -restore */